repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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CMU-SAFARI/NOCulator | hring/hw/buffered/src/vcr_sw_alloc_wf_mac.v | 9,512 | module MODULE1
(clk, reset, VAR46, VAR43);
parameter VAR24 = 5;
parameter VAR50 = VAR26;
parameter VAR33 = VAR23;
localparam VAR45 = (VAR33 == VAR18) ? 1 : (1 + 1);
localparam VAR17 = VAR45;
localparam VAR53 = VAR45;
localparam VAR32
= VAR17 + ((VAR33 != VAR18) ? 1 : 0);
parameter VAR10 = VAR7;
input clk;
input reset;
... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/phy/phy_pd.v | 23,428 | module MODULE1 #
(
parameter VAR68 = 100,
parameter VAR35 = "VAR66", parameter VAR48 = 16 )
(
output [99:0] VAR43, input [4:0] VAR52,
output [4:0] VAR25,
output reg VAR50, output reg VAR75, output VAR72, input VAR84, input VAR81,
input VAR56, input [1:0] VAR19, input VAR64,
input VAR7,
input VAR76, input VAR2, input VA... | lgpl-3.0 |
donnaware/ZBC---The-Zero-Board-Computer | rtl/ver1/rtl/ram2.v | 10,647 | module MODULE1 (
VAR48,
VAR30,
VAR13,
VAR46,
VAR15,
VAR52,
VAR7,
VAR63,
VAR54,
VAR32);
input [10:0] VAR48;
input [10:0] VAR30;
input VAR13;
input VAR46;
input [7:0] VAR15;
input [7:0] VAR52;
input VAR7;
input VAR63;
output [7:0] VAR54;
output [7:0] VAR32;
tri1 VAR13;
tri0 VAR7;
tri0 VAR63;
wire [7:0] VAR1;
wire [7:0] V... | gpl-3.0 |
timtian090/Playground | UVM/UVMPlayground/Lab2/Lab2-Project/EECS301_Lab2_TopLevel.v | 2,161 | module MODULE1
(
input VAR3,
output [9:0] VAR5,
output [6:0] VAR8,
output [6:0] VAR15,
output [6:0] VAR1,
output [6:0] VAR4,
output [6:0] VAR10,
output [6:0] VAR16,
input [3:0] VAR2,
input [1:0] VAR14
);
localparam VAR9 = 50000000;
assign VAR8 = |VAR2 ? 7'h7F : 7'h00;
assign VAR15 = |VAR2 ? 7'h7F : 7'h00;
assign VAR1 =... | mit |
ncos/Xilinx-Verilog | GYRACC/src/GYRO/two_bit_counter.v | 1,854 | module MODULE1(
VAR2,
rst,
VAR1
);
input VAR2;
input rst;
output [1:0] VAR1;
reg [1:0] VAR3;
always @(posedge VAR2 or posedge rst)
begin
if (rst == 1'b1)
VAR3 <= {2{1'b0}};
end
else
VAR3 <= VAR3 + 1'b1;
end
assign VAR1 = VAR3;
endmodule | mit |
sh-chris110/chris | FPGA/HPS/Qsys/hps_design/synthesis/submodules/hps_design_SMP_HPS.v | 7,933 | module MODULE1 #(
parameter VAR18 = 0,
parameter VAR13 = 0
) (
output wire VAR54, input wire VAR38, output wire [11:0] VAR23, output wire [20:0] VAR44, output wire [3:0] VAR53, output wire [2:0] VAR2, output wire [1:0] VAR49, output wire [1:0] VAR10, output wire [3:0] VAR35, output wire [2:0] VAR26, output wire VAR15, ... | gpl-2.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/ui_cmd.v | 8,317 | module MODULE1 #
(
parameter VAR42 = 100,
parameter VAR43 = 33,
parameter VAR39 = 3,
parameter VAR58 = 12,
parameter VAR32 = 2,
parameter VAR27 = 16,
parameter VAR20 = 4,
parameter VAR52 = "VAR25"
)
(
VAR49, VAR38, VAR22, VAR7, VAR14, VAR36, VAR48, VAR21, VAR51,
VAR54, VAR28, VAR47,
rst, clk, VAR37, VAR8, VAR23, VAR41,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxbp/sky130_fd_sc_lp__dfxbp.functional.pp.v | 1,767 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR9 ,
VAR1 ,
VAR4,
VAR11,
VAR13 ,
VAR7
);
output VAR8 ;
output VAR10 ;
input VAR9 ;
input VAR1 ;
input VAR4;
input VAR11;
input VAR13 ;
input VAR7 ;
wire VAR2;
VAR14 VAR3 VAR12 (VAR2 , VAR1, VAR9, , VAR4, VAR11);
buf VAR5 (VAR8 , VAR2 );
not VAR6 (VAR10 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtn/sky130_fd_sc_ls__dlrtn.functional.v | 1,806 | module MODULE1 (
VAR7 ,
VAR11,
VAR5 ,
VAR1
);
output VAR7 ;
input VAR11;
input VAR5 ;
input VAR1 ;
wire VAR3 ;
wire VAR6;
wire VAR8 ;
not VAR13 (VAR3 , VAR11 );
not VAR12 (VAR6, VAR1 );
VAR9 VAR2 VAR4 (VAR8 , VAR5, VAR6, VAR3);
buf VAR10 (VAR7 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2.pp.symbol.v | 1,322 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR4 ,
input VAR6,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/bufinv/sky130_fd_sc_ls__bufinv.pp.symbol.v | 1,272 | module MODULE1 (
input VAR1 ,
output VAR4 ,
input VAR6 ,
input VAR5,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_prog_rom_0_0/RAT_prog_rom_0_0_stub.v | 1,298 | module MODULE1(VAR3, VAR1, VAR2)
;
input [9:0]VAR3;
output [17:0]VAR1;
input VAR2;
endmodule | mit |
ptracton/pmodacl2 | soc/wb_uart/uart_top.v | 13,130 | module MODULE1 (
VAR32,
VAR44, VAR43, VAR3, VAR24, VAR38, VAR49, VAR10, VAR20, VAR6,
VAR2,
VAR1, VAR51,
VAR47, VAR28, VAR34, VAR50, VAR37, VAR21
, VAR33
);
parameter VAR31 = VAR46;
parameter VAR17 = VAR13;
input VAR32;
input VAR44;
input [VAR17-1:0] VAR43;
input [VAR31-1:0] VAR3;
output [VAR31-1:0] VAR24;
input VAR38;
... | mit |
freecores/zet86 | impl/virtex4-ml403ep/syn/clock.v | 1,572 | module MODULE1 (
input VAR26,
output clk,
output VAR14,
output VAR5,
output rst
);
reg [6:0] VAR27;
wire VAR1;
wire VAR18;
wire VAR19;
wire VAR30;
wire VAR10;
wire VAR25;
wire VAR2;
wire VAR34;
wire VAR6;
VAR11 VAR20 (
.VAR22 (VAR1),
.VAR16 (VAR26)
);
VAR29 VAR12 (
.VAR17 (VAR1),
.VAR31 (VAR14),
.VAR3 (VAR18),
.VAR8 (V... | gpl-3.0 |
glennchid/font5-firmware | src/verilog/synthesis/DriveOutput.v | 6,954 | module MODULE1 (
input clk,
input VAR12,
input VAR26,
input VAR24,
input [9:0] VAR43,
input [9:0] VAR20,
input [4:0] VAR5,
input [1:0] VAR23, input signed [12:0] VAR1,
input signed [24:0] din,
input signed [6:0] VAR34,
input VAR19,
input signed [6:0] VAR41,
output reg signed [12:0] dout = 13'd0, output reg VAR14 = 1'b0... | gpl-3.0 |
frisnit/fpga-noise | verilog/seven_segment.v | 2,910 | module MODULE2(VAR3, VAR5, VAR2);
input [3:0] VAR3;
input VAR5;
output reg [7:0] VAR2;
always @(VAR3, VAR5) begin
case (VAR3)
4'h1 : VAR2 = 7'b1001111;
4'h2 : VAR2 = 7'b0010010;
4'h3 : VAR2 = 7'b0000110;
4'h4 : VAR2 = 7'b1001100;
4'h5 : VAR2 = 7'b0100100;
4'h6 : VAR2 = 7'b0100000;
4'h7 : VAR2 = 7'b0001111;
4'h8 : VAR2 ... | mit |
chriswynnyk/american-put-verilog | american_put_stratix/src/fp_sub.v | 132,559 | module MODULE1
(
VAR10,
VAR2,
VAR1,
VAR7,
VAR6,
VAR11) ;
input VAR10;
input VAR2;
input VAR1;
input [54:0] VAR7;
input [5:0] VAR6;
output [54:0] VAR11;
reg [54:0] VAR9;
wire VAR5;
wire [31:0] VAR4;
wire [384:0] VAR3;
wire [5:0] VAR8; | apache-2.0 |
Gurint/EPC-Gen2-RFID-Tag-Baseband-Processor | tx.v | 1,645 | module MODULE1
(
output VAR19,
output VAR13,
output VAR7,
output VAR23,
input VAR18,
input VAR17,
input VAR5,
input VAR20,
input VAR11,
input VAR12,
input [15:0]VAR4,
input [1:0]VAR22,
input VAR3,
input VAR10,
input VAR9,
input VAR30
);
VAR14 VAR28
(
.VAR29(VAR29),
.VAR27(VAR27),
.VAR25(VAR25),
.VAR13(VAR13),
.VAR7(VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_4.behavioral.v | 3,726 | module MODULE1( VAR31, VAR30, VAR8, VAR13 );
input VAR31, VAR30, VAR8;
output VAR13;
reg VAR27;
VAR17 VAR9(.VAR31(VAR31),.VAR30(VAR30),.VAR8(VAR8),.VAR13(VAR13),.VAR27(VAR27));
VAR17 VAR5(.VAR31(VAR31),.VAR30(VAR30),.VAR8(VAR8),.VAR13(VAR13),.VAR27(VAR27));
not VAR11(VAR29,VAR30);
and VAR21(VAR26,VAR8,VAR29);
and VAR3(... | apache-2.0 |
masson2013/heterogeneous_hthreads | src/hardware/XilinxProcessorIP/pcores/plb_tft_cntlr_ref_v1_00_c/hdl/verilog/plb_if.v | 8,313 | module MODULE1(
clk, rst,
VAR30, VAR46, VAR44, VAR29, VAR43, VAR13, VAR6, VAR4, VAR37,
VAR36, VAR10, VAR19,
VAR38, VAR27, VAR14, VAR3,
VAR25,
VAR34, VAR24 );
input clk;
input rst;
input VAR30;
output VAR46;
output [0:1] VAR44;
output VAR29;
output [0:7] VAR43;
output [0:3] VAR13;
output [0:2] VAR6;
output [0:1] VAR4;
o... | bsd-3-clause |
ncos/Xilinx-Verilog | GYRACC/src/OLED/ZedboardOLED.v | 21,599 | module MODULE1
(
output VAR85,
output VAR103,
output VAR14,
output VAR56,
output VAR49,
output VAR81,
input wire VAR30,
input wire [127:0] VAR17,
input wire [127:0] VAR52,
input wire [127:0] VAR73,
input wire [127:0] VAR59,
input wire VAR105,
input wire VAR87
);
reg [143:0] VAR29;
reg [111:0] VAR89;
reg [142:0] VAR44;
... | mit |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/Seven_Segment_Display.v | 4,925 | module MODULE1 #(
parameter
VAR24 = 100, VAR16 = 4
)
(
input wire VAR19,
input wire [VAR16*4-1:0] VAR10,
input wire [VAR16-1:0] VAR21,
output reg [VAR16-1:0] VAR25,
output wire [7:0] VAR23
);
parameter integer VAR5 = 20*VAR16;
parameter integer VAR30 = (VAR24*1000/VAR5);
parameter VAR18 = 7'b1000000; parameter VAR8 = 7... | gpl-3.0 |
kyzhai/NUNY | src/hardware/whoosh_new_bb.v | 5,034 | module MODULE1 (
address,
VAR1,
VAR2);
input [12:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3/sky130_fd_sc_hdll__or3.functional.v | 1,273 | module MODULE1 (
VAR4,
VAR1,
VAR3,
VAR6
);
output VAR4;
input VAR1;
input VAR3;
input VAR6;
wire VAR7;
or VAR2 (VAR7, VAR3, VAR1, VAR6 );
buf VAR5 (VAR4 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fah/sky130_fd_sc_ms__fah_4.v | 2,283 | module MODULE1 (
VAR10,
VAR7 ,
VAR11 ,
VAR6 ,
VAR9 ,
VAR3,
VAR5,
VAR1 ,
VAR4
);
output VAR10;
output VAR7 ;
input VAR11 ;
input VAR6 ;
input VAR9 ;
input VAR3;
input VAR5;
input VAR1 ;
input VAR4 ;
VAR8 VAR2 (
.VAR10(VAR10),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.V... | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/video_sys/submodules/video_sys_sdram_0.v | 23,777 | module MODULE2 (
clk,
rd,
VAR59,
wr,
VAR18,
VAR42,
VAR74,
VAR73,
VAR7,
VAR68
)
;
output VAR42;
output VAR74;
output VAR73;
output VAR7;
output [ 40: 0] VAR68;
input clk;
input rd;
input VAR59;
input wr;
input [ 40: 0] VAR18;
wire VAR42;
wire VAR74;
wire VAR73;
reg [ 1: 0] VAR35;
reg [ 40: 0] VAR28;
reg [ 40: 0] VAR17;
... | gpl-2.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/openMSP430_fpga.v | 21,973 | module MODULE1 (
input VAR154,
input VAR113,
input VAR118,
input [1:0] VAR37,
input [3:0] VAR63,
output [7:0] VAR92,
inout [35:0] VAR27,
inout [35:0] VAR112,
inout [15:0] VAR150,
inout VAR170,
output VAR15,
output VAR123,
output VAR62,
input VAR34
);
wire [VAR59:0] VAR106;
wire [15:0] VAR11;
wire VAR181;
wire [1:0] VAR... | bsd-3-clause |
timtian090/Playground | UVM/UVMPlayground/Lab2/Lab2-Project/TF_CLS_PWM_DutyCycle_Timer.v | 1,948 | module MODULE1();
reg VAR3;
reg VAR2;
wire VAR9;
reg [127:0] VAR1;
localparam VAR5 = 50000000; localparam VAR8 = ((1.0 / VAR5) * 1000000000.0) / 2.0;
localparam VAR6 = 1000; localparam VAR4 = 20;
localparam VAR7 = VAR5 / VAR6;
begin
begin
begin
begin
end
begin | mit |
himingway/PIC16C5x | src/PC.v | 2,673 | module MODULE1 (
input clk , input VAR9 , input [ 8:0] VAR10 , input [ VAR13-1:0] VAR15, input [ VAR8-1:0] VAR17 , input [VAR19-1:0] VAR11 , input [ VAR4-1:0] VAR6 , input [ VAR18-1:0] VAR3 , input [ 2:0] VAR2, input [ 4:0] VAR7 , output [ VAR18-1:0] MODULE1 , output VAR12 ,
output VAR14
);
reg[VAR18-1:0] VAR20;
reg VA... | mit |
tdene/synth_opt_adders | src/pptrees/mappings/sky130_fd_sc_ms_map.v | 4,263 | module MODULE24
(
VAR36, VAR20
);
output VAR36;
input VAR20;
VAR19 MODULE24(.VAR36(VAR36), .VAR20(VAR20));
endmodule
module MODULE2
(
VAR36, VAR20
);
output VAR36;
input VAR20;
VAR2 MODULE2(.VAR21(VAR36), .VAR20(VAR20));
endmodule
module MODULE16
(
VAR36, VAR20, VAR3
);
output VAR36;
input VAR20, VAR3;
VAR4 MODULE16(.V... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_4.behavioral.pp.v | 2,782 | module MODULE1( VAR26, VAR24, VAR7, VAR18, VAR6, VAR2 );
input VAR7, VAR24, VAR26;
inout VAR6, VAR2;
output VAR18;
reg VAR1;
VAR20 VAR13(.VAR26(VAR26),.VAR24(VAR24),.VAR7(VAR7),.VAR18(VAR18),.VAR6(VAR6),.VAR2(VAR2),.VAR1(VAR1));
VAR20 VAR25(.VAR26(VAR26),.VAR24(VAR24),.VAR7(VAR7),.VAR18(VAR18),.VAR6(VAR6),.VAR2(VAR2),.... | apache-2.0 |
trun/fpgaboy | src/io/debug/oled_spi.v | 5,155 | module MODULE1(
input wire VAR25,
input wire reset,
input wire VAR18,
output wire VAR17,
output reg VAR7,
output wire VAR6,
output reg VAR14,
output reg VAR21,
output reg VAR11,
output reg VAR19
);
parameter VAR13 = 1;
parameter VAR26 = 2; parameter VAR33 = 3; parameter VAR2 = 4; parameter VAR23 = 5;
parameter VAR12 = ... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/ui/ui_rd_data.v | 19,243 | module MODULE1 #
(
parameter VAR1 = 100,
parameter VAR94 = 256,
parameter VAR19 = 5,
parameter VAR52 = "VAR46",
parameter VAR59 = 2 ,
parameter VAR57 = "VAR9"
)
(
VAR90, VAR53, VAR4, VAR80,
VAR24, VAR49, VAR23, VAR33,
rst, clk, VAR17, VAR61, VAR82, VAR74,
VAR92, VAR50, VAR71
);
input rst;
input clk;
output wire VAR90;
... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_2.behavioral.pp.v | 1,159 | module MODULE1( VAR2, VAR1, VAR3, VAR6 );
input VAR2;
inout VAR3, VAR6;
output VAR1;
VAR4 VAR5(.VAR2(VAR2),.VAR1(VAR1),.VAR3(VAR3),.VAR6(VAR6));
VAR4 VAR7(.VAR2(VAR2),.VAR1(VAR1),.VAR3(VAR3),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtn/sky130_fd_sc_hdll__dlrtn.functional.v | 1,807 | module MODULE1 (
VAR11 ,
VAR6,
VAR1 ,
VAR13
);
output VAR11 ;
input VAR6;
input VAR1 ;
input VAR13 ;
wire VAR9;
wire VAR8 ;
wire VAR5;
not VAR12 (VAR9 , VAR6 );
not VAR2 (VAR8 , VAR13 );
VAR4 VAR7 VAR3 (VAR5 , VAR1, VAR8, VAR9 );
buf VAR10 (VAR11 , VAR5 );
endmodule | apache-2.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v4_0_infrastructure.v | 30,832 | module MODULE1 #
(
parameter VAR63 = "VAR12", parameter VAR59 = 100, parameter VAR29 = 3000, parameter VAR65 = 2, parameter VAR32 = "VAR10",
parameter VAR4 = "VAR12",
parameter VAR34 = 4, parameter VAR33 = 1, parameter VAR14 = 45.0, parameter VAR68 = 16, parameter VAR1 = 4, parameter VAR66 = 64, parameter VAR26 = 16, p... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.symbol.v | 1,442 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR4 ,
input VAR1,
input VAR5 ,
input VAR6
);
endmodule | apache-2.0 |
Siliciumer/DOS-Mario-FPGA | sources/mario_score24x1.v | 5,605 | module MODULE1 (
input wire [7:0] VAR13,
input wire [3:0] VAR12,
input wire [3:0] VAR4,
input wire [11:0] VAR6,
output wire [7:0] VAR2
);
reg [7:0] VAR10;
reg [3:0] VAR9, VAR1, VAR5;
reg [3:0] VAR8, VAR15, VAR11, VAR3, VAR14;
integer VAR7;
always @(VAR6)
begin
VAR9 = 0;
VAR1 = 0;
VAR5 = 0;
for ( VAR7 = 11; VAR7 >= 0; V... | mit |
TheHouseHippo/verilog | alu3_add_sub.v | 6,057 | module MODULE11(VAR27, VAR2, VAR5, VAR24);
input VAR27, VAR2;
output VAR5, VAR24;
assign VAR24 = VAR27 ^ VAR2;
assign VAR5 = VAR27 & VAR2;
endmodule
module MODULE4(VAR27, VAR2, VAR14, VAR5, VAR24);
input VAR27, VAR2, VAR14;
output VAR5, VAR24;
assign VAR5 = (VAR27 & VAR2) | (VAR27 & VAR14) | (VAR2 & VAR14);
assign VAR2... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Mark_Extract_Bits.v | 1,245 | module MODULE1
(
VAR6,
VAR5
);
input [35:0] VAR6; output [17:0] VAR5;
wire [17:0] VAR4;
VAR3 VAR1 (.VAR2(VAR6), .VAR7(VAR4) );
assign VAR5 = VAR4;
endmodule | gpl-3.0 |
olgirard/openmsp430 | core/synthesis/altera/src/megawizard/stratix_pmem.v | 7,627 | module MODULE1 (
address,
VAR13,
VAR35,
VAR53,
VAR42,
VAR36,
VAR52);
input [11:0] address;
input [1:0] VAR13;
input VAR35;
input VAR53;
input [15:0] VAR42;
input VAR36;
output [15:0] VAR52;
tri1 [1:0] VAR13;
tri1 VAR35;
tri1 VAR53;
wire [15:0] VAR48;
wire [15:0] VAR52 = VAR48[15:0];
VAR8 VAR34 (
.VAR50 (VAR35),
.VAR25 ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211ai/sky130_fd_sc_hd__o211ai.symbol.v | 1,375 | module MODULE1 (
input VAR5,
input VAR3,
input VAR4,
input VAR6,
output VAR8
);
supply1 VAR9;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
kigawas/MipsCPU | CPU/regfile.v | 5,234 | module MODULE1(VAR74, VAR24, VAR13, VAR33, VAR32, clk, VAR69, VAR31, VAR25, VAR55, VAR45 );
input [4:0] VAR74, VAR24, VAR33;
input [31:0] VAR13;
input clk, VAR69, VAR32;
output [31:0] VAR31, VAR25;
input [4:0] VAR55;
output [31:0] VAR45;
wire [31:0] VAR73;
wire [31:0] VAR44, VAR76, VAR40, VAR77, VAR39, VAR6, VAR27, VAR... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v | 8,261 | module MODULE1
(input VAR51, input VAR23,
input [4:0] VAR32,
input [15:0] VAR58,
output reg [15:0] VAR14,
input [1:0] VAR25,
input VAR38, input VAR54, input VAR29,
output reg VAR9, output VAR68, output reg VAR26,
output [15:0] VAR17, output VAR46, output VAR36, input VAR7);
reg [15:0] VAR47; reg [VAR43-1:0] VAR24; reg ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31a/sky130_fd_sc_ls__o31a.functional.pp.v | 2,015 | module MODULE1 (
VAR14 ,
VAR13 ,
VAR2 ,
VAR6 ,
VAR16 ,
VAR5,
VAR4,
VAR17 ,
VAR10
);
output VAR14 ;
input VAR13 ;
input VAR2 ;
input VAR6 ;
input VAR16 ;
input VAR5;
input VAR4;
input VAR17 ;
input VAR10 ;
wire VAR1 ;
wire VAR12 ;
wire VAR15;
or VAR3 (VAR1 , VAR2, VAR13, VAR6 );
and VAR7 (VAR12 , VAR1, VAR16 );
VAR11 VA... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/enet_if/v6_emac_v2_2_fifo_block.v | 14,000 | module MODULE1 (
input VAR40,
output VAR21,
output VAR23,
output [27:0] VAR41,
output VAR30,
input VAR3,
input VAR14,
output [7:0] VAR6,
output VAR35,
input VAR26,
output VAR7,
output VAR45,
output VAR28,
input [7:0] VAR18,
output [31:0] VAR43,
output VAR44,
input VAR36,
input VAR29,
input [7:0] VAR4,
input VAR24,
outp... | mit |
sh-chris110/chris | FPGA/chris.system_ok/db/ip/soc_design/submodules/soc_design_SRAM.v | 2,841 | module MODULE1 (
address,
VAR29,
VAR4,
clk,
VAR20,
reset,
VAR3,
write,
VAR16,
VAR25
)
;
parameter VAR34 = "MODULE1.VAR26";
output [ 31: 0] VAR25;
input [ 13: 0] address;
input [ 3: 0] VAR29;
input VAR4;
input clk;
input VAR20;
input reset;
input VAR3;
input write;
input [ 31: 0] VAR16;
wire VAR9;
wire [ 31: 0] VAR25;
w... | gpl-2.0 |
jplevyak/ifa | prelude.v | 5,243 | in VAR34 MODULE1 "VAR34";
type VAR28 MODULE1 "VAR28";
type VAR27 MODULE1 "VAR27";
type module MODULE1 "module";
type VAR10 MODULE1 "VAR10";
type VAR26 MODULE1 "VAR26";
type function MODULE1 "function";
type VAR2 MODULE1 "VAR2";
type VAR40 MODULE1 "VAR40";
type VAR55 MODULE1 "VAR55";
type VAR43 MODULE1 "VAR43";
type VAR... | mit |
balangs/eTeak | runtime/verilog/example.v | 4,022 | module MODULE16 (VAR16, VAR12, VAR24);
output VAR16;
input VAR12, VAR24;
and #(VAR18,VAR18) (VAR16, VAR12, VAR24);
endmodule
module MODULE10 (VAR16, VAR12, VAR24, VAR7);
output VAR16;
input VAR12, VAR24, VAR7;
and #(VAR18,VAR18) (VAR16, VAR12, VAR24, VAR7);
endmodule
module MODULE2 (VAR16, VAR12, VAR24);
output VAR16;
... | bsd-3-clause |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Cache/Bus_Arbiter/Bus_Arbiter.v | 3,197 | module MODULE1(
input VAR11,
input VAR5,
input VAR18,
input VAR1,
input [29:0] VAR12,
input [4095:0] VAR7,
output reg VAR22,
output reg [4095:0] VAR8,
input VAR6,
input VAR14,
input [29:0] VAR20,
input [4095:0] VAR19,
output reg VAR4,
output reg[4095:0] VAR17,
output reg VAR9,
output reg VAR3,
output reg [29:0] VAR2,
o... | lgpl-3.0 |
dhesant/elec4320 | Lab1A/src/control_LED.v | 1,130 | module MODULE1
( input [7:0] VAR4,
output [7:0] VAR2
);
wire [2:0] VAR1;
reg[7:0] VAR3;
assign VAR1 = VAR4[2:0];
assign VAR2 = VAR3;
always@*
case (VAR1)
3'b000 : VAR3 <= 8'b00000001;
3'b001 : VAR3 <= 8'b00000010;
3'b010 : VAR3 <= 8'b00000100;
3'b011 : VAR3 <= 8'b00001000;
3'b100 : VAR3 <= 8'b00010000;
3'b101 : VAR3 <=... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/ip_top/infrastructure.v | 13,841 | module MODULE1 #
(
parameter VAR27 = 100, parameter VAR30 = 3000, parameter VAR15 = 2, parameter VAR7 = "VAR20", parameter VAR23 = "VAR10", parameter VAR2 = 2, parameter VAR5 = 1, parameter VAR1 = 2, parameter VAR9 = 1
)
(
input VAR28, input VAR4, input VAR17, output VAR16, output clk, output VAR8, output VAR13, input ... | lgpl-3.0 |
VCTLabs/DE1_SOC_Linux_FB | ip/TERASIC_AUDIO/AUDIO_DAC.v | 3,826 | module MODULE1(
clk,
reset,
write,
VAR9,
VAR20,
VAR3,
VAR22,
VAR8,
VAR23
);
parameter VAR13 = 32;
input clk;
input reset;
input write;
input [(VAR13-1):0] VAR9;
output VAR20;
input VAR3;
input VAR22;
input VAR8;
output VAR23;
reg VAR7;
reg VAR24;
reg [4:0] VAR27; reg VAR26;
reg [(VAR13-1):0] VAR28;
reg [(VAR13-1):0] VA... | epl-1.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_2.behavioral.v | 2,510 | module MODULE1( VAR4, VAR2, VAR6, VAR7 );
input VAR2, VAR4, VAR6;
output VAR7;
VAR1 VAR3(.VAR4(VAR4),.VAR2(VAR2),.VAR6(VAR6),.VAR7(VAR7));
VAR1 VAR5(.VAR4(VAR4),.VAR2(VAR2),.VAR6(VAR6),.VAR7(VAR7)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4bb/sky130_fd_sc_lp__nand4bb.behavioral.v | 1,532 | module MODULE1 (
VAR2 ,
VAR1,
VAR10,
VAR14 ,
VAR4
);
output VAR2 ;
input VAR1;
input VAR10;
input VAR14 ;
input VAR4 ;
supply1 VAR9;
supply0 VAR8;
supply1 VAR11 ;
supply0 VAR13 ;
wire VAR12;
wire VAR6;
nand VAR3 (VAR12, VAR4, VAR14 );
or VAR7 (VAR6, VAR10, VAR1, VAR12);
buf VAR5 (VAR2 , VAR6 );
endmodule | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/temperature/temp_sense.v | 6,301 | module MODULE2
(
VAR12,
clk,
VAR4,
VAR5,
VAR6) ;
input VAR12;
input clk;
input VAR4;
output VAR5;
output [7:0] VAR6;
tri1 VAR12;
tri0 VAR4;
wire VAR7;
wire [7:0] VAR13;
VAR2 VAR1
(
.VAR12(VAR12),
.clk(clk),
.VAR4(VAR4),
.VAR5(VAR7),
.VAR6(VAR13));
VAR1.VAR9 = "true",
VAR1.VAR8 = 80,
VAR1.VAR14 = 0,
VAR1.VAR15 = "VAR2"... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4bb/sky130_fd_sc_ls__nand4bb.functional.v | 1,436 | module MODULE1 (
VAR5 ,
VAR7,
VAR9,
VAR4 ,
VAR8
);
output VAR5 ;
input VAR7;
input VAR9;
input VAR4 ;
input VAR8 ;
wire VAR10;
wire VAR2;
nand VAR3 (VAR10, VAR8, VAR4 );
or VAR6 (VAR2, VAR9, VAR7, VAR10);
buf VAR1 (VAR5 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor2/sky130_fd_sc_ls__xnor2.functional.pp.v | 1,827 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR13 ,
VAR11,
VAR8,
VAR3 ,
VAR9
);
output VAR5 ;
input VAR7 ;
input VAR13 ;
input VAR11;
input VAR8;
input VAR3 ;
input VAR9 ;
wire VAR1 ;
wire VAR12;
xnor VAR10 (VAR1 , VAR7, VAR13 );
VAR6 VAR2 (VAR12, VAR1, VAR11, VAR8);
buf VAR4 (VAR5 , VAR12 );
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | fpga/src/stubs/hdl/fifo_async_104x32.v | 1,697 | module MODULE1(rst, VAR5, VAR4, din, VAR7, VAR2, dout, VAR1, VAR3, VAR6)
;
input rst;
input VAR5;
input VAR4;
input [103:0]din;
input VAR7;
input VAR2;
output [103:0]dout;
output VAR1;
output VAR3;
output VAR6;
assign VAR3 =1'b0;
assign VAR6 =1'b0;
assign dout[103:0] =104'b0;
assign VAR1 =1'b0;
endmodule | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_4.behavioral.pp.v | 1,333 | module MODULE1( VAR5, VAR3, VAR1, VAR9, VAR8, VAR7 );
input VAR9, VAR5, VAR1;
inout VAR8, VAR7;
output VAR3;
VAR6 VAR4(.VAR5(VAR5),.VAR3(VAR3),.VAR1(VAR1),.VAR9(VAR9),.VAR8(VAR8),.VAR7(VAR7));
VAR6 VAR2(.VAR5(VAR5),.VAR3(VAR3),.VAR1(VAR1),.VAR9(VAR9),.VAR8(VAR8),.VAR7(VAR7)); | apache-2.0 |
alexforencich/xfcp | example/VCU108/fpga_gty/rtl/debounce_switch.v | 2,576 | module MODULE1 #(
parameter VAR5=1, parameter VAR2=3, parameter VAR3=125000 )(
input wire clk,
input wire rst,
input wire [VAR5-1:0] in,
output wire [VAR5-1:0] out
);
reg [23:0] VAR4 = 24'd0;
reg [VAR2-1:0] VAR6[VAR5-1:0];
reg [VAR5-1:0] state;
assign out = state;
integer VAR1;
always @(posedge clk or posedge rst) begi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211o/sky130_fd_sc_ms__a211o.functional.v | 1,443 | module MODULE1 (
VAR8 ,
VAR2,
VAR5,
VAR10,
VAR7
);
output VAR8 ;
input VAR2;
input VAR5;
input VAR10;
input VAR7;
wire VAR1 ;
wire VAR6;
and VAR4 (VAR1 , VAR2, VAR5 );
or VAR3 (VAR6, VAR1, VAR7, VAR10);
buf VAR9 (VAR8 , VAR6 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_4.behavioral.v | 1,802 | module MODULE1( VAR8, VAR7, VAR4, VAR6, VAR3 );
input VAR4, VAR8, VAR6, VAR3;
output VAR7;
VAR1 VAR5(.VAR8(VAR8),.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6),.VAR3(VAR3));
VAR1 VAR2(.VAR8(VAR8),.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6),.VAR3(VAR3)); | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3/ddr3_int_example_top_4.v | 7,205 | module MODULE1 (
VAR30,
VAR62,
VAR59,
VAR14,
VAR33,
VAR32,
VAR43,
VAR45,
VAR38,
VAR48,
VAR72,
VAR57,
VAR54,
VAR29,
VAR22,
VAR17,
VAR71,
VAR5,
VAR2,
VAR12,
VAR42
)
;
output [ 14: 0] VAR59;
output [ 2: 0] VAR14;
output VAR33;
output [ 0: 0] VAR32;
inout [ 0: 0] VAR43;
inout [ 0: 0] VAR45;
output [ 0: 0] VAR38;
output [ 3... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build2/datamem.v | 2,545 | module MODULE1 (VAR4,VAR3,VAR1,clk,VAR2);
output [0:127] VAR4;
input [0:127] VAR3;
input [0:31] VAR1;
input clk;
input [0:1] VAR2;
reg [0:127] VAR4;
reg [127:0] MODULE1 [255:0];
begin
begin
begin
begin
begin
begin | mit |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/pcie_core/source/pcie_core_qpll_drp.v | 20,745 | module MODULE1 #
(
parameter VAR48 = "VAR21", parameter VAR32 = "3.0", parameter VAR44 = "VAR8", parameter VAR69 = 0, parameter VAR76 = 2'd3, parameter VAR1 = 3'd6
)
(
input VAR42,
input VAR58,
input VAR4,
input VAR59,
input VAR7,
input VAR15,
input [15:0] VAR20,
input VAR23,
output [ 7:0] VAR25,
output VAR38,
output [... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_4.behavioral.v | 1,410 | module MODULE1( VAR2, VAR6, VAR3 );
input VAR6, VAR2;
output VAR3;
VAR4 VAR5(.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3));
VAR4 VAR1(.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3)); | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/system/main_mem.v | 7,935 | module MODULE1#(
parameter VAR31 = 32,
parameter VAR17 = 4
)(
input VAR10,
input VAR33, input [31:0] VAR35,
input [VAR17-1:0] VAR14,
input VAR28,
output [VAR31-1:0] VAR34,
input [VAR31-1:0] VAR12,
input VAR39,
input VAR29,
output VAR21,
output VAR38
);
reg [127:0] VAR11 [2**(VAR16-2)-1:0];
wire VAR8;
wire VAR4;
reg VAR... | lgpl-3.0 |
xuefei1/ElectronicEngineControl | niosII_system/synthesis/submodules/niosII_system_buttons.v | 5,456 | module MODULE1 (
address,
VAR8,
clk,
VAR5,
VAR11,
VAR2,
VAR3,
irq,
VAR13
)
;
output irq;
output [ 31: 0] VAR13;
input [ 1: 0] address;
input VAR8;
input clk;
input [ 7: 0] VAR5;
input VAR11;
input VAR2;
input [ 31: 0] VAR3;
wire VAR9;
reg [ 7: 0] VAR15;
reg [ 7: 0] VAR12;
wire [ 7: 0] VAR10;
reg [ 7: 0] VAR14;
wire VAR... | apache-2.0 |
cpulabs/mist1032sa | src/core/execute/old_execute/adder.v | 3,854 | module MODULE1
parameter VAR2 = 32
)(
input [VAR2-1:0] VAR13,
input [VAR2-1:0] VAR6,
input [4:0] VAR14,
output [VAR2-1:0] VAR16,
output VAR4,
output VAR12,
output VAR3,
output VAR5,
output VAR7
);
assign {VAR7, VAR5, VAR12, VAR4, VAR3, VAR16} = VAR9(VAR14, VAR13, VAR6);
function [36:0] VAR9;
input [4:0] VAR8;
input [31... | bsd-2-clause |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/NTNU FPU/low-cost-fpu-src/sig_register_file.v | 3,018 | module MODULE1(VAR13, VAR1, VAR22, VAR3, VAR17, VAR21,
VAR20,
VAR2, VAR10, VAR19, VAR12);
parameter VAR14 = 'd32;
parameter VAR9 = 32'd0; parameter VAR6 = 32'd1; parameter VAR11 = 32'd2; parameter VAR4 = 32'd128; parameter VAR8 = 32'd127; parameter VAR16 = 32'd5; parameter VAR23 = 32'd6; parameter VAR15 = 32'h20000000;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21bo/sky130_fd_sc_ls__a21bo.pp.symbol.v | 1,385 | module MODULE1 (
input VAR6 ,
input VAR7 ,
input VAR3,
output VAR2 ,
input VAR8 ,
input VAR1,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
google/myelin-acorn-electron-hardware | bga_in_two_layers/10m04_cpu_socket/internal_flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v | 5,567 | module MODULE1 (
VAR18,
VAR9,
VAR1,
VAR11,
VAR19,
VAR5,
VAR17,
VAR15,
VAR3
);
parameter VAR20 = 32;
localparam [1:0] VAR2 = 0,
VAR30 = 1,
VAR22 = 2;
localparam [1:0] VAR16 = 0,
VAR23 = 1,
VAR27 = 2,
VAR21 = 3;
input VAR18;
input VAR9;
input VAR1;
input VAR11;
input VAR19;
input [VAR20-1:0] VAR5;
output [VAR20-1:0] VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfrtp/sky130_fd_sc_hdll__dfrtp_4.v | 2,345 | module MODULE2 (
VAR8 ,
VAR9 ,
VAR7 ,
VAR2,
VAR10 ,
VAR1 ,
VAR5 ,
VAR4
);
output VAR8 ;
input VAR9 ;
input VAR7 ;
input VAR2;
input VAR10 ;
input VAR1 ;
input VAR5 ;
input VAR4 ;
VAR6 VAR3 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODU... | apache-2.0 |
asicguy/gplgpu | hdl/hbi/hbi_wcregs.v | 11,199 | module MODULE1
(
input VAR56, input VAR18, input VAR39, input [31:0] VAR52, input [3:0] VAR10, input [3:0] VAR34, input VAR22, input VAR42, input VAR20, input VAR50, input VAR33, input VAR46, input [2:0] VAR8, input VAR36,
input VAR14,
input [1:0] VAR31,
input select,
output [127:0] VAR35, output reg [15:0] VAR32, outp... | gpl-3.0 |
e33b1711/rfnoc_pp_channelizer | sysgen_models/channelizer/checkpoint256/sysgen/channelizer_256_entity_declarations.v | 326,406 | module MODULE1 (
output [(8 - 1):0] VAR3,
input clk,
input VAR6,
input VAR4);
assign VAR3 = 8'b00000001;
endmodule
module MODULE2 (
input [(1 - 1):0] VAR2,
output [(1 - 1):0] VAR3,
input clk,
input VAR6,
input VAR4);
wire VAR5;
reg VAR1[0:(1 - 1)];
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin... | gpl-3.0 |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_xbar_0/synth/zynq_1_xbar_0.v | 22,150 | module MODULE1 (
VAR7,
VAR108,
VAR28,
VAR118,
VAR43,
VAR59,
VAR16,
VAR70,
VAR111,
VAR69,
VAR104,
VAR96,
VAR15,
VAR76,
VAR119,
VAR2,
VAR130,
VAR34,
VAR41,
VAR116,
VAR68,
VAR3,
VAR107,
VAR51,
VAR103,
VAR8,
VAR66,
VAR39,
VAR88,
VAR55,
VAR11,
VAR98,
VAR80,
VAR106,
VAR38,
VAR90,
VAR35,
VAR112,
VAR114,
VAR79,
VAR97,
VAR62,
V... | mit |
monotone-RK/FACE | IEICE-Trans/4-way_2-tree/src/ip_dram/phy/mig_7series_v2_3_ddr_byte_lane.v | 28,186 | module MODULE1 #(
parameter VAR183 = "VAR104", parameter VAR349 = "VAR88",
parameter VAR207 = 12'b111111111111,
parameter VAR44 = 12'b111111111111,
parameter VAR58 = 24'b001000100010001000100010,
parameter VAR82 = "VAR52",
parameter VAR209 = 4,
parameter VAR86 = "VAR88",
parameter VAR213 = 1,
parameter VAR201 = 1,
para... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2_1.v | 2,164 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR4,
VAR3,
VAR2 ,
VAR5
);
output VAR1 ;
input VAR7 ;
input VAR4;
input VAR3;
input VAR2 ;
input VAR5 ;
VAR8 VAR6 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR1,
VAR7
);
output VAR1;
input VAR7;
supply1 VAR4;
supply0 VAR3;... | apache-2.0 |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_abot/db/ip/niosii/submodules/niosii_epcs_flash_controller_0.v | 16,590 | module MODULE2 (
VAR88,
clk,
VAR22,
VAR40,
VAR6,
VAR46,
VAR80,
VAR44,
VAR19,
VAR16,
VAR30,
VAR32,
VAR3,
VAR85,
irq,
VAR53
)
;
output VAR19;
output VAR16;
output VAR30;
output [ 15: 0] VAR32;
output VAR3;
output VAR85;
output irq;
output VAR53;
input VAR88;
input clk;
input [ 15: 0] VAR22;
input VAR40;
input [ 2: 0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor2/sky130_fd_sc_hs__xor2.behavioral.v | 1,706 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR2 ,
VAR10,
VAR7
);
output VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR10;
input VAR7;
wire VAR11 ;
wire VAR3;
xor VAR9 (VAR11 , VAR2, VAR1 );
VAR6 VAR8 (VAR3, VAR11, VAR10, VAR7);
buf VAR5 (VAR4 , VAR3 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | rtl/mkAXBLUART.v | 30,982 | module MODULE1(VAR149,
VAR38,
VAR134,
VAR64,
VAR135,
VAR16,
VAR37,
VAR200,
VAR163,
VAR148,
VAR28,
VAR195,
VAR131,
VAR82,
VAR205,
VAR178,
VAR103,
VAR10,
VAR164,
VAR142,
VAR203,
VAR215,
VAR122,
VAR201,
VAR78);
input VAR149;
input VAR38;
input VAR134;
output VAR64;
input [31 : 0] VAR135;
input [2 : 0] VAR16;
input VAR37;
... | lgpl-3.0 |
blackmesalabs/sump2 | deep_sump_hyperram.v | 10,522 | module MODULE1 #
(
parameter VAR47 = 65536,
parameter VAR42 = 16
)
(
input wire reset,
input wire VAR39,
input wire VAR14,
input wire VAR17,
input wire [VAR42-1:0] VAR13,
input wire [63:0] VAR78,
output reg VAR18,
input wire VAR37,
input wire [VAR42-1:0] VAR25,
output reg [63:0] VAR61,
input wire [7:0] VAR63,
output wi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4bb/sky130_fd_sc_hd__nand4bb.behavioral.pp.v | 2,000 | module MODULE1 (
VAR15 ,
VAR12 ,
VAR8 ,
VAR6 ,
VAR9 ,
VAR2,
VAR1,
VAR17 ,
VAR14
);
output VAR15 ;
input VAR12 ;
input VAR8 ;
input VAR6 ;
input VAR9 ;
input VAR2;
input VAR1;
input VAR17 ;
input VAR14 ;
wire VAR10 ;
wire VAR7 ;
wire VAR4;
nand VAR3 (VAR10 , VAR9, VAR6 );
or VAR11 (VAR7 , VAR8, VAR12, VAR10 );
VAR13 VAR... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/bw_clk_gl_vrt_all.v | 7,957 | module MODULE1(VAR19 ,VAR34 ,VAR14 ,VAR26 );
output [1:0] VAR14 ;
output [7:0] VAR26 ;
input [1:0] VAR34 ;
input VAR19 ;
wire [1:0] VAR37 ;
wire [3:0] VAR42 ;
wire [1:0] VAR27 ;
wire [1:0] VAR36 ;
assign VAR42[2] = VAR34[1] ;
assign VAR42[1] = VAR34[0] ;
assign VAR14[1] = VAR36[1] ;
assign VAR14[0] = VAR36[0] ;
VAR43 V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor3/sky130_fd_sc_hs__xor3.functional.pp.v | 1,742 | module MODULE1 (
VAR10 ,
VAR2 ,
VAR12 ,
VAR1 ,
VAR3,
VAR9
);
output VAR10 ;
input VAR2 ;
input VAR12 ;
input VAR1 ;
input VAR3;
input VAR9;
wire VAR11 ;
wire VAR5;
xor VAR8 (VAR11 , VAR2, VAR12, VAR1 );
VAR7 VAR4 (VAR5, VAR11, VAR3, VAR9);
buf VAR6 (VAR10 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2.behavioral.pp.v | 1,867 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR8,
VAR11,
VAR3 ,
VAR10
);
output VAR5 ;
input VAR1 ;
input VAR8;
input VAR11;
input VAR3 ;
input VAR10 ;
wire VAR7 ;
wire VAR2;
not VAR9 (VAR7 , VAR1 );
VAR6 VAR4 (VAR2, VAR7, VAR8, VAR11);
buf VAR12 (VAR5 , VAR2 );
endmodule | apache-2.0 |
dachdecker2/icoboard_ws2812b_display | spi.v | 6,329 | module MODULE1 (
input clk,
input VAR30,
input VAR11,
input VAR12,
input VAR20,
input [7:0] VAR19,
output [7:0] VAR32,
output [0:0] VAR33,
output [0:0] VAR25,
output [0:0] VAR16,
output [7:0] VAR27
);
parameter VAR4 = 0;
parameter VAR14 = 0;
parameter VAR1 = 0;
parameter VAR28 = 0;
parameter VAR21 = 2;
reg [3:0] state ... | gpl-3.0 |
walkthetalk/fsref | ip/mm2s_adv/src/include/asym_ram.v | 1,907 | module MODULE1(VAR4, VAR28, VAR1, VAR8, VAR29, VAR16, VAR19, rd);
parameter VAR26 = 64;
parameter VAR24 = 9;
parameter VAR27 = 8;
parameter VAR13 = 12;
input VAR4;
input VAR1;
input [VAR24-1:0] VAR29;
input [VAR26-1:0] VAR19;
input VAR28;
input VAR8;
input [VAR13-1:0] VAR16;
output [VAR27-1:0] rd;
function integer VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4bb/sky130_fd_sc_ls__or4bb.functional.v | 1,414 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR3 ,
VAR8,
VAR5
);
output VAR4 ;
input VAR9 ;
input VAR3 ;
input VAR8;
input VAR5;
wire VAR7;
wire VAR6;
nand VAR10 (VAR7, VAR5, VAR8 );
or VAR1 (VAR6, VAR3, VAR9, VAR7);
buf VAR2 (VAR4 , VAR6 );
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/settings_bus_16LE.v | 2,050 | module MODULE1
(input VAR12,
input VAR8,
input [VAR10-1:0] VAR4,
input [15:0] VAR6,
input VAR5,
input VAR9,
output reg VAR2,
output VAR11,
output reg [7:0] addr,
output reg [31:0] VAR7);
reg VAR3;
always @(posedge VAR12)
if(VAR8)
begin
VAR3 <= 1'b0;
addr <= 8'd0;
VAR7 <= 32'd0;
end
else if(VAR9 & VAR5)
begin
addr <= VA... | gpl-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_sprs.v | 16,632 | module MODULE1(
clk, rst,
VAR31, VAR54, flag, VAR10, VAR37, VAR22,
VAR61, VAR70, VAR5, VAR20, VAR72,
VAR49, VAR65, VAR17, VAR8,
VAR39, VAR77, VAR47, VAR48, VAR79, VAR50, VAR66, VAR58,
VAR21, VAR82, VAR42, VAR7, VAR25,
VAR29, VAR11, VAR19,
VAR24, VAR28, VAR73,
VAR9, VAR38, VAR3, VAR52,
VAR45, VAR64, VAR30,
VAR1, VAR62
)... | gpl-3.0 |
origintfj/riscv | rv32i/rtl/merlin_cs_regs.v | 81,081 | module MODULE1
parameter VAR216 = 30'h0
)
(
input wire VAR213,
input wire VAR223,
input wire VAR126,
input wire VAR104,
input wire VAR249,
input wire [11:0] VAR75,
output wire VAR170,
output wire VAR259,
output wire VAR105,
output reg [VAR210-1:0] VAR111,
input wire VAR164, input wire [1:0] VAR39,
input wire [11:0] VAR... | apache-2.0 |
euryecetelecom/euryspace | hw/rtl/euryspace_soc/rtl/verilog/clkgen.v | 3,765 | module MODULE1
(
input VAR3,
input VAR11,
output VAR6,
output VAR8,
output VAR17,
output VAR4,
input VAR12,
output VAR20,
output VAR1,
output VAR24
);
wire VAR15;
wire VAR23;
assign VAR23 = VAR11;
assign VAR15 = ~VAR23;
assign VAR6 = ~VAR23;
assign VAR20 = VAR12;
wire VAR9;
wire VAR14;
VAR19 VAR16
(
.VAR22 (VAR15),
.VA... | mit |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/MySource/MIG_4Ports.v | 25,397 | module MODULE1 #(
parameter VAR93 = 64, parameter VAR141 = 3, parameter VAR162 = 2, parameter VAR64 = 2, parameter VAR72 = 1, parameter VAR161 = 2, parameter VAR49 = 8, parameter VAR148 = 64, parameter VAR139 = 8,
parameter VAR120 = 2, parameter VAR140 = 15, parameter VAR90 = 29,
parameter VAR61 = 64,
parameter VAR179 ... | gpl-2.0 |
leekeith/DEVBOX | Dev_Box_HW/HPS_LED_HEX.v | 17,578 | module MODULE1(
output VAR154,
output VAR180,
input VAR55,
output VAR156,
input VAR56,
inout VAR124,
inout VAR196,
output VAR111,
inout VAR153,
output VAR110,
input VAR21,
input VAR89,
input VAR161,
input VAR169,
output [12:0] VAR133,
output [1:0] VAR140,
output VAR148,
output VAR165,
output VAR211,
output VAR102,
inou... | gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_qmem_top.v | 21,664 | module MODULE1(
clk, rst,
VAR1, VAR43, VAR84,
VAR72,
VAR98,
VAR36,
VAR23,
VAR9,
VAR93,
VAR12,
VAR82,
VAR41,
VAR89,
VAR68,
VAR35,
VAR33,
VAR5,
VAR13,
VAR52,
VAR53,
VAR14,
VAR26,
VAR92,
VAR42,
VAR51,
VAR19,
VAR62,
VAR69,
VAR24,
VAR37,
VAR10,
VAR21,
VAR58,
VAR45,
VAR27,
VAR86, VAR48, VAR76,
VAR11, VAR91, VAR85, VAR83,
VAR... | gpl-2.0 |
mbus/mbus | layer_controller_v1/verilog/rf_ctrl.v | 1,857 | module MODULE2( VAR2, VAR10, VAR6, VAR13);
parameter VAR7 = 64; parameter VAR3 =24;
input VAR2;
input [VAR3-1:0] VAR10;
input [VAR7-1:0] VAR6;
output [VAR3*VAR7-1:0] VAR13;
reg [VAR3-1:0] VAR1 [0:VAR7-1];
genvar VAR12;
generate
for (VAR12=0; VAR12<(VAR7); VAR12=VAR12+1)
begin: VAR5
assign VAR13[VAR3*(VAR12+1)-1:VAR3*VA... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/yf32/alu.v | 6,266 | module MODULE1 (VAR13, VAR4, VAR23, VAR26);
input [31:0] VAR13 ;
input [31:0] VAR4 ;
input [ 3:0] VAR23;
output [31:0] VAR26 ;
wire [32:0] VAR28 ;
wire [32:0] VAR11 ;
wire [32:0] sum ;
wire VAR34 ;
wire VAR35;
assign VAR34 = (VAR23 == VAR16 ) ? 1'b1 : 1'b0 ;
assign VAR35 = (VAR23 == VAR21) ? 1'b0 : 1'b1 ;
assign VAR28 ... | mit |
scalable-networks/ext | uhd/fpga/usrp2/fifo/crossbar36.v | 1,954 | module MODULE1
(input clk, input reset, input VAR3,
input cross,
input [35:0] VAR2, input VAR11, output VAR18,
input [35:0] VAR8, input VAR17, output VAR14,
output [35:0] VAR4, output VAR7, input VAR5,
output [35:0] VAR1, output VAR10, input VAR12);
reg VAR6, VAR16, VAR13;
wire VAR9 = (VAR11 & VAR18)? ~VAR2[33] : VAR16... | gpl-2.0 |
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