repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
aospan/NetUP_Dual_Universal_CI-fpga | ip_compiler_for_pci_express-library/altpcie_pll_125_250.v | 10,257 | module MODULE1 (
VAR32,
VAR14,
VAR48);
input VAR32;
input VAR14;
output VAR48;
wire [5:0] VAR4;
wire [0:0] VAR5 = 1'h0;
wire [0:0] VAR51 = 1'h1;
wire [0:0] VAR15 = VAR4[0:0];
wire VAR48 = VAR15;
wire [5:0] VAR10 = {VAR5, VAR5, VAR5, VAR5, VAR5, VAR51};
wire VAR22 = VAR14;
wire [1:0] VAR34 = {VAR5, VAR22};
wire [3:0] VA... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_2.behavioral.pp.v | 3,700 | module MODULE1( VAR1, VAR13, VAR23, VAR18, VAR33, VAR31 );
input VAR1, VAR13, VAR23;
inout VAR33, VAR31;
output VAR18;
reg VAR17;
VAR19 VAR15(.VAR1(VAR1),.VAR13(VAR13),.VAR23(VAR23),.VAR18(VAR18),.VAR33(VAR33),.VAR31(VAR31),.VAR17(VAR17));
VAR19 VAR2(.VAR1(VAR1),.VAR13(VAR13),.VAR23(VAR23),.VAR18(VAR18),.VAR33(VAR33),.... | apache-2.0 |
ptracton/wb_soc_template | rtl/wb_ram/rtl/verilog/wb_rom.v | 2,641 | module MODULE1
parameter VAR12 = 256,
parameter VAR15 = VAR20(VAR12),
parameter VAR22 = "")
(input VAR26,
input VAR4,
input [VAR15-1:0] VAR19,
input [VAR6-1:0] VAR21,
input [3:0] VAR14,
input [1:0] VAR2,
input [2:0] VAR10,
input VAR7,
input VAR8,
output reg VAR17,
output VAR5,
output [VAR6-1:0] VAR3);
reg [VAR15-1:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311ai/sky130_fd_sc_ls__o311ai_1.v | 2,435 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR2 ,
VAR9 ,
VAR12 ,
VAR5 ,
VAR1,
VAR11,
VAR3 ,
VAR10
);
output VAR4 ;
input VAR6 ;
input VAR2 ;
input VAR9 ;
input VAR12 ;
input VAR5 ;
input VAR1;
input VAR11;
input VAR3 ;
input VAR10 ;
VAR8 VAR7 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR1(V... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ksgen_verilog/hdl/ks26.v | 26,795 | module MODULE1(VAR198, VAR210, VAR222);
input wire [0:25] VAR198;
input wire [0:25] VAR210;
output wire [0:50] VAR222;
wire VAR156, VAR273, VAR202, VAR114, VAR88, VAR81, VAR15, VAR232, VAR127, VAR244, VAR230, VAR343, VAR32, VAR246, VAR117, VAR96, VAR157, VAR183, VAR92, VAR291, VAR239, VAR17, VAR243, VAR35, VAR42, VAR28... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211ai/sky130_fd_sc_hd__o211ai_2.v | 2,361 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR3 ,
VAR8 ,
VAR9 ,
VAR5,
VAR4,
VAR2 ,
VAR6
);
output VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR8 ;
input VAR9 ;
input VAR5;
input VAR4;
input VAR2 ;
input VAR6 ;
VAR10 VAR11 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(V... | apache-2.0 |
gbraad/minimig-de1 | rtl/ctrl/qmem_arbiter.v | 2,945 | module MODULE1 #(
parameter VAR14 = 32, parameter VAR16 = 32, parameter VAR25 = VAR16/8, parameter VAR5 = 2 )(
input wire clk,
input wire rst,
input wire [VAR5 -1:0] VAR20,
input wire [VAR5 -1:0] VAR19,
input wire [VAR5*VAR25-1:0] VAR18,
input wire [VAR5*VAR14-1:0] VAR6,
input wire [VAR5*VAR16-1:0] VAR23,
output wire [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fahcin/sky130_fd_sc_lp__fahcin_1.v | 2,337 | module MODULE2 (
VAR8,
VAR9 ,
VAR3 ,
VAR6 ,
VAR4 ,
VAR2,
VAR7,
VAR1 ,
VAR5
);
output VAR8;
output VAR9 ;
input VAR3 ;
input VAR6 ;
input VAR4 ;
input VAR2;
input VAR7;
input VAR1 ;
input VAR5 ;
VAR11 VAR10 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VA... | apache-2.0 |
lkesteloot/alice | alice4/fpga/Alice4-DE0-Nano-SoC/soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v | 4,028 | module MODULE1
(
VAR32,
VAR21,
VAR35) ;
input [0:0] VAR32;
output [0:0] VAR21;
output [0:0] VAR35;
wire [0:0] VAR26;
wire [0:0] VAR7;
wire [0:0] VAR16;
wire [0:0] VAR33;
wire [0:0] VAR23;
wire [0:0] VAR15;
wire [0:0] VAR9;
wire [0:0] VAR5;
wire [0:0] VAR27;
wire [0:0] VAR1;
VAR30 VAR20
(
.VAR17(VAR15),
.VAR14(VAR26[0:0... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22ai/sky130_fd_sc_lp__o22ai.behavioral.v | 1,615 | module MODULE1 (
VAR8 ,
VAR14,
VAR11,
VAR7,
VAR6
);
output VAR8 ;
input VAR14;
input VAR11;
input VAR7;
input VAR6;
supply1 VAR10;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR15 ;
wire VAR1 ;
wire VAR3 ;
wire VAR13;
nor VAR16 (VAR1 , VAR7, VAR6 );
nor VAR9 (VAR3 , VAR14, VAR11 );
or VAR12 (VAR13, VAR3, VAR1);
buf VAR5 (VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_p_pp_pkg_s/sky130_fd_sc_hs__udp_dff_p_pp_pkg_s.symbol.v | 1,434 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR5 ,
input VAR4,
input VAR1 ,
input VAR7 ,
input VAR6
);
endmodule | apache-2.0 |
jmacneal/Design-Project | Display/DE2_Default.v | 16,170 | module MODULE1
(
VAR144, VAR88, VAR89, VAR48, VAR36, VAR65, VAR80, VAR71, VAR110, VAR34, VAR64, VAR30, VAR78, VAR123, VAR103, VAR60, VAR131, VAR67, VAR143, VAR128, VAR82, VAR98, VAR43, VAR134, VAR85, VAR104, VAR109, VAR127, VAR74, VAR42, VAR114, VAR51, VAR17, VAR149, VAR111, VAR115, VAR24, VAR93, VAR52, VAR118, VAR135,... | gpl-3.0 |
glennchid/font5-firmware | src/verilog/synthesis/ampDrive.v | 9,063 | module MODULE1 (
input clk,
input VAR21,
input VAR40,
input VAR10, input [4:0] VAR11,
input signed [12:0] VAR1,
input signed [15:0] din,
input VAR6,
input signed [6:0] VAR12,
output reg VAR4 = 1'b0,
output reg signed [12:0] dout = 13'd0, output reg VAR15 = 1'b0 );
parameter VAR30 = 4'd8;
reg signed [15:0] VAR19 = 16'VA... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_async/bsg_launch_sync_sync.v | 17,378 | \
module MODULE2 \
(input VAR23 \
, input VAR4 \
, input VAR26 \
, input [VAR33-1:0] VAR7 \
, output [VAR33-1:0] VAR5 \
, output [VAR33-1:0] VAR8 \
); \
\
\
logic [VAR33-1:0] VAR17; \
assign VAR5 = VAR17; \
\
VAR29 @(VAR1 VAR23) \
begin \
\
if (VAR4) \
VAR17 <= {VAR33{1'b0}}; \
end
else \
VAR17 <= VAR7; \
end \
\
logic... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2.pp.blackbox.v | 1,291 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR3,
VAR2
);
output VAR4 ;
input VAR1 ;
input VAR3;
input VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31ai/sky130_fd_sc_hd__o31ai.functional.pp.v | 2,027 | module MODULE1 (
VAR8 ,
VAR12 ,
VAR14 ,
VAR15 ,
VAR1 ,
VAR16,
VAR2,
VAR10 ,
VAR6
);
output VAR8 ;
input VAR12 ;
input VAR14 ;
input VAR15 ;
input VAR1 ;
input VAR16;
input VAR2;
input VAR10 ;
input VAR6 ;
wire VAR5 ;
wire VAR3 ;
wire VAR9;
or VAR7 (VAR5 , VAR14, VAR12, VAR15 );
nand VAR11 (VAR3 , VAR1, VAR5 );
VAR17 VA... | apache-2.0 |
Pylonight/MIPS-CPU | cpu/Register_Group.v | 1,130 | module MODULE1(
output [15 : 0] VAR3,
output [15 : 0] VAR2,
input write,
input [3 : 0] address,
input [7 : 0] VAR4,
input [15 : 0] VAR1
);
reg [15 : 0] register [15 : 0];
begin
begin | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/mod.v | 10,809 | module MODULE1(VAR1, VAR2);
input wire [464:0] VAR1;
output wire [232:0] VAR2;
assign VAR2[0] = VAR1[0] ^ VAR1[233] ^ VAR1[392];
assign VAR2[1] = VAR1[1] ^ VAR1[234] ^ VAR1[393];
assign VAR2[2] = VAR1[2] ^ VAR1[235] ^ VAR1[394];
assign VAR2[3] = VAR1[3] ^ VAR1[236] ^ VAR1[395];
assign VAR2[4] = VAR1[4] ^ VAR1[237] ^ VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o.blackbox.v | 1,462 | module MODULE1 (
VAR5 ,
VAR3,
VAR2,
VAR8 ,
VAR4
);
output VAR5 ;
input VAR3;
input VAR2;
input VAR8 ;
input VAR4 ;
supply1 VAR9;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4/sky130_fd_sc_hs__and4_2.v | 2,115 | module MODULE2 (
VAR7 ,
VAR2 ,
VAR1 ,
VAR5 ,
VAR4 ,
VAR9,
VAR6
);
output VAR7 ;
input VAR2 ;
input VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR9;
input VAR6;
VAR8 VAR3 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR7,
VAR2,
VAR1,
VAR5,
VAR4
);
... | apache-2.0 |
Kipsora/MIPS-CPU | source/machine/cpu/stages/ex-mem-buffer.v | 4,389 | module MODULE1(
input wire VAR7,
input wire reset,
input wire[VAR30] VAR16,
input wire VAR31,
input wire[VAR8] VAR19,
input wire[VAR21] VAR9,
input wire VAR27,
input wire[VAR21] VAR29,
input wire[VAR21] VAR13,
input wire[VAR12] VAR11,
input wire[VAR14] VAR17,
input wire[VAR20] VAR23,
input wire[VAR21] VAR2,
input wire[... | mit |
chriswynnyk/american-put-verilog | american_put_cyclone/src/mem_1k.v | 9,450 | module MODULE1 (
VAR12,
VAR42,
VAR13,
VAR48,
VAR17,
VAR7,
VAR49);
input [63:0] VAR12;
input [9:0] VAR42;
input VAR13;
input [9:0] VAR48;
input VAR17;
input VAR7;
output [63:0] VAR49;
wire [63:0] VAR18;
wire [63:0] VAR49 = VAR18[63:0];
VAR40 VAR24 (
.VAR8 (VAR7),
.VAR36 (VAR17),
.VAR22 (VAR13),
.VAR37 (VAR48),
.VAR15 (V... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/phy/phy_write.v | 86,909 | module MODULE1 #
(
parameter VAR5 = 100,
parameter VAR85 = "VAR8",
parameter VAR88 = "VAR16",
parameter VAR59 = 64,
parameter VAR89 = 8,
parameter VAR17 = 5,
parameter VAR87 = "VAR93",
parameter VAR50 = 1,
parameter VAR84 = "VAR93"
)
(
input clk,
input rst,
input VAR26,
input VAR63,
input VAR83,
input [VAR89-1:0] VAR36... | lgpl-3.0 |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v | 15,181 | module MODULE1 #
( parameter
VAR52 = 40,
VAR12 = 8,
VAR18 = 1,
VAR9 = 0,
VAR55 = 0,
VAR8 = 7,
VAR4 = 7,
VAR17 = 1
)
(
VAR19,
VAR23,
VAR38,
VAR3,
VAR43,
VAR1,
VAR51,
VAR50,
VAR21,
VAR30,
VAR2,
VAR53,
VAR26,
VAR35
);
localparam VAR10 = (VAR52 > 8) ? (VAR52 - VAR12) : (VAR52);
input VAR19;
input VAR23;
input [VAR8 - 1 : 0... | gpl-3.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/db/ip/SOC/submodules/SoC_NIOS_mult_cell.v | 6,245 | module MODULE1 (
VAR37,
VAR33,
clk,
VAR9,
VAR34
)
;
output [ 31: 0] VAR34;
input [ 31: 0] VAR37;
input [ 31: 0] VAR33;
input clk;
input VAR9;
wire [ 31: 0] VAR34;
wire [ 31: 0] VAR54;
wire [ 15: 0] VAR44;
wire VAR6;
assign VAR6 = ~VAR9;
VAR17 VAR36
(
.VAR31 (VAR6),
.VAR10 (clk),
.VAR35 (VAR37[15 : 0]),
.VAR7 (VAR33[15 ... | gpl-2.0 |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/db/ip/tracking_camera_system/submodules/tracking_camera_system_green_leds.v | 2,370 | module MODULE1 (
address,
VAR9,
clk,
VAR6,
VAR8,
VAR7,
VAR3,
VAR1
)
;
output [ 7: 0] VAR3;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input VAR9;
input clk;
input VAR6;
input VAR8;
input [ 31: 0] VAR7;
wire VAR5;
reg [ 7: 0] VAR2;
wire [ 7: 0] VAR3;
wire [ 7: 0] VAR4;
wire [ 31: 0] VAR1;
assign VAR5 = 1;
assign VAR4 ... | gpl-2.0 |
asicguy/gplgpu | hdl/mc_graph/mc_de.v | 6,830 | module MODULE1
(
input VAR23,
input VAR17,
input VAR20,
input VAR33,
input VAR16,
input VAR27,
input [3:0] VAR6,
input [31:0] VAR34,
input VAR12,
input VAR28,
input VAR4,
output reg VAR15,
output VAR30,
output reg VAR5,
output reg VAR7,
output reg VAR10,
output reg [1:0] VAR9, output reg [31:0] VAR29,
output reg VAR1, ... | gpl-3.0 |
horia141/bachelor-thesis | prj/applications/PressCount/PressCountFPGA.v | 1,081 | module MODULE1(VAR10,reset,VAR16,VAR14,VAR7,VAR1,VAR13,VAR15,VAR12,VAR18);
input wire VAR10;
input wire reset;
input wire VAR16;
input wire VAR14;
output wire [7:0] VAR7;
output wire VAR1;
output wire VAR13;
output wire VAR15;
output wire VAR12;
output wire VAR18;
wire VAR11;
wire VAR6;
wire VAR8;
VAR19
VAR2 (.VAR10(VA... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_16b_es_v1_00_a/hdl/verilog/cf_h2v_vdma.v | 13,673 | module MODULE1 (
VAR8,
VAR83, VAR55,
VAR51,
VAR46,
VAR79,
VAR13, VAR5,
VAR78,
VAR65,
VAR22,
VAR77,
VAR44,
VAR12,
VAR24,
VAR20,
VAR64,
VAR74,
VAR31,
VAR4,
VAR28,
VAR53,
VAR75);
input VAR8;
input VAR83;
input [ 8:0] VAR55;
input VAR51;
input [ 8:0] VAR46;
input [48:0] VAR79;
input VAR13;
input [ 8:0] VAR5;
input [ 8:0] V... | mit |
rurume/openrisc_vision_hardware | ISE/or1200_spram_64x22.v | 10,826 | module MODULE1(
VAR14, VAR13, VAR5,
clk, rst, VAR21, VAR29, VAR39, addr, VAR24, VAR23
);
parameter VAR10 = 6;
parameter VAR19 = 22;
input VAR14;
input [VAR16 - 1:0] VAR5;
output VAR13;
input clk; input rst; input VAR21; input VAR29; input VAR39; input [VAR10-1:0] addr; input [VAR19-1:0] VAR24; output [VAR19-1:0] VAR23;... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_dac_common.v | 12,763 | module MODULE1 (
VAR15,
VAR37,
VAR28,
VAR5,
VAR54,
VAR68,
VAR25,
VAR32,
VAR14,
VAR72,
VAR62,
VAR43,
VAR4,
VAR35,
VAR38,
VAR47,
VAR20,
VAR67,
VAR87,
VAR3,
VAR49,
VAR48,
VAR52,
VAR77,
VAR51,
VAR42,
VAR13,
VAR60,
VAR34,
VAR39,
VAR81,
VAR9,
VAR86,
VAR64,
VAR36);
localparam VAR2 = 32'h00080062;
parameter VAR73 = 0;
output V... | gpl-3.0 |
YosysHQ/yosys | techlibs/common/cmp2lut.v | 2,540 | module MODULE1(
module 90lutcmp (VAR7, VAR17, VAR20);
parameter VAR11 = 0;
parameter VAR6 = 0;
parameter VAR24 = 0;
parameter VAR12 = 0;
parameter VAR34 = 0;
input [VAR24-1:0] VAR7;
input [VAR12-1:0] VAR17;
output [VAR34-1:0] VAR20;
parameter VAR15 = "";
parameter VAR10 = 0;
parameter VAR27 = 0;
parameter VAR21 = 0;
pa... | isc |
Digilent/vivado-library | ip/video_scaler/hdl/verilog/video_scaler_ctrl_s_axi.v | 11,993 | module MODULE1
VAR47 = 6,
VAR8 = 32
)(
input wire VAR51,
input wire VAR37,
input wire VAR68,
input wire [VAR47-1:0] VAR14,
input wire VAR4,
output wire VAR64,
input wire [VAR8-1:0] VAR17,
input wire [VAR8/8-1:0] VAR6,
input wire VAR61,
output wire VAR55,
output wire [1:0] VAR10,
output wire VAR22,
input wire VAR9,
inpu... | mit |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/gt0000_digital_top.v | 11,417 | module MODULE1(
clk , VAR33 , en , VAR24 , VAR43 , VAR38 , VAR2 );
input clk ; input VAR33 ; input en ; input VAR24 ; input VAR43 ; output [07:00] VAR38 ; output [07:00] VAR2 ;
wire VAR42 ; wire VAR8 ; wire VAR1 ; wire VAR36 ; wire VAR12 ; reg [07:00] VAR17 ; wire [15:00] VAR39 ;
reg [03:00] VAR14 ; reg [03:00] VAR16 ;... | apache-2.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/ddr2/alt_ddrx_avalon_if.v | 13,228 | module MODULE1
VAR45 = 6,
VAR62 = 0,
VAR73 = 28,
VAR82 = 33,
VAR16 = 2,
VAR85 = 64,
VAR77 = 32
)
(
VAR58,
VAR22,
VAR75 ,
VAR25 ,
VAR74,
VAR4,
VAR11,
VAR70,
VAR67,
VAR31,
VAR47,
VAR33,
VAR35,
VAR17,
VAR41,
VAR63,
VAR20,
VAR39,
VAR8,
VAR84,
VAR48,
VAR44,
VAR27,
VAR64,
VAR28,
VAR87,
VAR19,
VAR3,
VAR46,
VAR86
);
localparam... | apache-2.0 |
mcgodfrey/i2c-eeprom | read_eeprom.v | 5,095 | module MODULE1(
input wire clk,
input wire reset,
input wire [6:0] VAR3,
input wire [15:0] VAR11,
input wire [7:0] VAR24,
input wire VAR27,
output reg [7:0] VAR19,
output reg VAR1,
output reg [6:0] VAR28,
output reg VAR14,
output reg [7:0] VAR16,
output reg [7:0] VAR22,
input wire [7:0] VAR2,
input wire VAR23,
input wi... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_2.behavioral.v | 2,148 | module MODULE1( VAR6, VAR5, VAR7 );
input VAR6, VAR5;
output VAR7;
reg VAR9;
VAR2 VAR8(.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7),.VAR9(VAR9));
VAR2 VAR3(.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7),.VAR9(VAR9));
not VAR4(VAR10,VAR5);
buf VAR11(VAR1,VAR5); | apache-2.0 |
Raimmaster/Breakout-FPGA | VGA.v | 3,831 | module MODULE1(
input VAR15,
input VAR27,
output reg [5:0] VAR8,
output reg VAR22,
output reg VAR21,
output [9:0] VAR30,
output [9:0] VAR1,
input [2:0] VAR14,
input [9:0] VAR5,
input [9:0] VAR13,
input [9:0] VAR28,
input reset,
input VAR16,
input [5:0] VAR7,
input [1:0] VAR17
);
parameter
VAR12 = 7,
VAR29 = 10'd40,
VAR... | gpl-3.0 |
cafe-alpha/wasca | v12/fpga_firmware/wasca/synthesis/submodules/wasca_spi_stm32.v | 10,986 | module MODULE1 (
VAR33,
VAR49,
VAR17,
clk,
VAR60,
VAR34,
VAR46,
VAR45,
VAR18,
VAR20,
VAR57,
VAR22,
VAR6,
VAR12,
irq,
VAR54
)
;
output VAR57;
output [ 15: 0] VAR22;
output VAR6;
output VAR12;
output irq;
output VAR54;
input VAR33;
input VAR49;
input VAR17;
input clk;
input [ 15: 0] VAR60;
input [ 2: 0] VAR34;
input VAR4... | gpl-2.0 |
merckhung/zet | cores/zet/rtl/zet_bitlog.v | 1,032 | module MODULE1 (
input [15:0] VAR1,
output [15:0] VAR4,
output VAR2,
output VAR3
);
assign VAR4 = ~VAR1;
assign VAR2 = 1'b0;
assign VAR3 = 1'b0;
endmodule | gpl-3.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_rxcounters.v | 8,707 | module MODULE1 (VAR29, VAR27, VAR31, VAR6, VAR25, VAR36, VAR28, VAR30,
VAR1, VAR18, VAR16, VAR32, VAR26, VAR13, VAR20, VAR35,
VAR21, VAR23, VAR14,VAR7,VAR15,VAR4, VAR8,
VAR33, VAR5, VAR17, VAR10, VAR37
);
parameter VAR11 = 1;
input VAR29;
input VAR27;
input VAR31;
input VAR25;
input [1:0] VAR36;
input VAR1;
input VAR6;... | gpl-2.0 |
Jside/nova1 | nova_alu.v | 3,498 | module MODULE1(
VAR13, VAR6,
VAR25, VAR22, VAR4, VAR21, VAR12);
input VAR13;
input VAR6;
input [0:15] VAR25;
input [0:15] VAR22;
input [0:15] VAR4;
output reg [0:15] VAR21;
output reg VAR12;
wire [0:1] VAR9;
wire [0:2] VAR15;
wire VAR17;
wire [0:2] VAR24;
wire [0:2] VAR5;
assign VAR9 = VAR25[VAR10];
assign VAR15 = VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/mux2/sky130_fd_sc_hvl__mux2.pp.symbol.v | 1,329 | module MODULE1 (
input VAR4 ,
input VAR6 ,
output VAR8 ,
input VAR2 ,
input VAR5 ,
input VAR1,
input VAR3,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3/sky130_fd_sc_hs__or3_2.v | 2,026 | module MODULE2 (
VAR4 ,
VAR1 ,
VAR7 ,
VAR5 ,
VAR2,
VAR8
);
output VAR4 ;
input VAR1 ;
input VAR7 ;
input VAR5 ;
input VAR2;
input VAR8;
VAR6 VAR3 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR4,
VAR1,
VAR7,
VAR5
);
output VAR4;
input VAR1;
input VAR7;
in... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hd__udp_dff_nsr_pp_pg_n.symbol.v | 1,655 | module MODULE1 (
input VAR7 ,
output VAR4 ,
input VAR1 ,
input VAR3 ,
input VAR2 ,
input VAR5,
input VAR6 ,
input VAR8
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill/sky130_fd_sc_ms__fill_1.v | 1,840 | module MODULE2 (
VAR5,
VAR6,
VAR2 ,
VAR3
);
input VAR5;
input VAR6;
input VAR2 ;
input VAR3 ;
VAR4 VAR1 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE2 ();
supply1 VAR5;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR3 ;
VAR4 VAR1 ();
endmodule | apache-2.0 |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/mouse_ps2.v | 2,793 | module MODULE1(
input wire clk, reset,
inout wire VAR17, VAR27,
output wire [9:0] VAR19,
output wire [8:0] VAR26,
output wire [2:0] VAR28,
output reg VAR1
);
localparam VAR8=8'hf4;
localparam [2:0]
VAR25 = 3'b000,
VAR4 = 3'b001,
VAR5 = 3'b010,
VAR16 = 3'b011,
VAR12 = 3'b100,
VAR18 = 3'b101,
VAR22 = 3'b110;
reg [2:0] VA... | mit |
zhaishaomin/ring_network-based-multicore- | communication_assist/FSM_download_flit.v | 7,898 | module MODULE1(
VAR30,
VAR39,
VAR28,
VAR35,
clk,
rst,
VAR25,
VAR37,
VAR9,
VAR3,
VAR52,
VAR40,
VAR17,
VAR24,
VAR45,
VAR36,
VAR31,
VAR48,
VAR53,
VAR42,
VAR33
);
input [17:0] VAR30; input VAR39;
input [17:0] VAR28; input VAR35;
input clk;
input rst;
input VAR25;
output VAR37;
output VAR9;
output VAR3;
output [15:0] VAR52;... | apache-2.0 |
chebykinn/university | circuitry/lab3/src/hdl/ioctrl_wb.v | 1,388 | module MODULE1 #(parameter VAR24 = 32'h00000800) (
input VAR8,
input VAR18,
input [31:0] VAR25,
output reg [31:0] VAR21,
input [31:0] VAR16,
input VAR10,
input [3:0] VAR23,
input VAR22,
input VAR9,
output reg VAR3,
input VAR5,
output VAR1,
output VAR17
);
localparam VAR11 = 0;
localparam VAR15 = 1;
wire VAR6;
wire read... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111ai/sky130_fd_sc_ms__o2111ai.pp.blackbox.v | 1,435 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR3 ,
VAR10 ,
VAR9 ,
VAR7 ,
VAR6,
VAR5,
VAR2 ,
VAR1
);
output VAR4 ;
input VAR8 ;
input VAR3 ;
input VAR10 ;
input VAR9 ;
input VAR7 ;
input VAR6;
input VAR5;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_SEQ_SRAM_TT_210930.v | 73,272 | module MODULE1 (VAR10, VAR12, VAR4, VAR1);
output VAR10;
input VAR12, VAR4, VAR1;
reg VAR7;
wire VAR5, VAR13;
wire VAR11, VAR8, VAR2;
wire VAR14;
not (VAR11, VAR5);
not (VAR2, VAR4);
VAR16 (VAR14, VAR13, VAR11, VAR2);
VAR9 (VAR8, VAR7, VAR13, VAR11, VAR2, VAR14);
buf (VAR10, VAR8);
wire VAR3, VAR15, VAR6;
and (VAR3, VA... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlrtp/sky130_fd_sc_hvl__dlrtp.symbol.v | 1,432 | module MODULE1 (
input VAR5 ,
output VAR1 ,
input VAR4,
input VAR6
);
supply1 VAR2;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
monotone-RK/FACE | MCSoC-15/16-way_2-parallel/src/vivado_ip_dram/phy/mig_7series_v2_3_ddr_phy_ocd_edge.v | 7,895 | module MODULE1 #
(parameter VAR3 = 100)
(
VAR42, VAR16, VAR32, VAR27, VAR19, VAR4, VAR6,
VAR30, VAR26,
clk, VAR24, VAR17, VAR12, VAR43,
VAR18, VAR5
);
localparam [1:0] VAR41 = 2'b11,
VAR28 = 2'b00,
VAR39 = 2'b10,
VAR34 = 2'b01;
input clk;
input VAR24;
input VAR17;
wire VAR13 = VAR24 && VAR17;
input VAR12;
input VAR43;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21ba/sky130_fd_sc_ms__o21ba.symbol.v | 1,386 | module MODULE1 (
input VAR4 ,
input VAR6 ,
input VAR5,
output VAR7
);
supply1 VAR2;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtn/sky130_fd_sc_lp__dlrtn.behavioral.pp.v | 2,446 | module MODULE1 (
VAR18 ,
VAR17,
VAR4 ,
VAR12 ,
VAR6 ,
VAR13 ,
VAR3 ,
VAR14
);
output VAR18 ;
input VAR17;
input VAR4 ;
input VAR12 ;
input VAR6 ;
input VAR13 ;
input VAR3 ;
input VAR14 ;
wire VAR10 ;
wire VAR5 ;
reg VAR15 ;
wire VAR20 ;
wire VAR24 ;
wire VAR21 ;
wire VAR1;
wire VAR22 ;
wire VAR19 ;
wire VAR7 ;
wire VAR... | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/triple_speed_ethernet-library/altera_tse_rgmii_out1.v | 4,468 | module MODULE1 (
VAR8,
VAR2,
VAR11,
VAR15,
VAR22);
input VAR8;
input VAR2;
input VAR11;
input VAR15;
output VAR22;
wire [0:0] VAR20;
wire [0:0] VAR7 = VAR20[0:0];
wire VAR22 = VAR7;
wire VAR16 = VAR2;
wire VAR12 = VAR16;
wire VAR6 = VAR11;
wire VAR5 = VAR6;
VAR21 VAR14 (
.VAR15 (VAR15),
.VAR2 (VAR12),
.VAR8 (VAR8),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s.functional.pp.v | 1,868 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR1,
VAR12,
VAR3 ,
VAR6
);
output VAR7 ;
input VAR5 ;
input VAR1;
input VAR12;
input VAR3 ;
input VAR6 ;
wire VAR11 ;
wire VAR10;
buf VAR9 (VAR11 , VAR5 );
VAR4 VAR2 (VAR10, VAR11, VAR1, VAR12);
buf VAR8 (VAR7 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fahcon/sky130_fd_sc_lp__fahcon.pp.blackbox.v | 1,396 | module MODULE1 (
VAR8,
VAR1 ,
VAR2 ,
VAR7 ,
VAR4 ,
VAR6 ,
VAR5 ,
VAR3 ,
VAR9
);
output VAR8;
output VAR1 ;
input VAR2 ;
input VAR7 ;
input VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR3 ;
input VAR9 ;
endmodule | apache-2.0 |
bunnie/novena-afe-hs-fpga | novena-afe-hs.srcs/sources_1/imports/imports/ddr3_eim_burst.v | 6,567 | module MODULE1(
input wire VAR52,
input wire [15:0] VAR41, input wire [2:0] VAR14, input wire VAR13, input wire VAR18, input wire VAR23,
output reg [15:0] VAR8,
output wire [2:0] VAR50,
output wire [5:0] VAR42,
output reg [29:0] VAR1,
output reg VAR9,
input wire VAR27,
input wire VAR19,
input wire [31:0] VAR12,
input w... | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/dbg_if/dbg_cpu_registers.v | 6,415 | module MODULE1 (
VAR13,
VAR4,
VAR1,
VAR9,
VAR6,
VAR8,
VAR12,
VAR14,
VAR19
);
input [VAR7 -1:0] VAR13;
input VAR4;
input VAR1;
input VAR9;
input VAR6;
input VAR8;
output [VAR7 -1:0]VAR12;
output VAR14;
output VAR19;
reg VAR18;
wire [2:1] VAR10;
reg VAR3, VAR11, VAR5;
reg VAR16, VAR2, VAR15;
reg VAR17;
reg VAR19;
always ... | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado-hls/pointer_basic/proj_pointer_basic/solution2/impl/ip/hdl/verilog/pointer_basic_pointer_basic_io_s_axi.v | 11,159 | module MODULE1
VAR15 = 5,
VAR31 = 32
)(
input wire VAR64,
input wire VAR63,
input wire VAR54,
input wire [VAR15-1:0] VAR33,
input wire VAR47,
output wire VAR40,
input wire [VAR31-1:0] VAR16,
input wire [VAR31/8-1:0] VAR41,
input wire VAR66,
output wire VAR62,
output wire [1:0] VAR2,
output wire VAR32,
input wire VAR27,... | mit |
trivoldus28/pulsarch-verilog | verif/env/cmp/exu_mon.v | 3,240 | module MODULE1(
clk, VAR3, VAR7, VAR5, VAR2, VAR1,
VAR6, VAR4, VAR8
);
input clk;
input VAR3;
input VAR7;
input VAR5;
input [71:0] VAR2;
input [71:0] VAR1;
input [4:0] VAR6;
input VAR4;
input VAR8;
reg enable;
integer VAR10, VAR9; | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkbuf/sky130_fd_sc_hs__clkbuf.pp.blackbox.v | 1,196 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR3,
VAR2
);
output VAR4 ;
input VAR1 ;
input VAR3;
input VAR2;
endmodule | apache-2.0 |
ychaim/FPGA-Litecoin-Miner | experimental/CM1/uart_tx.v | 2,725 | module MODULE1(
clk, VAR4, VAR10, VAR11, VAR12 );
parameter VAR1 = 25000000; parameter VAR3 = 9600;
input clk;
wire VAR5;
output reg VAR4;
input [7:0] VAR10;
input VAR11;
output VAR12;
reg [3:0] state = 0;
reg [7:0] VAR2;
reg VAR9;
wire ready;
VAR7 #(
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(5)
) VAR6 (
.clk(clk),
.VAR5(VAR5)
)... | gpl-3.0 |
marcuseng/synchronousRead | DisplayCtrl.v | 1,989 | module MODULE1(VAR8, reset, VAR19,
VAR3, VAR5, VAR1, VAR20, VAR16, VAR4, VAR23, VAR13, VAR7, VAR11, VAR24, VAR14
);
input [26:0] VAR8;
input reset;
input [15:0] VAR19;
output VAR3, VAR5, VAR1, VAR20, VAR16, VAR4, VAR23, VAR13, VAR7, VAR11, VAR24, VAR14;
reg [6:0] VAR17;
wire [26:0] VAR2;
reg [3:0] VAR18;
wire [3:0] VAR... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/CNN_Optimization2/solution1/syn/verilog/convolve_kernel_fcud.v | 1,944 | module MODULE1
VAR23 = 1,
VAR2 = 5,
VAR19 = 32,
VAR13 = 32,
VAR15 = 32
)(
input wire clk,
input wire reset,
input wire VAR7,
input wire [VAR19-1:0] VAR1,
input wire [VAR13-1:0] VAR10,
output wire [VAR15-1:0] dout
);
wire VAR22;
wire VAR8;
wire VAR20;
wire [31:0] VAR18;
wire VAR3;
wire [31:0] VAR12;
wire VAR4;
wire [31:... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v | 2,222 | module MODULE1 (
address,
VAR5,
clk,
VAR7,
VAR2,
VAR8,
VAR3,
VAR4
)
;
output VAR3;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input VAR5;
input clk;
input VAR7;
input VAR2;
input [ 31: 0] VAR8;
wire VAR1;
reg VAR6;
wire VAR3;
wire VAR9;
wire [ 31: 0] VAR4;
assign VAR1 = 1;
assign VAR9 = {1 {(address == 0)}} & VAR6;
a... | gpl-3.0 |
cynngah/virtualsynthesizer | sound_files/Altera_UP_Slow_Clock_Generator.v | 7,827 | module MODULE1 (
clk,
reset,
VAR5,
VAR7,
VAR8,
VAR3,
VAR4,
VAR9
);
parameter VAR6 = 10;
parameter VAR1 = 10'h001;
input clk;
input reset;
input VAR5;
output reg VAR7;
output reg VAR8;
output reg VAR3;
output reg VAR4;
output reg VAR9;
reg [VAR6:1] VAR2;
always @(posedge clk)
begin
if (reset == 1'b1)
VAR2 <= {VAR6{1'b0}... | mit |
HSID/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/CRC8_gen.v | 4,161 | module MODULE1(
input [47:0] VAR2,
output [7:0] VAR1
);
assign VAR1[0] = VAR2[46] ^ VAR2[42] ^ VAR2[41] ^ VAR2[37] ^ VAR2[36] ^ VAR2[35] ^ VAR2[34] ^
VAR2[33] ^ VAR2[31] ^ VAR2[30] ^ VAR2[29] ^ VAR2[27] ^ VAR2[26] ^ VAR2[24] ^
VAR2[20] ^ VAR2[18] ^ VAR2[17] ^ VAR2[16] ^ VAR2[15] ^ VAR2[14] ^ VAR2[13] ^
VAR2[8] ^ VAR2[7... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor3/sky130_fd_sc_hs__xor3_2.v | 2,072 | module MODULE2 (
VAR8 ,
VAR6 ,
VAR1 ,
VAR7 ,
VAR4,
VAR5
);
output VAR8 ;
input VAR6 ;
input VAR1 ;
input VAR7 ;
input VAR4;
input VAR5;
VAR2 VAR3 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR8,
VAR6,
VAR1,
VAR7
);
output VAR8;
input VAR6;
input VAR1;
in... | apache-2.0 |
tmolteno/TART | hardware/FPGA/wishbone/example/wb_sram.v | 1,897 | module MODULE1
parameter VAR6 = VAR7-1,
parameter VAR12 = 10,
parameter VAR13 = 1 << VAR12,
parameter VAR15 = VAR12-1,
parameter VAR19 = 3)
(
input VAR17,
input VAR5,
input VAR3,
input VAR4,
input VAR9,
input VAR2, output reg VAR14 = 0,
input [VAR15:0] VAR11,
input [VAR6:0] VAR18,
output reg [VAR6:0] VAR8
);
reg [VAR6:... | lgpl-3.0 |
jncronin/jca | cpu/vga_ram.v | 10,748 | module MODULE1 (
VAR28,
VAR8,
VAR17,
VAR58,
VAR57,
VAR23,
VAR24,
VAR60,
VAR59,
VAR21);
input [11:0] VAR28;
input [11:0] VAR8;
input VAR17;
input VAR58;
input [7:0] VAR57;
input [7:0] VAR23;
input VAR24;
input VAR60;
output [7:0] VAR59;
output [7:0] VAR21;
tri1 VAR17;
tri0 VAR24;
tri0 VAR60;
wire [7:0] VAR33;
wire [7:0]... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_2.behavioral.pp.v | 3,755 | module MODULE1( VAR1, VAR29, VAR28, VAR31, VAR8, VAR25 );
input VAR1, VAR29, VAR28;
inout VAR8, VAR25;
output VAR31;
reg VAR23;
VAR26 VAR9(.VAR1(VAR1),.VAR29(VAR29),.VAR28(VAR28),.VAR31(VAR31),.VAR8(VAR8),.VAR25(VAR25),.VAR23(VAR23));
VAR26 VAR21(.VAR1(VAR1),.VAR29(VAR29),.VAR28(VAR28),.VAR31(VAR31),.VAR8(VAR8),.VAR25(... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ifu/rtl/sparc_ifu_fdp.v | 42,712 | module MODULE1(
VAR226, VAR181, VAR39, VAR41,
VAR216, VAR56, VAR193, VAR87,
VAR48, VAR170, VAR80, VAR150,
VAR179, VAR62, VAR14,
VAR19, VAR86, VAR103,
VAR173, VAR218,
VAR272, VAR240, VAR180, VAR225, VAR42,
VAR45, VAR26, VAR207,
VAR192, VAR146, VAR187,
VAR74, VAR202, VAR136,
VAR167, VAR67, VAR113,
VAR168, VAR58, VAR40,
V... | gpl-2.0 |
skatpgusskat/KoreaUnivHomework_2015_1 | Computer Architecture/Homework/Lab10/alu_beh.v | 1,305 | module MODULE2(VAR5, VAR4, VAR1, VAR2, VAR6);
input [31:0] VAR5, VAR4;
input [2:0] VAR1;
output [31:0] VAR2;
reg [31:0] VAR2;
output VAR6;
reg VAR6;
always @(VAR5 or VAR4 or VAR1)
begin
case(VAR1)
3'b010: VAR2 = VAR5 + VAR4;
3'b110: VAR2 = VAR5 - VAR4;
3'b001: VAR2 = VAR5 | VAR4;
3'b000: VAR2 = VAR5 & VAR4;
3'b111:
beg... | mit |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/verilog/ANN_mux_4to1_sel2_32_1.v | 1,205 | module MODULE1 #(
parameter
VAR2 = 0,
VAR16 = 1,
VAR8 = 32,
VAR14 = 32,
VAR10 = 32,
VAR6 = 32,
VAR7 = 32,
VAR3 = 32
)(
input [31 : 0] VAR1,
input [31 : 0] VAR15,
input [31 : 0] VAR12,
input [31 : 0] VAR4,
input [1 : 0] VAR13,
output [31 : 0] dout);
wire [1 : 0] sel;
wire [31 : 0] VAR9;
wire [31 : 0] VAR11;
wire [31 : 0... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/SDRAM_Controller_v.v | 24,163 | module MODULE1 (
clk, reset,
VAR8, VAR100, VAR99, VAR117, VAR93, VAR50,
VAR70, VAR119,
VAR92, VAR58, VAR55, VAR105, VAR95,
VAR22, VAR31, VAR41, VAR26, VAR112
);
parameter VAR76 = 10; parameter VAR106 = 25; parameter VAR48 = 10100; parameter VAR87 = 780; else
parameter VAR76 = 8; parameter VAR106 = 22; parameter VAR48 =... | lgpl-3.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/demux.v | 2,689 | module MODULE1
parameter VAR7 = 12,
parameter VAR1 = 1
)
(
input [VAR1-1:0] VAR3, input [VAR6(VAR7)-1:0] VAR8, output [VAR7*VAR1-1:0] VAR5 );
genvar VAR2;
reg [VAR7*VAR1-1:0] VAR4;
assign VAR5 = VAR4;
always @(*) begin
VAR4 = 0;
VAR4[VAR1*VAR8 +: VAR1] = VAR3;
end
endmodule | gpl-3.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_register.v | 4,646 | module MODULE1(VAR6, VAR5, VAR2, VAR7, VAR4, VAR8);
parameter VAR3 = 8; parameter VAR1 = 0;
input [VAR3-1:0] VAR6;
input VAR2;
input VAR7;
input VAR4;
input VAR8;
output [VAR3-1:0] VAR5;
reg [VAR3-1:0] VAR5;
always @ (posedge VAR7 or posedge VAR4)
begin
if(VAR4)
VAR5<=VAR1;
end
else
if(VAR8)
VAR5<=VAR1;
else
if(VAR2) V... | gpl-2.0 |
GREO/GNU-Radio | usrp/fpga/sdr_lib/strobe_gen.v | 1,362 | module MODULE1
( input VAR4,
input reset,
input enable,
input [7:0] VAR3, input VAR1,
output wire VAR2 );
reg [7:0] counter;
assign VAR2 = ~|counter && enable && VAR1;
always @(posedge VAR4)
if(reset | ~enable)
counter <= 8'd0;
else if(VAR1)
if(counter == 0)
counter <= VAR3;
else
counter <= counter - 8'd1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvn/sky130_fd_sc_hdll__einvn_1.v | 2,166 | module MODULE2 (
VAR1 ,
VAR9 ,
VAR3,
VAR2,
VAR4,
VAR6 ,
VAR8
);
output VAR1 ;
input VAR9 ;
input VAR3;
input VAR2;
input VAR4;
input VAR6 ;
input VAR8 ;
VAR7 VAR5 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR1 ,
VAR9 ,
VAR3
);
output VAR1 ;... | apache-2.0 |
pemsac/ANN_project | ANN_project.ip_user_files/ipstatic/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_addr_arbiter_sasd.v | 13,349 | module MODULE1 #
(
parameter VAR76 = "none",
parameter integer VAR19 = 1,
parameter integer VAR5 = 1,
parameter integer VAR20 = 1,
parameter VAR45 = 0,
parameter [VAR19*32-1:0] VAR23 = {VAR19{32'h00000000}}
)
(
input wire VAR61,
input wire VAR68,
input wire [VAR19*VAR20-1:0] VAR24,
input wire [VAR19*VAR20-1:0] VAR44,
i... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_2.behavioral.pp.v | 2,623 | module MODULE1( VAR1, VAR9, VAR3, VAR8, VAR7, VAR6 );
input VAR9, VAR1, VAR3;
inout VAR7, VAR6;
output VAR8;
VAR5 VAR4(.VAR1(VAR1),.VAR9(VAR9),.VAR3(VAR3),.VAR8(VAR8),.VAR7(VAR7),.VAR6(VAR6));
VAR5 VAR2(.VAR1(VAR1),.VAR9(VAR9),.VAR3(VAR3),.VAR8(VAR8),.VAR7(VAR7),.VAR6(VAR6)); | apache-2.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/db/ip/niosII_system/submodules/niosII_system_altpll_0.v | 10,334 | module MODULE1
(
VAR9,
VAR8,
VAR3,
VAR6) ;
input VAR9;
input VAR8;
input [0:0] VAR3;
output [0:0] VAR6;
tri0 VAR9;
tri1 VAR8;
reg [0:0] VAR1;
reg [0:0] VAR4;
reg [0:0] VAR7;
wire VAR2;
wire VAR5;
wire VAR10; | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_dcfilter.v | 5,733 | module MODULE1 (
clk,
valid,
VAR7,
VAR65,
VAR66,
VAR59,
VAR39,
VAR63);
input clk;
input valid;
input [15:0] VAR7;
output VAR65;
output [15:0] VAR66;
input VAR59;
input [15:0] VAR39;
input [15:0] VAR63;
reg [47:0] VAR1 = 'd0;
reg [47:0] VAR55 = 'd0;
reg VAR51 = 'd0;
reg [15:0] VAR44 = 'd0;
reg VAR48 = 'd0;
reg [15:0] VA... | gpl-3.0 |
JohnOrlando/gnuradio-bitshark | gr-gpio/src/fpga/lib/io_pins.v | 2,558 | module MODULE1
( inout wire [15:0] VAR10, inout wire [15:0] VAR2, inout wire [15:0] VAR8, inout wire [15:0] VAR11,
input wire [15:0] VAR16, input wire [15:0] VAR18, input wire [15:0] VAR21, input wire [15:0] VAR23,
input wire [15:0] VAR20, input wire [15:0] VAR27,
input wire [15:0] VAR5, input wire [15:0] VAR3,
input V... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp1/megacells/clk_doubler.v | 9,124 | module MODULE1 (
VAR13,
VAR12);
input VAR13;
output VAR12;
wire [5:0] VAR18;
wire [0:0] VAR2 = 1'h0;
wire [0:0] VAR6 = VAR18[0:0];
wire VAR12 = VAR6;
wire VAR45 = VAR13;
wire [1:0] VAR8 = {VAR2, VAR45};
VAR1 VAR29 (
.VAR26 (VAR8),
.clk (VAR18)
,
.VAR39 (),
.VAR35 (),
.VAR43 (),
.VAR7 (),
.VAR33 (),
.VAR5 (),
.VAR3 (),
... | gpl-2.0 |
ngoel9/progressive-learning-platform | reference/hw/verilog/mod_plpid.v | 1,452 | module MODULE1(rst, clk, VAR3, VAR5, VAR9, VAR1, VAR8, din, VAR2, dout);
input rst;
input clk;
input VAR3,VAR5;
input [31:0] VAR9, VAR1;
input [1:0] VAR8;
input [31:0] din;
output [31:0] VAR2, dout;
wire [31:0] VAR10, VAR4;
assign VAR2 = VAR10;
assign dout = VAR4;
parameter VAR6 = 32'h00000401;
parameter VAR7 = 32'h017... | gpl-3.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/arSRLFIFOD.v | 2,868 | module MODULE1 (VAR9,VAR7,VAR19,VAR3,VAR18,VAR5,VAR6,VAR17,VAR14);
parameter VAR1 = 128;
parameter VAR13 = 5;
localparam VAR8 = 2**VAR13;
input VAR9;
input VAR7;
input VAR14;
input VAR19;
input VAR3;
output VAR18;
output VAR5;
input[VAR1-1:0] VAR6;
output[VAR1-1:0] VAR17;
reg[VAR13-1:0] pos; reg[VAR1-1:0] VAR15[VAR8-1:... | lgpl-3.0 |
twlostow/dsi-shield | hdl/rtl/hpdmc/spartan6/hpdmc_odelay.v | 1,922 | module MODULE1
parameter VAR20 = 0)
(
input VAR30,
input VAR28,
input VAR24,
input [VAR32-1:0] VAR13,
output [VAR32-1:0] VAR43
);
genvar VAR41;
wire [VAR32-1:0] VAR2;
generate
for(VAR41=0; VAR41<VAR32; VAR41=VAR41+1) begin
VAR39
.VAR25 (1'b0),
.VAR29 ("VAR26"))
VAR17
(.VAR12 (VAR13[VAR41]),
.VAR1 (VAR13[VAR41]),
.VAR31... | lgpl-3.0 |
parallella/oh | common/hdl/oh_fifo_async.v | 2,641 | module MODULE1 # (parameter VAR13 = 104, parameter VAR21 = 32, parameter VAR17 = "VAR7", parameter VAR23 = (VAR21/2), parameter VAR19 = VAR9(VAR21) )
(
input VAR22, input VAR15, input VAR12, input [VAR13-1:0] din, input VAR8, input VAR14, output [VAR13-1:0] dout, output VAR26, output VAR24, output VAR4, output [VAR19-1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgndnovpb/sky130_fd_sc_ls__tapvgndnovpb.blackbox.v | 1,220 | module MODULE1 ();
supply1 VAR3;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4bb/sky130_fd_sc_lp__or4bb.blackbox.v | 1,326 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR1 ,
VAR2,
VAR5
);
output VAR9 ;
input VAR8 ;
input VAR1 ;
input VAR2;
input VAR5;
supply1 VAR7;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tap/sky130_fd_sc_hs__tap.functional.v | 1,129 | module MODULE1 (
VAR1,
VAR2
);
input VAR1;
input VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41a/sky130_fd_sc_hs__o41a.functional.pp.v | 1,948 | module MODULE1 (
VAR12,
VAR2,
VAR8 ,
VAR14 ,
VAR16 ,
VAR15 ,
VAR9 ,
VAR5
);
input VAR12;
input VAR2;
output VAR8 ;
input VAR14 ;
input VAR16 ;
input VAR15 ;
input VAR9 ;
input VAR5 ;
wire VAR9 VAR7 ;
wire VAR3 ;
wire VAR6;
or VAR10 (VAR7 , VAR9, VAR15, VAR16, VAR14 );
and VAR11 (VAR3 , VAR7, VAR5 );
VAR13 VAR1 (VAR6, V... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_mult_mac.v | 10,575 | module MODULE1(
clk, rst,
VAR41, VAR36, VAR14, VAR39, VAR12, VAR26, VAR30, VAR37, VAR16,
VAR48, VAR46, VAR27, VAR15, VAR1
);
parameter VAR5 = VAR17;
input clk;
input rst;
input VAR41;
input VAR36;
input VAR14;
input [VAR5-1:0] VAR39;
input [VAR5-1:0] VAR12;
input [VAR6-1:0] VAR26;
input [VAR24-1:0] VAR30;
output [VAR5-... | apache-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/bram/bram_stub.v | 1,304 | module MODULE1(VAR7, VAR3, VAR4, VAR5, VAR1, VAR2, VAR6)
;
input VAR7;
input [0:0]VAR3;
input [10:0]VAR4;
input [15:0]VAR5;
input VAR1;
input [10:0]VAR2;
output [15:0]VAR6;
endmodule | gpl-2.0 |
csturton/wirepatch | system/hardware/cores/ddr2/ddr2_phy_top.v | 17,089 | module MODULE1 #
(
parameter VAR76 = 2,
parameter VAR65 = 1,
parameter VAR97 = 1,
parameter VAR21 = 10,
parameter VAR102 = 0,
parameter VAR56 = 1,
parameter VAR86 = 1,
parameter VAR127 = 1,
parameter VAR121 = 9,
parameter VAR32 = 72,
parameter VAR12 = 7,
parameter VAR115 = 8,
parameter VAR57 = 9,
parameter VAR26 = 4,
p... | mit |
osrf/wandrr | firmware/motor_controller/fpga/udp_rxq.v | 3,527 | module MODULE1
(input clk,
input [7:0] VAR42, input VAR28, input VAR16,
output [7:0] VAR55, output VAR51, output VAR40);
wire [3:0] VAR38;
wire VAR34 = VAR38[3];
VAR30 #(4) VAR49
(.VAR62(clk), .VAR26({VAR38[2:0], VAR28}), .rst(1'b0), .en(1'b1), .VAR44(VAR38));
wire VAR7 = ~VAR28 & VAR34;
wire [31:0] VAR33;
wire [7:0] V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3b/sky130_fd_sc_hdll__nor3b.functional.pp.v | 2,015 | module MODULE1 (
VAR4 ,
VAR16 ,
VAR12 ,
VAR5 ,
VAR6,
VAR8,
VAR13 ,
VAR15
);
output VAR4 ;
input VAR16 ;
input VAR12 ;
input VAR5 ;
input VAR6;
input VAR8;
input VAR13 ;
input VAR15 ;
wire VAR14 ;
wire VAR10 ;
wire VAR9;
nor VAR1 (VAR14 , VAR16, VAR12 );
and VAR3 (VAR10 , VAR5, VAR14 );
VAR11 VAR2 (VAR9, VAR10, VAR6, VA... | apache-2.0 |
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