repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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|---|---|---|---|---|
versaloon/vsf | vsf/old/example/vsfusbh/proj/Keil_v5_CMEM7/fpga/src/top.v | 2,627 | module MODULE1(
VAR18,
VAR17,
);
input VAR18;
inout [31:0] VAR17;
wire [31:0] VAR9;
wire [31:0] VAR13;
wire [31:0] VAR3;
assign VAR3 = VAR17;
assign VAR17[0] = (VAR13[0])? VAR9[0] : 1'VAR4;
assign VAR17[1] = (VAR13[1])? VAR9[1] : 1'VAR4;
assign VAR17[2] = (VAR13[2])? VAR9[2] : 1'VAR4;
assign VAR17[3] = (VAR13[3])? VAR9... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_023bits.v | 1,917 | module MODULE1 (
clk,
VAR7, VAR18, VAR23, VAR22, VAR10, VAR19, VAR13, VAR29,
sum,
);
input clk;
input [VAR11+0-1:0] VAR7, VAR18, VAR23, VAR22, VAR10, VAR19, VAR13, VAR29;
output [VAR11 :0] sum;
reg [VAR11 :0] sum;
wire [VAR11+3-1:0] VAR17;
wire [VAR11+2-1:0] VAR15, VAR28;
wire [VAR11+1-1:0] VAR25, VAR12, VAR20, VAR5;
r... | mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_fp_asinpi_s5.v | 1,188 | module MODULE1 (
enable,
VAR8,
VAR6,
VAR5);
input enable;
input VAR8;
input [31:0] VAR6;
output [31:0] VAR5;
wire [31:0] VAR9;
wire [31:0] VAR5 = VAR9[31:0];
VAR1 VAR4 (
.en (enable),
.VAR3(1'b0),
.clk(VAR8),
.VAR2(VAR6),
.VAR7(VAR9));
endmodule | mit |
ammelto/FPGAdventure | Adventure/SWMaze.v | 3,607 | module MODULE1(VAR3, VAR5, VAR6, VAR4, VAR2);
input VAR3;
input [9:0]VAR5;
input [8:0]VAR6;
input [7:0]VAR2;
output [7:0]VAR4;
reg [7:0]VAR1;
always @(posedge VAR3) begin
if((VAR6 < 40) && (VAR5 >= 0))
VAR1[7:0] <= VAR2;
end
else if((VAR5 >= 0 && VAR5 <=63) && (
(VAR6 >= 120 && VAR6 <= 359) ||
(VAR6 >= 441) ) )
VAR1[7:... | mit |
finnball/igloo | projects/chip8/hdl/draw.v | 7,416 | module MODULE1(
input clk,
input en,
input VAR33,
input [15 : 0] VAR8,
input [10 : 0] VAR45,
input [3 : 0] VAR3,
output [VAR40 - 1 : 0] VAR49,
input [VAR34 - 1 : 0] VAR36,
output VAR38,
output VAR6,
output VAR25,
output VAR54,
output VAR31
);
localparam VAR52 = 0;
localparam VAR29 = 1;
localparam VAR47 = 2;
localparam ... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/controller/arb_row_col.v | 15,977 | module MODULE1 #
(
parameter VAR74 = 100,
parameter VAR48 = "1T",
parameter VAR37 = 5,
parameter VAR15 = "VAR69",
parameter VAR98 = 4,
parameter VAR55 = 2,
parameter VAR71 = 2,
parameter VAR33 = 37500, parameter VAR90 = 12500, parameter VAR26 = 6 )
(
VAR11, VAR22, VAR1, VAR97, VAR45, VAR85,
VAR42, VAR84, VAR6,
VAR35, V... | lgpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Approx_adder.v | 6,587 | module MODULE1
input wire VAR13,
input wire [VAR18-1:0] VAR16,
input wire [VAR18-1:0] VAR9,
output wire [VAR18:0] VAR23
);
wire [VAR18-1:0] VAR3;
wire [VAR19-1:0] VAR22;
wire VAR21;
assign VAR3 = (VAR13) ? ~VAR9 : VAR9;
VAR24 VAR2 (.VAR16(VAR16[VAR19-1:0]), .VAR9(VAR3[VAR19-1:0]), .VAR23({VAR21,VAR22}));
always @* begi... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/dram/rtl/dram.v | 50,773 | module MODULE1 (
VAR28, VAR12, VAR8, VAR242,
VAR269, VAR320, VAR92,
VAR328, VAR118, VAR130,
VAR98, VAR211, VAR284,
VAR229, VAR208, VAR260,
VAR193, VAR7, VAR187,
VAR319, VAR259, VAR25,
VAR218, VAR173, VAR152,
VAR207, VAR209, VAR4,
VAR296, VAR83, VAR288,
VAR293, VAR350,
VAR103, VAR2,
VAR314, VAR166,
VAR189, VAR54,
VAR234... | gpl-2.0 |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CORESPI/4.2.116/rtl/vlog/core/corespi.v | 3,588 | module
MODULE1
( VAR7, VAR22, VAR25, VAR5, VAR29, VAR19, VAR14, VAR24, VAR8, VAR30,
VAR33, VAR6, VAR2, VAR21, VAR28, VAR20, VAR15, VAR31, VAR12, VAR13,
VAR9
);
parameter VAR32 = 15;
parameter VAR11 = 8;
parameter VAR23 = 4;
parameter VAR4 = 4;
parameter VAR18 = 7;
parameter VAR26 = 0;
parameter VAR1 = 0;
parameter VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dlatch_pr/sky130_fd_sc_hvl__udp_dlatch_pr.blackbox.v | 1,295 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR4 ,
VAR1
);
output VAR3 ;
input VAR2 ;
input VAR4 ;
input VAR1;
endmodule | apache-2.0 |
jacgoudsmit/P8X32A_Emulation | Altera/hub.v | 8,090 | module MODULE1
(
input VAR26,
input VAR40,
input VAR28,
input [7:0] VAR50,
input VAR27,
input VAR21,
input VAR33,
input [1:0] VAR18,
input [15:0] VAR39,
input [31:0] VAR5,
output reg [31:0] VAR35,
output VAR8,
output [7:0] VAR15,
output reg [7:0] VAR32,
output [7:0] VAR11,
output [27:0] VAR14,
output reg [7:0] VAR45
);... | gpl-3.0 |
freecores/orsoc_graphics_accelerator | bench/verilog/gfx/fragment_bench.v | 3,396 | module MODULE1();
reg VAR34;
reg VAR7;
parameter VAR14 = 16;
reg [7:0] VAR15;
reg [VAR14-1:0] VAR11;
reg [VAR14-1:0] VAR25;
reg signed [VAR14-1:0] VAR10;
reg [VAR14-1:0] VAR2;
reg [VAR14-1:0] VAR8;
reg [VAR14-1:0] VAR4;
reg [VAR14-1:0] VAR16;
reg VAR33;
reg [31:0] VAR6;
reg VAR28;
reg VAR1;
reg VAR27;
wire [VAR14-1:0] ... | gpl-3.0 |
tugrulyatagan/RISC-processor | xilinx_processor/Atlys_Spartan6.v | 1,073 | module MODULE1(
input clk,
input [7:0] VAR6,
input [5:0] VAR4,
input VAR3,
output VAR5,
output [7:0] VAR2
);
reg VAR1; | gpl-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_qmem_top.v | 13,667 | module MODULE1(
clk, rst,
VAR8, VAR71, VAR32,
VAR37,
VAR38,
VAR48,
VAR36,
VAR65,
VAR61,
VAR46,
VAR76,
VAR7,
VAR1,
VAR34,
VAR21,
VAR9,
VAR14,
VAR47,
VAR50,
VAR15,
VAR73,
VAR55,
VAR57,
VAR18,
VAR53,
VAR20,
VAR62,
VAR33,
VAR24,
VAR63,
VAR70,
VAR35,
VAR39,
VAR52,
VAR22,
VAR66, VAR51, VAR44,
VAR64, VAR45, VAR67, VAR69,
VAR7... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_multiplexer.v | 14,042 | module MODULE1
parameter VAR18 = 128,
parameter VAR46 = 12,
parameter VAR12 = 5,
parameter VAR15 = "VAR56",
parameter VAR23 = 10
)
(
input VAR4,
input VAR66,
input [VAR46-1:0] VAR61, input [(VAR46*VAR31)-1:0] VAR73, input [(VAR46*VAR65)-1:0] VAR59, input [(VAR46*VAR18)-1:0] VAR33, output [VAR46-1:0] VAR5, output [VAR46... | gpl-3.0 |
Cognoscan/BoostDSP | verilog/src/signalGen/functionGen.v | 12,822 | module MODULE1 #(
parameter VAR8 = "VAR13", parameter VAR12 = 1, parameter VAR5 = 1, parameter VAR6 = 16, parameter VAR10 = 16, parameter VAR4 = 1 )
(
input clk, input rst, input en, input [1:0] VAR2, input [VAR10-1:0] VAR9, input [VAR10-1:0] VAR7, input [VAR6-1:0] VAR11, input [VAR6-1:0] VAR3, output signed [VAR6-1:0]... | apache-2.0 |
sabertazimi/hust-lab | verilog/labs/lab5/src/_3bit_binary_multiplier_control_unit.v | 2,298 | module MODULE1(
module 3bitbinarymultipliercontrolunit
(
input VAR13,
input clk,
input VAR11,
input VAR2,
output VAR8,
output reg VAR1,
output reg VAR12,
output reg VAR9,
output reg VAR10
);
reg [2:0] state, VAR3;
parameter VAR7 = 0, VAR4 = 1, VAR5 = 2, VAR6 = 3;
assign VAR8 = VAR13; | mit |
plindstroem/oh | elink/hdl/etx_core.v | 11,312 | module MODULE1(
VAR28, VAR39, VAR66, VAR4, VAR21, VAR68,
VAR27, VAR51,
reset, clk, VAR3, VAR4, VAR68, VAR40,
VAR74, VAR37, VAR17, VAR38, VAR73,
VAR8
);
parameter VAR57 = 32;
parameter VAR54 = 32;
parameter VAR64 = 104;
parameter VAR13 = 6;
parameter VAR6 = 12'h000;
input reset;
input clk;
output VAR28;
output VAR39;
ou... | gpl-3.0 |
Progressive-Learning-Platform/progressive-learning-platform | reference/hw/verilog/mod_memory_hierarchy.v | 5,704 | module MODULE2(rst, clk, VAR25, VAR54, VAR65, VAR29, VAR34, din, VAR16, dout, VAR18, VAR12, VAR23, VAR66, VAR31, VAR17, VAR5, VAR50, VAR61, VAR19, VAR39, VAR30, VAR63, VAR8, VAR60, VAR57, VAR1, VAR33, VAR22);
input rst;
input clk;
input VAR25, VAR54;
input [31:0] VAR65, VAR29;
input [1:0] VAR34;
input [31:0] din;
outpu... | gpl-3.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/NIOS_SYSTEMV3/synthesis/submodules/NIOS_SYSTEMV3_MENU_DOWN.v | 1,920 | module MODULE1 (
address,
clk,
VAR1,
VAR3,
VAR6
)
;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input clk;
input VAR1;
input VAR3;
wire VAR2;
wire VAR5;
wire VAR4;
reg [ 31: 0] VAR6;
assign VAR2 = 1;
assign VAR4 = {1 {(address == 0)}} & VAR5;
always @(posedge clk or negedge VAR3)
begin
if (VAR3 == 0)
VAR6 <= 0;
end
el... | gpl-2.0 |
SteffenReith/J1Sc | src/main/verilog/arch/IcoBoard/Board_IcoBoard.v | 2,242 | module MODULE1 (reset,
VAR25,
VAR30,
VAR16,
VAR17,
VAR11,
VAR10,
VAR27,
VAR28,
VAR9,
VAR12,
VAR2);
input reset;
input VAR25;
input [0:0] VAR30;
input VAR12;
input VAR10;
input VAR27;
input VAR28;
output [7:0] VAR16;
output [2:0] VAR17;
output VAR2;
output VAR9;
inout [7:0] VAR11;
wire VAR23;
wire VAR7;
wire [7:0] VAR24... | bsd-3-clause |
sabertazimi/hust-lab | architecture/design/fpga/src/forward_unit.v | 3,483 | module MODULE1
(
input [4:0] VAR6,
input [4:0] VAR4,
input [4:0] VAR1,
input [4:0] VAR15,
input [4:0] VAR10,
input VAR8,
input VAR13,
input VAR12,
input [4:0] VAR7,
input [4:0] VAR3,
output reg [1:0] VAR11,
output reg [1:0] VAR2,
output reg [1:0] VAR9,
output reg [1:0] VAR14,
output VAR5
);
always @ ( * ) begin
if ((VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_4.behavioral.v | 1,188 | module MODULE1( VAR4, VAR3, VAR5 );
input VAR5, VAR3;
output VAR4;
VAR6 VAR1(.VAR4(VAR4),.VAR3(VAR3),.VAR5(VAR5));
VAR6 VAR2(.VAR4(VAR4),.VAR3(VAR3),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc.behavioral.v | 1,525 | module MODULE1 (
VAR10 ,
VAR2,
VAR1
);
output VAR10 ;
input VAR2;
input VAR1 ;
supply1 VAR7;
supply0 VAR11;
supply1 VAR4 ;
supply0 VAR6 ;
wire VAR8 ;
wire VAR12;
not VAR5 (VAR8 , VAR2 );
and VAR3 (VAR12, VAR8, VAR1 );
buf VAR9 (VAR10 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbp/sky130_fd_sc_hs__dlxbp.pp.blackbox.v | 1,283 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR3 ,
VAR6,
VAR2,
VAR1
);
output VAR4 ;
output VAR5 ;
input VAR3 ;
input VAR6;
input VAR2;
input VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ba/sky130_fd_sc_lp__o21ba.behavioral.v | 1,563 | module MODULE1 (
VAR10 ,
VAR11 ,
VAR13 ,
VAR6
);
output VAR10 ;
input VAR11 ;
input VAR13 ;
input VAR6;
supply1 VAR12;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR4 ;
wire VAR8 ;
wire VAR3;
nor VAR9 (VAR8 , VAR11, VAR13 );
nor VAR7 (VAR3, VAR6, VAR8 );
buf VAR2 (VAR10 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxtn/sky130_fd_sc_ls__dlxtn.pp.blackbox.v | 1,323 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR7,
VAR2 ,
VAR3 ,
VAR1 ,
VAR4
);
output VAR5 ;
input VAR6 ;
input VAR7;
input VAR2 ;
input VAR3 ;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
zhijian-liu/mips-cpu | src/cpu/register.v | 1,210 | module MODULE1(
input VAR11 ,
input reset ,
input VAR7 ,
input [ 4:0] VAR13,
output reg [31:0] VAR3 ,
input VAR4 ,
input [ 4:0] VAR1,
output reg [31:0] VAR9 ,
input VAR14 ,
input [ 4:0] VAR2 ,
input [31:0] VAR5
);
reg [31:0] VAR10[31:0];
always @ begin
if (reset == VAR12 && VAR4 == VAR6 && VAR1 != 5'b0) begin
VAR9 <= V... | mit |
sam-falvo/kestrel | cores/KCP53K/cpu2/rtl/verilog/ram16b.v | 1,312 | module MODULE3(
input [15:0] VAR9,
input VAR11,
input [4:0] VAR4,
input VAR5,
output [15:0] VAR6,
input [4:0] VAR20,
input VAR16
);
MODULE1 MODULE1(
.VAR9(VAR9),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR20(VAR20),
.VAR16(VAR16)
);
MODULE2 MODULE1(
.VAR9(VAR9),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR5(VAR5),
.... | mpl-2.0 |
bluespec/Flute | builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkSoC_Map.v | 7,880 | module MODULE1(VAR21,
VAR22,
VAR18,
VAR27,
VAR1,
VAR19,
VAR7,
VAR25,
VAR14,
VAR29,
VAR2,
VAR12,
VAR28,
VAR6,
VAR23,
VAR15,
VAR9,
VAR5,
VAR8,
VAR4,
VAR3,
VAR13,
VAR24,
VAR11,
VAR26,
VAR20,
VAR17,
VAR10,
VAR16);
input VAR21;
input VAR22;
output [63 : 0] VAR18;
output [63 : 0] VAR27;
output [63 : 0] VAR1;
output [63 : 0] ... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w_sync_synth.v | 3,543 | module MODULE1 #(parameter VAR15(VAR18)
, parameter VAR15(VAR8)
, parameter VAR5=0
, parameter VAR22=VAR10(VAR8)
, parameter VAR7=0
)
(input VAR20
, input VAR24
, input VAR21
, input [VAR22-1:0] VAR11
, input [VAR3(VAR18, 1):0] VAR26
, input VAR28
, input [VAR22-1:0] VAR12
, output logic [VAR3(VAR18, 1):0] VAR14
, inpu... | bsd-3-clause |
dm-urievich/afc-smm | software/third-patry/pipelined_fft_256/trunk/SRC/mpuc924_383.v | 5,912 | module MODULE1 ( VAR17,VAR23 ,VAR10, VAR18,VAR13,VAR24,VAR4 ,VAR14 ,VAR22 );
input VAR17 ;
wire VAR17 ;
input VAR23 ;
wire VAR23 ;
input VAR10; input VAR18 ; wire VAR18 ;
input VAR13 ; wire VAR13 ;
input [VAR1-1:0] VAR24 ;
wire signed [VAR1-1:0] VAR24 ;
input [VAR1-1:0] VAR4 ;
wire signed [VAR1-1:0] VAR4 ;
output [VAR1... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/NVMeHostController_v2_0_0/ba7abda2/src/pcie_hcmd_table_cid.v | 3,777 | module MODULE1 # (
parameter VAR2 = 20,
parameter VAR33 = 7
)
(
input clk,
input VAR34,
input [VAR33-1:0] VAR14,
input [VAR2-1:0] VAR35,
input [VAR33-1:0] VAR5,
output [VAR2-1:0] VAR23
);
localparam VAR20 = "7SERIES";
localparam VAR13 = "18Kb";
localparam VAR1 = 0;
localparam VAR26 = VAR2;
localparam VAR18 = VAR2;
loca... | gpl-3.0 |
monotone-RK/FACE | IEICE-Trans/bandwidth/DRAM/src/ip_dram/phy/mig_7series_v2_3_ddr_phy_top.v | 68,935 | module MODULE1 #
(
parameter VAR182 = 100, parameter VAR117 = 135, parameter VAR60 = "0", parameter VAR273 = 3, parameter VAR297 = "8", parameter VAR72 = "VAR112", parameter VAR399 = "VAR1", parameter VAR23 = 1, parameter VAR337 = 5,
parameter VAR401 = 12, parameter VAR165 = 1, parameter VAR162 = 1, parameter VAR18 = 5... | mit |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_example_top_5.v | 7,205 | module MODULE1 (
VAR49,
VAR25,
VAR33,
VAR3,
VAR30,
VAR23,
VAR60,
VAR26,
VAR45,
VAR14,
VAR15,
VAR7,
VAR36,
VAR11,
VAR67,
VAR53,
VAR51,
VAR8,
VAR68,
VAR55,
VAR24
)
;
output [ 13: 0] VAR33;
output [ 2: 0] VAR3;
output VAR30;
output [ 0: 0] VAR23;
inout [ 0: 0] VAR60;
inout [ 0: 0] VAR26;
output [ 0: 0] VAR45;
output [ 3: ... | gpl-3.0 |
everskar2013/PentiumX | Hardware/Code/wb_conbus_arb.v | 7,300 | module MODULE1(
clk,
rst,
req,
VAR3
);
input clk;
input rst;
input [ 1: 0] req; output VAR3;
parameter VAR4 = 1'h0,
VAR1 = 1'h1;
reg state = 0, VAR2 = 0;
assign VAR3 = state;
always@(posedge clk or posedge rst)
if(rst) state <= VAR4;
else state <= VAR2;
always@(state or req ) begin
VAR2 = state; case(state) VAR4:
if(!r... | mit |
SI-RISCV/e200_opensource | rtl/e203/subsys/e203_subsys_pll.v | 2,140 | module MODULE1(
input VAR7,
input VAR1, output VAR8,
input VAR3,
input [1:0] VAR5,
input [7:0] VAR6,
input [4:0] VAR4
);
wire VAR2;
assign VAR8 = VAR2;
endmodule | apache-2.0 |
Blunk-electronic/M-1 | HW/ise/trc_mini/src/bcd_to_7seg_dec.v | 1,374 | module MODULE1 (VAR1, VAR3, VAR2);
output reg [6:0] VAR3;
input [3:0] VAR1;
input VAR2;
reg [6:0] VAR4;
always @*
case (VAR1)
4'b0001 : VAR4 = 7'b1111001; 4'b0010 : VAR4 = 7'b0100100; 4'b0011 : VAR4 = 7'b0110000; 4'b0100 : VAR4 = 7'b0011001; 4'b0101 : VAR4 = 7'b0010010; 4'b0110 : VAR4 = 7'b0000010; 4'b0111 : VAR4 = 7'b... | gpl-2.0 |
plindstroem/oh | xilibs/hdl/MMCME2_ADV.v | 7,177 | module MODULE1 # (
parameter VAR26 = "VAR31",
parameter real VAR61 = 5.000,
parameter real VAR4 = 0.000,
parameter VAR42 = "VAR48",
parameter real VAR77 = 10.000,
parameter real VAR88 = 0.000,
parameter real VAR44 = 1.000,
parameter real VAR81 = 0.500,
parameter real VAR57 = 0.000,
parameter VAR46 = "VAR48",
parameter ... | gpl-3.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/CS_bak/synthesis/submodules/altera_up_video_ascii_rom_128.v | 4,305 | module MODULE1 (
clk,
VAR3,
VAR5,
VAR2,
VAR7,
VAR4
);
input clk;
input VAR3;
input [ 6: 0] VAR5;
input [ 2: 0] VAR2;
input [ 2: 0] VAR7;
output reg VAR4;
wire [12: 0] VAR6;
reg VAR1 [8191:0];
begin
begin | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_1.functional.pp.v | 1,772 | module MODULE1( VAR20, VAR26, VAR5, VAR10, VAR18, VAR1, VAR2 );
input VAR26, VAR10, VAR5;
inout VAR1, VAR2;
output VAR18, VAR20;
wire VAR9;
and VAR8( VAR9, VAR26, VAR10 );
wire VAR24;
and VAR3( VAR24, VAR26, VAR5 );
wire VAR15;
and VAR17( VAR15, VAR10, VAR5 );
or VAR28( VAR18, VAR9, VAR24, VAR15 );
wire VAR29;
and VAR7... | apache-2.0 |
Elphel/x393_sata | generated/action_decoder.v | 5,126 | module MODULE1 (
input clk,
input enable,
input [10:0] VAR1,
output reg VAR50,
output reg VAR12,
output reg VAR36,
output reg VAR2,
output reg VAR8,
output reg VAR34,
output reg VAR26,
output reg VAR41,
output reg VAR27,
output reg VAR40,
output reg VAR44,
output reg VAR5,
output reg VAR52,
output reg VAR16,
output reg... | gpl-3.0 |
peteasa/oh | src/gpio/hdl/axi_gpio.v | 7,844 | module MODULE1(
VAR56, VAR65, VAR42, VAR4, VAR84,
VAR72, VAR71, VAR44, VAR11, VAR3,
VAR14, VAR47, VAR19, VAR10,
VAR63, VAR76, VAR23, VAR55, VAR21,
VAR79, VAR43, VAR67, VAR13,
VAR28, VAR78, VAR5, VAR1, VAR37,
VAR2, VAR35, VAR33, VAR9,
VAR7, VAR85, VAR6, VAR22, VAR27,
VAR31, VAR45, VAR18, VAR12,
VAR26, VAR80, VAR29, VAR3... | mit |
lvd2/ngs | fpga/current/interrupts/timer.v | 1,367 | module MODULE1(
input wire VAR7,
input wire VAR3,
input wire [2:0] VAR9,
output reg VAR5
);
reg [ 2:0] VAR6;
reg [16:0] VAR4;
reg VAR2;
reg VAR1,VAR8,VAR10;
always @(posedge VAR7)
begin
if( !VAR6[2] )
VAR6 <= VAR6 + 3'd1;
end
else
VAR6 <= 3'd0;
end
begin
begin | gpl-3.0 |
cafe-alpha/wascafe | v13/wasca_10m08scv4k_no_spi_20190420/wasca/synthesis/submodules/wasca_nios2_gen2_0.v | 5,661 | module MODULE1 (
input wire clk, input wire VAR17, output wire [26:0] VAR2, output wire [3:0] VAR15, output wire VAR24, input wire [31:0] VAR6, input wire VAR3, output wire VAR22, output wire [31:0] VAR20, output wire VAR13, output wire [21:0] VAR21, output wire VAR1, input wire [31:0] VAR26, input wire VAR11, input wi... | gpl-2.0 |
camacazio/icestick_JSTK2_ORGB | source/ClkDiv_66_67kHz.v | 2,153 | module MODULE1(
VAR1, VAR3, VAR2 );
input VAR1;
input VAR3;
output VAR2;
reg VAR2 = 1'b1;
parameter VAR4 = 7'b1011010;
reg [6:0] VAR5 = 7'b0000000;
always @(posedge VAR1) begin
if(VAR3 == 1'b1) begin
VAR2 <= 1'b0;
VAR5 <= 0;
end
else begin
if(VAR5 == VAR4) begin
VAR2 <= ~VAR2;
VAR5 <= 0;
end
else begin
VAR5 <= VAR5 + 1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fahcon/sky130_fd_sc_hs__fahcon.functional.v | 2,591 | module MODULE1 (
VAR23,
VAR3 ,
VAR9 ,
VAR8 ,
VAR4 ,
VAR17 ,
VAR15
);
output VAR23;
output VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR4 ;
input VAR17 ;
input VAR15 ;
wire VAR11 ;
wire VAR16 ;
wire VAR22 ;
wire VAR20 ;
wire VAR18 ;
wire VAR6 ;
wire VAR5;
xor VAR13 (VAR11 , VAR9, VAR8, VAR4 );
VAR14 VAR19 (VAR16 , VAR11, V... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_rf_16x65.v | 13,061 | module MODULE1(
VAR30, VAR40, VAR77, VAR55, VAR45, VAR74, VAR65, VAR12, VAR70, VAR43, VAR39, VAR33, VAR64, VAR37, do
);
input VAR30;
input VAR40;
input VAR77;
input VAR55;
input VAR45;
input VAR74;
input VAR65;
input [4:0] VAR12;
input [3:0] VAR70;
input [3:0] VAR43;
input [64:0] VAR39;
input VAR33;
output VAR64;
outpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlclkp/sky130_fd_sc_ms__dlclkp_4.v | 2,154 | module MODULE1 (
VAR5,
VAR3,
VAR2 ,
VAR7,
VAR1,
VAR8 ,
VAR9
);
output VAR5;
input VAR3;
input VAR2 ;
input VAR7;
input VAR1;
input VAR8 ;
input VAR9 ;
VAR6 VAR4 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR5,
VAR3,
VAR2
);
output VAR5;
inpu... | apache-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/unencoded_cam_lut_sm.v | 9,208 | module MODULE1
parameter VAR31 = 3,
parameter VAR42 = 16,
parameter VAR46 = VAR1(VAR42),
parameter VAR9 = 0, parameter VAR4 = {VAR31{1'b0}}, parameter VAR3 = {VAR8{1'b0}}, parameter VAR29 = {VAR8{1'b0}} )
( input VAR53,
input [VAR8-1:0] VAR49,
input [VAR8-1:0] VAR18,
output reg VAR50,
output reg VAR25,
output [VAR31-1:... | apache-2.0 |
CospanDesign/nysa-artemis-platform | artemis/infrastructure/artemis_infrastructure.v | 29,719 | module MODULE1 (
input VAR106,
output clk,
input VAR63,
output VAR250,
output VAR74,
input VAR212,
input VAR239,
output rst,
output VAR246,
input VAR174,
inout [7:0] VAR82,
output [13:0] VAR148,
output [2:0] VAR83,
output VAR129,
output VAR103,
output VAR11,
output VAR170,
output VAR26,
output VAR142,
output VAR119,
in... | gpl-2.0 |
google/globalfoundries-pdk-ip-gf180mcu_fd_ip_sram | cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/gf180mcu_fd_ip_sram__sram256x8m8wm1.v | 16,447 | module MODULE1 (
VAR18,
VAR47,
VAR32,
VAR4,
VAR27,
VAR29,
VAR36,
VAR6,
VAR2
);
input VAR18;
input VAR47; input VAR32; input [7:0] VAR4; input [7:0] VAR27;
input [7:0] VAR29;
output [7:0] VAR36;
inout VAR6;
inout VAR2;
reg [7:0] VAR15[255:0];
reg [7:0] VAR12;
wire VAR19;
wire VAR48;
wire VAR39;
reg VAR28; reg VAR34;
reg... | apache-2.0 |
chiragsakhuja/gpu | frag_block.v | 10,796 | module MODULE1 (
VAR34,
VAR41,
VAR57,
VAR11,
VAR40,
VAR30,
VAR15,
VAR44,
VAR61);
input [5:0] VAR34;
input [5:0] VAR41;
input VAR57;
input [15:0] VAR11;
input [15:0] VAR40;
input VAR30;
input VAR15;
output [15:0] VAR44;
output [15:0] VAR61;
tri1 VAR57;
tri0 VAR30;
tri0 VAR15;
wire [15:0] VAR46;
wire [15:0] VAR25;
wire [... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_2.behavioral.v | 3,781 | module MODULE1( VAR9, VAR29, VAR12, VAR22 );
input VAR9, VAR29, VAR12;
output VAR22;
reg VAR15;
VAR7 VAR32(.VAR9(VAR9),.VAR29(VAR29),.VAR12(VAR12),.VAR22(VAR22),.VAR15(VAR15));
VAR7 VAR1(.VAR9(VAR9),.VAR29(VAR29),.VAR12(VAR12),.VAR22(VAR22),.VAR15(VAR15));
not VAR13(VAR20,VAR29);
and VAR4(VAR11,VAR12,VAR20);
and VAR16(... | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/iss/pli/sjm/rtl/sjm.v | 10,706 | module MODULE1 (VAR58,
VAR55,
VAR35,
VAR53,
VAR37,
VAR66,
VAR4,
VAR38,
VAR1,
VAR62,
VAR13,
VAR41,
VAR31,
VAR36,
VAR23,
VAR21,
VAR14,
VAR3
);
input [2:0] VAR58;
input [5:0] VAR55;
output [5:0] VAR35;
inout [127:0] VAR53;
inout [3:0] VAR37;
inout [7:0] VAR66;
inout [2:0] VAR4;
inout [2:0] VAR38;
inout [2:0] VAR1;
inout [... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fahcon/sky130_fd_sc_hs__fahcon.behavioral.v | 2,591 | module MODULE1 (
VAR5,
VAR11 ,
VAR1 ,
VAR10 ,
VAR4 ,
VAR24 ,
VAR15
);
output VAR5;
output VAR11 ;
input VAR1 ;
input VAR10 ;
input VAR4 ;
input VAR24 ;
input VAR15 ;
wire VAR3 ;
wire VAR23 ;
wire VAR18 ;
wire VAR19 ;
wire VAR7 ;
wire VAR17 ;
wire VAR22;
xor VAR21 (VAR3 , VAR1, VAR10, VAR4 );
VAR9 VAR6 (VAR23 , VAR3, VA... | apache-2.0 |
aquaxis/FPGAMAG18 | modules/axim_v1/src/fmrv32im_axim.v | 9,898 | module MODULE1
(
input VAR60,
input VAR69,
output [0:0] VAR58,
output [31:0] VAR82,
output [7:0] VAR6,
output [2:0] VAR12,
output [1:0] VAR16,
output VAR59,
output [3:0] VAR38,
output [2:0] VAR2,
output [3:0] VAR64,
output [0:0] VAR33,
output VAR5,
input VAR9,
output [31:0] VAR87,
output [3:0] VAR7,
output VAR24,
outpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3b/sky130_fd_sc_ls__nor3b_4.v | 2,254 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR10 ,
VAR6 ,
VAR9,
VAR7,
VAR8 ,
VAR5
);
output VAR4 ;
input VAR2 ;
input VAR10 ;
input VAR6 ;
input VAR9;
input VAR7;
input VAR8 ;
input VAR5 ;
VAR1 VAR3 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
kevintownsend/inara-hdl-libraries | linked_fifo/linked_fifo_gold.v | 1,561 | module MODULE1(rst, clk, VAR15, VAR2, VAR1, VAR8, VAR16, VAR12, VAR6, VAR18, VAR14);
parameter VAR7 = 8;
parameter VAR4 = 32;
parameter VAR17 = 8;
parameter VAR9 = VAR3(VAR17-1);
parameter VAR13 = VAR3(VAR4-1);
input rst, clk, VAR15;
input [VAR9-1:0] VAR2;
input VAR1;
input [VAR9-1:0] VAR8;
input [VAR7-1:0] VAR16;
outp... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrbp/sky130_fd_sc_hs__dfrbp.functional.v | 1,888 | module MODULE1 (
VAR13 ,
VAR12 ,
VAR9 ,
VAR15 ,
VAR1 ,
VAR8 ,
VAR7
);
input VAR13 ;
input VAR12 ;
output VAR9 ;
output VAR15 ;
input VAR1 ;
input VAR8 ;
input VAR7;
wire VAR10;
wire VAR11;
not VAR6 (VAR11 , VAR7 );
VAR3 VAR2 VAR14 (VAR10 , VAR8, VAR1, VAR11, VAR13, VAR12);
buf VAR5 (VAR9 , VAR10 );
not VAR4 (VAR15 , VA... | apache-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/acl_ic_mem_router_reorder.v | 14,258 | module MODULE1 #(
parameter integer VAR1 = 256, parameter integer VAR106 = 1, parameter integer VAR92 = 32, parameter integer VAR39 = VAR1 / 8,
parameter integer VAR35 = 8, parameter integer VAR54 = VAR92-VAR58(VAR35),
parameter integer VAR82 = 2*2**VAR106-4, parameter integer VAR94 = 2047,
parameter VAR15 = VAR82 + 3 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinvlp/sky130_fd_sc_lp__clkinvlp.blackbox.v | 1,252 | module MODULE1 (
VAR6,
VAR1
);
output VAR6;
input VAR1;
supply1 VAR2;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
Microsoft/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RX_MSG.v | 6,939 | module MODULE1(
input VAR24,
input VAR30,
input [7:0] VAR22,
output reg [39:0] VAR7,
output reg VAR23,
output reg VAR25,
output reg VAR11,
output reg VAR19
);
reg [7:0] VAR6;
always@(posedge VAR24) VAR6[7:0] <= VAR22[7:0];
parameter VAR1 = 8'hF5;
parameter VAR16 = 8'h06;
parameter VAR21 = 8'h5F;
parameter VAR20 = 8'hAF... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/fill/sky130_fd_sc_hvl__fill.pp.symbol.v | 1,179 | module MODULE1 (
input VAR2 ,
input VAR1,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/engine_layer.v | 27,104 | module MODULE1
parameter VAR122 = 128,
parameter VAR143=6,
parameter VAR62 = 1,
parameter VAR115 = 0,
parameter VAR18 = 64,
parameter VAR123="VAR146"
)
(
input VAR127,
input VAR108,
input [VAR65-1:0] VAR97,
input [VAR122-1:0] VAR106,
input VAR121,
input VAR21,
input [VAR13-1:0] VAR28,
input VAR102,
input [VAR13-1:0] VA... | gpl-3.0 |
Kipsora/MIPS-CPU | source/machine/cpu/stages/id.v | 41,363 | module MODULE1(
input wire reset,
input wire[VAR6] VAR1,
input wire[VAR20] VAR14,
input wire VAR18,
input wire[VAR40] VAR13,
input wire[VAR47] VAR31,
input wire VAR51,
input wire[VAR40] VAR37,
input wire[VAR47] VAR4,
input wire[VAR47] VAR12,
input wire[VAR47] VAR9,
input wire VAR15,
input wire[VAR21] VAR25,
output wire... | mit |
minosys-jp/FPGA | Zybo/fillbox/HDL/fillbox_v1_0_S00_AXI.v | 13,804 | module MODULE1 #
(
parameter integer VAR36 = 32,
parameter integer VAR9 = 5
)
(
output wire [27:0] VAR32,
output wire [9:0] VAR47,
output wire [9:0] VAR3,
output wire [15:0] VAR33,
output wire VAR12,
input wire VAR38,
input wire VAR6,
input wire VAR1,
input wire [VAR9-1 : 0] VAR18,
input wire [2 : 0] VAR22,
input wire ... | bsd-2-clause |
scalable-networks/ext | uhd/fpga/usrp2/models/gpmc_model_sync.v | 2,427 | module MODULE1
(output reg VAR1, inout [15:0] VAR4, output reg [10:1] VAR2, output reg [1:0] VAR6,
output reg VAR3, output reg VAR7, output reg VAR10,
output reg VAR5, output reg VAR8 );
reg [15:0] VAR9;
assign VAR4 = VAR9;
begin
begin
end
begin
end
begin | gpl-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/10KEYBOARD/Version_01/02 verilog/Touch/MódulosBásicos/PruebaPs2/ps2.v | 1,228 | module MODULE1 (
input VAR11,
input VAR8,
output reg VAR5,
output [7:0] VAR4,
output reg VAR12
);
reg [8:0] VAR1;
reg [7:0] VAR6;
reg [3:0] VAR2;
reg [3:0] VAR3;
reg [1:0] VAR7;
reg VAR10;
reg VAR9;
begin
begin
begin
begin
begin
begin
begin
begin
begin
end
begin
begin
begin
end
begin | gpl-3.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_03_a/hdl/verilog/spi_top.v | 6,380 | module MODULE1
(
VAR4, VAR15,
VAR38, VAR16, VAR35, VAR17, VAR9, VAR1, VAR7,
VAR41, VAR29, VAR18
);
parameter VAR10 = 1;
input VAR4; input VAR15;
input [13:0] VAR38;
input [7:0] VAR16;
input VAR35;
input [17:0] VAR17;
input VAR9;
input VAR1;
output VAR7;
output [VAR31-1:0] VAR41; output VAR29; output VAR18;
wire [VAR5-1... | bsd-2-clause |
toyoshim/tvcl | sample/RAM_spartan-3-starterkit.v | 4,982 | module MODULE1(
VAR7,
VAR69,
VAR32,
VAR57,
VAR64,
VAR35,
VAR26,
VAR52,
VAR31,
VAR45,
VAR51,
VAR3,
VAR55,
VAR8,
VAR68,
VAR44,
VAR4,
VAR6,
VAR15,
VAR25,
VAR56,
VAR62,
VAR33,
VAR59,
VAR48,
VAR38,
VAR53,
VAR46,
VAR37,
VAR27,
VAR60,
VAR42,
VAR17,
VAR10,
VAR29,
VAR39,
VAR63,
VAR23,
VAR74);
input VAR7;
input VAR69;
output [17... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.blackbox.v | 1,204 | module MODULE1 (
VAR4 ,
VAR2,
VAR3,
VAR1
);
output VAR4 ;
input VAR2;
input VAR3;
input VAR1 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_project/fifo_40x128/fifo_40x128_bb.v | 5,585 | module MODULE1 (
VAR2,
VAR7,
VAR4,
VAR3,
VAR5,
VAR8,
VAR1,
VAR9,
VAR6);
input [39:0] VAR2;
input VAR7;
input VAR4;
input VAR3;
input VAR5;
output [39:0] VAR8;
output VAR1;
output VAR9;
output [6:0] VAR6;
endmodule | gpl-3.0 |
timtian090/Playground | UVM/UVMPlayground/Lab2/Lab2-Project/CLS_Scan_Rate_Timer.v | 3,146 | module MODULE1
parameter VAR12 = 50000000 )
(
input [1:0] VAR8,
output reg VAR3,
input VAR10
);
localparam VAR4 = 32; localparam VAR15 = 16; localparam VAR14 = 8; localparam VAR19 = 2;
localparam VAR13 = VAR12 / VAR19;
localparam VAR1 = VAR9(VAR13);
localparam [VAR1:0] VAR5 = 1.0 * VAR12 / VAR4;
localparam [VAR1:0] VAR... | mit |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/spoof.v | 2,621 | module MODULE1(
VAR27,
VAR24,
VAR26,
VAR19,
reset,
VAR8
);
input [31:0] VAR27;
input VAR24;
input VAR26;
input reset;
output VAR19;
output VAR8;
localparam VAR17 = 3'd0,
VAR2 = 3'd1,
VAR13 = 3'd2,
VAR6 = 3'd3,
VAR7 = 3'd4,
VAR22 = 3'd5,
VAR9 = 3'd6,
VAR20 = 3'd7;
localparam VAR23 = 32'h15000000,
VAR25 = 32'h15000000,
V... | gpl-3.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/Computer_System/synthesis/submodules/altera_up_edge_detection_data_shift_register.v | 5,121 | module MODULE1 (
VAR15,
VAR13,
VAR9,
VAR1,
VAR5);
parameter VAR3 = 10;
parameter VAR7 = 720;
input VAR15;
input VAR13;
input [VAR3:1] VAR9;
output [VAR3:1] VAR1;
output [VAR3:1] VAR5;
wire [VAR3:1] VAR2;
wire [VAR3:1] VAR12;
wire [VAR3:1] VAR5 = VAR2[VAR3:1];
wire [VAR3:1] VAR1 = VAR12[VAR3:1];
VAR8 VAR6 (
.VAR15 (VAR1... | mit |
ptracton/wb_soc_template | rtl/MOR1KX/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v | 11,815 | module MODULE1
parameter VAR21 = 32,
parameter VAR100 = {{(VAR21-13){1'b0}},
parameter VAR99 = 5,
parameter VAR14 = "VAR87", parameter VAR25 = "VAR57"
)
(
input clk,
input rst,
input VAR88,
input VAR39,
input VAR50,
input VAR76,
input VAR53,
input VAR26,
input VAR42,
input VAR4,
input VAR44,
input VAR38,
input VAR62,
i... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31oi/sky130_fd_sc_hs__a31oi.symbol.v | 1,333 | module MODULE1 (
input VAR3,
input VAR7,
input VAR6,
input VAR1,
output VAR4
);
supply1 VAR5;
supply0 VAR2;
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_001.v | 1,531 | module MODULE2 (
VAR6,
VAR4
);
input [31:0] VAR6;
output [31:0]
VAR4;
wire [31:0]
VAR14,
VAR11,
VAR3,
VAR10,
VAR8,
VAR13,
VAR2,
VAR1,
VAR9;
assign VAR14 = VAR6;
assign VAR13 = VAR3 << 4;
assign VAR9 = VAR2 - VAR1;
assign VAR2 = VAR8 - VAR13;
assign VAR8 = VAR10 - VAR3;
assign VAR10 = VAR14 << 14;
assign VAR1 = VAR14 <<... | mit |
luebbers/reconos | support/refdesigns/10.1/xup/eth_tft_cf/pcores/opb_ps2_dual_ref_v1_00_a/hdl/verilog/ps2.v | 7,076 | module MODULE1 (
VAR9, VAR2, VAR16, VAR22, VAR12, VAR3, VAR27, VAR14, VAR30, VAR6, VAR31, VAR24, VAR25, VAR23, VAR17, VAR33, VAR10 );
input VAR9; input VAR2; input [0:7] VAR16; input [0:7] VAR22; input VAR12; input VAR3; output [0:7] VAR27; output VAR14; output VAR30; output VAR6; output VAR31; output VAR24; output VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/decap/sky130_fd_sc_hs__decap.pp.symbol.v | 1,169 | module MODULE1 (
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_1.functional.v | 1,064 | module MODULE1( VAR12, VAR11, VAR10, VAR7, VAR3 );
input VAR10, VAR11, VAR12, VAR3;
output VAR7;
or VAR9( VAR8, VAR11, VAR12 );
VAR6( VAR5, 1'b0, 1'b0, VAR10, VAR8, VAR3 );
wire VAR2;
not VAR1( VAR2, VAR5 );
or VAR4( VAR7, VAR10, VAR2 );
endmodule | apache-2.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/imports/new/music.v | 5,258 | module MODULE1 (
input [7:0] VAR11,
input clk,
output reg [31:0] VAR7
);
parameter VAR10 = 523;
parameter VAR4 = 587;
parameter VAR6 = 660;
parameter VAR2 = 698;
parameter VAR8 = 745;
parameter VAR5 = 784;
parameter VAR9 = 880;
parameter VAR3 = 932;
parameter VAR12 = 988;
parameter VAR1 = 20000;
always @(posedge clk) b... | gpl-3.0 |
eecsninja/duinocube-core | common/display_controller.v | 6,539 | module MODULE3(clk, reset, VAR22, VAR5, VAR25);
input clk; input reset; input [VAR33-1:0] VAR25;
output reg [VAR11-1:0] VAR22; output reg [VAR11-1:0] VAR5;
wire VAR31, VAR6;
MODULE1 MODULE2(.VAR22(VAR22),
.VAR5(VAR5),
.VAR31(VAR31),
.VAR6(VAR6),
.VAR25(VAR25));
reg VAR21;
always @ (posedge clk or posedge reset)
if (res... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbp/sky130_fd_sc_hs__dlxbp.functional.v | 1,747 | module MODULE1 (
VAR3,
VAR11,
VAR13 ,
VAR7 ,
VAR5 ,
VAR10
);
input VAR3;
input VAR11;
output VAR13 ;
output VAR7 ;
input VAR5 ;
input VAR10;
wire VAR8 VAR12;
wire VAR8 VAR2 ;
wire VAR8 ;
VAR1 VAR6 VAR14 (VAR8 , VAR5, VAR10, VAR3, VAR11);
buf VAR9 (VAR13 , VAR8 );
not VAR4 (VAR7 , VAR8 );
endmodule | apache-2.0 |
YurongYou/MIPS_CPU | pipeline_CPU.v | 11,250 | module MODULE1 (
input clk,
input rst,
input[VAR115-1:0] VAR105,
output[VAR198-1:0] VAR93,
output[3:0] VAR73,
output[VAR115-1:0] VAR13,
output VAR196,
output VAR4,
input[VAR160-1:0] VAR169,
output[VAR48-1:0] VAR154,
output VAR116
);
supply1 VAR149;
supply0 VAR144;
wire[1:0] VAR179;
wire[1:0] VAR142;
wire[1:0] VAR17;
wi... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxbp/sky130_fd_sc_hs__sedfxbp.functional.pp.v | 2,092 | module MODULE1 (
VAR10 ,
VAR8 ,
VAR17 ,
VAR18 ,
VAR20 ,
VAR4 ,
VAR16 ,
VAR11,
VAR7
);
output VAR10 ;
output VAR8 ;
input VAR17 ;
input VAR18 ;
input VAR20 ;
input VAR4 ;
input VAR16 ;
input VAR11;
input VAR7;
wire VAR9 ;
wire VAR15;
wire VAR2 ;
VAR13 VAR3 (VAR15, VAR2, VAR4, VAR16 );
VAR13 VAR12 (VAR2 , VAR9, VAR18, VA... | apache-2.0 |
qeedquan/fpga | de2-115/nios_lights/lights/synthesis/submodules/lights_nios2_qsys_0_jtag_debug_module_wrapper.v | 10,255 | module MODULE1 (
VAR51,
VAR42,
clk,
VAR21,
VAR14,
VAR5,
VAR57,
VAR41,
VAR20,
VAR12,
VAR39,
VAR17,
VAR11,
VAR50,
VAR56,
VAR15,
VAR31,
VAR26,
VAR47,
VAR9,
VAR10,
VAR22,
VAR18,
VAR36,
VAR13,
VAR33,
VAR37,
VAR6,
VAR16,
VAR54,
VAR35,
VAR60,
VAR55,
VAR49,
VAR46,
VAR8
)
;
output [ 37: 0] VAR10;
output VAR22;
output VAR18;
out... | mit |
benreynwar/fpga-sdrlib | verilog/message/qa_splitcombiner.v | 1,664 | module MODULE1
parameter VAR17 = 32
)
(
input wire clk,
input wire reset,
input wire [VAR17-1:0] VAR19,
input wire VAR7,
output reg [VAR17-1:0] VAR16,
output reg VAR9
);
wire [VAR17-1:0] VAR10;
wire [VAR17-1:0] VAR3;
wire [VAR17-1:0] VAR13;
wire VAR1;
wire VAR8;
wire VAR18;
wire VAR14;
assign VAR14 = ~reset;
VAR2 #(2, ... | mit |
hydai/Verilog-Practice | HardwareLab/Lab8/WhacAMole.v | 2,912 | module MODULE1(VAR10, VAR18, VAR5, VAR4, VAR19, VAR12, VAR9, reset, VAR6);
input VAR9, reset, VAR6;
input [3:0] VAR4;
input [3:0] VAR19;
input VAR12;
output [3:0] VAR10, VAR18;
output [4:0] VAR5;
reg [4:0] VAR5;
wire [4:0] VAR3;
reg [3:0] VAR18, VAR10;
wire [3:0] VAR15, VAR14;
reg[19:0] VAR13, VAR2; reg [1:0] state, VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311a/sky130_fd_sc_hs__o311a.pp.symbol.v | 1,346 | module MODULE1 (
input VAR2 ,
input VAR1 ,
input VAR3 ,
input VAR7 ,
input VAR6 ,
output VAR5 ,
input VAR8,
input VAR4
);
endmodule | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_sa1/bsx.v | 8,798 | module MODULE1(
input VAR27,
input VAR24,
input VAR52,
input VAR14,
input [23:0] VAR28,
input [7:0] VAR56,
output [7:0] VAR25,
input [7:0] VAR36,
input [7:0] VAR31,
output [14:0] VAR20,
input VAR23,
input VAR2,
output VAR4,
output VAR57,
input [59:0] VAR40,
output [9:0] VAR53, output VAR38,
output [8:0] VAR7
);
wire [3... | gpl-2.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/rtr_top.v | 22,541 | module MODULE1
(clk, reset, VAR150, VAR98, VAR13, VAR92,
VAR174, VAR8);
parameter VAR76 = 32;
parameter VAR22 = 2;
parameter VAR37 = 2;
parameter VAR190 = 1;
parameter VAR38 = 4;
parameter VAR50 = 2;
parameter VAR192 = 1;
parameter VAR145 = VAR188;
parameter VAR111 = VAR47;
parameter VAR42 = VAR15;
parameter VAR136 = 1... | gpl-2.0 |
xuefei1/ElectronicEngineControl | niosII_system/synthesis/submodules/niosII_system_solenoid_out.v | 2,473 | module MODULE1 (
address,
VAR9,
clk,
VAR1,
VAR6,
VAR7,
VAR10,
VAR8
)
;
output [ 7: 0] VAR10;
output [ 31: 0] VAR8;
input [ 2: 0] address;
input VAR9;
input clk;
input VAR1;
input VAR6;
input [ 31: 0] VAR7;
wire VAR3;
reg [ 7: 0] VAR4;
wire [ 7: 0] VAR10;
wire [ 7: 0] VAR5;
wire [ 31: 0] VAR8;
wire VAR2;
assign VAR3 = 1... | apache-2.0 |
diegovalverde/papiGB | rtl/dzcpu.v | 38,687 | module MODULE1
(
input wire VAR204,
input wire VAR57,
input wire [7:0] VAR278,
output wire [7:0] VAR194,
output wire [15:0] VAR61,
output wire VAR74,
input wire [3:0] VAR176,
output reg VAR254,
output wire [7:0] VAR9,
output wire VAR49,
output wire VAR23,
output wire VAR7,
input wire [5:0] VAR262
);
wire[15:0] VAR227, ... | gpl-2.0 |
rhalstea/cidr_15_fpga_join | probe_engine/verilog/sync_3_fifo.v | 3,338 | module MODULE1 (
input clk,
input rst,
output [2:0] VAR14,
input [2:0] VAR12,
input [63:0] VAR7,
input [63:0] VAR9,
input [63:0] VAR6,
output VAR13,
input VAR3,
output [63:0] VAR1,
output [63:0] VAR19,
output [63:0] VAR10
);
wire [2:0] VAR11;
VAR4 VAR8 (
.clk (clk),
.rst (rst),
.din (VAR6),
.VAR20 (VAR12[0]),
.VAR16 (V... | bsd-3-clause |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/rw_manager_inst_ROM_reg.v | 1,430 | module MODULE1(
VAR2,
VAR9,
VAR7,
VAR1,
VAR5,
VAR4);
parameter VAR3 = "";
parameter VAR6 = "";
input [(VAR6-1):0] VAR2;
input VAR9;
input [(VAR6-1):0] VAR1;
input [(VAR3-1):0] VAR7;
input VAR5;
output reg [(VAR3-1):0] VAR4;
reg [(VAR3-1):0] VAR8[(2**VAR6-1):0];
always @(posedge VAR9)
begin
if (VAR5)
VAR8[VAR1]<= VAR7;
... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/minimig/denise_bitplane_shifter.v | 4,824 | module MODULE1
(
input wire clk, input wire VAR10, input wire VAR6, input wire VAR14, input wire VAR9, input wire VAR13, input wire VAR2, input wire [ 2-1:0] VAR7, input wire [ 64-1:0] VAR15, input wire [ 8-1:0] VAR16, output wire out );
reg [ 6-1:0] VAR11; reg [64-1:0] VAR5; reg [64-1:0] VAR3; reg VAR12; reg [ 6-1:0] ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_2.functional.pp.v | 1,027 | module MODULE1( VAR18, VAR11, VAR6, VAR5, VAR3, VAR19, VAR12, VAR14 );
input VAR18, VAR11, VAR5, VAR6, VAR19, VAR12, VAR14;
output VAR3;
not VAR2( VAR7, VAR18 );
not VAR9( VAR15, VAR5 );
not VAR10( VAR13, VAR6 );
not VAR4( VAR16, VAR11 );
VAR17( VAR8, VAR13, VAR15, VAR7, VAR16, VAR14 );
not VAR1( VAR3, VAR8 );
endmodul... | apache-2.0 |
csturton/wirepatch | system/hardware/cores/or1200/or1200_ic_ram.v | 4,354 | module MODULE1(
clk, rst,
VAR5, VAR14, VAR15,
addr, en, VAR1, VAR4, VAR6
);
parameter VAR16 = VAR10;
parameter VAR3 = VAR11;
input clk;
input rst;
input [VAR3-1:0] addr;
input en;
input [3:0] VAR1;
input [VAR16-1:0] VAR4;
output [VAR16-1:0] VAR6;
input VAR5;
input [VAR12 - 1:0] VAR15;
output VAR14;
assign VAR6 = {VAR16... | mit |
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