repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
asicguy/gplgpu | hdl/de/dex_smlablt.v | 11,515 | module MODULE1
(
input VAR44,
input VAR6,
input VAR11,
input VAR87,
input VAR76,
input VAR24,
input VAR33,
input VAR1,
input VAR68,
input VAR94,
input VAR8,
input [2:0] VAR40,
input VAR41,
input VAR72,
input VAR88,
input VAR17,
input VAR82,
output reg [21:0] VAR86,
output reg [4:0] VAR70,
output reg VAR7,
output reg VA... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_4.behavioral.pp.v | 3,792 | module MODULE1( VAR9, VAR27, VAR31, VAR17, VAR14, VAR10 );
input VAR9, VAR27, VAR31;
inout VAR14, VAR10;
output VAR17;
reg VAR22;
VAR8 VAR25(.VAR9(VAR9),.VAR27(VAR27),.VAR31(VAR31),.VAR17(VAR17),.VAR14(VAR14),.VAR10(VAR10),.VAR22(VAR22));
VAR8 VAR2(.VAR9(VAR9),.VAR27(VAR27),.VAR31(VAR31),.VAR17(VAR17),.VAR14(VAR14),.VA... | apache-2.0 |
azonenberg/yosys | techlibs/greenpak4/cells_map.v | 5,303 | module MODULE8(input VAR9, VAR38, VAR24, output reg VAR18);
parameter [0:0] VAR3 = 1'VAR41;
VAR26 #(
.VAR3(VAR3),
.VAR22(1'b1),
) VAR37 (
.VAR9(VAR9),
.VAR38(VAR38),
.VAR4(VAR24),
.VAR18(VAR18)
);
endmodule
module MODULE10(input VAR9, VAR38, VAR27, output reg VAR18);
parameter [0:0] VAR3 = 1'VAR41;
VAR26 #(
.VAR3(VAR3)... | isc |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/wb_conmax/wb_conmax_master_if.v | 22,791 | module MODULE1(
VAR152, VAR59,
VAR93, VAR51, VAR27, VAR73, VAR33, VAR40,
VAR74, VAR65, VAR147, VAR173,
VAR24, VAR38, VAR95, VAR85, VAR35, VAR120,
VAR99, VAR128, VAR57, VAR86,
VAR188, VAR192, VAR179, VAR110, VAR8, VAR23,
VAR10, VAR15, VAR135, VAR4,
VAR104, VAR56, VAR139, VAR132, VAR106, VAR155,
VAR76, VAR6, VAR100, VAR1... | gpl-2.0 |
asicguy/gplgpu | hdl/altera_ddr3/alt_ddrx_timers_fsm.v | 45,504 | module MODULE1 #
( parameter
VAR51 = 10,
VAR11 = 10,
VAR24 = 10,
VAR3 = 10,
VAR129 = 10,
VAR109 = 10,
VAR108 = 10,
VAR164 = 10,
VAR10 = 10,
VAR91 = 10,
VAR186 = 10,
VAR106 = 10,
VAR61 = 10,
VAR151 = 10,
VAR192 = 10,
VAR12 = 10,
VAR156 = 10
)
(
VAR191,
VAR16,
VAR149,
VAR63,
VAR136,
VAR100,
VAR54,
VAR4,
VAR119,
VAR198,
V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111ai/sky130_fd_sc_hs__o2111ai.functional.pp.v | 1,987 | module MODULE1 (
VAR14,
VAR7,
VAR8 ,
VAR10 ,
VAR5 ,
VAR6 ,
VAR1 ,
VAR12
);
input VAR14;
input VAR7;
output VAR8 ;
input VAR10 ;
input VAR5 ;
input VAR6 ;
input VAR1 ;
input VAR12 ;
wire VAR1 VAR16 ;
wire VAR13 ;
wire VAR4;
or VAR9 (VAR16 , VAR5, VAR10 );
nand VAR15 (VAR13 , VAR1, VAR6, VAR12, VAR16 );
VAR3 VAR11 (VAR4,... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/hrfp_1.0/hrfp_mult_round_final.v | 7,369 | module MODULE1(
input wire clk,
input wire VAR16,
input wire VAR28,
input wire VAR15,VAR24, VAR26, VAR18,
input wire [53:0] VAR4, VAR27,
input wire [VAR20-1:0] VAR23,
input wire [VAR2-1:0] VAR12,
input wire [53:0] VAR21,VAR22,
input wire [VAR2-1+1:0] VAR17, VAR14,
output wire [VAR9:0] VAR25);
parameter VAR6 = 0;
reg [5... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dmac_v1_00_a/hdl/verilog/dest_fifo_inf.v | 4,524 | module MODULE1 (
input clk,
input VAR32,
input enable,
output VAR24,
input VAR29,
output VAR2,
input [VAR9-1:0] VAR6,
output [VAR9-1:0] VAR4,
output [VAR9-1:0] VAR19,
input VAR13,
input VAR40,
input en,
output [VAR20-1:0] dout,
output reg valid,
output reg VAR41,
output VAR3,
input VAR28,
input [VAR20-1:0] VAR31,
input... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_pwrgood_pp_pg_s/sky130_fd_sc_hdll__udp_pwrgood_pp_pg_s.blackbox.v | 1,361 | module MODULE1 (
VAR4,
VAR1 ,
VAR5 ,
VAR2 ,
VAR3
);
output VAR4;
input VAR1 ;
input VAR5 ;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
lokisz/openzcore | pippo-riscv/rtl/verilog/pippo_wbmux.v | 2,009 | module MODULE1(
clk, rst,
VAR6, VAR2,
VAR1, VAR11, VAR9, VAR5,
VAR12, VAR10
);
parameter VAR8 = VAR7;
input clk;
input rst;
input VAR6;
input [VAR8-1:0] VAR1; input [VAR8-1:0] VAR11; input [VAR8-1:0] VAR9; input [VAR8-1:0] VAR5;
input [VAR4-1:0] VAR2;
output [VAR8-1:0] VAR12; output [VAR8-1:0] VAR10;
reg [VAR8-1:0] VAR... | gpl-2.0 |
aap/pdp6 | verilog/iobus_2_connect.v | 2,415 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR15,
input wire VAR36,
input wire VAR1,
input wire VAR6,
input wire VAR10,
input wire VAR4,
input wire VAR14,
input wire VAR39,
input wire VAR34,
input wire [3:9] VAR26,
input wire [0:35] VAR20,
output wire [1:7] VAR5,
output wire [0:35] VAR27,
output wire ... | mit |
aquaxis/synverll | lib/llvm_memcpy/aq_axi_memcpy32.v | 6,224 | module MODULE1
(
input VAR57,
input VAR92,
output [0:0] VAR106,
output [31:0] VAR107,
output [7:0] VAR38,
output [2:0] VAR31,
output [1:0] VAR88,
output VAR78,
output [3:0] VAR46,
output [2:0] VAR74,
output [3:0] VAR6,
output [0:0] VAR69,
output VAR15,
input VAR129,
output [63:0] VAR119,
output [7:0] VAR26,
output VAR1... | mit |
lvd2/ngs | fpga/obsolete/fpgaF_dma2/sound/sound_mulacc.v | 3,386 | module MODULE1(
VAR2,
VAR13, VAR7,
VAR15,
VAR14, VAR17,
ready, VAR12 );
input VAR2;
input [5:0] VAR13;
input [7:0] VAR7;
input VAR15;
input VAR14;
input VAR17;
output reg ready;
output reg [15:0] VAR12;
wire [5:0] VAR5;
wire [6:0] VAR10;
reg [6:0] VAR18;
reg [7:0] VAR9;
reg [5:0] VAR6;
wire VAR8;
reg [3:0] counter;
reg... | gpl-3.0 |
freecores/tiny_tate_bilinear_pairing | group_size_is_151_bits/rtl/fsm.v | 4,375 | module MODULE1(clk, reset, VAR10, VAR17, VAR31, VAR32, VAR21, VAR12, VAR29);
input clk;
input reset;
output reg [8:0] VAR10;
input [25:0] VAR17;
output reg [5:0] VAR31;
output reg [5:0] VAR32;
output VAR21;
output reg [10:0] VAR12;
output reg VAR29;
reg [5:0] state;
parameter VAR16=0, VAR4=1, VAR14=2, VAR11=4, VAR28=8,... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_decode.v | 1,423 | module MODULE1
,localparam VAR5 = VAR1(VAR2)
)
(input [VAR5-1:0] VAR10
, output logic [VAR3(VAR2, 2):0] VAR8
, output logic [VAR3(VAR2, 2):0] VAR4
);
genvar VAR9;
generate
if (VAR2 == 1) begin: VAR6
assign VAR4[0] = 1'b1;
assign VAR8[0] = 1'b0;
end
else begin: VAR7
for(VAR9=0; VAR9<VAR2-1; VAR9++) begin: VAR12
if(VAR9 ... | bsd-3-clause |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/altera_pli_streaming.v | 3,156 | module MODULE1 (
clk,
VAR9,
VAR12,
VAR13,
VAR4,
VAR6,
VAR2,
VAR10,
VAR1
);
parameter VAR20 = 50000;
parameter VAR8 = 0;
input clk;
input VAR9;
output reg VAR12;
output reg [7 : 0] VAR13;
input VAR4;
input VAR6;
input [7 : 0] VAR2;
output reg VAR10;
output reg VAR1;
reg VAR5;
reg VAR16;
reg [7 : 0] VAR3;
always @(posedg... | gpl-3.0 |
MeshSr/onetswitch30 | ons30-app21-ref_switch/vivado/onets_7030_4x_ref_switch/ip/ref_switch_core/src/core/axis_control_if.v | 3,363 | module MODULE1
parameter VAR8 = 32,
parameter VAR22 = 32,
parameter VAR34 = 1
)
(
input VAR11,
input VAR31,
input VAR15,
input [11:0] VAR21,
input VAR16,
input VAR28,
input VAR36,
output VAR29,
input [VAR8-1 : 0] VAR1,
input [(VAR8/8)-1 : 0] VAR23,
input VAR19,
input VAR39,
input VAR18,
input VAR27,
output reg VAR14,
o... | lgpl-2.1 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/controller/arb_row_col.v | 12,634 | module MODULE1 #
(
parameter VAR66 = 100,
parameter VAR6 = "VAR4",
parameter VAR74 = "VAR70",
parameter VAR37 = 4,
parameter VAR52 = 2,
parameter VAR15 = 2
)
(
VAR54, VAR25, VAR41, VAR75,
VAR73, VAR8, VAR65,
VAR3, VAR11, VAR19, VAR28, VAR14,
VAR38, VAR33, VAR69, VAR23,
clk, rst, VAR46, VAR55, VAR64, VAR5,
VAR63, VAR7
)... | lgpl-3.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/mig_wrap_mig_7series_0_0.v | 10,632 | module MODULE1 (
inout [15:0] VAR21,
inout [1:0] VAR1,
inout [1:0] VAR60,
output [12:0] VAR46,
output [2:0] VAR44,
output VAR23,
output VAR61,
output VAR50,
output [0:0] VAR55,
output [0:0] VAR48,
output [0:0] VAR33,
output [0:0] VAR62,
output [1:0] VAR51,
output [0:0] VAR5,
input VAR37,
input VAR39,
output VAR14,
outp... | mit |
merckhung/zet | cores/vga/rtl/vga_palette_regs.v | 1,390 | module MODULE1 (
input clk,
input [3:0] VAR2,
output reg [7:0] VAR3,
input [3:0] address,
input write,
output reg [7:0] VAR1,
input [7:0] VAR5
);
reg [7:0] VAR4 [0:15];
always @(posedge clk) VAR3 <= VAR4[VAR2];
always @(posedge clk) VAR1 <= VAR4[address];
always @(posedge clk)
if (write) VAR4[address] <= VAR5;
endmodul... | gpl-3.0 |
terriblefire/tf328 | rtl/fastmem.v | 5,951 | module MODULE1(
input VAR3,
input VAR5,
input [23:0] VAR40,
inout [7:0] VAR4,
input [1:0] VAR30,
input VAR23,
input VAR39,
input VAR11,
output reg VAR14,
output VAR22,
output reg [3:0] VAR35,
output reg [1:0] VAR38,
output [1:0] VAR16,
output VAR28,
output VAR2,
output reg VAR26
);
wire [5:0] VAR17 = {VAR40[6:1]};
reg ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32ai/sky130_fd_sc_hd__o32ai.behavioral.v | 1,643 | module MODULE1 (
VAR10 ,
VAR4,
VAR11,
VAR1,
VAR15,
VAR8
);
output VAR10 ;
input VAR4;
input VAR11;
input VAR1;
input VAR15;
input VAR8;
supply1 VAR12;
supply0 VAR6;
supply1 VAR16 ;
supply0 VAR7 ;
wire VAR9 ;
wire VAR3 ;
wire VAR5;
nor VAR13 (VAR9 , VAR1, VAR4, VAR11 );
nor VAR14 (VAR3 , VAR15, VAR8 );
or VAR17 (VAR5, V... | apache-2.0 |
keith-epidev/VHDL-lib | top/lab_2/part_3/ip/bram/bram/bram_stub.v | 1,284 | module MODULE1(VAR7, VAR5, VAR6, VAR2, VAR4, VAR1, VAR3)
;
input VAR7;
input [0:0]VAR5;
input [10:0]VAR6;
input [15:0]VAR2;
input VAR4;
input [10:0]VAR1;
output [15:0]VAR3;
endmodule | gpl-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_qspi_physical.v | 19,310 | module MODULE1(
input VAR190,
input reset,
output VAR212,
input VAR204,
output VAR169,
output VAR208,
input VAR183,
output VAR185,
output VAR206,
input VAR61,
output VAR151,
output VAR121,
input VAR127,
output VAR182,
output VAR227,
output VAR239,
input [11:0] VAR41,
input VAR115,
input VAR215,
input [1:0] VAR203,
inpu... | apache-2.0 |
cr88192/bgbtech_bjx1core | bjx1core32/ExUop.v | 17,887 | parameter[7:0] VAR40 = 8'h00; parameter[7:0] VAR194 = 8'h01;
parameter[7:0] VAR69 = 8'h02;
parameter[7:0] VAR191 = 8'h03;
parameter[7:0] VAR19 = 8'h04;
parameter[7:0] VAR36 = 8'h05;
parameter[7:0] VAR176 = 8'h06;
parameter[7:0] VAR189 = 8'h07;
parameter[7:0] VAR177 = 8'h08;
parameter[7:0] VAR169 = 8'h09;
parameter[7:0]... | mit |
iemxblog/dds-icestick | communication.v | 1,674 | module MODULE1(
input wire clk,
output reg VAR4=0,
output reg [7:0] VAR2=0,
input wire VAR11,
input wire [7:0] VAR6,
output reg en=0,
output wire [39:0] VAR13,
output reg VAR7=0,
output reg VAR3=0
);
reg [7:0] state=0;
reg [7:0] VAR15=0;
reg [7:0] VAR16=0, VAR1=0, VAR9=0, VAR12=0, VAR14=0;
reg [23:0] VAR8=0;
assign VAR... | gpl-2.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/source/rtl/KOA_2.v | 9,919 | module MODULE1 #(parameter VAR10 = 12)
(
input wire clk,
input wire rst,
input wire VAR22,
input wire [VAR10-1:0] VAR32,
input wire [VAR10-1:0] VAR34,
output wire [2*VAR10-1:0] VAR7
);
wire [VAR10/2+1:0] VAR40;
wire [VAR10/2+1:0] VAR15;
wire [VAR10-1:0] VAR36;
wire [VAR10+1:0] VAR6;
wire [VAR10+3:0] VAR2;
wire [2*(VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21oi/sky130_fd_sc_ls__a21oi_2.v | 2,261 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR4 ,
VAR9 ,
VAR10,
VAR3,
VAR2 ,
VAR5
);
output VAR6 ;
input VAR7 ;
input VAR4 ;
input VAR9 ;
input VAR10;
input VAR3;
input VAR2 ;
input VAR5 ;
VAR1 VAR8 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31o/sky130_fd_sc_hs__a31o.pp.symbol.v | 1,333 | module MODULE1 (
input VAR5 ,
input VAR6 ,
input VAR1 ,
input VAR3 ,
output VAR2 ,
input VAR4,
input VAR7
);
endmodule | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/phy_data_io.v | 17,005 | module MODULE1 #
(
parameter VAR57 = 100, parameter VAR72 = 2, parameter VAR75 = 3000, parameter VAR98 = 8, parameter VAR11 = 9, parameter VAR65 = 72, parameter VAR53 = 9, parameter VAR49 = "VAR4",
parameter VAR84 = 5, parameter VAR42 = "VAR21", parameter VAR56 = 300.0, parameter VAR66 = "VAR21", parameter VAR69 = "VAR... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0_0/bd_0/ip/ip_5/synth/bd_c3fe_slot_0_ar_0.v | 4,561 | module MODULE1 (
VAR59,
VAR40,
dout
);
input wire [0 : 0] VAR59;
input wire [0 : 0] VAR40;
output wire [1 : 0] dout;
VAR56 #(
.VAR12(1),
.VAR16(1),
.VAR15(1),
.VAR11(1),
.VAR25(1),
.VAR63(1),
.VAR23(1),
.VAR9(1),
.VAR41(1),
.VAR62(1),
.VAR35(1),
.VAR17(1),
.VAR44(1),
.VAR2(1),
.VAR66(1),
.VAR30(1),
.VAR22(1),
.VAR13(1)... | mit |
cpulabs/mist1032sa | src/dps/dps_lsflags.v | 1,038 | module MODULE1(
input wire VAR5,
input wire VAR1,
input wire VAR4,
input wire VAR6,
input wire VAR9,
input wire VAR11,
input wire VAR2,
output wire VAR3,
output wire [31:0] VAR10
);
reg [31:0] VAR12;
always@(posedge VAR5 or negedge VAR1)begin
if(!VAR1)begin
VAR12 <= 32'h0;
end
else if(VAR4 || VAR2)begin
VAR12 <= 32'h0;... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_2.behavioral.pp.v | 18,378 | module MODULE1( VAR151, VAR243, VAR32, VAR18, VAR200, VAR44, VAR58, VAR198 );
input VAR18, VAR32, VAR200, VAR151, VAR243;
inout VAR58, VAR198;
output VAR44;
reg VAR155;
VAR62 VAR249(.VAR151(VAR151),.VAR243(VAR243),.VAR32(VAR32),.VAR18(VAR18),.VAR200(VAR200),.VAR44(VAR44),.VAR58(VAR58),.VAR198(VAR198),.VAR155(VAR155));
... | apache-2.0 |
AmeerAbdelhadi/2D-Binary-Content-Addressable-Memory-BCAM | bcam_trc.v | 6,781 | module MODULE1
localparam VAR15 = VAR14/VAR25+((VAR14%VAR25)>1) ; localparam VAR22 = ((VAR14%VAR25)==0) ? VAR25 : (((VAR14%VAR25)==1) ? (VAR25+1) : (VAR14%VAR25));
wire [VAR2-1:0] VAR20 [VAR15-1:0];
genvar VAR8;
generate
for (VAR8=0 ; VAR8<VAR15 ; VAR8=VAR8+1) begin: VAR10
VAR11 #( .VAR2 ( VAR2 ), .VAR14 ( VAR8<(VAR15-... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputisolatch/sky130_fd_sc_lp__inputisolatch.pp.blackbox.v | 1,377 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR5,
VAR4 ,
VAR7 ,
VAR2 ,
VAR6
);
output VAR1 ;
input VAR3 ;
input VAR5;
input VAR4 ;
input VAR7 ;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
MeshSr/onetswitch45 | ons45-app52-ref_ofshw/vivado/onets_7045_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/user_data_path.v | 37,305 | module MODULE1
parameter VAR28=VAR78/8,
parameter VAR88 = 2,
parameter VAR85 = 8,
parameter VAR122 = 8
)
(
input [VAR78-1:0] VAR131,
input [VAR28-1:0] VAR26,
input VAR222,
output VAR114,
input [VAR78-1:0] VAR217,
input [VAR28-1:0] VAR17,
input VAR92,
output VAR11,
input [VAR78-1:0] VAR210,
input [VAR28-1:0] VAR211,
inp... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkbuf/sky130_fd_sc_hdll__clkbuf.behavioral.v | 1,353 | module MODULE1 (
VAR7,
VAR5
);
output VAR7;
input VAR5;
supply1 VAR8;
supply0 VAR2;
supply1 VAR9 ;
supply0 VAR4 ;
wire VAR1;
buf VAR3 (VAR1, VAR5 );
buf VAR6 (VAR7 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbp/sky130_fd_sc_lp__dfbbp.pp.symbol.v | 1,474 | module MODULE1 (
input VAR3 ,
output VAR9 ,
output VAR7 ,
input VAR10,
input VAR2 ,
input VAR1 ,
input VAR8 ,
input VAR6 ,
input VAR4 ,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s.behavioral.v | 1,438 | module MODULE1 (
VAR9,
VAR4
);
output VAR9;
input VAR4;
supply1 VAR7;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR1 ;
wire VAR8;
buf VAR3 (VAR8, VAR4 );
buf VAR2 (VAR9 , VAR8 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.functional.pp.v | 1,745 | module MODULE1( VAR16, VAR8, VAR23, VAR18, VAR6, VAR9, VAR12, VAR26, VAR21 );
input VAR18, VAR23, VAR6, VAR16, VAR8, VAR12, VAR26, VAR21;
output VAR9;
not VAR1( VAR4, VAR6 );
wire VAR7;
not VAR22( VAR7, VAR23 );
wire VAR25;
not VAR3( VAR25, VAR16 );
wire VAR11;
and VAR17( VAR11, VAR7, VAR25 );
wire VAR5;
not VAR2( VAR5... | apache-2.0 |
csturton/wirepatch | system/hardware/cores/ethmac/eth_receivecontrol.v | 13,718 | module MODULE1 (VAR46, VAR37, VAR40, VAR18, VAR58, VAR50, VAR4,
VAR55, VAR19, VAR31, VAR3, VAR28, VAR53,
VAR11, VAR22, VAR24, VAR5,
VAR14, VAR13, VAR38, VAR27,
VAR30, VAR35, VAR51
);
parameter VAR12 = 1;
input VAR46;
input VAR37;
input VAR40;
input VAR18;
input [7:0] VAR58;
input VAR50;
input VAR4;
input VAR55;
input V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o221ai/sky130_fd_sc_hd__o221ai_4.v | 2,457 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR4 ,
VAR10 ,
VAR3 ,
VAR11 ,
VAR1,
VAR9,
VAR8 ,
VAR5
);
output VAR2 ;
input VAR7 ;
input VAR4 ;
input VAR10 ;
input VAR3 ;
input VAR11 ;
input VAR1;
input VAR9;
input VAR8 ;
input VAR5 ;
VAR12 VAR6 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR1(... | apache-2.0 |
cliffordwolf/picorv32 | picosoc/icebreaker.v | 3,862 | module MODULE1 (
input clk,
output VAR2,
input VAR39,
output VAR11,
output VAR30,
output VAR31,
output VAR47,
output VAR26,
output VAR21,
output VAR10,
output VAR44,
output VAR52,
inout VAR25,
inout VAR16,
inout VAR18,
inout VAR45
);
parameter integer VAR20 = 32768;
reg [5:0] VAR4 = 0;
wire VAR51 = &VAR4;
always @(pose... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4/sky130_fd_sc_ls__nor4_4.v | 2,275 | module MODULE2 (
VAR2 ,
VAR1 ,
VAR3 ,
VAR7 ,
VAR5 ,
VAR11,
VAR10,
VAR4 ,
VAR9
);
output VAR2 ;
input VAR1 ;
input VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR11;
input VAR10;
input VAR4 ;
input VAR9 ;
VAR8 VAR6 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR4(VAR4),
.... | apache-2.0 |
blu006/de0-nano-clock | FPGA/count_minutes.v | 1,035 | module MODULE1(
VAR9,
VAR2,
VAR11,
VAR5,
VAR6
);
input VAR9;
input VAR2;
output [3:0] VAR11;
output [3:0] VAR5;
output reg VAR6;
wire VAR8;
reg VAR1;
reg VAR10;
reg VAR4;
VAR7 VAR1 <= 0;
VAR12 VAR13(VAR1, VAR4, VAR11, VAR8);
VAR12 VAR3(VAR1, VAR8, VAR5, );
always begin
if (VAR9) begin
VAR6 <= 0;
VAR4 <= 1;
end else beg... | bsd-2-clause |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_pcie_bram_top_7x.v | 8,665 | module MODULE1
parameter VAR33 = "VAR9", parameter VAR18 = 0, parameter [3:0] VAR28 = 4'h1, parameter [5:0] VAR14 = 6'h08,
parameter VAR20 = 31, parameter VAR3 = 24, parameter VAR7 = 1, parameter VAR27 = 2, parameter VAR30 = 1,
parameter VAR4 = 'h1FFF, parameter VAR22 = 1, parameter VAR11 = 2, parameter VAR2 = 1 )
(
in... | gpl-3.0 |
yard2010/Arducar | Car/Modules/Video-and-Image-Processing-Design-Using-FPGAs-master/de1_ov7670/SRC/MAC_3.v | 14,205 | module MODULE1 (
VAR58,
VAR98,
VAR69,
VAR107,
VAR37,
VAR57,
VAR82,
VAR112,
VAR76);
input VAR112;
input VAR76;
input [7:0] VAR58;
input [7:0] VAR98;
input [7:0] VAR69;
input [16:0] VAR107;
input [16:0] VAR37;
input [16:0] VAR57;
output [26:0] VAR82;
wire [26:0] VAR100;
wire [16:0] VAR80 = VAR57[16:0];
wire [16:0] VAR60 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_4.v | 2,440 | module MODULE1 (
VAR8,
VAR6 ,
VAR2 ,
VAR4 ,
VAR5 ,
VAR3 ,
VAR1 ,
VAR10
);
input VAR8;
input VAR6 ;
input VAR2 ;
output VAR4 ;
input VAR5 ;
input VAR3 ;
input VAR1 ;
input VAR10 ;
VAR7 VAR9 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR10(VAR10)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2/sky130_fd_sc_hs__or2.functional.pp.v | 1,672 | module MODULE1 (
VAR8,
VAR10,
VAR2 ,
VAR1 ,
VAR6
);
input VAR8;
input VAR10;
output VAR2 ;
input VAR1 ;
input VAR6 ;
wire VAR3 ;
wire VAR7;
or VAR9 (VAR3 , VAR6, VAR1 );
VAR5 VAR11 (VAR7, VAR3, VAR8, VAR10);
buf VAR4 (VAR2 , VAR7 );
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_ifu_ift2icb.v | 39,608 | module MODULE1(
input VAR79,
input VAR152, output VAR106, input [VAR39-1:0] VAR89, input VAR114, input VAR49, input [VAR39-1:0] VAR73,
output VAR4, input VAR77, output VAR5, output [32-1:0] VAR53,
output VAR121, input VAR37, output [VAR110-1:0] VAR130,
input VAR60, output VAR30, input VAR129, input [VAR3-1:0] VAR2,
inp... | apache-2.0 |
archlabo/Frix | common/io_bus.v | 16,237 | module MODULE1
(
input wire VAR5,
input wire rst,
input wire [15:0] VAR86,
output wire VAR42,
input wire [3:0] VAR16,
input wire VAR83,
output wire [31:0] VAR15,
output wire VAR7,
input wire VAR21,
input wire [31:0] VAR59,
output wire [3:0] VAR8,
output wire VAR53,
output wire [7:0] VAR30,
output wire VAR95,
input wire... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtp/sky130_fd_sc_ms__dlxtp.behavioral.pp.v | 1,841 | module MODULE1 (
VAR12 ,
VAR15 ,
VAR8,
VAR5,
VAR11,
VAR6 ,
VAR3
);
output VAR12 ;
input VAR15 ;
input VAR8;
input VAR5;
input VAR11;
input VAR6 ;
input VAR3 ;
wire VAR7 ;
wire VAR14;
wire VAR1 ;
reg VAR13 ;
wire VAR9 ;
VAR2 VAR10 (VAR7 , VAR1, VAR14, VAR13, VAR5, VAR11);
buf VAR4 (VAR12 , VAR7 );
assign VAR9 = ( VAR5 =... | apache-2.0 |
olajep/oh | src/adi/hdl/library/axi_dmac/axi_dmac_resize_dest.v | 3,758 | module MODULE1 #(
parameter VAR1 = 64,
parameter VAR6 = 64
) (
input clk,
input reset,
input VAR8,
output VAR3,
input [VAR6-1:0] VAR16,
input VAR4,
output VAR7,
input VAR14,
output [VAR1-1:0] VAR10,
output VAR12
);
generate if (VAR1 == VAR6) begin
assign VAR7 = VAR8;
assign VAR10 = VAR16;
assign VAR12 = VAR4;
assign VA... | mit |
theapi/nand2tetris_fpga | hack/ip/qsys/qsys/synthesis/submodules/qsys_sdram.v | 23,501 | module MODULE2 (
clk,
rd,
VAR2,
wr,
VAR31,
VAR50,
VAR61,
VAR36,
VAR69,
VAR76
)
;
output VAR50;
output VAR61;
output VAR36;
output VAR69;
output [ 42: 0] VAR76;
input clk;
input rd;
input VAR2;
input wr;
input [ 42: 0] VAR31;
wire VAR50;
wire VAR61;
wire VAR36;
reg [ 1: 0] VAR68;
reg [ 42: 0] VAR60;
reg [ 42: 0] VAR77;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3.functional.v | 1,309 | module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
wire VAR2;
buf VAR3 (VAR2, VAR4 );
buf VAR5 (VAR1 , VAR2 );
endmodule | apache-2.0 |
zYeoman/32BIT-MIPS-CPU | pipeline/ID2EX.v | 3,475 | module MODULE1(
input clk, rst, VAR34,
input VAR10, VAR26, VAR1, VAR24, VAR8, VAR11, VAR2, VAR14,
input [31:0] VAR16, VAR9, VAR33, VAR36,
input [4:0] VAR17, VAR20, VAR21, VAR38,
input [5:0] VAR22,
input [2:0] VAR18,
input [1:0] VAR41, VAR27,
output reg VAR30, VAR23, VAR35, VAR31, VAR5, VAR37, VAR13, VAR19,
output reg [... | gpl-2.0 |
cafe-alpha/wascafe | v13/wasca_10m08sc_20191205_abus_divide/wasca/synthesis/wasca.v | 75,084 | module MODULE1 (
input wire [9:0] VAR98, input wire [2:0] VAR432, input wire VAR428, input wire [1:0] VAR393, output wire VAR187, output wire VAR70, inout wire [15:0] VAR101, output wire VAR454, output wire [1:0] VAR225, output wire VAR12, input wire VAR355, input wire VAR56, output wire VAR326, output wire VAR320, inp... | gpl-2.0 |
chriswynnyk/american-put-verilog | american_put_cyclone/src/int_to_fp.v | 25,183 | module MODULE1
(
VAR3,
VAR14,
VAR10,
VAR6,
VAR12,
VAR7) ;
input VAR3;
input VAR14;
input VAR10;
input [31:0] VAR6;
input [4:0] VAR12;
output [31:0] VAR7;
reg [31:0] VAR2;
reg [31:0] VAR5;
reg VAR11;
reg VAR13;
wire VAR9;
wire [15:0] VAR4;
wire [191:0] VAR1;
wire [4:0] VAR8; | apache-2.0 |
sh-chris110/chris | FPGA/chris/Qsys/convoluation_core.v | 1,659 | module MODULE1 (
input clk,
input reset,
input [31:0] VAR35,
input [31:0] VAR25,
input [31:0] VAR13,
input [31:0] VAR9,
input [31:0] VAR20,
input [31:0] VAR2,
input [31:0] VAR17,
input [31:0] VAR10,
input [31:0] VAR23,
input VAR22,
output reg VAR18,
input VAR15,
output reg [31:0] VAR29
);
parameter VAR19 = 8'd1;
parame... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fill/sky130_fd_sc_hd__fill_8.v | 1,840 | module MODULE1 (
VAR2,
VAR6,
VAR4 ,
VAR1
);
input VAR2;
input VAR6;
input VAR4 ;
input VAR1 ;
VAR5 VAR3 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE1 ();
supply1 VAR2;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR1 ;
VAR5 VAR3 ();
endmodule | apache-2.0 |
Jesus89/open-fpga-verilog-tutorial | tutorial/ICESTICK/T09-inicializador/init.v | 1,069 | module MODULE1(input wire clk, output VAR1);
reg VAR1 = 0;
always @(posedge(clk))
VAR1 <= 1;
endmodule | gpl-2.0 |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_stub.v | 4,412 | module MODULE1(VAR50, VAR8, VAR53, VAR55,
VAR24, VAR42, VAR23, VAR33, VAR20, VAR41,
VAR16, VAR1, VAR17, VAR59, VAR5, VAR54, VAR57,
VAR2, VAR44, VAR28, VAR14, VAR32, VAR19, VAR13,
VAR3, VAR25, VAR43, VAR46, VAR26, VAR45,
VAR51, VAR48, VAR34, VAR37, VAR40, VAR4, VAR52,
VAR12, VAR18, VAR36, VAR27, VAR39, VAR35,
VAR7, VAR9... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.v | 2,460 | module MODULE1 (
VAR6 ,
VAR11,
VAR3,
VAR10 ,
VAR5 ,
VAR7,
VAR2,
VAR8 ,
VAR4
);
output VAR6 ;
input VAR11;
input VAR3;
input VAR10 ;
input VAR5 ;
input VAR7;
input VAR2;
input VAR8 ;
input VAR4 ;
VAR9 VAR1 (
.VAR6(VAR6),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR4... | apache-2.0 |
ptracton/wb_soc_template | rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v | 4,300 | module MODULE1 (clk, VAR9, enable, VAR2, VAR5, rst, VAR1, VAR8);
input clk;
input VAR9;
input enable;
input VAR2;
input VAR5;
input rst;
output [31:0] VAR1;
output VAR8;
reg [31:0] VAR7;
wire [31:0] VAR6;
wire VAR3;
assign VAR3 = (VAR9 === 1'VAR4 || VAR9 === 1'b0) ? 1'b0 : 1'b1;
assign VAR3 = VAR9;
assign VAR6[0] = VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1_1.v | 1,992 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR4,
VAR3
);
output VAR1 ;
input VAR5 ;
input VAR4;
input VAR3;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR1,
VAR5
);
output VAR1;
input VAR5;
supply1 VAR4;
supply0 VAR3;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/adv_debug_sys/Hardware/xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag.v | 16,664 | module MODULE1 (
VAR42,
VAR31,
VAR15,
VAR34,
VAR3,
VAR45,
VAR4,
VAR40,
VAR30,
VAR12
);
parameter VAR44 = 1;
input VAR31;
output VAR42;
output VAR15;
output VAR34;
output VAR3;
output VAR45;
output VAR4;
output VAR40;
output VAR30;
output VAR12;
wire VAR31;
wire VAR42;
wire VAR14;
wire VAR15;
wire VAR34;
wire VAR3;
wire... | mit |
zhaishaomin/ring_network-based-multicore- | core/core_ex.v | 6,654 | module MODULE1( VAR3,
VAR14,
VAR36,
VAR27,
VAR23,
VAR15,
VAR32,
VAR35,
VAR4,
VAR29,
VAR19,
VAR2,
VAR46,
VAR26,
VAR39,
VAR43,
VAR25,
VAR24,
VAR44
);
parameter VAR9=6'b000000;
parameter VAR48=6'b000010;
parameter VAR20=6'b000011;
parameter VAR34=6'b000100;
parameter VAR47=6'b000110;
parameter VAR8=6'b000111;
parameter VA... | apache-2.0 |
betontalpfa2/AXI2SPI-bridge | hdl/spi_controller.v | 5,803 | module MODULE1(
input clk,
input VAR38,
output VAR17,
input wire [31:0] VAR34,
input wire VAR6, input wire VAR35, input wire VAR14,
output wire [31:0] VAR27,
output wire [31:0] VAR4,
output wire [31:0] VAR40,
input VAR44,
output VAR21,
output VAR18
);
reg [31:0] VAR13;
wire [31:0] VAR22;
reg [7:0] VAR42;
reg [7:0] VAR8... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.symbol.v | 1,257 | module MODULE1 (
input VAR4,
input VAR3,
output VAR2 ,
input VAR1
);
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/tse_mac_loopback.v | 3,191 | module MODULE1 (
VAR4,
VAR2,
VAR1
);
output VAR4;
input VAR2;
output VAR1;
reg VAR3; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlrtp/sky130_fd_sc_hvl__dlrtp.blackbox.v | 1,370 | module MODULE1 (
VAR8 ,
VAR1,
VAR2 ,
VAR7
);
output VAR8 ;
input VAR1;
input VAR2 ;
input VAR7 ;
supply1 VAR6;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
gbraad/minimig-de1 | rtl/or1200/or1200_tt.v | 6,064 | module MODULE1(
clk, rst, VAR14,
VAR16, VAR23, VAR7, VAR2, VAR13,
VAR18
);
input clk; input rst; input VAR14; input VAR16; input VAR23; input [31:0] VAR7; input [31:0] VAR2; output [31:0] VAR13; output VAR18;
reg [31:0] VAR10; else
wire [31:0] VAR10; VAR24
reg [31:0] VAR21; else
wire [31:0] VAR21; VAR24
wire VAR15; wir... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor2/sky130_fd_sc_lp__xnor2.symbol.v | 1,301 | module MODULE1 (
input VAR5,
input VAR1,
output VAR4
);
supply1 VAR7;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux4/sky130_fd_sc_ms__mux4.pp.blackbox.v | 1,376 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR11 ,
VAR6 ,
VAR1 ,
VAR10 ,
VAR3 ,
VAR8,
VAR9,
VAR7 ,
VAR2
);
output VAR5 ;
input VAR4 ;
input VAR11 ;
input VAR6 ;
input VAR1 ;
input VAR10 ;
input VAR3 ;
input VAR8;
input VAR9;
input VAR7 ;
input VAR2 ;
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v | 18,247 | module MODULE1 (
input wire VAR102, input wire VAR53, input wire [29:0] VAR81, output wire VAR84, input wire [4:0] VAR38, input wire [31:0] VAR6, input wire VAR87, output wire [255:0] VAR86, output wire VAR12, input wire VAR74, input wire [255:0] VAR18, input wire VAR2, output wire [24:0] VAR46, output wire VAR24, outp... | mit |
nyaxt/dmix | rom_firbank_441_480.v | 117,018 | module MODULE1(
input wire clk,
input wire [11:0] addr,
output wire [23:0] VAR1);
reg [23:0] VAR2;
assign VAR1 = VAR2;
always @(posedge clk) begin
case(addr)
0: VAR2 <= 24'h005690; 1: VAR2 <= 24'hFFC696; 2: VAR2 <= 24'h002C4B; 3: VAR2 <= 24'hFFDD3C; 4: VAR2 <= 24'h001AC2; 5: VAR2 <= 24'hFFEC21; 6: VAR2 <= 24'h000E18; 7... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2/sky130_fd_sc_ms__and2_4.v | 2,086 | module MODULE2 (
VAR3 ,
VAR1 ,
VAR9 ,
VAR5,
VAR2,
VAR4 ,
VAR6
);
output VAR3 ;
input VAR1 ;
input VAR9 ;
input VAR5;
input VAR2;
input VAR4 ;
input VAR6 ;
VAR8 VAR7 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR3,
VAR1,
VAR9
);
output VAR3;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfstp/sky130_fd_sc_lp__dfstp.pp.blackbox.v | 1,335 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR1 ,
VAR5,
VAR3 ,
VAR4 ,
VAR7 ,
VAR2
);
output VAR6 ;
input VAR8 ;
input VAR1 ;
input VAR5;
input VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR2 ;
endmodule | apache-2.0 |
silent-observer/RCPU | CPU/source/KeyboardReader.v | 1,124 | module MODULE1 (
input wire rst,
input wire clk,
inout wire VAR16,
inout wire VAR8,
output reg[8:0] VAR14,
output reg VAR15
);
wire[7:0] VAR10;
wire VAR17;
reg VAR3;
always @ (posedge clk)
VAR3 <= VAR17;
wire VAR11 = !VAR3 && VAR17;
VAR6 VAR7 (
.reset (rst),
.VAR12 (clk),
.VAR2(VAR16),
.VAR13(VAR8),
.VAR1(VAR10),
.VAR5... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_link/bsg_link_sdr_upstream.v | 3,406 | module MODULE1
,parameter VAR24 = 3
,parameter VAR25 = 0
,parameter VAR11 = 0
,parameter VAR18 = 0
)
( input VAR14
,input VAR26
,input VAR9
,input VAR16
,input [VAR10-1:0] VAR5
,output VAR15
,output VAR22
,output VAR4
,output [VAR10-1:0] VAR6
,input VAR2
);
logic VAR17;
logic [VAR10-1:0] VAR12;
VAR19
,.VAR24 (VAR24)
,.... | bsd-3-clause |
SymbiFlow/fpga-tool-perf | third_party/picorv32_wrappers/attosoc.v | 3,368 | module MODULE1 (
input clk,
input reset,
output reg [7:0] VAR1
);
reg [5:0] VAR5 = 0;
wire VAR6 = &VAR5;
always @(posedge clk) begin
if (reset)
VAR5 <= 0;
end
else
VAR5 <= VAR5 + !VAR6;
end
parameter integer VAR8 = 256;
parameter [31:0] VAR4 = (4*VAR8); parameter [31:0] VAR9 = 32'VAR11 00000000; parameter integer VAR3 ... | isc |
olajep/oh | src/adi/hdl/library/util_axis_fifo/util_axis_fifo.v | 6,840 | module MODULE1 #(
parameter VAR42 = 64,
parameter VAR9 = 1,
parameter VAR45 = 4,
parameter VAR26 = 1
) (
input VAR35,
input VAR23,
input VAR11,
output VAR47,
output [VAR42-1:0] VAR18,
output [VAR45:0] VAR34,
input VAR32,
input VAR36,
output VAR10,
input VAR13,
input [VAR42-1:0] VAR44,
output VAR37,
output [VAR45:0] VAR... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/f7abcf1d6f5a92f5/ip_design_nco_0_0_stub.v | 2,652 | module MODULE1(VAR19,
VAR9, VAR7, VAR1,
VAR16, VAR14, VAR3,
VAR4, VAR18, VAR12,
VAR10, VAR8, VAR15,
VAR11, VAR5, VAR13,
VAR2, VAR17, VAR6)
;
input [5:0]VAR19;
input VAR9;
output VAR7;
input [31:0]VAR1;
input [3:0]VAR16;
input VAR14;
output VAR3;
output [1:0]VAR4;
output VAR18;
input VAR12;
input [5:0]VAR10;
input VAR8;... | mit |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_monitor_ram.v | 185,056 | module MODULE1 (VAR43, VAR125, VAR79, VAR189, VAR179,
VAR113, VAR106, VAR18, VAR131, VAR108, VAR81, VAR105, VAR193, VAR14);
input [31:0] VAR43;
input [31:0] VAR125;
input [8:0] VAR79;
input [8:0] VAR189;
input VAR179;
input VAR113;
input VAR106;
input VAR18;
input VAR131;
input VAR108;
input VAR81;
input VAR105;
output... | lgpl-3.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/uart16550/uart_sync_flops.v | 5,909 | module MODULE1
(
VAR9,
VAR8,
VAR1,
VAR6,
VAR2,
VAR3
);
parameter VAR7 = 1;
parameter VAR5 = 1;
parameter VAR4 = 1'b0;
input VAR9; input VAR8; input VAR1; input VAR6; input [VAR5-1:0] VAR2; output [VAR5-1:0] VAR3;
reg [VAR5-1:0] VAR3;
reg [VAR5-1:0] VAR10;
always @ (posedge VAR8 or posedge VAR9)
begin
if (VAR9)
VAR10 <=... | apache-2.0 |
ShepardSiegel/ocpi | rtl/mkDDCWorker.v | 73,719 | module MODULE1(VAR92,
VAR210,
VAR137,
VAR171,
VAR99,
VAR374,
VAR377,
VAR370,
VAR60,
VAR353,
VAR360,
VAR332,
VAR423,
VAR437,
VAR460,
VAR410,
VAR372,
VAR252,
VAR492,
VAR119,
VAR161,
VAR179,
VAR238,
VAR200,
VAR397,
VAR456,
VAR166,
VAR30,
VAR167,
VAR280,
VAR479,
VAR286);
parameter [31 : 0] VAR406 = 32'b0;
parameter [0 : 0]... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32a/sky130_fd_sc_ms__o32a.blackbox.v | 1,384 | module MODULE1 (
VAR5 ,
VAR7,
VAR1,
VAR3,
VAR4,
VAR9
);
output VAR5 ;
input VAR7;
input VAR1;
input VAR3;
input VAR4;
input VAR9;
supply1 VAR6;
supply0 VAR10;
supply1 VAR8 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
samyk/proxmark3 | fpga/hi_sniffer.v | 1,064 | module MODULE1(
VAR2,
VAR10, VAR12, VAR13, VAR1, VAR7, VAR3,
VAR11, VAR5,
VAR9, VAR6, VAR8
);
input VAR2;
output VAR10, VAR12, VAR13, VAR1, VAR7, VAR3;
input [7:0] VAR11;
output VAR5;
output VAR9, VAR6, VAR8;
assign VAR12 = 1'b0;
assign VAR10 = 1'b0;
assign VAR13 = 1'b0;
assign VAR1 = 1'b0;
assign VAR7 = 1'b0;
assign V... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp1/megacells/fifo_4kx16_dc_bb.v | 5,996 | module MODULE1 (
VAR10,
VAR7,
VAR11,
VAR4,
VAR8,
VAR6,
VAR3,
VAR2,
VAR5,
VAR9,
VAR1);
input VAR10;
input [15:0] VAR7;
input VAR11;
input VAR4;
input VAR8;
input VAR6;
output [15:0] VAR3;
output VAR2;
output [11:0] VAR5;
output VAR9;
output [11:0] VAR1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2_1.v | 2,119 | module MODULE2 (
VAR7 ,
VAR8 ,
VAR4,
VAR6,
VAR3 ,
VAR1
);
output VAR7 ;
input VAR8 ;
input VAR4;
input VAR6;
input VAR3 ;
input VAR1 ;
VAR5 VAR2 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR7,
VAR8
);
output VAR7;
input VAR8;
supply1 VAR4;
supply0 VAR6;... | apache-2.0 |
bobnewgard/fcs | ver/uut_32_top.v | 2,956 | module MODULE1
(
output wire [31:0] VAR8,
output wire [31:0] VAR5,
output wire [31:0] VAR14,
output wire VAR4,
input wire [31:0] VAR19,
input wire VAR21,
input wire VAR12,
input wire VAR20
);
localparam VAR1 = 1'b0;
localparam VAR11 = 1'b1;
localparam [31:0] VAR16 = {32{VAR1}};
localparam [31:0] VAR17 = {32{VAR11}};
re... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_091.v | 1,516 | module MODULE1 (
VAR3,
VAR9
);
input [31:0] VAR3;
output [31:0]
VAR9;
wire [31:0]
VAR6,
VAR11,
VAR8,
VAR10,
VAR13,
VAR5,
VAR7,
VAR2,
VAR14;
assign VAR6 = VAR3;
assign VAR10 = VAR8 << 2;
assign VAR13 = VAR6 + VAR10;
assign VAR7 = VAR5 - VAR6;
assign VAR5 = VAR13 << 4;
assign VAR8 = VAR11 - VAR6;
assign VAR11 = VAR6 << 5... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrbp/sky130_fd_sc_lp__sdfrbp.functional.pp.v | 2,360 | module MODULE1 (
VAR19 ,
VAR10 ,
VAR17 ,
VAR4 ,
VAR20 ,
VAR12 ,
VAR16,
VAR7 ,
VAR13 ,
VAR18 ,
VAR6
);
output VAR19 ;
output VAR10 ;
input VAR17 ;
input VAR4 ;
input VAR20 ;
input VAR12 ;
input VAR16;
input VAR7 ;
input VAR13 ;
input VAR18 ;
input VAR6 ;
wire VAR15 ;
wire VAR9 ;
wire VAR14;
not VAR2 (VAR9 , VAR16 );
VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxbp/sky130_fd_sc_ls__sdfxbp.pp.blackbox.v | 1,398 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR9 ,
VAR7 ,
VAR10 ,
VAR1 ,
VAR2,
VAR6,
VAR8 ,
VAR3
);
output VAR5 ;
output VAR4 ;
input VAR9 ;
input VAR7 ;
input VAR10 ;
input VAR1 ;
input VAR2;
input VAR6;
input VAR8 ;
input VAR3 ;
endmodule | apache-2.0 |
yaqwsx/MandelbrotFPGA | mandelbrot.v | 2,565 | module MODULE1(clk, reset, VAR16, VAR19, VAR13, VAR15, VAR9, VAR2);
parameter VAR14 = 20;
parameter VAR11 = 30;
input reset;
input clk;
input signed [VAR14 - 1:0] VAR16;
input signed [VAR14 - 1:0] VAR19;
output reg VAR13;
output signed [VAR14 - 1:0] VAR15;
output signed [VAR14 - 1:0] VAR9;
output unsigned [7:0] VAR2;
r... | mit |
fpgasystems/caribou | hw/src/net/network_module.v | 11,996 | module MODULE1(
input VAR80,
input reset,
input VAR92,
input VAR58,
input VAR5,
input VAR7,
output VAR111,
input VAR147,
input VAR56,
input VAR118,
input VAR62,
input VAR28,
input VAR73,
input VAR19,
input VAR148,
input VAR60,
input VAR89,
input VAR120,
output VAR151,
output VAR144,
output VAR81,
input VAR35,
input VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4/sky130_fd_sc_hd__nand4.pp.symbol.v | 1,303 | module MODULE1 (
input VAR7 ,
input VAR9 ,
input VAR3 ,
input VAR5 ,
output VAR1 ,
input VAR4 ,
input VAR8,
input VAR2,
input VAR6
);
endmodule | apache-2.0 |
sudov/options-accel | xillinux-eval-zedboard-1.1/system/pcores/xillyvga_v1_00_a/hdl/verilog/xillyvga.v | 3,888 | module MODULE1 #(
parameter VAR13 = 32,
parameter VAR46 = 32,
parameter VAR25 = 32,
parameter VAR2 = 32,
parameter VAR20 = 32'h000001ff,
parameter VAR50 = 1,
parameter VAR55 = 8,
parameter VAR52 = 32'h79c00000,
parameter VAR27 = 32'h79c0ffff,
parameter VAR62 = 32,
parameter VAR8 = 32,
parameter VAR23 = 256,
parameter V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211o/sky130_fd_sc_ms__a211o.blackbox.v | 1,360 | module MODULE1 (
VAR9 ,
VAR1,
VAR7,
VAR2,
VAR8
);
output VAR9 ;
input VAR1;
input VAR7;
input VAR2;
input VAR8;
supply1 VAR5;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_exu_alu.v | 31,917 | module MODULE1(
input VAR61,
output VAR279,
output VAR237,
input VAR146,
input VAR103,
output [31:0] VAR259,
output VAR162,
output [31:0] VAR215,
input [31:0] VAR109,
output VAR32,
input VAR227,
input [VAR116-1:0] VAR77,
input [VAR254-1:0] VAR128,
input [VAR254-1:0] VAR14,
input [VAR254-1:0] VAR69,
input [VAR99-1:0] VA... | apache-2.0 |
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