repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
kDaniu/miaow | src/verilog/rtl/issue/spr_dependency_table.v | 9,999 | module MODULE1
(
VAR48,
VAR13, VAR52, VAR87,
VAR32, VAR41, VAR3, VAR34,
VAR90, VAR60, VAR74,
VAR85, VAR68, VAR96,
VAR67, VAR94,
VAR69, VAR84, VAR14,
VAR24, VAR72, VAR58, VAR1,
VAR2, VAR97, VAR73,
VAR64, VAR20, VAR61,
VAR44, clk, rst
);
input[VAR17-1:0] VAR13, VAR52, VAR87,
VAR32;
input VAR41,
VAR3, VAR34, VAR90,
VAR60,... | bsd-3-clause |
rkrajnc/minimig-mist | rtl/minimig/paula_audio.v | 12,783 | module MODULE1
(
input wire clk, input wire VAR40, input wire VAR17, input wire rst, input wire VAR21, input wire [ 9-1:1] VAR1, input wire [ 16-1:0] VAR35, input wire [ 4-1:0] VAR26, output wire [ 4-1:0] VAR2, input wire [ 4-1:0] VAR27, output reg [ 4-1:0] VAR3, output reg [ 4-1:0] VAR6, output wire VAR8, output wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4/sky130_fd_sc_hdll__nor4_8.v | 2,291 | module MODULE2 (
VAR7 ,
VAR10 ,
VAR5 ,
VAR6 ,
VAR4 ,
VAR1,
VAR8,
VAR9 ,
VAR11
);
output VAR7 ;
input VAR10 ;
input VAR5 ;
input VAR6 ;
input VAR4 ;
input VAR1;
input VAR8;
input VAR9 ;
input VAR11 ;
VAR2 VAR3 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR9(VAR9),
.VA... | apache-2.0 |
jaaguzmanro/piano | piano.v | 1,209 | module MODULE1(VAR20, VAR15,VAR3,VAR6,VAR21,VAR30,VAR35,VAR5,VAR38,clk);
output wire[7:0] VAR20;
input VAR15,VAR3,VAR6,VAR21,VAR30,VAR35,VAR5,VAR38,clk;
wire [7:0] VAR24;
wire [7:0] VAR26;
wire [7:0] VAR13,VAR14,VAR25,VAR8,VAR23,VAR33,VAR31,VAR39;
wire VAR17,VAR19,VAR32,VAR9,VAR2,VAR18;
wire [7:0]VAR27;
wire [15:0]VAR... | gpl-3.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/up_dac_channel.v | 12,752 | module MODULE1 (
VAR29,
VAR21,
VAR33,
VAR25,
VAR34,
VAR16,
VAR7,
VAR54,
VAR24,
VAR70,
VAR40,
VAR37,
VAR47,
VAR64,
VAR62,
VAR43,
VAR66,
VAR26,
VAR60,
VAR2,
VAR38,
VAR67,
VAR11,
VAR5,
VAR45,
VAR39,
VAR27,
VAR48,
VAR12,
VAR19,
VAR30,
VAR28,
VAR18,
VAR51,
VAR56,
VAR32,
VAR10,
VAR4);
parameter VAR35 = 4'h0;
input VAR29;
inp... | lgpl-3.0 |
lokisz/openzcore | pippo-0.9/rtl/verilog/pippo_id.v | 81,603 | module MODULE1(
clk, rst,
VAR77, VAR133, VAR58, VAR14,
VAR141, VAR183, VAR120, VAR7,
VAR6, VAR69, VAR34, VAR8, VAR62, VAR123,
VAR176, VAR153, VAR79,
VAR40, VAR114, VAR57,
VAR112, VAR92,
VAR101, VAR108, VAR182, VAR19, VAR151,
VAR135, VAR66, VAR2,
VAR128, VAR172, VAR29, VAR100, VAR73,
VAR138, VAR31, VAR179, VAR126, VAR52... | gpl-2.0 |
freecores/tiny_tate_bilinear_pairing | group_size_is_911_bits/rtl/tiny.v | 2,889 | module MODULE2(clk, reset, sel, addr, VAR28, VAR1, out, VAR30);
input clk, reset;
input sel;
input [5:0] addr;
input VAR28;
input [VAR20:0] VAR1;
output [VAR20:0] out;
output VAR30;
wire [5:0] VAR32;
wire [5:0] VAR11, VAR9;
wire [VAR20:0] VAR38;
wire VAR2, VAR13;
wire [VAR20:0] VAR40, VAR36;
wire [VAR20:0] VAR37, VAR7;... | apache-2.0 |
praveendath92/securePUF | source/Frequency_Block.v | 1,508 | module MODULE1(
input wire clk,
input wire rst,
input wire rand,
output reg VAR3
);
parameter VAR6 = 100, VAR8 = 200, VAR4 = 6790;
reg [7:0] VAR1, VAR2, VAR10;
reg [6:0] VAR5;
reg [19:0] VAR9;
always @(posedge clk)
if (rst) begin
VAR1 <= 8'VAR7;
VAR2 <= 0;
VAR5 <= 0;
VAR10 <= 0;
VAR9 <= 0;
VAR3 <= 0;
end
else begin
VAR... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/rtl/iobdg.v | 66,182 | module MODULE1 (
VAR234, VAR233, VAR70,
VAR315, VAR304, VAR246,
VAR363, VAR300, VAR215,
VAR263, VAR276, VAR375,
VAR60, VAR206, VAR97, VAR114,
VAR4, VAR157, VAR184, VAR2,
VAR381, VAR374, VAR369,
VAR120, VAR310, VAR122,
VAR331, VAR121, VAR314,
VAR284, VAR259, VAR282, VAR131,
VAR265, VAR214,
VAR350, VAR81, VAR256, VAR64,
... | gpl-2.0 |
fpgasystems/caribou | hw/src/nukv/nukv_ht_read_v2.v | 5,062 | module MODULE1 #(
parameter VAR18 = 128,
parameter VAR17 = 96,
parameter VAR8 = 64,
parameter VAR2 = 21
)
(
input wire clk,
input wire rst,
input wire [VAR18+VAR17+VAR8-1:0] VAR24,
input wire VAR9,
output wire VAR23,
input wire [VAR18+VAR17+VAR8-1:0] VAR27,
input wire VAR20,
output wire VAR19,
output reg [VAR18+VAR17+V... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_port_lookup/cam_router/src/router_op_lut_regs_non_cntr.v | 19,117 | module MODULE1
parameter VAR12 = 4,
parameter VAR47 = 4,
parameter VAR13 = 4,
parameter VAR49 = 2
)
(
input VAR21,
input VAR33,
input VAR35,
input [VAR84-1:0] VAR11,
input [VAR40-1:0] VAR86,
input [VAR49-1:0] VAR80,
output reg VAR57,
output reg VAR14,
output reg VAR38,
output reg [VAR84-1:0] VAR22,
output reg [VAR40-1:... | mit |
jairov4/accel-oil | solution_spartan6/syn/verilog/sample_iterator_get_offset.v | 30,628 | module MODULE1 (
VAR26,
VAR90,
VAR84,
VAR82,
VAR9,
VAR58,
VAR62,
VAR72,
VAR57,
VAR67,
VAR21,
VAR59,
VAR74,
VAR55,
VAR48,
VAR19,
VAR107,
VAR110,
VAR29,
VAR18,
VAR80,
VAR34,
VAR41,
VAR105,
VAR44,
VAR15,
VAR64,
VAR31,
VAR6,
VAR102,
VAR22,
VAR88,
VAR36,
VAR5,
VAR93,
VAR24,
VAR30,
VAR92,
VAR97
);
input VAR26;
input VAR90;
i... | lgpl-3.0 |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/soc_system_pll_0.v | 2,211 | module MODULE1(
input wire VAR45,
input wire rst,
output wire VAR17,
output wire VAR39,
output wire VAR2,
output wire VAR52
);
VAR11 #(
.VAR61("false"),
.VAR23("50.0 VAR64"),
.VAR42("VAR55"),
.VAR16(3),
.VAR69("100.000000 VAR64"),
.VAR35("0 VAR14"),
.VAR18(50),
.VAR7("40.000000 VAR64"),
.VAR59("0 VAR14"),
.VAR26(50),
.... | gpl-3.0 |
jayrandez/Processor | interpreter.v | 1,765 | module MODULE1(
input wire VAR2,
input wire VAR1,
output reg[31:0] VAR5,
output reg[31:0] VAR4,
input wire[31:0] VAR3,
output reg VAR7 = 0,
output reg VAR6 = 0
); | apache-2.0 |
manili/Pipelined_6502 | System.v | 3,324 | module MODULE1(
VAR43,
VAR66,
VAR4,
VAR24,
VAR33,
VAR10,
VAR31,
VAR58,
VAR17,
VAR35,
VAR71,
VAR78,
VAR44,
VAR62,
VAR50,
VAR22,
VAR56,
VAR3,
VAR57
,VAR40,
VAR9,
VAR7,
VAR67,
VAR54,
VAR63,
VAR28,
VAR11,
VAR77,
VAR45
);
input wire VAR43;
input wire VAR66;
input wire VAR4;
input wire VAR24;
input wire VAR33;
output wire VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xor3/sky130_fd_sc_ls__xor3.behavioral.pp.v | 1,845 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR12 ,
VAR2 ,
VAR11,
VAR7,
VAR9 ,
VAR3
);
output VAR1 ;
input VAR6 ;
input VAR12 ;
input VAR2 ;
input VAR11;
input VAR7;
input VAR9 ;
input VAR3 ;
wire VAR8 ;
wire VAR14;
xor VAR13 (VAR8 , VAR6, VAR12, VAR2 );
VAR4 VAR5 (VAR14, VAR8, VAR11, VAR7);
buf VAR10 (VAR1 , VAR14 );
endmodule | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | core/core_id_ex.v | 4,313 | module MODULE1( clk,
rst,
VAR12,
VAR5,
VAR8,
VAR16,
VAR2,
VAR6,
VAR9,
VAR18,
VAR1,
VAR3,
VAR25,
VAR20,
VAR23,
VAR21,
VAR26,
VAR13,
VAR30,
VAR15,
VAR10,
VAR24,
VAR7,
VAR17,
VAR27,
VAR19,
VAR14,
VAR22,
VAR4,
VAR28,
VAR29,
VAR11);
input clk;
input rst;
input VAR12;
input VAR5;
input VAR8;
input VAR16;
input VAR2;
input VA... | apache-2.0 |
manili/Pipelined_6502 | Other_Modules.v | 1,340 | module MODULE3(
out,
sel,
VAR7,
VAR8
);
parameter VAR4 = 8;
output wire [VAR4 - 1 : 0] out;
input wire sel;
input wire [VAR4 - 1 : 0] VAR7;
input wire [VAR4 - 1 : 0] VAR8;
assign out = (sel == 2'h0) ? VAR7 : VAR8;
endmodule
module MODULE2(
out,
sel,
VAR7,
VAR8,
VAR5,
VAR1
);
parameter VAR4 = 8;
output wire [VAR4 - 1 : ... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_inv.v | 3,299 | if (VAR3 && (VAR2==VAR18) && VAR12) \
begin: VAR5 \
VAR9 VAR11 (.VAR17(VAR7),.VAR4); \
end \
else \
if (VAR3 && (VAR2==VAR18) && ~VAR12) \
begin: VAR5 \
VAR1 VAR11 (.VAR17(VAR7),.VAR4); \
end
module MODULE1 #(parameter VAR15(VAR2)
, parameter VAR3=1
, parameter VAR12=1
)
(input [VAR2-1:0] VAR7
, output [VAR2-1:0] VAR4
... | bsd-3-clause |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_009bits.v | 1,917 | module MODULE1 (
clk,
VAR12, VAR3, VAR25, VAR17, VAR34, VAR19, VAR23, VAR7,
sum,
);
input clk;
input [VAR16+0-1:0] VAR12, VAR3, VAR25, VAR17, VAR34, VAR19, VAR23, VAR7;
output [VAR16 :0] sum;
reg [VAR16 :0] sum;
wire [VAR16+3-1:0] VAR24;
wire [VAR16+2-1:0] VAR11, VAR9;
wire [VAR16+1-1:0] VAR26, VAR27, VAR28, VAR30;
reg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/conb/sky130_fd_sc_hdll__conb.functional.pp.v | 1,911 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR8,
VAR14,
VAR6 ,
VAR12
);
output VAR9 ;
output VAR1 ;
input VAR8;
input VAR14;
input VAR6 ;
input VAR12 ;
wire VAR10 ;
wire VAR5;
pullup VAR4 (VAR10 );
VAR13 VAR3 (VAR9 , VAR10, VAR8 );
pulldown VAR11 (VAR5);
VAR7 VAR2 (VAR1 , VAR5, VAR14);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v | 2,030 | module MODULE1 #( parameter VAR1(VAR2 )
, parameter VAR1(VAR19 )
, parameter VAR4 = VAR26(VAR2)
, parameter VAR20 = VAR19>>3
, parameter VAR17 = 1
, parameter VAR15 = 1
)
( input VAR11
, input VAR5
, input VAR28
, input VAR24
, input [VAR4-1:0] VAR21
, input [VAR19-1:0] VAR23
, input [VAR20-1:0] VAR27
, output logic [V... | bsd-3-clause |
travisg/cpu | altera/top.v | 11,118 | module MODULE1(
input VAR17,
output [8:0] VAR3,
output [17:0] VAR7,
input [3:0] VAR10,
input [17:0] VAR8,
output [6:0] VAR2,
output [6:0] VAR11,
output [6:0] VAR1,
output [6:0] VAR18,
output [6:0] VAR4,
output [6:0] VAR15,
output [6:0] VAR13,
output [6:0] VAR14,
input VAR16,
output VAR12,
inout [35:0] VAR5,
input VAR6
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inv/sky130_fd_sc_hdll__inv.functional.pp.v | 1,766 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR12,
VAR7,
VAR6 ,
VAR3
);
output VAR2 ;
input VAR8 ;
input VAR12;
input VAR7;
input VAR6 ;
input VAR3 ;
wire VAR1 ;
wire VAR5;
not VAR11 (VAR1 , VAR8 );
VAR10 VAR9 (VAR5, VAR1, VAR12, VAR7);
buf VAR4 (VAR2 , VAR5 );
endmodule | apache-2.0 |
hakehuang/pycpld | ips/ip/uart7bit/uart_top7to7.v | 1,761 | module MODULE1(
clk,
VAR9,
VAR13,
VAR14,
VAR5,
VAR1
);
input clk; input VAR9;
input VAR13; input [2:0] VAR1;
output VAR14; output VAR5;
parameter VAR7 = 15;
wire [2:0] VAR1;
wire [6:0] VAR8, VAR20;
wire VAR15, VAR18;
wire VAR19;
reg [VAR7 - 1: 0] VAR21;
wire VAR17 ;
assign VAR17 = VAR21[VAR7 - 1];
always@(posedge clk o... | mit |
jameshegarty/rigel | platform/camera2.0/vsrc/DramReader.v | 3,607 | module MODULE1(
input VAR8,
input VAR6,
output VAR29,
output reg VAR19,
input VAR30,
output reg [31:0] VAR24,
output [1:0] VAR23,
output [3:0] VAR12,
output [1:0] VAR10,
input VAR13,
output VAR34,
input VAR31,
input [63:0] VAR33,
input [1:0] VAR9,
input VAR27,
output reg VAR5,
input [31:0] VAR21,
input [31:0] VAR32,
ou... | mit |
marqs85/ossc | rtl/lpm_mult_4_hybr_ref.v | 4,710 | module MODULE1 (
VAR20,
VAR13,
VAR15,
VAR8);
input VAR20;
input [8:0] VAR13;
input [7:0] VAR15;
output [8:0] VAR8;
wire [8:0] VAR1;
wire [8:0] VAR8 = VAR1[8:0];
VAR19 VAR10 (
.VAR20 (VAR20),
.VAR13 (VAR13),
.VAR15 (VAR15),
.VAR8 (VAR1),
.VAR11 (1'b0),
.VAR17 (1'b1),
.VAR18 (1'b0),
.sum (1'b0));
VAR10.VAR5 = "VAR6=9",
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41ai/sky130_fd_sc_ms__o41ai.blackbox.v | 1,375 | module MODULE1 (
VAR7 ,
VAR6,
VAR9,
VAR5,
VAR3,
VAR1
);
output VAR7 ;
input VAR6;
input VAR9;
input VAR5;
input VAR3;
input VAR1;
supply1 VAR8;
supply0 VAR2;
supply1 VAR10 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4/sky130_fd_sc_hs__or4.symbol.v | 1,246 | module MODULE1 (
input VAR7,
input VAR3,
input VAR6,
input VAR5,
output VAR4
);
supply1 VAR2;
supply0 VAR1;
endmodule | apache-2.0 |
yipenghuang0302/csee4840_14 | rtl/ik_swift_32/inverse/cholesky_block/sqrt_43/sqrt_43.v | 3,707 | module MODULE1 (
clk,
VAR1,
VAR5,
VAR8,
VAR4);
input clk;
input VAR1;
input [42:0] VAR5;
output [21:0] VAR8;
output [22:0] VAR4;
wire [21:0] VAR2;
wire [22:0] VAR7;
wire [21:0] VAR8 = VAR2[21:0];
wire [22:0] VAR4 = VAR7[22:0];
VAR11 VAR6 (
.clk (clk),
.VAR1 (VAR1),
.VAR5 (VAR5),
.VAR8 (VAR2),
.VAR4 (VAR7)
,
.VAR9 ()
);... | mit |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_pixout.v | 3,060 | module MODULE1 #(
parameter VAR2 = 26
) (
input VAR5,
input VAR17,
output reg VAR19,
input VAR21,
output reg VAR6,
input [VAR2-5-1:0] VAR12,
input [15:0] VAR23,
input [255:0] VAR16,
output reg [VAR2-1:0] VAR24,
output reg VAR22,
input VAR8,
output reg [7:0] VAR18,
output reg [63:0] VAR4
);
reg [15:0] VAR14;
reg [255:0]... | lgpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_AsyncResetRegVec_36.v | 2,676 | module MODULE1(
input VAR13,
input reset,
input [2:0] VAR20,
output [2:0] VAR12,
input VAR2
);
wire VAR11;
wire VAR30;
wire VAR29;
wire VAR8;
wire VAR4;
wire VAR15;
wire VAR25;
wire VAR17;
wire VAR19;
wire VAR9;
wire VAR21;
wire VAR18;
wire VAR16;
wire VAR1;
wire VAR3;
wire VAR7;
wire VAR22;
wire VAR28;
wire [1:0] VAR2... | apache-2.0 |
olgirard/openmsp430 | fpga/OBSOLETE/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_gpio.v | 35,207 | module MODULE1 (
VAR145, VAR215, VAR99, VAR250, VAR175, VAR190, VAR263, VAR143, VAR18, VAR159, VAR234, VAR39, VAR30, VAR168, VAR210, VAR192, VAR182, VAR105, VAR71, VAR183, VAR277,
VAR44, VAR86, VAR125, VAR85, VAR163, VAR164, VAR220, VAR208, VAR36, VAR216, VAR60, VAR49 );
parameter VAR15 = 1'b1; parameter VAR11 = 1'b1; ... | bsd-3-clause |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/altera_jtag_dc_streaming.v | 8,636 | module MODULE2 (
clk,
VAR56,
VAR18,
VAR62,
VAR66
);
input clk;
input VAR56;
input VAR18;
input VAR62;
output VAR66;
parameter VAR53 = 3;
reg VAR66;
wire VAR17;
reg VAR71;
VAR61 #(.VAR50(VAR53)) VAR63 (
.clk(clk),
.VAR56(VAR56),
.din(VAR18),
.dout(VAR17)
);
always @ (posedge clk or negedge VAR56)
if (~VAR56)
VAR71 <= 1'... | epl-1.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_2.behavioral.v | 2,113 | module MODULE1( VAR3, VAR11, VAR10 );
input VAR3, VAR11;
output VAR10;
reg VAR5;
VAR2 VAR8(.VAR3(VAR3),.VAR11(VAR11),.VAR10(VAR10),.VAR5(VAR5));
VAR2 VAR4(.VAR3(VAR3),.VAR11(VAR11),.VAR10(VAR10),.VAR5(VAR5));
not VAR7(VAR1,VAR11);
buf VAR9(VAR6,VAR11); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2b/sky130_fd_sc_ms__nand2b.symbol.v | 1,297 | module MODULE1 (
input VAR5,
input VAR1 ,
output VAR4
);
supply1 VAR6;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
jaruiz/ION | boards/zybo/zybo_top.v | 2,049 | module MODULE1
(
input VAR14,
input [3:0] VAR15,
input [3:0] VAR9,
output reg [3:0] VAR6,
output reg VAR4,
input VAR13
);
reg [31:0] VAR1;
wire [31:0] VAR11;
reg [31:0] VAR3;
reg reset;
VAR10 # (
.VAR8(1024)
)
VAR10 (
.VAR5 (VAR14),
.VAR7 (reset),
.VAR12 (VAR3),
.VAR2 (VAR11)
);
always @(*) begin
VAR6 =
VAR11[31:28] ^ ... | lgpl-3.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/Write_Master/byte_enable_generator.v | 31,072 | module MODULE6 (
clk,
reset,
VAR14,
VAR16,
VAR24,
VAR12,
VAR25
);
parameter VAR8 = 4;
input clk;
input reset;
input VAR14; input [VAR8-1:0] VAR16; output wire VAR24;
output wire [VAR8-1:0] VAR12; input VAR25;
generate
if (VAR8 == 1) begin
assign VAR12 = VAR16;
assign VAR24 = VAR25;
end
else if (VAR8 == 2)
begin
MODULE5... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtp/sky130_fd_sc_hs__dlrtp.pp.blackbox.v | 1,334 | module MODULE1 (
VAR2,
VAR3 ,
VAR1 ,
VAR5 ,
VAR4 ,
VAR6
);
input VAR2;
input VAR3 ;
input VAR1 ;
output VAR5 ;
input VAR4 ;
input VAR6 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/controller/rank_cntrl.v | 20,921 | module MODULE1 #
(
parameter VAR9 = 100, parameter VAR88 = "8", parameter VAR55 = 5, parameter VAR61 = 5, parameter VAR77 = 0, parameter VAR42 = 4, parameter VAR101 = 2, parameter VAR90 = 30, parameter VAR56 = 8, parameter VAR76 = 4, parameter VAR24 = 4, parameter VAR27 = 20, parameter VAR87 = 16, parameter VAR44 = 2, ... | lgpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_PPS_OPENFLOW/DISPATHER/DISPATHER_INPUT.v | 6,606 | module MODULE1(
input clk,
input reset,
input [4:0] VAR7,input VAR36,
input VAR44,
output reg VAR3,
output reg [4:0] VAR29,
input VAR17,
input [133:0] VAR30,
input VAR41,
input VAR9,
output VAR27,
output reg VAR26,
output reg [133:0] VAR42,
output reg VAR23,
output reg VAR31,
input VAR15,
output reg VAR6,
output reg [1... | apache-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/SpecialAddProcess.v | 5,627 | module MODULE1(
input [31:0] VAR7,
input [3:0] VAR13,
input [31:0] VAR27,
input [31:0] VAR11,
input [7:0] VAR20,
input VAR17,
output reg VAR30 = 1'b0,
output reg [7:0] VAR1,
output reg [35:0] VAR28,
output reg [35:0] VAR12,
output reg [31:0] VAR2,
output reg [3:0] VAR8,
output reg [31:0] VAR15,
output reg [7:0] VAR32
)... | apache-2.0 |
ineganov/flight_control | hard/mcpu.v | 7,446 | module MODULE1( input VAR46,
input VAR22,
input VAR33,
input VAR1,
output [29:0] VAR37,
input [31:0] VAR16,
output VAR17,
output [3:0] VAR36,
output [29:0] VAR40,
output [31:0] VAR2,
input [31:0] VAR45 );
wire VAR51, VAR9, VAR26, VAR42,
VAR15, VAR3, VAR54, VAR44, VAR23,
VAR35, VAR39, VAR34, VAR18,
VAR48, VAR41, VAR47,
... | gpl-2.0 |
golfit/QcmPhaseDelayBoard | Decoder.v | 4,701 | module MODULE1(clk, VAR1, VAR10);
parameter VAR13=7;
parameter VAR5=13;
parameter VAR8=127;
input clk, VAR1;
output wire [VAR13-1:0] VAR10;
reg [VAR13-1:0] VAR12, VAR7;
reg [3:0] VAR4;
reg VAR9;
reg [VAR5-1:0] VAR6, VAR3, VAR11;
reg [1:0] VAR2;
reg VAR14;
assign VAR10=VAR7; | mit |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/sfp/triple_speed_ethernet-library/altera_tse_pcs.v | 7,088 | module MODULE1 (
VAR34, VAR13, VAR40, VAR25, VAR9, VAR52, VAR5, VAR30, VAR3,
VAR7,
VAR15,
VAR41,
VAR10,
VAR19,
VAR29,
VAR14,
VAR47,
VAR48,
VAR21,
VAR50,
VAR12,
VAR1,
VAR31,
VAR32,
VAR51,
VAR26,
VAR20,
VAR18,
VAR39,
VAR6,
VAR23,
VAR4,
VAR16,
VAR22,
VAR45,
VAR8,
VAR49,
VAR35,
VAR43,
VAR27,
VAR37,
VAR33,
VAR42,
VAR11);
pa... | apache-2.0 |
mlarouche/sd2snes | verilog/sd2snes_cx4/main.v | 19,587 | module MODULE1(
input VAR264,
input [23:0] VAR287,
input VAR171,
input VAR229,
input VAR19,
inout [7:0] VAR273,
input VAR284,
input VAR281,
output VAR113,
output VAR169,
output VAR78,
input VAR128,
input [7:0] VAR94,
input VAR179,
input VAR153,
inout [15:0] VAR73,
output [22:0] VAR306,
output VAR204,
output VAR162,
out... | gpl-2.0 |
masc-ucsc/cmpe220fall16 | rtl/DC_1_tagbank.v | 5,109 | module MODULE1 #(parameter VAR16 = 15, VAR22 =256, VAR14=0)
(
input clk
,input reset
,input VAR34
,input VAR2
,input VAR11 ,input [7:0] VAR8
,input [VAR16-1:0] VAR12
,output VAR13
,output VAR24
,output [14:0] VAR1
,input VAR9
,output VAR7
,input [4:0] VAR25
,input VAR4
,output VAR5
,input [6:0] VAR29
,input VAR20
,inpu... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_4.functional.v | 1,909 | module MODULE1( VAR18, VAR14, VAR20, VAR24, VAR22, VAR25, VAR15 );
input VAR25, VAR15, VAR24, VAR22, VAR18, VAR20;
output VAR14;
wire VAR23;
not VAR17( VAR23, VAR25 );
wire VAR7;
not VAR5( VAR7, VAR15 );
wire VAR6;
and VAR12( VAR6, VAR23, VAR7 );
wire VAR8;
not VAR10( VAR8, VAR24 );
wire VAR2;
not VAR4( VAR2, VAR22 );
... | apache-2.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/core/coreahblite_masterstage.v | 16,325 | module MODULE1 #(
parameter [2:0]VAR43 = 0,
parameter [0:0]VAR51 = 1,
parameter [15:0]VAR48 = 0,
parameter [16:0]VAR88 = (2**17)-1
)
(
input VAR102,
input VAR87,
input [31:0] VAR23,
input VAR29,
input [2:0] VAR59,
input VAR68,
input VAR81,
output reg VAR69,
output reg [31:0] VAR1,
output wire VAR44,
input VAR74,
input ... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_020bits.v | 1,917 | module MODULE2 (
clk,
VAR26, VAR22, VAR33, VAR14, VAR21, VAR18, VAR13, VAR32,
sum,
);
input clk;
input [VAR34+0-1:0] VAR26, VAR22, VAR33, VAR14, VAR21, VAR18, VAR13, VAR32;
output [VAR34 :0] sum;
reg [VAR34 :0] sum;
wire [VAR34+3-1:0] VAR19;
wire [VAR34+2-1:0] VAR29, VAR9;
wire [VAR34+1-1:0] VAR1, VAR7, VAR24, VAR16;
r... | mit |
calee0219/Course | DLAB/Lab09/VGA_0416037_李家安.v | 30,693 | module MODULE1(
output VAR25,
output VAR47,
output VAR31,
output VAR120,
output VAR138,
input rst,
input clk
);
parameter VAR156 = 104;
parameter VAR78 = 904;
parameter VAR33 = 504;
parameter VAR72 = 24;
parameter VAR6 = 632;
parameter VAR34 = 328;
parameter VAR153 = 70; parameter VAR79 = 150; parameter VAR28 = 482; pa... | mit |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/cpu/ctrl.v | 9,229 | module MODULE1 (
input wire clk,
input wire reset,
input wire [VAR29] VAR37,
output reg [VAR10] VAR31,
output reg [VAR46] VAR22,
input wire [VAR15-1:0] irq,
output reg VAR56,
input wire [VAR40] VAR33,
input wire [VAR40] VAR1,
input wire VAR18,
input wire VAR2,
input wire [VAR19] VAR6,
input wire [VAR29] VAR51,
input wi... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21bo/sky130_fd_sc_lp__a21bo.pp.blackbox.v | 1,392 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR7 ,
VAR3,
VAR8,
VAR6,
VAR5 ,
VAR2
);
output VAR4 ;
input VAR1 ;
input VAR7 ;
input VAR3;
input VAR8;
input VAR6;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
mamijaz/RISC-V | src/riscv_pipeline/decode/INSTRUCTION_DECODER.v | 24,970 | module MODULE1 #(
parameter VAR98 = 32 ,
parameter VAR31 = 32 ,
parameter VAR40 = 5 ,
parameter VAR33 = 5 ,
parameter VAR17 = 3 ,
parameter VAR7 = 3 ,
parameter VAR96 = 2 ,
parameter VAR114 = 7'b0110111 ,
parameter VAR26 = 7'b0010111 ,
parameter VAR101 = 7'b1101111 ,
parameter VAR73 = 7'b1100111 ,
parameter VAR82 = 7'b... | bsd-2-clause |
peteasa/parallella-fpga | AdiHDLLib/library/common/up_adc_channel.v | 13,997 | module MODULE1 (
VAR37,
VAR80,
VAR84,
VAR29,
VAR18,
VAR64,
VAR1,
VAR22,
VAR17,
VAR48,
VAR19,
VAR6,
VAR9,
VAR70,
VAR51,
VAR34,
VAR71,
VAR75,
VAR24,
VAR41,
VAR69,
VAR82,
VAR40,
VAR61,
VAR52,
VAR68,
VAR83,
VAR76,
VAR74,
VAR72,
VAR20,
VAR8,
VAR21,
VAR57,
VAR31,
VAR79,
VAR59,
VAR49,
VAR13,
VAR15,
VAR46,
VAR28,
VAR65,
VAR16)... | lgpl-3.0 |
horia141/bachelor-thesis | prj/components/RegBank/RegBankS4.v | 6,871 | module MODULE1(VAR25,reset,VAR14,VAR24,out);
input wire VAR25;
input wire reset;
input wire [11:0] VAR14;
input wire VAR24;
output wire [7:0] out;
reg [1:0] VAR30;
reg [1:0] VAR8;
reg [7:0] VAR10;
reg [7:0] VAR11;
reg [7:0] VAR9;
reg [7:0] VAR1;
wire [7:0] VAR3;
wire [3:0] VAR22;
wire [7:0] VAR5;
wire [1:0] VAR2;
reg [... | mit |
joaocarlos/udlx-verilog | rtl/common/clk_rst_mngr.v | 1,150 | module MODULE1 (
input VAR4,
input VAR8,
input VAR12,
output VAR1,
output VAR7,
output VAR6,
output VAR3,
output VAR9,
output VAR2
);
reg [2:0] counter;
reg VAR5, VAR10;
reg VAR11;
always@(posedge VAR4)begin
if(!VAR8)
counter <= 0;
end
else
counter <= counter-1;
end
assign VAR7 = VAR4;
assign VAR6 = counter[0];
assign ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso1p/sky130_fd_sc_hdll__inputiso1p_1.v | 2,273 | module MODULE2 (
VAR9 ,
VAR8 ,
VAR5,
VAR6 ,
VAR7 ,
VAR1 ,
VAR4
);
output VAR9 ;
input VAR8 ;
input VAR5;
input VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR4 ;
VAR2 VAR3 (
.VAR9(VAR9),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR9 ,
VAR8 ,
VAR5
);
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2/sky130_fd_sc_lp__nor2.blackbox.v | 1,233 | module MODULE1 (
VAR3,
VAR5,
VAR1
);
output VAR3;
input VAR5;
input VAR1;
supply1 VAR4;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
sam-falvo/polaris | ramcon/rtl/verilog/kseq.v | 5,448 | module MODULE1(
input VAR100,
input VAR18,
input VAR94,
input VAR41,
input VAR1,
input VAR44,
input VAR8,
input VAR86,
input VAR93,
input VAR47,
input VAR25,
input VAR99,
output VAR40,
output VAR49,
output VAR112,
output VAR109,
output VAR37,
output VAR65,
output VAR43,
output VAR95,
output VAR46,
output VAR54,
output ... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp.pp.symbol.v | 1,414 | module MODULE1 (
input VAR1 ,
output VAR6 ,
input VAR4,
input VAR7 ,
input VAR3,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
KorotkiyEugene/Netmaker_vc_router_syn_quartus | unary_select_pair.v | 1,719 | module MODULE1 (VAR8, VAR7, VAR11, VAR3);
parameter VAR1 = 0; parameter VAR13 = 4;
parameter VAR9 = 4;
input [VAR13-1:0] VAR8;
input [VAR9-1:0] VAR7;
input [VAR13*VAR9-1:0] VAR11;
output VAR3;
genvar VAR10,VAR5;
wire [VAR13*VAR9-1:0] VAR12;
generate
for (VAR10=0; VAR10<VAR13; VAR10=VAR10+1) begin:VAR2
for (VAR5=0; VAR5... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_1.behavioral.pp.v | 1,407 | module MODULE1( VAR2, VAR7, VAR5, VAR8, VAR4, VAR3, VAR10 );
input VAR4, VAR8, VAR5, VAR2;
inout VAR3, VAR10;
output VAR7;
VAR1 VAR9(.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5),.VAR8(VAR8),.VAR4(VAR4),.VAR3(VAR3),.VAR10(VAR10));
VAR1 VAR6(.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5),.VAR8(VAR8),.VAR4(VAR4),.VAR3(VAR3),.VAR10(VAR10)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_ground_lvc_wpad/sky130_fd_io__top_ground_lvc_wpad.pp.blackbox.v | 2,066 | module MODULE1 (
VAR3 ,
VAR20 ,
VAR14 ,
VAR8,
VAR11,
VAR19 ,
VAR10 ,
VAR15 ,
VAR17 ,
VAR7 ,
VAR2 ,
VAR9 ,
VAR16 ,
VAR18 ,
VAR1 ,
VAR6 ,
VAR5 ,
VAR4 ,
VAR13 ,
VAR12
);
inout VAR3 ;
inout VAR20 ;
inout VAR14 ;
inout VAR8;
inout VAR11;
inout VAR19 ;
inout VAR10 ;
inout VAR15 ;
inout VAR17 ;
inout VAR7 ;
inout VAR2 ;
inout... | apache-2.0 |
martinmiranda14/Digitales | Lab_6/new/flags_monitor.v | 1,294 | module MODULE1(
input [3:0] flag,
output reg [11:0] VAR1,
output reg [11:0] VAR4,
output reg [11:0] VAR3,
output reg [11:0] VAR2
);
always @ begin
if (flag[2]==1'b1)
VAR4= 12'h0F0;
end
else
VAR4= 12'h000;
end
always @ begin
if (flag[0]==1'b1)
VAR2= 12'h0F0;
end
else
VAR2= 12'h000;
end
endmodule | apache-2.0 |
tomhartley/EIEProj | dot_product/dot_product/dot_product.v7/concat_rtl.v | 36,040 | module MODULE21 (VAR74, VAR3);
parameter integer VAR87 = 1;
parameter integer VAR10 = 8;
output [VAR10-1:0] VAR74;
input [VAR10-1:0] VAR3;
wire [VAR10-1:0] VAR74;
assign VAR74 = VAR3;
endmodule
module MODULE9 (VAR54, VAR74, VAR40, VAR3);
parameter integer VAR87 = 1;
parameter integer VAR10 = 8;
input VAR54;
output [VAR... | mit |
dagrende/rpi_fpga_stepper | wdt.v | 1,259 | module MODULE1(clk, VAR3, VAR2, out);
input clk, VAR3, VAR2;
output out;
reg [6:0] VAR1;
wire VAR5 = (VAR1 == 7'd127);
reg VAR4;
wire out = VAR4 && VAR5;
always @(posedge clk) begin
if(VAR3) begin
VAR4 <= 1;
VAR1 <= 0;
end
else if(VAR2 && !VAR5) VAR1 <= VAR1 + 7'd1;
end
endmodule | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_1.behavioral.pp.v | 1,164 | module MODULE1( VAR4, VAR5, VAR1, VAR2 );
input VAR4;
inout VAR1, VAR2;
output VAR5;
VAR3 VAR6(.VAR4(VAR4),.VAR5(VAR5),.VAR1(VAR1),.VAR2(VAR2));
VAR3 VAR7(.VAR4(VAR4),.VAR5(VAR5),.VAR1(VAR1),.VAR2(VAR2)); | apache-2.0 |
zYeoman/32BIT-MIPS-CPU | pipeline/Control.v | 5,208 | module MODULE1 (
input irq, VAR31,
input [5:0] VAR8, VAR15,
output [2:0] VAR17,
output [1:0] VAR27, VAR33, output VAR6, VAR13, VAR7, VAR26,
VAR10, VAR1, VAR32, VAR14, VAR11,
output reg VAR35,
output reg [5:0] VAR21
);
wire VAR2; reg [5:0] VAR5;
parameter VAR20 = 6'b000000;
parameter VAR12 = 6'b000001;
parameter VAR16 =... | gpl-2.0 |
fallen/milkymist-mmu | cores/ac97/rtl/ac97.v | 5,024 | module MODULE1 #(
parameter VAR52 = 4'h0
) (
input VAR71,
input VAR20,
input VAR19,
input VAR6,
input VAR26,
output VAR68,
output VAR59,
input [13:0] VAR23,
input VAR65,
input [31:0] VAR18,
output [31:0] VAR54,
output VAR29,
output VAR76,
output VAR42,
output VAR74,
output [31:0] VAR58,
output [2:0] VAR77,
output VAR66... | lgpl-3.0 |
alexforencich/hdg2000 | fpga/lib/dsp/rtl/iq_split.v | 2,771 | module MODULE1 #
(
parameter VAR10 = 16
)
(
input wire clk,
input wire rst,
input wire [VAR10-1:0] VAR8,
input wire [VAR10-1:0] VAR3,
input wire VAR15,
output wire VAR7,
output wire [VAR10-1:0] VAR9,
output wire VAR4,
input wire VAR2,
output wire [VAR10-1:0] VAR1,
output wire VAR13,
input wire VAR14
);
reg [VAR10-1:0] ... | mit |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_mem.v | 3,349 | module MODULE1 (
VAR10,
VAR1,
VAR8,
VAR2,
VAR6,
VAR3,
VAR5);
parameter VAR9 = 16;
parameter VAR4 = 5;
input VAR10;
input VAR1;
input [VAR4-1:0] VAR8;
input [VAR9-1:0] VAR2;
input VAR6;
input [VAR4-1:0] VAR3;
output [VAR9-1:0] VAR5;
reg [VAR9-1:0] VAR7[0:((2**VAR4)-1)];
reg [VAR9-1:0] VAR5;
always @(posedge VAR10) begin... | mit |
kramble/FPGA-Litecoin-Miner | experimental/hashvariant-C.v | 23,174 | module MODULE1 (VAR125, VAR166, VAR45, VAR99, VAR44, VAR68, VAR61, VAR133, VAR157, VAR12);
input VAR125;
input [255:0] VAR166;
input [255:0] VAR45;
input [127:0] VAR99;
input [31:0] VAR44;
input [3:0] VAR68; output [31:0] VAR61;
output [31:0] VAR133;
output VAR157; input VAR12;
reg VAR155 = 1'b1;
reg reset = 1'b1;
reg ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21oi/sky130_fd_sc_ms__a21oi.behavioral.pp.v | 2,006 | module MODULE1 (
VAR14 ,
VAR5 ,
VAR6 ,
VAR16 ,
VAR4,
VAR12,
VAR15 ,
VAR8
);
output VAR14 ;
input VAR5 ;
input VAR6 ;
input VAR16 ;
input VAR4;
input VAR12;
input VAR15 ;
input VAR8 ;
wire VAR1 ;
wire VAR3 ;
wire VAR9;
and VAR2 (VAR1 , VAR5, VAR6 );
nor VAR11 (VAR3 , VAR16, VAR1 );
VAR13 VAR7 (VAR9, VAR3, VAR4, VAR12);
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkbuf/sky130_fd_sc_hd__clkbuf_4.v | 2,034 | module MODULE2 (
VAR1 ,
VAR8 ,
VAR6,
VAR4,
VAR3 ,
VAR7
);
output VAR1 ;
input VAR8 ;
input VAR6;
input VAR4;
input VAR3 ;
input VAR7 ;
VAR2 VAR5 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR1,
VAR8
);
output VAR1;
input VAR8;
supply1 VAR6;
supply0 VAR4;... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/pcie_7x_v1_8_qpll_wrapper.v | 28,520 | module MODULE1 #
(
parameter VAR126 = "VAR56", parameter VAR114 = "VAR7", parameter VAR64 = "1.1", parameter VAR8 = "VAR23", parameter VAR102 = 0
)
(
input VAR136,
input VAR3,
output VAR127,
output VAR95,
output VAR75,
input VAR38,
input VAR70,
input VAR54,
input [ 7:0] VAR57,
input VAR19,
input [15:0] VAR4,
input VAR7... | mit |
combinatorylogic/soc | backends/c2/hw/blackice2/ice.v | 6,506 | module MODULE1(input clk,
input rst,
input VAR31,
output VAR5,
output [31:0] VAR17,
output reg VAR38,
input [31:0] VAR34,
input [31:0] VAR13,
input [31:0] VAR42);
wire VAR3;
VAR26 VAR43(.clk(clk), .VAR36(VAR31), .rd(VAR3));
reg VAR39, VAR37, VAR15, VAR45;
wire VAR51, VAR44;
wire [7:0] VAR12;
reg [7:0] VAR29;
wire [7:0]... | mit |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/dds/dds_stub.v | 1,531 | module MODULE1(VAR6, VAR4, VAR7, VAR2, VAR5, VAR1, VAR3)
;
input VAR6;
input VAR4;
input [23:0]VAR7;
output VAR2;
output [31:0]VAR5;
output VAR1;
output [23:0]VAR3;
endmodule | gpl-2.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/rli/pass_through.v | 3,816 | module MODULE1(
clk,
reset,
VAR7,
VAR22,
VAR25,
VAR9,
VAR27,
VAR23,
VAR14,
VAR15,
VAR16,
VAR24
);
input clk;
input reset;
input VAR7;
input [138:0]VAR22;
output [7:0]VAR25;
input VAR9;
input VAR27;
output VAR23;
output [138:0]VAR14;
input [7:0]VAR15;
output VAR16;
output VAR24;
reg VAR23;
reg [138:0]VAR14;
reg VAR16;
r... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufinv/sky130_fd_sc_hs__bufinv.blackbox.v | 1,202 | module MODULE1 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
supply1 VAR2;
supply0 VAR4;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_250/source/pcie_7x_v1_3_gt_rx_valid_filter_7x.v | 9,415 | module MODULE1 #(
parameter VAR42 = 28,
parameter VAR19 = 1
)
(
output [1:0] VAR34,
output [15:0] VAR31,
output VAR41,
output VAR35,
output [ 2:0] VAR17,
output VAR40,
input [1:0] VAR12,
input [15:0] VAR5,
input VAR39,
input VAR14,
input [ 2:0] VAR1,
input VAR6,
input VAR16,
input VAR44,
input VAR38,
input VAR7
);
loca... | lgpl-3.0 |
berickson1/ECE492 | Quartus/ip/TERASIC_CAMERA/CAMERA_IF.v | 2,703 | module MODULE1( VAR10,
VAR13,
VAR7,
VAR3,
VAR5,
VAR12,
VAR14,
VAR11,
VAR8,
VAR2,
VAR9,
VAR6,
VAR1,
VAR4
);
input VAR10;
input [1:0] VAR13;
output [31:0] VAR7;
input VAR3;
input [31:0] VAR5;
input VAR12;
input VAR14;
output VAR11;
output [1:0] VAR8;
input [31:0] VAR2;
output VAR9;
output [31:0] VAR6;
output VAR1;
output... | gpl-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_nh_lcd/rtl/nh_lcd_command.v | 2,287 | module MODULE1 (
input rst,
input clk,
output [31:0] VAR9,
input VAR11,
input VAR12,
input [7:0] VAR8,
output reg [7:0] VAR3,
input VAR10,
input VAR13,
output reg VAR15,
output VAR4,
output reg VAR5,
output reg VAR16,
output reg [7:0] VAR2,
input [7:0] VAR7,
output reg VAR6
);
localparam VAR1 = 4'h0;
localparam VAR14 =... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbp/sky130_fd_sc_hs__dlrbp.functional.pp.v | 1,930 | module MODULE1 (
VAR7 ,
VAR11 ,
VAR6 ,
VAR14 ,
VAR2,
VAR5 ,
VAR9
);
input VAR7 ;
input VAR11 ;
output VAR6 ;
output VAR14 ;
input VAR2;
input VAR5 ;
input VAR9 ;
wire VAR3;
wire VAR1;
not VAR15 (VAR3 , VAR2 );
VAR12 VAR4 VAR10 (VAR1 , VAR5, VAR9, VAR3, VAR7, VAR11);
buf VAR8 (VAR6 , VAR1 );
not VAR13 (VAR14 , VAR1 );
e... | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/MULT_FIRSQ/MULT_FIRSQ_bb.v | 3,522 | module MODULE1 (
VAR2,
VAR1);
input [29:0] VAR2;
output [59:0] VAR1;
endmodule | gpl-2.0 |
jotego/jt12 | hdl/adpcm/jt10_adpcm_gain.v | 5,174 | module MODULE1(
input VAR26,
input clk, input VAR13, input [5:0] VAR37,
input [5:0] VAR35,
input VAR1,
input [5:0] VAR7, input [7:0] VAR14,
input [2:0] VAR16,
output [1:0] VAR21,
input signed [15:0] VAR10,
output signed [15:0] VAR9
);
reg [5:0] VAR15;
always @
case( VAR34[2:0] )
3'd0: VAR39 = 10'd512;
3'd1: VAR39 = 10'... | gpl-3.0 |
cpulabs/mist1032sa | src/core/pipeline_control/core_interrupt_manager.v | 4,417 | module MODULE1(
input wire VAR27,
input wire VAR28,
input wire VAR34,
input wire VAR32,
input wire [5:0] VAR30,
input wire VAR15,
input wire VAR8,
input wire [1:0] VAR16,
input wire [31:0] VAR14,
input wire VAR17,
input wire [5:0] VAR3,
output wire VAR4,
input wire VAR18,
input wire [6:0] VAR22,
input wire [31:0] VAR11... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtp/sky130_fd_sc_ms__dlrtp.symbol.v | 1,428 | module MODULE1 (
input VAR1 ,
output VAR4 ,
input VAR5,
input VAR7
);
supply1 VAR3;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
Canaan-Creative/MM | verilog/superkdf9/components/lm32_top/lm32_instruction_unit.v | 32,524 | module MODULE1 (
VAR35,
VAR39,
VAR63,
VAR114,
VAR157,
VAR65,
VAR83,
VAR152,
VAR85,
VAR79,
VAR109,
VAR74,
VAR55,
VAR28,
VAR102,
VAR133,
VAR13,
VAR67,
VAR59,
VAR40,
VAR164,
VAR68,
VAR62,
VAR119,
VAR78,
VAR168,
VAR165,
VAR166,
VAR121,
VAR100,
VAR64,
VAR22,
VAR16,
VAR20,
VAR98,
VAR163,
VAR134,
VAR49,
VAR161,
VAR144,
VAR147... | unlicense |
vipinkmenon/fpgadriver | src/hw/fpga/source/user_logic_if/user_pcie_stream_generator.v | 9,281 | module MODULE1
parameter VAR59 = 8'd0
)
(
input VAR2,
input VAR47,
input VAR23,
input VAR11,
input VAR3,
output reg VAR62,
input VAR6,
input [31:0] VAR35,
input [31:0] VAR36,
input [31:0] VAR42,
output reg VAR38,
input VAR54,
input [31:0] VAR18,
output reg VAR49,
input VAR34,
input [7:0] VAR28,
input VAR14,
input [63:0... | mit |
alexforencich/xfcp | rtl/xfcp_mod_i2c_master.v | 28,609 | module MODULE1 #
(
parameter VAR8 = 16'h2C00,
parameter VAR9 = "VAR21 VAR14",
parameter VAR17 = 0,
parameter VAR33 = "",
parameter VAR13 = 1
)
(
input wire clk,
input wire rst,
input wire [7:0] VAR10,
input wire VAR1,
output wire VAR7,
input wire VAR6,
input wire VAR4,
output wire [7:0] VAR31,
output wire VAR29,
input ... | mit |
VishalRohra/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/crypto_aes/rtl/verilog/wb_aes_ctrl.v | 5,123 | module MODULE1 (
input VAR7,
input VAR9,
input [31:0] VAR22,
input [31:0] VAR27,
input [3:0] VAR11,
input VAR20,
input [1:0] VAR21,
input [2:0] VAR34,
input VAR36,
input VAR30,
output reg VAR32,
output VAR19,
output VAR6,
output reg [31:0] VAR31,
output reg [255:0] VAR16,
output reg VAR5,
output reg [1:0] VAR12,
output... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_i2s/rtl/wb_i2s.v | 12,379 | module MODULE1 (
input clk,
input rst,
input VAR90,
input VAR30,
input VAR46,
input [3:0] VAR58,
input [31:0] VAR106,
input [31:0] VAR77,
output reg [31:0] VAR91,
output reg VAR16,
output reg VAR17,
output VAR60,
output VAR41,
output VAR83,
output [3:0] VAR65,
output [31:0] VAR56,
output [31:0] VAR23,
input [31:0] VAR7... | mit |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/Read_Master/read_burst_control.v | 4,543 | module MODULE1 (
address,
VAR12,
VAR13,
VAR7,
VAR8,
VAR1,
VAR11
);
parameter VAR9 = 1; parameter VAR15 = 3;
parameter VAR17 = 2; parameter VAR10 = 32;
parameter VAR3 = 32;
parameter VAR5 = 1; localparam VAR16 = (VAR15 == 1)? 1: (VAR15-1);
input [VAR10-1:0] address;
input [VAR3-1:0] VAR12;
input [VAR15-1:0] VAR13; input... | mit |
alexforencich/verilog-ethernet | example/AU250/fpga_10g/rtl/fpga.v | 23,146 | module MODULE1 (
input wire reset,
input wire [3:0] VAR51,
output wire [2:0] VAR139,
inout wire VAR132,
inout wire VAR20,
output wire VAR70,
output wire VAR17,
input wire VAR15,
input wire VAR213,
output wire VAR224,
output wire VAR31,
input wire VAR338,
input wire VAR115,
output wire VAR171,
output wire VAR293,
input ... | mit |
praveendath92/securePUF | ipcore_dir/emac_single/example_design/client/fifo/rx_client_fifo_8.v | 29,974 | module MODULE1
(
VAR82,
VAR12,
VAR102,
VAR77,
VAR41,
VAR74,
VAR67,
VAR36,
VAR42,
VAR20,
VAR56,
VAR16,
VAR40,
VAR44,
VAR9,
VAR103
);
input VAR82;
input VAR12;
output [7:0] VAR102;
output VAR77;
output VAR41;
output VAR74;
input VAR67;
output [3:0] VAR36;
input VAR42;
input VAR20;
input VAR56;
input [7:0] VAR16;
input VA... | gpl-2.0 |
trander1/Dual-Core-Processor | FinalProjectV3/Modules/alu.v | 8,357 | module MODULE1 (
VAR20,VAR26, VAR68,
VAR6, VAR28, clk
);
parameter VAR47 = 4;
parameter VAR14 = 8;
parameter VAR43 = VAR47 + VAR14 + VAR14;
parameter VAR51 = 4'b0000;
parameter VAR17 = 4'b0001;
parameter VAR48 = 4'b0010;
parameter VAR19 = 4'b0011;
parameter VAR24 = 4'b0100;
parameter VAR27 = 4'b0110;
parameter VAR52 = ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21a/sky130_fd_sc_ms__o21a.pp.blackbox.v | 1,351 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR8 ,
VAR6 ,
VAR1,
VAR5,
VAR7 ,
VAR4
);
output VAR3 ;
input VAR2 ;
input VAR8 ;
input VAR6 ;
input VAR1;
input VAR5;
input VAR7 ;
input VAR4 ;
endmodule | apache-2.0 |
alexforencich/hdg2000 | fpga/rtl/soc_interface.v | 17,293 | module MODULE1
(
input wire clk,
input wire rst,
input wire [7:0] VAR74,
input wire VAR7,
output wire VAR54,
input wire VAR83,
output wire [7:0] VAR6,
output wire VAR2,
input wire VAR3,
output wire VAR49,
output wire VAR85,
output wire VAR31,
output wire [2:0] VAR69,
output wire [5:0] VAR13,
output wire [31:0] VAR95,
i... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s18/sky130_fd_sc_hd__clkdlybuf4s18_1.v | 2,163 | module MODULE2 (
VAR7 ,
VAR3 ,
VAR8,
VAR5,
VAR2 ,
VAR6
);
output VAR7 ;
input VAR3 ;
input VAR8;
input VAR5;
input VAR2 ;
input VAR6 ;
VAR1 VAR4 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR7,
VAR3
);
output VAR7;
input VAR3;
supply1 VAR8;
supply0 VAR5;... | apache-2.0 |
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