repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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HarmonInstruments/verilog | sincos/cosgen.v | 1,179 | module MODULE1 (input VAR5, input [25:0] VAR1, output signed [VAR12-1:0] VAR11);
parameter VAR12 = 23;
reg [23:0] VAR2 = 0;
reg VAR15 = 0;
always @ (posedge VAR5) begin
VAR2 <= VAR1[24] ? ~ VAR1[23:0] : VAR1[23:0];
VAR15 <= VAR1[25] ^ VAR1[24];
end
wire [34:0] VAR10;
VAR3 VAR3
(.VAR5(VAR5), .VAR2(VAR2[23:14]), .VAR6(10... | gpl-3.0 |
J-Ford/374CPU | registers.v | 2,758 | module MODULE1(VAR14, VAR18, clk, VAR19, VAR11);
input VAR18,clk, VAR19;
input [31:0] VAR11;
output [31:0]VAR14;
reg[31:0] VAR14;
always @ (posedge clk)begin
if(VAR18) begin
VAR14 = 32'h00000000;
end
if(VAR19) begin
VAR14 = VAR11;
end
end
endmodule
module MODULE6(VAR14, VAR18, clk, VAR2, VAR19, VAR11);
input VAR18,clk,... | mit |
subailong/miaow | src/verilog/rtl/issue/instr_info_table.v | 2,875 | module MODULE1
(
VAR18, VAR8, VAR19,
VAR34, VAR24,
VAR9, clk, rst, VAR23, VAR30,
VAR17, VAR11,
VAR3, VAR13, VAR12
);
input VAR9;
input clk, rst;
input [VAR28-1:0] VAR23;
input [VAR26-1:0] VAR30;
input [VAR28-1:0] VAR17, VAR11,
VAR3, VAR13,
VAR12;
output [VAR26-1:0] VAR18, VAR8,
VAR19, VAR34,
VAR24;
wire [VAR26-1:0] VAR... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41oi/sky130_fd_sc_lp__a41oi_m.v | 2,436 | module MODULE2 (
VAR7 ,
VAR9 ,
VAR12 ,
VAR6 ,
VAR4 ,
VAR3 ,
VAR8,
VAR11,
VAR1 ,
VAR5
);
output VAR7 ;
input VAR9 ;
input VAR12 ;
input VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR8;
input VAR11;
input VAR1 ;
input VAR5 ;
VAR10 VAR2 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR12(VAR12),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VA... | apache-2.0 |
dawsonjon/fpu | float_to_int/file_reader_a.v | 7,932 | module MODULE1(VAR2,clk,rst,VAR19,VAR14);
integer VAR37;
integer VAR33;
input VAR2;
input clk;
input rst;
output [31:0] VAR19;
output VAR14;
reg [31:0] VAR27;
reg VAR32;
reg VAR17;
reg VAR25;
reg VAR39;
reg [3:0] VAR18;
reg [3:0] VAR34;
reg [39:0] VAR3;
reg [3:0] VAR16;
reg [1:0] VAR30;
reg [1:0] VAR22;
reg [1:0] VAR15... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4/sky130_fd_sc_lp__nand4.behavioral.pp.v | 1,846 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR4 ,
VAR3 ,
VAR6 ,
VAR14,
VAR15,
VAR5 ,
VAR7
);
output VAR2 ;
input VAR8 ;
input VAR4 ;
input VAR3 ;
input VAR6 ;
input VAR14;
input VAR15;
input VAR5 ;
input VAR7 ;
wire VAR13 ;
wire VAR10;
nand VAR1 (VAR13 , VAR6, VAR3, VAR4, VAR8 );
VAR12 VAR11 (VAR10, VAR13, VAR14, VAR15);
buf VAR9 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2/sky130_fd_sc_lp__nor2_1.v | 2,086 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR9 ,
VAR8,
VAR7,
VAR5 ,
VAR1
);
output VAR3 ;
input VAR2 ;
input VAR9 ;
input VAR8;
input VAR7;
input VAR5 ;
input VAR1 ;
VAR6 VAR4 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR3,
VAR2,
VAR9
);
output VAR3;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4/sky130_fd_sc_ms__or4.pp.symbol.v | 1,291 | module MODULE1 (
input VAR5 ,
input VAR1 ,
input VAR6 ,
input VAR2 ,
output VAR4 ,
input VAR8 ,
input VAR3,
input VAR9,
input VAR7
);
endmodule | apache-2.0 |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/new/i2c/EEPROM_Top.v | 14,305 | module MODULE1( clk, VAR24, VAR12, VAR51,VAR13,VAR23,
VAR1, VAR25, VAR6, VAR20, VAR7, VAR48,
VAR72, VAR38);
input clk, VAR24, VAR12;
output reg VAR51,VAR23,VAR13;
output reg VAR1,VAR25,VAR20,VAR7;
input VAR6,VAR48;
input [47:0] VAR72;
output reg [47:0] VAR38;
parameter VAR5 = 1'b0, VAR53 = 1'b1;
localparam VAR27 = 7'b1... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build2/mult.v | 61,284 | module MODULE1 (VAR30,VAR13,VAR22,VAR26,VAR14);
output [0:127] VAR14;
input [0:127] VAR30;
input [0:127] VAR13;
input [0:1] VAR22;
input [0:4] VAR26;
integer VAR6;
reg [0:127] VAR14;
reg [0:127] VAR27;
reg [0:15] VAR1;
reg [0:15] VAR16;
reg [0:15] VAR11;
reg [0:15] VAR29;
reg [0:15] VAR24;
reg [0:15] VAR21;
reg [0:15] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtn/sky130_fd_sc_hs__dlrtn_1.v | 2,214 | module MODULE1 (
VAR6,
VAR2 ,
VAR5 ,
VAR7 ,
VAR4 ,
VAR3
);
input VAR6;
input VAR2 ;
input VAR5 ;
output VAR7 ;
input VAR4 ;
input VAR3 ;
VAR1 VAR8 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR6,
VAR2 ,
VAR5 ,
VAR7
);
input VAR6;
input VAR2 ;
input VAR5 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ha/sky130_fd_sc_hd__ha.behavioral.v | 1,511 | module MODULE1 (
VAR7,
VAR11 ,
VAR8 ,
VAR9
);
output VAR7;
output VAR11 ;
input VAR8 ;
input VAR9 ;
supply1 VAR1;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR14 ;
wire VAR12;
wire VAR10 ;
and VAR6 (VAR12, VAR8, VAR9 );
buf VAR5 (VAR7 , VAR12 );
xor VAR13 (VAR10 , VAR9, VAR8 );
buf VAR3 (VAR11 , VAR10 );
endmodule | apache-2.0 |
open-fpga-nvm/open-nvm-source | fpga/MRAM/uart_tx.v | 3,737 | module MODULE1(
input clk,
input rst,
input VAR13,
input [7:0] VAR4,
output VAR11,
output VAR6
);
reg [9:0] VAR12;
reg [3:0] VAR1;
wire VAR10;
reg [1:0] VAR7;
assign VAR11 = (VAR7 == VAR3) ? 1'b1 : 1'b0;
assign VAR6 = (VAR7 == VAR8) ? VAR10 : 1'b1;
assign VAR10 =( (VAR1 == 0) ? 1'b0 :
( (VAR1 == 1) ? VAR4[0] :
( (VAR1 ... | gpl-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/cpu/id_reg.v | 5,476 | module MODULE1 (
input wire clk, input wire reset, input wire [VAR22] VAR12, input wire [VAR29] VAR2, input wire [VAR29] VAR32, input wire VAR41, input wire [VAR40] VAR21, input wire [VAR29] VAR42, input wire [VAR24] VAR19, input wire [VAR14] VAR10, input wire VAR20, input wire [VAR25] VAR31, input wire VAR1, input wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso0p/sky130_fd_sc_hdll__inputiso0p.pp.blackbox.v | 1,376 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR1,
VAR2 ,
VAR5 ,
VAR7 ,
VAR3
);
output VAR4 ;
input VAR6 ;
input VAR1;
input VAR2 ;
input VAR5 ;
input VAR7 ;
input VAR3 ;
endmodule | apache-2.0 |
olgirard/openmsp430 | core/synthesis/altera/src/megawizard/cyclone4gx_pmem.v | 7,663 | module MODULE1 (
address,
VAR30,
VAR23,
VAR15,
VAR57,
VAR55,
VAR14);
input [11:0] address;
input [1:0] VAR30;
input VAR23;
input VAR15;
input [15:0] VAR57;
input VAR55;
output [15:0] VAR14;
tri1 [1:0] VAR30;
tri1 VAR23;
tri1 VAR15;
wire [15:0] VAR36;
wire [15:0] VAR14 = VAR36[15:0];
VAR6 VAR2 (
.VAR7 (VAR23),
.VAR38 (V... | bsd-3-clause |
mda-ut/AquaTux | fpga/fpga_hw/top_level/DE0_Nano.v | 8,402 | module MODULE1(
VAR34,
VAR4,
VAR57,
VAR80,
VAR48,
VAR56,
VAR82,
VAR23,
VAR35,
VAR21,
VAR90,
VAR68,
VAR26,
VAR12,
VAR59,
VAR32,
VAR9,
VAR38,
VAR14,
VAR7,
VAR45,
VAR50,
VAR61,
VAR92,
VAR24,
VAR60,
VAR55,
VAR33,
VAR16,
VAR29,
VAR72,
VAR39
);
input VAR34;
output [7:0] VAR4;
input [1:0] VAR57;
input [3:0] VAR80;
output [12:... | gpl-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v | 11,233 | module MODULE1
parameter VAR79 = 32,
parameter VAR49 = 8,
parameter VAR18 = 10,
parameter VAR62 = 1,
parameter VAR67 = 4,
parameter VAR82 = 4,
parameter VAR75 = 2,
parameter VAR32 = 2,
parameter VAR84 = VAR79 / VAR49
)
(
input VAR73,
input VAR93,
input VAR83,
input VAR26,
output VAR19,
output [VAR79-1:0] VAR39,
output ... | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | source/hardware/low-level-nfc/llnfc-ddr200mt-1.0.0/NPM_Toggle_DO_tADL_DDR100_OTHER.v | 20,636 | module MODULE1
(
parameter VAR22 = 4
)
(
VAR44 ,
VAR25 ,
VAR24 ,
VAR36 ,
VAR34 ,
VAR14 ,
VAR27 ,
VAR35 ,
VAR7 ,
VAR43 ,
VAR39 ,
VAR49 ,
VAR18 ,
VAR16 ,
VAR26 ,
VAR28 ,
VAR30 ,
VAR48 ,
VAR19
);
input VAR44 ;
input VAR25 ;
output VAR24 ;
output VAR36 ;
input VAR34 ;
input VAR14 ;
input [VAR22 - 1:0] VAR27 ;
input [31:0] ... | gpl-3.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0_1/design_1_auto_pc_0_stub.v | 4,500 | module MODULE1(VAR32, VAR45, VAR41, VAR19,
VAR13, VAR16, VAR18, VAR25, VAR44, VAR40,
VAR3, VAR49, VAR48, VAR15, VAR51, VAR7, VAR5,
VAR24, VAR37, VAR36, VAR30, VAR56, VAR20, VAR8,
VAR26, VAR1, VAR2, VAR57, VAR31, VAR46,
VAR27, VAR22, VAR29, VAR28, VAR54, VAR10, VAR14,
VAR12, VAR34, VAR9, VAR11, VAR39, VAR17,
VAR4, VAR42... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21bo/sky130_fd_sc_lp__a21bo_4.v | 2,318 | module MODULE2 (
VAR2 ,
VAR7 ,
VAR9 ,
VAR3,
VAR1,
VAR5,
VAR8 ,
VAR6
);
output VAR2 ;
input VAR7 ;
input VAR9 ;
input VAR3;
input VAR1;
input VAR5;
input VAR8 ;
input VAR6 ;
VAR4 VAR10 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
V... | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_obc1/mcu_cmd.v | 12,331 | module MODULE1(
input clk,
input VAR23,
input VAR29,
input [7:0] VAR11,
input [7:0] VAR16,
output [2:0] VAR17,
output reg VAR26 = 0,
output VAR3,
output reg VAR32 = 0,
input VAR22,
output [7:0] VAR51,
input [7:0] VAR6,
output [7:0] VAR14,
input [31:0] VAR40,
input [2:0] VAR55,
output [23:0] VAR45,
output [23:0] VAR28,
... | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_3/ff169405/src/AXI4MasterInterfaceReadChannel.v | 11,122 | module MODULE1
(
parameter VAR52 = 32 ,
parameter VAR5 = 32 ,
parameter VAR64 = 16 ,
parameter VAR3 = 16
)
(
VAR88 ,
VAR55 ,
VAR94 ,
VAR15 ,
VAR6 ,
VAR27 ,
VAR109 ,
VAR7 ,
VAR65 ,
VAR63 ,
VAR104 ,
VAR8 ,
VAR33 ,
VAR76 ,
VAR84 ,
VAR96 ,
VAR54 ,
VAR95 ,
VAR79 ,
VAR60 ,
VAR58 ,
VAR21 ,
VAR4
);
input VAR88 ;
input VAR55 ;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.v | 2,128 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR8 ,
VAR9,
VAR1,
VAR3 ,
VAR4
);
output VAR5 ;
input VAR6 ;
input VAR8 ;
input VAR9;
input VAR1;
input VAR3 ;
input VAR4 ;
VAR2 VAR7 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR5 ,
VAR6,
VAR8
);
output VAR5 ... | apache-2.0 |
freecores/orsoc_graphics_accelerator | bench/verilog/gfx/line_bench.v | 2,464 | module MODULE1();
parameter VAR10 = 16;
parameter VAR1 = 16;
reg VAR2;
reg VAR15;
reg signed [VAR10-1:-VAR1] VAR5;
reg signed [VAR10-1:-VAR1] VAR4;
reg signed [VAR10-1:-VAR1] VAR6;
reg signed [VAR10-1:-VAR1] VAR11;
reg [VAR10-1:0] VAR3;
reg [VAR10-1:0] VAR16;
reg VAR18;
reg VAR8;
reg VAR7;
reg VAR12;
wire VAR13;
wire s... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4b/sky130_fd_sc_ls__or4b.pp.blackbox.v | 1,335 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR5 ,
VAR4 ,
VAR7 ,
VAR9,
VAR3,
VAR6 ,
VAR1
);
output VAR2 ;
input VAR8 ;
input VAR5 ;
input VAR4 ;
input VAR7 ;
input VAR9;
input VAR3;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1.blackbox.v | 1,252 | module MODULE1 (
VAR2,
VAR3
);
output VAR2;
input VAR3;
supply1 VAR4;
supply0 VAR1;
endmodule | apache-2.0 |
frisnit/fpga-noise | verilog/vga_noise.v | 2,685 |
input clk;
output [7:0] VAR1;
input VAR4;
input VAR3, VAR14;
input VAR15;
output VAR9, VAR7;
reg [1:0] VAR8;
reg [7:0] VAR6;
reg [7:0] VAR5;
reg [12:0] VAR12;
wire VAR2;
VAR11 VAR13 (
.clk(clk),
.reset(VAR4&VAR3), .VAR10(VAR2)
);
always @(negedge clk)
begin
if(VAR14)
VAR12 <= 0;
end
else
VAR12 <= VAR12 + 1;
end
alway... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3.pp.symbol.v | 1,289 | module MODULE1 (
input VAR1 ,
output VAR2 ,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/8d6f9c45e1ea3378/zqynq_lab_1_design_auto_pc_3_stub.v | 5,782 | module MODULE1(VAR43, VAR25, VAR34, VAR30,
VAR23, VAR56, VAR33, VAR52, VAR6, VAR44,
VAR35, VAR55, VAR38, VAR71, VAR67, VAR10, VAR79,
VAR42, VAR5, VAR69, VAR15, VAR1, VAR73, VAR18,
VAR8, VAR16, VAR14, VAR39, VAR19, VAR50,
VAR63, VAR7, VAR77, VAR58, VAR65, VAR53, VAR54,
VAR72, VAR9, VAR60, VAR36, VAR74, VAR75, VAR78,
VAR... | mit |
zhangry868/MultiCycleCPU | Multiple_Cycles_CPU/Memory.v | 6,766 | module MODULE1
(
input [(VAR1-1):0] VAR4,
input [(VAR3-1):0] addr,
input [3:0] VAR5,
input clk,
output [(VAR1-1):0] VAR6
);
reg [VAR1-1:0] VAR2[2**(VAR3 - 22) - 1:0];
reg [VAR3-1:0] VAR7;
always @ (negedge clk)
begin
case(VAR5)
4'b0001: VAR2[addr[9:2]][7:0] <= VAR4[7:0];
4'b0010: VAR2[addr[9:2]][15:8] <= VAR4[15:8];
4'... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfstp/sky130_fd_sc_lp__dfstp_4.v | 2,273 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR5 ,
VAR4,
VAR3 ,
VAR1 ,
VAR6 ,
VAR8
);
output VAR2 ;
input VAR9 ;
input VAR5 ;
input VAR4;
input VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR8 ;
VAR10 VAR7 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE1... | apache-2.0 |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/redundant/ovl_even_parity.v | 1,431 | module MODULE1 (VAR2, reset, enable, VAR5, VAR16);
parameter VAR15 = VAR19;
parameter VAR8 = 1;
parameter VAR20 = VAR17;
parameter VAR1 = VAR18;
parameter VAR9 = VAR11;
parameter VAR4 = VAR14;
parameter VAR13 = VAR3;
parameter VAR6 = VAR7;
input VAR2, reset, enable;
input [VAR8-1:0] VAR5;
output [VAR22-1:0] VAR16;
para... | mit |
AleCher/ipstack | sources/ip_minimal.v | 11,632 | module MODULE1 #(
parameter VAR14 = 48'h00AABBCCDDEE,
parameter VAR11 = {8'd10, 8'd5, 8'd5, 8'd5},
parameter VAR10 = 48'h3085A9130532, parameter VAR12 = {8'd10, 8'd5, 8'd5, 8'd1}
) (
input wire VAR15,
output reg [ 7: 0] VAR18,
output reg VAR5,
input wire VAR9,
input wire VAR17,
input wire [ 7: 0] VAR6,
input wire VAR3,... | gpl-2.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/pcie_core/source/pcie_core_pipe_clock.v | 21,207 | module MODULE1 #
(
parameter VAR15 = "VAR47", parameter VAR45 = "VAR47", parameter VAR86 = 1, parameter VAR123 = 3, parameter VAR98 = 0, parameter VAR4 = 2, parameter VAR1 = 2, parameter VAR7 = 1, parameter VAR139 = 0
)
(
input VAR36,
input VAR37,
input [VAR86-1:0] VAR129,
input VAR13,
input [VAR86-1:0] VAR142,
input V... | lgpl-3.0 |
plindstroem/oh | memory/hdl/fifo_cdc.v | 2,693 | module MODULE1 (
VAR17, VAR6, VAR2,
VAR18, VAR3, VAR1, VAR21, VAR4, VAR7,
VAR20
);
parameter VAR23 = 104;
parameter VAR15 = 16;
input VAR18;
input VAR3;
input VAR1;
input [VAR23-1:0] VAR21;
output VAR17;
input VAR4;
input VAR7;
output VAR6;
output [VAR23-1:0] VAR2;
input VAR20;
wire VAR14;
wire VAR5;
wire VAR8;
wire VA... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/spree/tmp/shifter_barrel_pipe1.v | 1,704 | module MODULE1(
clk, VAR21,
VAR2, VAR12,
VAR17,
VAR13);
parameter VAR11=32;
input clk;
input VAR21;
input [VAR11-1:0] VAR2;
input [4:0] VAR12; input [2-1:0] VAR17;
output [VAR11-1:0] VAR13;
wire VAR15;
wire VAR20;
assign VAR15=VAR17[1];
assign VAR20=VAR17[0];
wire VAR14,VAR14,VAR25;
wire [VAR11-1:0] VAR7,VAR7;
VAR18 VA... | mit |
IzyaSoft/EasyHDLLibrary | src/data_structures/FIFO.v | 3,288 | module MODULE1 #
(
parameter VAR15 = 8,
parameter VAR10 = 32
)
(
input wire enable,
input wire VAR12,
output wire VAR8,
input wire VAR14,
input wire VAR1,
input wire [VAR10 - 1 : 0] VAR5,
output wire [VAR10 - 1 : 0] VAR11,
output wire VAR13,
output wire VAR16
);
reg [VAR10 - 1 : 0] VAR2 [VAR15 - 1 : 0];
reg [VAR10 - 1 ... | gpl-3.0 |
zambreno/RCL | parallelCyGraph/verilog/instdec.v | 2,724 | module MODULE1 (
input [31:0] VAR14,
input [63:0] VAR10,
input VAR2,
output VAR9,
output [4:0] VAR3,
output VAR8,
output VAR15,
output [17:0] VAR7,
output VAR6
);
reg VAR13, VAR4, VAR11, VAR12;
reg [4:0] VAR1;
reg [17:0] VAR5;
always @* begin
VAR13 = 'b0;
VAR1 = 'b0;
VAR4 = 'b0;
VAR11 = 'b0;
VAR5 = 'b0;
VAR12 = 'b0;
ca... | apache-2.0 |
Marcoslz22/Tercer_Proyecto | Control.v | 1,152 | module MODULE1(
input wire clk,rst,
input [7:0] VAR6,VAR3,VAR7,VAR2,
output reg [3:0] VAR9,
output reg [7:0] VAR1
);
localparam VAR8 = 18;
reg [VAR8-1:0] VAR5;
wire [VAR8-1:0] VAR4;
always @(posedge clk, posedge rst)
if (rst)
VAR5 <= 0;
else
VAR5 <= VAR4;
assign VAR4 = VAR5 + 1;
always @(*)
case (VAR5[VAR8-1:VAR8-2])
2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_ps_pp_pkg_sn/sky130_fd_sc_hs__udp_dff_ps_pp_pkg_sn.blackbox.v | 1,519 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR2 ,
VAR8 ,
VAR4 ,
VAR6,
VAR7 ,
VAR3 ,
VAR1
);
output VAR5 ;
input VAR9 ;
input VAR2 ;
input VAR8 ;
input VAR4 ;
input VAR6;
input VAR7 ;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/data_mover.v | 5,466 | module MODULE1 (
input clk,
input VAR10,
input [VAR30-1:0] VAR27,
output [VAR30-1:0] VAR18,
input VAR4,
input VAR22,
input enable,
output reg VAR20,
output VAR6,
output VAR31,
input VAR16,
input [VAR32-1:0] VAR2,
input VAR7,
output VAR13,
output [VAR32-1:0] VAR29,
output VAR12,
input VAR24,
output VAR11,
input [VAR26-1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/fill/sky130_fd_sc_hdll__fill_8.v | 1,856 | module MODULE1 (
VAR3,
VAR4,
VAR1 ,
VAR6
);
input VAR3;
input VAR4;
input VAR1 ;
input VAR6 ;
VAR5 VAR2 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE1 ();
supply1 VAR3;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR6 ;
VAR5 VAR2 ();
endmodule | apache-2.0 |
Jawanga/ece385final | usb_system/synthesis/submodules/usb_system_sdram.v | 24,482 | module MODULE1 (
clk,
rd,
VAR66,
wr,
VAR42,
VAR53,
VAR40,
VAR20,
VAR57,
VAR41
)
;
output VAR53;
output VAR40;
output VAR20;
output VAR57;
output [ 61: 0] VAR41;
input clk;
input rd;
input VAR66;
input wr;
input [ 61: 0] VAR42;
wire VAR53;
wire VAR40;
wire VAR20;
reg [ 1: 0] VAR54;
reg [ 61: 0] VAR84;
reg [ 61: 0] VAR9;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ba/sky130_fd_sc_hs__o21ba.symbol.v | 1,350 | module MODULE1 (
input VAR6 ,
input VAR3 ,
input VAR5,
output VAR4
);
supply1 VAR2;
supply0 VAR1;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/example/HXT100G/fpga/rtl/i2c_master.v | 29,761 | module MODULE1 (
input wire clk,
input wire rst,
input wire [6:0] VAR30,
input wire VAR23,
input wire VAR48,
input wire VAR5,
input wire VAR52,
input wire VAR8,
input wire VAR108,
output wire VAR105,
input wire [7:0] VAR35,
input wire VAR85,
output wire VAR1,
input wire VAR36,
output wire [7:0] VAR114,
output wire VAR9... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tap/sky130_fd_sc_ls__tap_2.v | 1,877 | module MODULE2 (
VAR3,
VAR2,
VAR6 ,
VAR5
);
input VAR3;
input VAR2;
input VAR6 ;
input VAR5 ;
VAR1 VAR4 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE2 ();
supply1 VAR3;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR5 ;
VAR1 VAR4 ();
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_rdctrl_sync.v | 7,492 | module MODULE1 #
(
parameter VAR4 = 100
)
(
input clk,
input VAR22, input VAR15,
input [4:0] VAR7,
input VAR18,
input VAR16,
output reg VAR19,
output reg VAR17,
output reg VAR5 );
localparam VAR13 = 10;
wire VAR2;
wire VAR21;
wire VAR14;
reg [VAR13-1:0] VAR6;
assign VAR2 = (VAR15) ? VAR18 : VAR16;
VAR9 VAR10
(
.VAR3 (V... | lgpl-3.0 |
cfangmeier/VFPIX-telescope-Code | utils/apc128_pattern_generator/step_curve_new.v | 11,424 | module MODULE1
(
input clk,
input [15:0]VAR11,
output reg VAR3,
output VAR24,
output VAR16,
output VAR17,
output reg VAR26,
output reg VAR6,
output reg VAR7,
output reg VAR5,
output reg VAR14,
output reg VAR22,
output reg VAR12,
output reg VAR18,
output reg VAR9,
output reg VAR21,
output VAR27,
output [15:0]VAR2,
outpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21boi/sky130_fd_sc_ls__a21boi.blackbox.v | 1,392 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR6 ,
VAR8
);
output VAR2 ;
input VAR4 ;
input VAR6 ;
input VAR8;
supply1 VAR5;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv.behavioral.v | 1,430 | module MODULE1 (
VAR5,
VAR3
);
output VAR5;
input VAR3 ;
supply1 VAR7;
supply1 VAR4 ;
supply0 VAR1 ;
wire VAR2;
pulldown VAR6 (VAR2 );
bufif0 VAR8 (VAR5, VAR7, VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22oi/sky130_fd_sc_hs__a22oi.blackbox.v | 1,328 | module MODULE1 (
VAR6 ,
VAR5,
VAR3,
VAR7,
VAR1
);
output VAR6 ;
input VAR5;
input VAR3;
input VAR7;
input VAR1;
supply1 VAR4;
supply0 VAR2;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/ks233.v | 20,804 | module MODULE1(VAR13, VAR7, VAR3);
input wire [232:0] VAR13;
input wire [232:0] VAR7;
output wire [464:0] VAR3;
wire [230:0] VAR8;
wire [232:0] VAR11;
wire [232:0] VAR5;
wire [116:0] VAR1;
wire [116:0] VAR6;
VAR2 VAR9(VAR13[116:0], VAR7[116:0], VAR11);
VAR4 VAR12(VAR13[232:117], VAR7[232:117], VAR8);
assign VAR1[115:0]... | gpl-3.0 |
housq/lc3-pipeline | lc3_pipeline_stage1.v | 7,261 | module MODULE1(
input reset,
input clk,
input VAR27,
input [5:0] state,
input [15:0] VAR20,
input [15:0] VAR11,
input [15:0] VAR15,
input [19:0] VAR8,
input [19:0] VAR10,
output reg [15:0] VAR9,
output reg [19:0] VAR19,
output reg [19:0] VAR2,
output reg [19:0] VAR24, output reg [1:0] VAR5,
output reg [1:0] VAR36,
outp... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/1134498f5baab19e/ip_design_processing_system7_0_0_stub.v | 5,531 | module MODULE1(VAR71, VAR63, VAR52, VAR10,
VAR41, VAR68, VAR54, VAR61, VAR14, VAR51,
VAR35, VAR45, VAR30, VAR50,
VAR1, VAR73, VAR24, VAR62, VAR33,
VAR12, VAR44, VAR16, VAR74, VAR70,
VAR49, VAR20, VAR34, VAR27,
VAR66, VAR31, VAR4, VAR17, VAR43,
VAR26, VAR3, VAR46, VAR55, VAR28,
VAR40, VAR9, VAR58, VAR18, VAR23,
VAR5, VA... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_to_dram_ctrl_rx.v | 3,150 | module MODULE1
, parameter VAR22(VAR1)
, parameter VAR22(VAR48)
, parameter VAR22(VAR41)
, localparam VAR6=VAR52(VAR29)
, localparam VAR21=VAR52(VAR41)
, localparam VAR23=(VAR48/VAR41)
)
(
input VAR31
, input VAR24
, input VAR45
, input [VAR6-1:0] VAR26
, output logic VAR8
, output logic [VAR29-1:0][VAR1-1:0] VAR39
, o... | bsd-3-clause |
silverfoxy/MIPS-Verilog | Forwarding/Core.v | 15,805 | module MODULE1(
input clk,
input VAR76,
output VAR55,
output VAR72,
output VAR44,
output VAR66,
output VAR74,
output VAR73,
output dout,
output VAR23,
output wr,
output VAR21,
output VAR56,
output VAR7,
output VAR6,
output VAR20,
output VAR10,
output VAR54,
output VAR64,
output VAR18,
output VAR37,
output VAR63,
output... | mit |
gtaylormb/opl3_fpga | fpga/bd/opl3_cpu/ip/opl3_cpu_auto_pc_0/synth/opl3_cpu_auto_pc_0.v | 13,154 | module MODULE1 (
VAR111,
VAR39,
VAR80,
VAR59,
VAR88,
VAR36,
VAR102,
VAR90,
VAR1,
VAR76,
VAR33,
VAR81,
VAR49,
VAR112,
VAR83,
VAR45,
VAR61,
VAR104,
VAR98,
VAR96,
VAR107,
VAR17,
VAR109,
VAR85,
VAR110,
VAR21,
VAR64,
VAR55,
VAR52,
VAR84,
VAR23,
VAR26,
VAR53,
VAR30,
VAR29,
VAR87,
VAR15,
VAR75,
VAR62,
VAR66,
VAR71,
VAR14,
VAR... | lgpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/mmio_if/synthesis/mmio_if.v | 31,225 | module MODULE1 (
input wire VAR53, output wire [14:0] VAR155, output wire [2:0] VAR24, output wire VAR14, output wire VAR30, output wire VAR36, output wire VAR98, output wire VAR190, output wire VAR152, output wire VAR116, output wire VAR153, inout wire [31:0] VAR101, inout wire [3:0] VAR104, inout wire [3:0] VAR154, o... | gpl-3.0 |
SiLab-Bonn/basil | basil/firmware/modules/utils/sbus_to_ip.v | 1,190 | module MODULE1
parameter VAR17 = 0,
parameter VAR12 = 0,
parameter VAR1 = 16,
parameter VAR14 = 8
)
(
input wire VAR10,
input wire VAR4,
input wire VAR13,
input wire [VAR1-1:0] VAR16,
input wire [VAR14-1:0] VAR5,
output wire [VAR14-1:0] VAR15,
output wire VAR8,
output wire VAR11,
output wire [VAR1-1:0] VAR3,
output wir... | bsd-3-clause |
lvd2/zxevo | fpga/sdload/trunk/vg93/fapch_counter.v | 2,566 | module MODULE1
(
input wire VAR8,
input wire VAR9,
output reg VAR1,
output reg VAR2
);
reg [4:0] VAR3;
reg VAR4, VAR7;
wire VAR10;
wire VAR5;
reg [3:0] VAR12;
wire VAR11;
reg [5:0] VAR6;
always @(posedge VAR8)
VAR3[4:0] <= { VAR3[3:0], (~VAR9) };
always @(posedge VAR8)
begin
if( VAR3[4:1]==4'b1111 ) VAR4 <= 1'b1;
end
e... | gpl-3.0 |
sjohann81/hf-risc | devices/controllers/spi_sram_controller/25LC256.v | 36,404 | module MODULE1 (VAR22, VAR10, VAR35, VAR21, VAR36, VAR24, VAR4);
input VAR22; input VAR35;
input VAR21; input VAR36;
input VAR24;
input VAR4;
output VAR10;
reg [15:00] VAR40; reg [07:00] VAR39; reg [31:00] VAR14; reg [07:00] VAR3; reg [15:00] VAR27;
wire VAR26; wire VAR7; wire VAR34; wire VAR44; wire VAR48; wire VAR50;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtp/sky130_fd_sc_lp__dfrtp.functional.v | 1,642 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR8 ,
VAR4
);
output VAR7 ;
input VAR2 ;
input VAR8 ;
input VAR4;
wire VAR3;
wire VAR10;
not VAR11 (VAR10 , VAR4 );
VAR1 VAR9 VAR5 (VAR3 , VAR8, VAR2, VAR10 );
buf VAR6 (VAR7 , VAR3 );
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_adc_common.v | 11,731 | module MODULE1 (
VAR54,
VAR64,
VAR57,
VAR35,
VAR29,
VAR78,
VAR65,
VAR28,
VAR47,
VAR41,
VAR61,
VAR5,
VAR59,
VAR24,
VAR60,
VAR46,
VAR55,
VAR56,
VAR13,
VAR23,
VAR43,
VAR4,
VAR39,
VAR63,
VAR32,
VAR34,
VAR70,
VAR38,
VAR7,
VAR17,
VAR58,
VAR80,
VAR74,
VAR2,
VAR68,
VAR6,
VAR12);
localparam VAR36 = 32'h00090062;
parameter VAR19... | gpl-3.0 |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_auto_pc_3/synth/ZynqDesign_auto_pc_3.v | 13,125 | module MODULE1 (
VAR55,
VAR104,
VAR112,
VAR114,
VAR45,
VAR76,
VAR84,
VAR77,
VAR106,
VAR46,
VAR58,
VAR75,
VAR5,
VAR71,
VAR113,
VAR9,
VAR25,
VAR73,
VAR57,
VAR53,
VAR100,
VAR40,
VAR27,
VAR95,
VAR20,
VAR63,
VAR6,
VAR12,
VAR3,
VAR72,
VAR7,
VAR83,
VAR22,
VAR24,
VAR49,
VAR94,
VAR97,
VAR34,
VAR41,
VAR85,
VAR62,
VAR74,
VAR78,
V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22oi/sky130_fd_sc_ls__a22oi.pp.symbol.v | 1,376 | module MODULE1 (
input VAR5 ,
input VAR9 ,
input VAR7 ,
input VAR3 ,
output VAR4 ,
input VAR1 ,
input VAR8,
input VAR6,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21bo/sky130_fd_sc_ms__a21bo.functional.v | 1,483 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR2 ,
VAR9
);
output VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR9;
wire VAR3 ;
wire VAR4;
nand VAR7 (VAR3 , VAR2, VAR5 );
nand VAR8 (VAR4, VAR9, VAR3);
buf VAR1 (VAR6 , VAR4 );
endmodule | apache-2.0 |
jncronin/jca | cpu/interrupt.v | 5,615 | module MODULE1(clk, rst, VAR12, addr, VAR10, VAR8, VAR6, VAR4, VAR9, VAR11);
input clk;
input rst;
inout [7:0] VAR12;
input [7:0] addr;
input VAR10;
input VAR8;
input VAR6;
input [31:0] VAR4;
output reg VAR9;
input VAR11;
reg [31:0] VAR5 = 32'd0;
reg [4:0] VAR1 = 5'd0;
reg VAR7 = 0;
assign VAR12 = (~VAR10 & ~VAR8) ?
((... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211oi/sky130_fd_sc_lp__a211oi_2.v | 2,361 | module MODULE2 (
VAR9 ,
VAR2 ,
VAR5 ,
VAR3 ,
VAR10 ,
VAR1,
VAR11,
VAR7 ,
VAR4
);
output VAR9 ;
input VAR2 ;
input VAR5 ;
input VAR3 ;
input VAR10 ;
input VAR1;
input VAR11;
input VAR7 ;
input VAR4 ;
VAR8 VAR6 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR7(VAR7),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4bb/sky130_fd_sc_ls__nor4bb.behavioral.pp.v | 1,998 | module MODULE1 (
VAR14 ,
VAR2 ,
VAR1 ,
VAR11 ,
VAR10 ,
VAR3,
VAR4,
VAR12 ,
VAR16
);
output VAR14 ;
input VAR2 ;
input VAR1 ;
input VAR11 ;
input VAR10 ;
input VAR3;
input VAR4;
input VAR12 ;
input VAR16 ;
wire VAR6 ;
wire VAR15 ;
wire VAR7;
nor VAR9 (VAR6 , VAR2, VAR1 );
and VAR17 (VAR15 , VAR6, VAR11, VAR10 );
VAR8 VA... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/bootram.v | 16,922 | module MODULE1
(input clk, input reset,
input [13:0] VAR16,
output [31:0] VAR48,
input [13:0] VAR41,
input [31:0] VAR3,
output [31:0] VAR47,
input VAR36,
output reg VAR17,
input VAR25,
input [3:0] VAR44);
wire [31:0] VAR51, VAR30, VAR52, VAR42, VAR45, VAR29, VAR14, VAR50;
wire [31:0] VAR23, VAR43, VAR13, VAR9, VAR12, V... | gpl-2.0 |
vipinkmenon/scas | hw/fpga/source/enet_if/ethernet_top.v | 5,186 | module MODULE1(
input VAR73,
input VAR21,
input VAR65,
output VAR6,
output [7:0] VAR30,
output VAR33,
output VAR62,
output VAR69,
input [7:0] VAR15,
input VAR68,
input VAR64,
input VAR48,
input VAR31,
input VAR8,
input VAR60,
input VAR35, input VAR29, output VAR58, output VAR72, input VAR49, input VAR4,
output VAR45,
o... | mit |
cafe-alpha/wascafe | v11/fpga_firmware/wasca/synthesis/submodules/wasca_external_sdram_controller.v | 24,345 | module MODULE2 (
clk,
rd,
VAR3,
wr,
VAR75,
VAR57,
VAR5,
VAR64,
VAR43,
VAR60
)
;
output VAR57;
output VAR5;
output VAR64;
output VAR43;
output [ 42: 0] VAR60;
input clk;
input rd;
input VAR3;
input wr;
input [ 42: 0] VAR75;
wire VAR57;
wire VAR5;
wire VAR64;
reg [ 1: 0] VAR32;
reg [ 42: 0] VAR79;
reg [ 42: 0] VAR80;
wir... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/spree/tmp/data_mem.v | 7,402 | module MODULE3( clk, VAR13, en,
VAR28,
VAR7,
VAR53, VAR17, VAR26,
VAR35,
VAR63);
parameter VAR8=32;
parameter VAR21=32;
parameter VAR38=4; parameter VAR22=16;
parameter VAR44=16384;
input clk;
input VAR13;
input en;
input [31:0] VAR53;
input [31:0] VAR17;
input VAR26;
input [VAR8-1:0] VAR7;
input [4-1:0] VAR35;
input [... | mit |
chahuja/hilbert-fpga | mpuc707.v | 1,654 | module MODULE1 ( VAR21,VAR2, VAR9, VAR16,VAR11,VAR13 ,VAR12 ,VAR15 );
parameter VAR10 = 32;
input VAR21 ;
wire VAR21 ;
input VAR9 ; wire VAR9 ;
input VAR2; input VAR16 ; wire VAR16 ;
input [VAR10-1:0] VAR11 ;
wire signed [VAR10-1:0] VAR11 ;
input [VAR10-1:0] VAR13 ;
wire signed [VAR10-1:0] VAR13 ;
output [VAR10-1:0] VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s.pp.blackbox.v | 1,345 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR6,
VAR5,
VAR4 ,
VAR1
);
output VAR3 ;
input VAR2 ;
input VAR6;
input VAR5;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_split.v | 3,559 | module MODULE1 #(
parameter VAR26 = 13,
parameter VAR36 = 26
) (
input VAR21,
input VAR5,
output VAR18,
input VAR49,
output VAR43,
input [VAR36-1-1:0] VAR38,
input [VAR36-1:0] VAR16,
input [VAR36-1:0] VAR11,
input [VAR36-1:0] VAR42,
input [VAR36-1:0] VAR25,
input [5:0] VAR50,
input [5:0] VAR14,
input VAR48,
input VAR45... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a21o/sky130_fd_sc_hvl__a21o.behavioral.pp.v | 2,004 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR15 ,
VAR3 ,
VAR13,
VAR5,
VAR12 ,
VAR2
);
output VAR6 ;
input VAR8 ;
input VAR15 ;
input VAR3 ;
input VAR13;
input VAR5;
input VAR12 ;
input VAR2 ;
wire VAR14 ;
wire VAR11 ;
wire VAR7;
and VAR4 (VAR14 , VAR8, VAR15 );
or VAR10 (VAR11 , VAR14, VAR3 );
VAR16 VAR9 (VAR7, VAR11, VAR13, VAR5... | apache-2.0 |
johngtimms/parallel-accumulator | accumulator_top.v | 1,515 | module MODULE1 (VAR4, VAR9, reset, VAR12, VAR5);
input VAR4, VAR9, reset;
input [31:0] VAR12;
output [31:0] VAR5;
wire [3:0] req;
wire [3:0] VAR6;
wire [1:0] VAR21;
wire VAR20;
wire [31:0] read;
wire [31:0] write;
wire VAR10, VAR2;
wire [9:0] VAR15;
wire [31:0] VAR8;
wire [4:0] state;
assign VAR10 = (VAR12 != 0) ? 1'b1... | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_dpram_256x32.v | 6,451 | module MODULE1(
VAR18, VAR12, VAR10, VAR24, VAR19, VAR30,
VAR15, VAR37, VAR8, VAR38, VAR21, VAR14
);
parameter VAR9 = 8;
parameter VAR32 = 32;
input VAR18; input VAR12; input VAR10; input VAR24; input [VAR9-1:0] VAR19; output [VAR32-1:0] VAR30; input VAR15; input VAR37; input VAR8; input VAR38; input [VAR9-1:0] VAR21; ... | gpl-2.0 |
alexforencich/verilog-ethernet | rtl/arp_cache.v | 6,952 | module MODULE1 #(
parameter VAR40 = 9
)
(
input wire clk,
input wire rst,
input wire VAR11,
output wire VAR21,
input wire [31:0] VAR56,
output wire VAR60,
input wire VAR5,
output wire VAR6,
output wire [47:0] VAR3,
input wire VAR45,
output wire VAR48,
input wire [31:0] VAR10,
input wire [47:0] VAR33,
input wire VAR34
)... | mit |
sh-chris110/chris | FPGA/chris.final/Qsys/soc_design/synthesis/submodules/chris_slave.v | 5,873 | module MODULE1 (
input wire [3:0] VAR18, input wire VAR29, output wire [31:0] VAR7, input wire VAR10, input wire [31:0] VAR34, output wire VAR9, input wire VAR11, input wire VAR38, output wire VAR37 );
reg [31:0] VAR1;
assign VAR7 = VAR1;
reg VAR36;
reg VAR17;
reg [31:0] VAR3[8:0];
reg VAR35;
reg [31:0] VAR42;
assign V... | gpl-2.0 |
jeffkub/n64-cart-reader | old/fpga/soc_system/soc_system/synthesis/submodules/soc_system_hps.v | 23,359 | module MODULE1 #(
parameter VAR4 = 1,
parameter VAR65 = 1
) (
output wire VAR94, input wire VAR128, input wire [7:0] VAR15, input wire [31:0] VAR58, input wire [3:0] VAR21, input wire [2:0] VAR64, input wire [1:0] VAR50, input wire [1:0] VAR13, input wire [3:0] VAR48, input wire [2:0] VAR5, input wire VAR99, output wir... | mit |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/MUL_FPU_FUNCIONAL_v1/MUL_FPU_FUNCIONAL_v1.srcs/sources_1/imports/rtl/KOA_c_v2.v | 9,723 | module MODULE1
(
input wire [VAR8-1:0] VAR19,
input wire [VAR8-1:0] VAR30,
output wire [2*VAR8-1:0] VAR12
);
wire [VAR8/2+1:0] VAR9;
wire [VAR8/2+1:0] VAR23;
wire [2*(VAR8/2)-1:0] VAR34;
wire [2*(VAR8/2+1)-1:0] VAR11;
wire [2*(VAR8/2+2)-1:0] VAR20;
wire [2*(VAR8/2+2)-1:0] VAR18;
wire [2*(VAR8/2+2)-1:0] VAR28;
wire [4*(... | gpl-3.0 |
Gurint/EPC-Gen2-RFID-Tag-Baseband-Processor | fs_detector.v | 1,050 | module MODULE1
(
output reg sync, input VAR7,
input VAR2,
input VAR8,
input VAR1
);
parameter VAR9 = 2'b00;
parameter VAR6 = 2'b01; parameter VAR5 = 2'b10;
reg [1:0]VAR3;
reg [1:0]VAR4;
always@(posedge VAR2 or negedge VAR8) begin
if(~VAR8) VAR3 <= VAR9;
end
else VAR3 <= VAR4;
end
always@ begin
case(VAR3)
VAR9 : sync = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4bb/sky130_fd_sc_ms__nand4bb_2.v | 2,334 | module MODULE2 (
VAR5 ,
VAR7 ,
VAR1 ,
VAR8 ,
VAR6 ,
VAR10,
VAR11,
VAR9 ,
VAR3
);
output VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR10;
input VAR11;
input VAR9 ;
input VAR3 ;
VAR4 VAR2 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR9(VAR9),
.... | apache-2.0 |
jotego/jt12 | hdl/jt12_exprom.v | 11,403 | module MODULE1
(
input [7:0] addr,
input clk,
input VAR2 ,
output reg [9:0] VAR1
);
reg [9:0] VAR3[255:0];
begin | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/nes_hci.v | 14,309 | module MODULE1 (
input clk,
input rst,
input VAR39,
input [7:0] VAR49,
input VAR59,
output reg [15:0] VAR40,
output reg VAR47,
input [15:0] VAR5,
input [31:0] VAR31,
input VAR53,
output reg VAR55,
input [7:0] VAR15,
output reg VAR2,
input VAR46,
output reg [7:0] VAR11,
input VAR30,
output reg VAR4, output reg [15:0] VA... | mit |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/phy_rdctrl_sync.v | 7,493 | module MODULE1 #
(
parameter VAR2 = 100
)
(
input clk,
input VAR8, input VAR4,
input [4:0] VAR20,
input VAR6,
input VAR14,
output reg VAR19,
output reg VAR7,
output reg VAR10 );
localparam VAR16 = 10;
wire VAR1;
wire VAR12;
wire VAR3;
reg [VAR16-1:0] VAR18;
assign VAR1 = (VAR4) ? VAR6 : VAR14;
VAR22 VAR9
(
.VAR15 (VAR3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41o/sky130_fd_sc_lp__a41o_0.v | 2,426 | module MODULE2 (
VAR1 ,
VAR9 ,
VAR8 ,
VAR6 ,
VAR10 ,
VAR2 ,
VAR11,
VAR5,
VAR12 ,
VAR3
);
output VAR1 ;
input VAR9 ;
input VAR8 ;
input VAR6 ;
input VAR10 ;
input VAR2 ;
input VAR11;
input VAR5;
input VAR12 ;
input VAR3 ;
VAR4 VAR7 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR11(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3/sky130_fd_sc_hs__and3.blackbox.v | 1,218 | module MODULE1 (
VAR5,
VAR3,
VAR4,
VAR1
);
output VAR5;
input VAR3;
input VAR4;
input VAR1;
supply1 VAR2;
supply0 VAR6;
endmodule | apache-2.0 |
dutra/vgacontroller | top_wrapper.v | 1,618 | module MODULE1(VAR1,
VAR12,
VAR16,
VAR14,
VAR13,
VAR15,
VAR2,
VAR21,
VAR9,
VAR10,
VAR20
);
input VAR1;
input VAR12;
output VAR20;
output [3 : 0] VAR16;
output [7 : 0] VAR14;
output [7 : 0] VAR13;
output [7 : 0] VAR15;
output VAR2;
output VAR21;
output VAR9;
output VAR10;
wire VAR17;
VAR6 VAR19 (
.VAR8(VAR1),
.rst(!VAR1... | mit |
htuNCSU/MmcCommunicationVerilog | MAX10_SLAVE/PHYctrl_Slave_MAX10.v | 5,672 | module MODULE1 (
input VAR73,
input VAR49,
input [3: 0] VAR13,
output [4: 0] VAR36,
output [1:0] VAR34,
output VAR42,
inout VAR71,
output VAR82,
output VAR38,
input VAR56,
input VAR70,
input [3: 0] VAR15,
input VAR12,
input VAR2,
output [3: 0] VAR37,
output VAR14,
output VAR90,
output VAR54,
output VAR6,
input VAR58,
i... | gpl-3.0 |
chaohu/Daily-Learning | Digital-Logic/autosm/autosm.srcs/sources_1/new/autosm.v | 5,303 | module MODULE1(
input clk,rst,
input VAR14,VAR8,
input [1:0] VAR10,
output reg VAR4,VAR7,VAR11,
output reg [2:0] VAR5
);
reg [2:0] state,VAR13;
parameter VAR9 = 0,VAR1 = 1,VAR3 = 2,VAR6 = 3,VAR15 = 4,VAR12 = 5,VAR2 = 6;
always @(posedge clk or posedge rst) if(rst)
state = VAR9;
else
state = VAR13;
always @(state or VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1.blackbox.v | 1,323 | module MODULE1 (
VAR3,
VAR4
);
output VAR3;
input VAR4;
supply1 VAR6;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/wb_conmax_slave_if.v | 12,697 | module MODULE1(
VAR95, VAR14, VAR67,
VAR77, VAR20, VAR53, VAR46, VAR16, VAR61,
VAR2, VAR109, VAR84, VAR36,
VAR42, VAR49, VAR29, VAR1, VAR4, VAR63,
VAR104, VAR68, VAR24, VAR87,
VAR37, VAR101, VAR105, VAR71, VAR92, VAR70,
VAR90, VAR31, VAR78, VAR55,
VAR47, VAR97, VAR107, VAR52, VAR89, VAR18,
VAR81, VAR8, VAR69, VAR91,
VA... | gpl-2.0 |
csturton/wirepatch | system/hardware/cores/bench/ddr2_model.v | 110,637 | module MODULE1 (
VAR68,
VAR44,
VAR53,
VAR5,
VAR61,
VAR33,
VAR27,
VAR47,
VAR30,
addr,
VAR8,
VAR70,
VAR45,
VAR42,
VAR60
);
input VAR68;
input VAR44;
input VAR53;
input VAR5;
input VAR61;
input VAR33;
input VAR27;
inout [VAR19-1:0] VAR47;
input [VAR43-1:0] VAR30;
input [VAR20-1:0] addr;
inout [VAR64-1:0] VAR8;
inout [VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1.symbol.v | 1,322 | module MODULE1 (
input VAR3,
output VAR5
);
supply1 VAR2;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
chahuja/hilbert-fpga | mpuc924_383.v | 2,083 | module MODULE1 ( VAR14,VAR3 ,VAR22, VAR16,VAR23,VAR8,VAR2 ,VAR21 ,VAR9 );
parameter VAR10 = 32;
input VAR14 ;
wire VAR14 ;
input VAR3 ;
wire VAR3 ;
input VAR22; input VAR16 ; wire VAR16 ;
input VAR23 ; wire VAR23 ;
input [VAR10-1:0] VAR8 ;
wire signed [VAR10-1:0] VAR8 ;
input [VAR10-1:0] VAR2 ;
wire signed [VAR10-1:0] ... | gpl-2.0 |
rfotino/consolite-hardware | src/instr_cache.v | 2,461 | module MODULE1
(
input clk,
input VAR16,
input [VAR15-1:0] VAR7,
output valid,
output reg [VAR6-1:0] VAR12,
output reg VAR13,
output [2:0] VAR10,
output [5:0] VAR3,
output reg [29:0] VAR1,
input VAR2,
input VAR5,
output reg VAR4,
input [31:0] VAR11,
input VAR17,
input VAR14,
input [6:0] VAR9,
input VAR8,
input VAR18
);... | mit |
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