repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3b/sky130_fd_sc_hs__and3b.functional.pp.v | 1,888 | module MODULE1 (
VAR14,
VAR1,
VAR7 ,
VAR6 ,
VAR2 ,
VAR8
);
input VAR14;
input VAR1;
output VAR7 ;
input VAR6 ;
input VAR2 ;
input VAR8 ;
wire VAR11 ;
wire VAR3 ;
wire VAR9;
not VAR10 (VAR11 , VAR6 );
and VAR12 (VAR3 , VAR8, VAR11, VAR2 );
VAR13 VAR5 (VAR9, VAR3, VAR14, VAR1);
buf VAR4 (VAR7 , VAR9 );
endmodule | apache-2.0 |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_adder_subtractor_0_1/affine_block_ieee754_fp_adder_subtractor_0_1_stub.v | 1,397 | module MODULE1(VAR2, VAR3, VAR1)
;
input [31:0]VAR2;
input [31:0]VAR3;
output [31:0]VAR1;
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_20.behavioral.pp.v | 1,179 | module MODULE1( VAR7, VAR2, VAR4, VAR1 );
input VAR7;
inout VAR4, VAR1;
output VAR2;
VAR3 VAR5(.VAR7(VAR7),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1));
VAR3 VAR6(.VAR7(VAR7),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
asicguy/gplgpu | hdl/de3d/de3d_reg.v | 52,531 | module MODULE1
(
input VAR413, input VAR335, input [31:0] VAR173, input [8:2] VAR112, input [8:2] VAR326, input VAR440, input [3:0] VAR421, input VAR121, input VAR134, input VAR281, input VAR428, input VAR152, input [1:0] VAR433, input VAR368,
input VAR401,
output [351:0] VAR140, output [351:0] VAR435, output [351:0] V... | gpl-3.0 |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/soc_system_button_pio.v | 3,739 | module MODULE1 (
address,
VAR10,
clk,
VAR5,
VAR14,
VAR2,
VAR4,
irq,
VAR15
)
;
output irq;
output [ 31: 0] VAR15;
input [ 1: 0] address;
input VAR10;
input clk;
input [ 1: 0] VAR5;
input VAR14;
input VAR2;
input [ 31: 0] VAR4;
wire VAR1;
reg [ 1: 0] VAR9;
reg [ 1: 0] VAR6;
wire [ 1: 0] VAR11;
reg [ 1: 0] VAR3;
wire VAR1... | epl-1.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ai/sky130_fd_sc_ls__o21ai.blackbox.v | 1,334 | module MODULE1 (
VAR5 ,
VAR4,
VAR7,
VAR8
);
output VAR5 ;
input VAR4;
input VAR7;
input VAR8;
supply1 VAR1;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_asg_ch.v | 9,132 | module MODULE1 #(
parameter VAR41 = 14,
parameter VAR20 = 32
)(
output reg [ 14-1: 0] VAR36 , input VAR39 , input VAR34 , input VAR28 , input VAR50 , input [ 3-1: 0] VAR23 , output VAR21 ,
input VAR11 , input [ 14-1: 0] VAR9 , input [ 14-1: 0] VAR42 , output reg [ 14-1: 0] VAR5 , output reg [VAR41-1: 0] VAR15 ,
input [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211o/sky130_fd_sc_lp__a211o_0.v | 2,348 | module MODULE2 (
VAR4 ,
VAR2 ,
VAR11 ,
VAR5 ,
VAR6 ,
VAR1,
VAR9,
VAR7 ,
VAR10
);
output VAR4 ;
input VAR2 ;
input VAR11 ;
input VAR5 ;
input VAR6 ;
input VAR1;
input VAR9;
input VAR7 ;
input VAR10 ;
VAR8 VAR3 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR7(VAR7),
.VA... | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Lab4/lab_pong/VGA_Display.v | 1,667 | module MODULE1(VAR6, VAR2, VAR10, VAR11, VAR7, VAR9, VAR13, VAR3);
input [9:0] VAR6, VAR11;
input [8:0] VAR2, VAR10, VAR7;
output reg VAR9, VAR13, VAR3;
always @(*) begin
if( (VAR6 < 10'd640) && (VAR2 < 10'd480) )
begin
if( (VAR6 > VAR8) && (VAR6 < VAR8 + VAR4) &&
(VAR2 > VAR10) && (VAR2 < (VAR10 + VAR12)) ||
(VAR6 > V... | mit |
Octoate/CPCCartridge | emulation/acid.v | 2,027 | module MODULE1(VAR8, VAR1, VAR7, VAR3, VAR6);
input VAR8;
input [7:0]VAR1;
input VAR7;
input VAR3;
output [7:0]VAR6;
wire VAR8;
reg [16:0]VAR2 = 17'h1FFFF;
wire [16:0]VAR4;
wire [16:0]VAR5;
assign VAR4 = 17'h13596 ^ (VAR1[0] ? 17'h0000c : 0)
^ (VAR1[1] ? 17'h06000 : 0)
^ (VAR1[2] ? 17'h000c0 : 0)
^ (VAR1[3] ? 17'h00030... | mit |
google/bbcpu | shl8.v | 1,185 | module MODULE1(
input [7 : 0] VAR1,
input [2 : 0] VAR3,
output [7 : 0] VAR2,
output VAR4);
assign {VAR4, VAR2} = (VAR3 == 3'b000) ? {1'b0, VAR1} :
(VAR3 == 3'b001) ? {VAR1[7 : 0], {1'b0}}:
(VAR3 == 3'b010) ? {VAR1[6 : 0], {2'b0}}:
(VAR3 == 3'b011) ? {VAR1[5 : 0], {3'b0}}:
(VAR3 == 3'b100) ? {VAR1[4 : 0], {4'b0}}:
(VAR3... | apache-2.0 |
SymbiFlow/yosys | techlibs/intel/cyclone10lp/cells_arith.v | 2,704 | module MODULE1(
module 80alteraa10gxalu (VAR28, VAR23, VAR22, VAR17, VAR9, VAR15, VAR1);
parameter VAR7 = 0;
parameter VAR30 = 0;
parameter VAR8 = 1;
parameter VAR5 = 1;
parameter VAR19 = 1;
input [VAR8-1:0] VAR28;
input [VAR5-1:0] VAR23;
output [VAR19-1:0] VAR9, VAR15;
input VAR22, VAR17;
output VAR1;
wire VAR11 = VAR... | isc |
saiedhk/WhirlpoolHashEngine | whirlpool_wcipher_sbox.v | 3,849 | module MODULE1 (
output reg [7:0 ] VAR3,
input [7:0 ] VAR7
);
reg [3:0] VAR2, VAR8, VAR4;
wire [3:0] VAR5, VAR6, VAR1;
always @*
begin
case (VAR7[3:0])
4'h0: VAR2 = 4'hF;
4'h1: VAR2 = 4'h0;
4'h2: VAR2 = 4'hD;
4'h3: VAR2 = 4'h7;
4'h4: VAR2 = 4'hB;
4'h5: VAR2 = 4'hE;
4'h6: VAR2 = 4'h5;
4'h7: VAR2 = 4'hA;
4'h8: VAR2 = 4'h... | mit |
VerticalResearchGroup/miaow | src/verilog/rtl/fetch/wavegrp_info.v | 1,845 | module MODULE1 (
VAR14,
VAR7,
VAR10,
VAR16,
VAR4,
VAR5,
VAR8,
VAR17,
VAR2,
clk,
rst
);
input clk;
input rst;
input VAR14;
input [14:0] VAR7;
input [3:0] VAR10;
input [5:0] VAR16;
input [5:0] VAR8;
input VAR4;
input [5:0] VAR5;
output [5:0] VAR17;
output [3:0] VAR2;
reg [5:0] VAR17;
reg [3:0] VAR2;
reg [879:0] VAR3;
reg... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3.behavioral.v | 1,405 | module MODULE1 (
VAR8,
VAR7
);
output VAR8;
input VAR7;
supply1 VAR3;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR6 ;
wire VAR2;
buf VAR5 (VAR2, VAR7 );
buf VAR4 (VAR8 , VAR2 );
endmodule | apache-2.0 |
alanachtenberg/CSCE-350 | Project 2/RegisterFile.v | 1,631 | module MODULE1(VAR10, VAR9, VAR8, VAR5, VAR7, VAR1, VAR4, VAR3, VAR6);
output [31:0] VAR10;
output [31:0] VAR9;
input [31:0] VAR8;
input [4:0] VAR5, VAR7, VAR1;
input VAR4, VAR3, VAR6;
reg [31:0] VAR2 [0:31];
always @(posedge VAR6)
begin
VAR2[0]=0;
VAR2[1]=0;
VAR2[2]=0;
VAR2[3]=0;
VAR2[4]=0;
VAR2[5]=0;
VAR2[6]=0;
VAR2[... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_1.functional.v | 1,264 | module MODULE1( VAR9, VAR5, VAR8, VAR4 );
input VAR8, VAR9, VAR4;
output VAR5;
wire VAR10;
not VAR7( VAR10, VAR8 );
wire VAR11;
not VAR12( VAR11, VAR9 );
wire VAR3;
and VAR6( VAR3, VAR10, VAR11 );
wire VAR13;
not VAR1( VAR13, VAR4 );
or VAR2( VAR5, VAR3, VAR13 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4b/sky130_fd_sc_hdll__nand4b.symbol.v | 1,337 | module MODULE1 (
input VAR7,
input VAR2 ,
input VAR6 ,
input VAR5 ,
output VAR8
);
supply1 VAR3;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_20.behavioral.pp.v | 1,187 | module MODULE1( VAR1, VAR3, VAR2, VAR4 );
input VAR1;
inout VAR2, VAR4;
output VAR3;
VAR6 VAR5(.VAR1(VAR1),.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4));
VAR6 VAR7(.VAR1(VAR1),.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2/sky130_fd_sc_hd__mux2.behavioral.v | 1,604 | module MODULE1 (
VAR3 ,
VAR6,
VAR8,
VAR9
);
output VAR3 ;
input VAR6;
input VAR8;
input VAR9 ;
supply1 VAR5;
supply0 VAR4;
supply1 VAR11 ;
supply0 VAR2 ;
wire VAR12;
VAR10 VAR1 (VAR12, VAR6, VAR8, VAR9 );
buf VAR7 (VAR3 , VAR12);
endmodule | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/synthesis/submodules/hps_sdram_p0_altdqdqs.v | 6,959 | module MODULE1 (
VAR29,
VAR26,
VAR93,
VAR83,
VAR54,
VAR42,
VAR57,
VAR12,
VAR10,
VAR86,
VAR69,
VAR71,
VAR33,
VAR3,
VAR52,
VAR92,
VAR7,
VAR84,
VAR60,
VAR19,
VAR89,
VAR30,
VAR13,
VAR27,
VAR56,
VAR31,
VAR79,
VAR44,
VAR73,
VAR75,
VAR65,
VAR14,
VAR47,
VAR24,
VAR51,
VAR43,
VAR25,
VAR8
);
input [7-1:0] VAR8;
input VAR29;
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3.pp.symbol.v | 1,357 | module MODULE1 (
input VAR4 ,
output VAR6 ,
input VAR5 ,
input VAR2,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
MarcoVogt/basil | firmware/modules/tdc_s3/tdc_s3.v | 2,181 | module MODULE1 #(
parameter VAR11 = 16'h0000,
parameter VAR21 = 16'h0000,
parameter VAR8 = 4,
parameter VAR16 = 4'b0100,
parameter VAR7 = 16,
parameter VAR23 = 1,
parameter VAR36 = 1
)(
input wire VAR30,
input wire [VAR7-1:0] VAR22,
inout wire [7:0] VAR3,
input wire VAR17,
input wire VAR10,
input wire VAR6,
input wire ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd3/sky130_fd_sc_hdll__dlygate4sd3.pp.blackbox.v | 1,317 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR4,
VAR2,
VAR3 ,
VAR5
);
output VAR1 ;
input VAR6 ;
input VAR4;
input VAR2;
input VAR3 ;
input VAR5 ;
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/or1200/or1200_dpram_32x32.v | 14,103 | module MODULE1(
VAR130, VAR141, VAR48, VAR13, VAR128, VAR110,
VAR105, VAR126, VAR56, VAR80, VAR2, VAR135
);
parameter VAR39 = 5;
parameter VAR100 = 32;
input VAR130; input VAR141; input VAR48; input VAR13; input [VAR39-1:0] VAR128; output [VAR100-1:0] VAR110; input VAR105; input VAR126; input VAR56; input VAR80; input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxbp/sky130_fd_sc_ms__sdfxbp.functional.pp.v | 2,082 | module MODULE1 (
VAR17 ,
VAR10 ,
VAR2 ,
VAR8 ,
VAR4 ,
VAR19 ,
VAR12,
VAR3,
VAR13 ,
VAR14
);
output VAR17 ;
output VAR10 ;
input VAR2 ;
input VAR8 ;
input VAR4 ;
input VAR19 ;
input VAR12;
input VAR3;
input VAR13 ;
input VAR14 ;
wire VAR9 ;
wire VAR15;
VAR16 VAR11 (VAR15, VAR8, VAR4, VAR19 );
VAR5 VAR7 VAR1 (VAR9 , VAR1... | apache-2.0 |
Elphel/x393_sata | ahci/ahci_fsm.v | 38,602 | module MODULE1
(
input VAR2, input VAR120, input VAR81, input VAR5,
input VAR169,
input VAR65,
input [17:0] VAR12, input VAR17, input VAR237,
input [1:0] VAR87, output VAR99, input VAR178, output VAR161, input VAR271, output VAR188, output VAR131, output VAR263,
output VAR258, output VAR89, input VAR72,
output VAR145, ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_1.v | 2,284 | module MODULE2 (
VAR7 ,
VAR5,
VAR4,
VAR2 ,
VAR3 ,
VAR1,
VAR6
);
output VAR7 ;
input VAR5;
input VAR4;
input VAR2 ;
input VAR3 ;
input VAR1;
input VAR6;
VAR9 VAR8 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR7 ,
VAR5,
VAR4,
VAR2 ,
VAR3
);
ou... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_2.functional.v | 1,676 | module MODULE1( VAR7, VAR18, VAR16, VAR20, VAR14, VAR15 );
input VAR14, VAR15, VAR18, VAR7, VAR20;
output VAR16;
wire VAR9;
not VAR13( VAR9, VAR14 );
wire VAR12;
not VAR6( VAR12, VAR15 );
wire VAR8;
and VAR4( VAR8, VAR9, VAR12 );
wire VAR21;
not VAR1( VAR21, VAR18 );
wire VAR3;
not VAR5( VAR3, VAR7 );
wire VAR10;
and V... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_1.behavioral.pp.v | 1,239 | module MODULE1( VAR2, VAR6, VAR3, VAR8, VAR7 );
input VAR2, VAR6;
inout VAR8, VAR7;
output VAR3;
VAR5 VAR1(.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3),.VAR8(VAR8),.VAR7(VAR7));
VAR5 VAR4(.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3),.VAR8(VAR8),.VAR7(VAR7)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtp/sky130_fd_sc_ms__dfrtp.functional.pp.v | 1,863 | module MODULE1 (
VAR9 ,
VAR13 ,
VAR7 ,
VAR10,
VAR2 ,
VAR12 ,
VAR5 ,
VAR15
);
output VAR9 ;
input VAR13 ;
input VAR7 ;
input VAR10;
input VAR2 ;
input VAR12 ;
input VAR5 ;
input VAR15 ;
wire VAR6;
wire VAR8;
not VAR1 (VAR8 , VAR10 );
VAR4 VAR3 VAR14 (VAR6 , VAR7, VAR13, VAR8, , VAR2, VAR12);
buf VAR11 (VAR9 , VAR6 );
en... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2/sky130_fd_sc_hd__nor2_8.v | 2,086 | module MODULE2 (
VAR8 ,
VAR7 ,
VAR2 ,
VAR1,
VAR5,
VAR9 ,
VAR6
);
output VAR8 ;
input VAR7 ;
input VAR2 ;
input VAR1;
input VAR5;
input VAR9 ;
input VAR6 ;
VAR3 VAR4 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR8,
VAR7,
VAR2
);
output VAR8;
... | apache-2.0 |
sorgelig/ZX_Spectrum-128K_MIST | sys/sd_card.v | 15,244 | module MODULE1 (
input VAR59,
output [31:0] VAR11,
output reg VAR56,
output reg VAR55,
input VAR41,
input VAR51,
output VAR42,
output VAR27,
input VAR8,
input [31:0] VAR29,
output reg VAR1 = 0,
input [7:0] VAR63,
input VAR36,
output [7:0] VAR74,
input [8:0] VAR57,
input VAR19,
input VAR31,
input VAR5,
input VAR43,
outp... | gpl-2.0 |
eda-globetrotter/PicenoDecoders | zhiyang_and_andrew/pipe.v | 6,782 | module MODULE1 (in,out,VAR5,reset);
output out;
input in; input VAR5; input reset;
reg out;
reg o1; reg o2; reg o3; reg o4; reg o5; reg o6; reg o7; reg VAR2; reg VAR3; reg o10; reg o11; reg o12; reg o13; reg o14;
reg o15; reg o16; reg o17; reg VAR7; reg VAR1; reg o20; reg o21; reg o22; reg o23; reg o24; reg o25; reg o2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xor3/sky130_fd_sc_ms__xor3.functional.v | 1,310 | module MODULE1 (
VAR2,
VAR7,
VAR6,
VAR1
);
output VAR2;
input VAR7;
input VAR6;
input VAR1;
wire VAR4;
xor VAR3 (VAR4, VAR7, VAR6, VAR1 );
buf VAR5 (VAR2 , VAR4 );
endmodule | apache-2.0 |
neale/CS-program | 474-VLSI/Lab_4/frame_rate_bb.v | 12,125 | module MODULE1 (
VAR4,
VAR2,
VAR3,
VAR1);
input VAR4;
output VAR2;
output VAR3;
output VAR1;
endmodule | unlicense |
ShirmanXia/EE469SPRING16 | lab4/db/ip/nios_system/submodules/nios_system_nios2_qsys_0_jtag_debug_slave_sysclk.v | 7,084 | module MODULE1 (
clk,
VAR5,
VAR15,
VAR10,
VAR27,
VAR23,
VAR2,
VAR14,
VAR24,
VAR21,
VAR11,
VAR13,
VAR30,
VAR7,
VAR8,
VAR12,
VAR26,
VAR1,
VAR33
)
;
output [ 37: 0] VAR23;
output VAR2;
output VAR14;
output VAR24;
output VAR21;
output VAR11;
output VAR13;
output VAR30;
output VAR7;
output VAR8;
output VAR12;
output VAR26;
... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/hb/coeff_ram.v | 1,524 | module MODULE1 (input VAR1, input [3:0] VAR3, output reg [15:0] VAR2);
always @(posedge VAR1)
case (VAR3)
4'd0 : VAR2 <= -16'd16;
4'd1 : VAR2 <= 16'd74;
4'd2 : VAR2 <= -16'd254;
4'd3 : VAR2 <= 16'd669;
4'd4 : VAR2 <= -16'd1468;
4'd5 : VAR2 <= 16'd2950;
4'd6 : VAR2 <= -16'd6158;
4'd7 : VAR2 <= 16'd20585;
4'd8 : VAR2 <= ... | gpl-2.0 |
masc-ucsc/cmpe220fall16 | rtl/dctlb.v | 6,484 | module MODULE1(
input clk
,input reset
,input VAR16
,output VAR3
,input VAR1 VAR17
,input VAR15
,output VAR45
,input VAR35 VAR52
,input VAR4
,output VAR13
,input VAR48 VAR19
,output VAR49
,input VAR55
,output VAR53 VAR42
,output VAR12
,input VAR7
,output VAR53 VAR63
,output VAR14
,input VAR5
,output VAR23 VAR8
,input V... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_ic_tag.v | 5,770 | module MODULE1(
clk, rst,
VAR17, VAR8, VAR14,
addr, en, VAR16, VAR1, VAR2, VAR20
);
parameter VAR13 = VAR10;
parameter VAR4 = VAR9;
input clk;
input rst;
input VAR17;
input [VAR11 - 1:0] VAR14;
output VAR8;
input [VAR4-1:0] addr;
input en;
input VAR16;
input [VAR13-1:0] VAR1;
output VAR2;
output [VAR13-2:0] VAR20;
assi... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxbp/sky130_fd_sc_ms__sdfxbp.functional.v | 1,869 | module MODULE1 (
VAR9 ,
VAR14,
VAR4,
VAR8 ,
VAR5,
VAR15
);
output VAR9 ;
output VAR14;
input VAR4;
input VAR8 ;
input VAR5;
input VAR15;
wire VAR3 ;
wire VAR2;
VAR10 VAR7 (VAR2, VAR8, VAR5, VAR15 );
VAR6 VAR13 VAR12 (VAR3 , VAR2, VAR4 );
buf VAR1 (VAR9 , VAR3 );
not VAR11 (VAR14 , VAR3 );
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/ETAII_N16_Q8_syn.v | 4,563 | module MODULE4 ( VAR34, VAR62, VAR71, VAR77, VAR58 );
input [8:0] VAR34;
input [8:0] VAR62;
output [8:0] VAR77;
input VAR71;
output VAR58;
wire VAR49, VAR54, VAR50, VAR70, VAR46, VAR15, VAR3, VAR38;
VAR51 VAR25 ( .VAR34(VAR34[3]), .VAR62(VAR62[3]), .VAR28(VAR50) );
VAR80 VAR4 ( .VAR44(VAR34[1]), .VAR53(VAR62[1]), .VAR6... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111a/sky130_fd_sc_hs__o2111a.behavioral.v | 1,968 | module MODULE1 (
VAR11 ,
VAR13 ,
VAR10 ,
VAR9 ,
VAR7 ,
VAR2 ,
VAR16,
VAR3
);
output VAR11 ;
input VAR13 ;
input VAR10 ;
input VAR9 ;
input VAR7 ;
input VAR2 ;
input VAR16;
input VAR3;
wire VAR7 VAR14 ;
wire VAR6 ;
wire VAR5;
or VAR1 (VAR14 , VAR10, VAR13 );
and VAR8 (VAR6 , VAR9, VAR7, VAR14, VAR2 );
VAR4 VAR12 (VAR5, ... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/enet_if/v7_enet_top.v | 4,011 | module MODULE1(
input VAR36,
input VAR14,
input VAR25,
output VAR42,
output [7:0] VAR19,
output VAR49,
output VAR16,
output VAR28,
input [7:0] VAR5,
input VAR24,
input VAR21,
input VAR38,
input VAR48,
input VAR43,
input VAR10,
input VAR53, input VAR23, output VAR35, output VAR20, input VAR37, input VAR3,
output VAR2,
o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4bb/sky130_fd_sc_ms__and4bb_1.v | 2,323 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR8 ,
VAR1 ,
VAR6 ,
VAR10,
VAR7,
VAR5 ,
VAR9
);
output VAR2 ;
input VAR4 ;
input VAR8 ;
input VAR1 ;
input VAR6 ;
input VAR10;
input VAR7;
input VAR5 ;
input VAR9 ;
VAR11 VAR3 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/col_mach.v | 18,166 | module MODULE1 #
(
parameter VAR113 = 100,
parameter VAR20 = 3,
parameter VAR92 = "8",
parameter VAR114 = 12,
parameter VAR51 = 4,
parameter VAR34 = 8,
parameter VAR79 = 1,
parameter VAR115 = 0,
parameter VAR36 = 8,
parameter VAR86 = "VAR7",
parameter VAR131 = "VAR73",
parameter VAR76 = "VAR73",
parameter VAR106 = 31,
... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/open_cores/verilog/processed_files/output/cordic.v | 13,262 | module MODULE2 ( VAR35,
VAR38,
VAR21);
input [4-1:0] VAR35;
input [16:0] VAR38;
output [16:0] VAR21;
reg [16:0] VAR21;
always @ (VAR38 or VAR35) begin
case (VAR35)
0: begin
VAR21[16-0:0] = VAR38[16: 0];
end
1: begin
VAR21[16-1:0] = VAR38[16: 1];
VAR21[16:16-1+1] = 1'b0;
end
2: begin
VAR21[16-2:0] = VAR38[16: 2];
VAR21[... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/acl_stall_free_sink.v | 5,207 | module MODULE1
parameter integer VAR44 = 32,
parameter integer VAR46 = 32,
parameter integer VAR47 = 1,
parameter integer VAR18 = 1
)
(
input logic VAR38,
input logic VAR3,
input logic [VAR44-1:0] VAR28,
output logic [VAR44-1:0] VAR10,
input logic VAR14,
output logic VAR6,
input logic VAR5,
output logic VAR16,
output l... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111ai/sky130_fd_sc_ls__o2111ai.behavioral.v | 1,610 | module MODULE1 (
VAR1 ,
VAR9,
VAR6,
VAR8,
VAR4,
VAR5
);
output VAR1 ;
input VAR9;
input VAR6;
input VAR8;
input VAR4;
input VAR5;
supply1 VAR13;
supply0 VAR11;
supply1 VAR2 ;
supply0 VAR14 ;
wire VAR10 ;
wire VAR7;
or VAR15 (VAR10 , VAR6, VAR9 );
nand VAR12 (VAR7, VAR4, VAR8, VAR5, VAR10);
buf VAR3 (VAR1 , VAR7 );
endm... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211a/sky130_fd_sc_ms__o211a.symbol.v | 1,367 | module MODULE1 (
input VAR7,
input VAR6,
input VAR3,
input VAR9,
output VAR1
);
supply1 VAR8;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxbp/sky130_fd_sc_ls__dfxbp.symbol.v | 1,338 | module MODULE1 (
input VAR8 ,
output VAR7 ,
output VAR5,
input VAR2
);
supply1 VAR6;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputisolatch/sky130_fd_sc_hd__lpflow_inputisolatch.pp.blackbox.v | 1,412 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR3,
VAR7 ,
VAR6 ,
VAR1 ,
VAR4
);
output VAR5 ;
input VAR2 ;
input VAR3;
input VAR7 ;
input VAR6 ;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/denise_bitplanes.v | 9,116 | module MODULE1
(
input clk, input VAR34,
input reset,
input VAR15, input VAR18,
input VAR3,
input [8:1] VAR35, input [15:0] VAR23, input [48-1:0] VAR2, input VAR36, input VAR50, input [8:0] VAR45, output [8:1] VAR12 );
parameter VAR20 = 9'h102;
parameter VAR43 = 9'h110;
parameter VAR44 = 9'h112;
parameter VAR26 = 9'h11... | gpl-3.0 |
monotone-RK/FACE | MCSoC-15/16-way_4-parallel/ise/ipcore_dir/dram/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_dqs_found_cal_hr.v | 51,690 | module MODULE1 #
(
parameter VAR60 = 100, parameter VAR122 = 2, parameter VAR26 = 5, parameter VAR106 = "0",
parameter VAR102 = 5, parameter VAR66 = "VAR135", parameter VAR112 = 1, parameter VAR71 = 3, parameter VAR108 = 8, parameter VAR111 = 8, parameter VAR117 = "VAR58", parameter VAR99 = "VAR74", parameter VAR134 = ... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_input_if.v | 10,789 | module MODULE1
VAR55 = 64,
VAR66 = 8,
VAR38 = 33,
VAR28 = 3,
VAR49 = 1,
VAR5 = 2,
VAR24 = "VAR19"
)
(
VAR60,
VAR34,
VAR85,
VAR29,
VAR52,
VAR4,
VAR68,
VAR67,
VAR13,
VAR65,
VAR11,
VAR43,
VAR7,
VAR44,
VAR50,
VAR1,
VAR27,
VAR53,
VAR56,
VAR76,
VAR42,
VAR74,
VAR10,
VAR8,
VAR70,
VAR57,
VAR72,
VAR82,
VAR47,
VAR20,
VAR79,
VAR58... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/aceusb/rtl/aceusb.v | 3,068 | module MODULE1(
input VAR24,
input VAR17,
input [31:0] VAR2,
input [31:0] VAR1,
output [31:0] VAR4,
input VAR19,
input VAR9,
input VAR10,
output reg VAR32,
output [6:0] VAR21,
inout [15:0] VAR29,
output VAR35,
output VAR11,
input VAR37,
output VAR15,
input VAR14,
output VAR3,
output VAR7,
input VAR20
);
wire VAR13;
wir... | lgpl-3.0 |
bigeagle/riffa | fpga/riffa_hdl/rx_port_64.v | 15,824 | module MODULE1 #(
parameter VAR40 = 9'd64,
parameter VAR41 = 1024,
parameter VAR117 = 512,
parameter VAR107 = 2, parameter VAR155 = VAR32((VAR40/32)+1),
parameter VAR50 = VAR32((2**VAR32(VAR41))+1),
parameter VAR67 = VAR32((2**VAR32(VAR117))+1)
)
(
input VAR28,
input VAR128,
input [2:0] VAR60,
output VAR51, input [31:0... | bsd-3-clause |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/io_queues/ethernet_mac/src/tx_queue.v | 12,827 | module MODULE1
parameter VAR29 = 64,
parameter VAR67 = VAR29/8,
parameter VAR77 = 0,
parameter VAR18 = 'hff
)
(input [VAR29-1:0] VAR4,
input [VAR67-1:0] VAR16,
input VAR45,
output VAR40,
input VAR71,
output reg VAR33,
output [7:0] VAR41,
output VAR54,
output VAR61,
input VAR55,
output VAR17,
output reg VAR59,
output re... | mit |
alexforencich/xfcp | lib/wb/rtl/wb_dp_ram.v | 4,811 | module MODULE1 #
(
parameter VAR11 = 32, parameter VAR29 = 16, parameter VAR28 = (VAR11/8) )
(
input wire VAR12,
input wire [VAR29-1:0] VAR27, input wire [VAR11-1:0] VAR4, output wire [VAR11-1:0] VAR13, input wire VAR8, input wire [VAR28-1:0] VAR7, input wire VAR15, output wire VAR33, input wire VAR26,
input wire VAR20... | mit |
olajep/oh | src/adi/hdl/library/common/ad_csc_1.v | 3,508 | module MODULE1 #(
parameter VAR14 = 16) (
input clk,
input [VAR5:0] sync,
input [23:0] VAR4,
input [16:0] VAR6,
input [16:0] VAR27,
input [16:0] VAR22,
input [24:0] VAR11,
output [VAR5:0] VAR3,
output [ 7:0] VAR24);
localparam VAR5 = VAR14 - 1;
wire [24:0] VAR23;
wire [24:0] VAR12;
wire [24:0] VAR9;
wire [VAR5:0] VAR16... | mit |
bbrown1867/ObjectTracking | hw/common/fixed_point/qdiv.v | 3,342 | module MODULE1 #(
parameter VAR7 = 15,
parameter VAR1 = 32
)
(
input [VAR1-1:0] VAR11,
input [VAR1-1:0] VAR2,
input VAR9,
input VAR18,
output [VAR1-1:0] VAR3,
output VAR10,
output VAR13
);
reg [2*VAR1+VAR7-3:0] VAR12; reg [VAR1-1:0] VAR14; reg [VAR1-2+VAR7:0] VAR16; reg [2*VAR1+VAR7-3:0] VAR5;
reg [VAR1-1:0] VAR17;
reg... | mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/bd/triangle_intersect/ip/triangle_intersect_auto_pc_1/synth/triangle_intersect_auto_pc_1.v | 15,750 | module MODULE1 (
VAR74,
VAR26,
VAR40,
VAR57,
VAR54,
VAR34,
VAR21,
VAR38,
VAR53,
VAR106,
VAR29,
VAR23,
VAR30,
VAR104,
VAR82,
VAR22,
VAR42,
VAR55,
VAR92,
VAR32,
VAR56,
VAR45,
VAR96,
VAR49,
VAR75,
VAR2,
VAR24,
VAR77,
VAR15,
VAR17,
VAR93,
VAR25,
VAR63,
VAR73,
VAR98,
VAR33,
VAR19,
VAR91,
VAR97,
VAR44,
VAR84,
VAR69,
VAR109,
... | mit |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_cpu_s1_jtag_debug_module_tck.v | 8,218 | module MODULE1 (
VAR28,
VAR24,
VAR37,
VAR3,
VAR39,
VAR27,
VAR6,
VAR21,
VAR36,
VAR19,
VAR9,
VAR1,
VAR20,
VAR11,
VAR23,
VAR8,
VAR10,
VAR22,
VAR35,
VAR30,
VAR12,
VAR32,
VAR31,
VAR15,
VAR7,
VAR38,
VAR29,
VAR17,
VAR25,
VAR34,
VAR26
)
;
output [ 1: 0] VAR29;
output VAR17;
output [ 37: 0] VAR25;
output VAR34;
output VAR26;
in... | gpl-2.0 |
acapola/opendev | sfr_gen/trng_apbif.v | 6,896 | module MODULE1 (
output reg VAR36,
output reg VAR35,
output reg VAR22,
output reg VAR10,
output reg [32-1:0] VAR27,
output reg [32-1:0] VAR8,
output reg [32-1:0] VAR30,
output reg [128-1:0] VAR29,
output reg [32-1:0] VAR7,
input wire VAR31,
input wire VAR19,
input wire [32-1:0] VAR24,
input wire VAR18,
output reg VAR26... | mit |
mda-ut/SubZero | fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/power_management.v | 1,811 | module MODULE1 (
output reg VAR5,
output reg [2:0] sel,
output VAR9,
input ack,
input VAR6,
input VAR1,
input clk
);
reg [9:0] VAR2;
reg [3:0] VAR7;
reg [15:0] VAR8;
reg VAR10;
always @(posedge clk)
if (VAR1 == 1'd0)
begin
VAR5 <= 1'b0;
sel <= 3'b111;
VAR2 = 10'd0;
VAR10 = 1'b0;
VAR7 = VAR3;
VAR8 = VAR4;
end
else
begin... | mit |
unihd-cag/openhmc | rtl/hmc_controller/openhmc_top.v | 25,571 | module MODULE1 #(
parameter VAR72 = 4, parameter VAR41 = 2, parameter VAR64 = VAR72*128, parameter VAR172 = 3, parameter VAR184 = 2**VAR172, parameter VAR218 = VAR72*16, parameter VAR108 = 64, parameter VAR138 = 64, parameter VAR31 = 4, parameter VAR59 = 8, parameter VAR166 = 10, parameter VAR80 = 1, parameter VAR14 = ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v | 2,329 | module MODULE2 (
VAR1 ,
VAR4 ,
VAR9 ,
VAR8,
VAR6 ,
VAR7 ,
VAR2 ,
VAR10
);
output VAR1 ;
input VAR4 ;
input VAR9 ;
input VAR8;
input VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR10 ;
VAR5 VAR3 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR10(VAR10)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlxtp/sky130_fd_sc_lp__srdlxtp.behavioral.v | 1,907 | module MODULE1 (
VAR11 ,
VAR7 ,
VAR3 ,
VAR15
);
output VAR11 ;
input VAR7 ;
input VAR3 ;
input VAR15;
supply1 VAR16;
supply1 VAR5 ;
supply0 VAR2 ;
supply1 VAR6 ;
supply0 VAR8 ;
wire VAR4 ;
wire VAR9;
wire VAR14 ;
reg VAR13 ;
wire VAR12 ;
VAR17 VAR10 (VAR4 , VAR14, VAR9, VAR15, VAR13, VAR16, VAR2, VAR5);
assign VAR12 = ... | apache-2.0 |
lbl-cal/StanfordNoC | router/src/vcr_op_ctrl_mac.v | 13,182 | module MODULE1
(clk, reset, VAR38, VAR66, VAR27, VAR42,
VAR52, VAR31, VAR85, VAR61, VAR98, VAR14,
VAR76, VAR53, VAR77, VAR46, VAR81, VAR97,
VAR107);
parameter VAR95 = 32;
parameter VAR113 = 2;
parameter VAR32 = 2;
localparam VAR22 = VAR113 * VAR32;
parameter VAR54 = 1;
localparam VAR60 = VAR22 * VAR54;
localparam VAR87... | bsd-2-clause |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_auto_pc_2/synth/tutorial_auto_pc_2.v | 13,148 | module MODULE1 (
VAR25,
VAR62,
VAR21,
VAR22,
VAR91,
VAR92,
VAR74,
VAR89,
VAR54,
VAR100,
VAR79,
VAR48,
VAR57,
VAR70,
VAR4,
VAR7,
VAR60,
VAR105,
VAR47,
VAR40,
VAR16,
VAR44,
VAR68,
VAR1,
VAR82,
VAR24,
VAR18,
VAR93,
VAR96,
VAR85,
VAR109,
VAR114,
VAR38,
VAR8,
VAR31,
VAR112,
VAR43,
VAR35,
VAR29,
VAR19,
VAR36,
VAR80,
VAR17,
V... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_data_pipeline.v | 7,324 | module MODULE1
parameter VAR29 = 128,
parameter VAR21 = 1,
parameter VAR12 = 1,
parameter VAR28 = 256,
parameter VAR6 = 10,
parameter VAR31 = "VAR26"
)
(
input VAR19,
input VAR15,
input VAR27,
input [VAR29-1:0] VAR24,
input VAR17,
input [VAR33(VAR29/32)-1:0] VAR32,
input VAR23,
input [VAR33(VAR29/32)-1:0] VAR25,
output... | gpl-3.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v | 28,427 | module MODULE1 (
VAR104,
VAR11,
VAR84,
VAR207,
VAR235,
VAR120,
VAR155,
VAR198,
VAR151,
VAR173,
VAR5,
VAR160,
VAR187,
VAR204,
VAR47,
VAR115,
VAR199,
VAR244,
VAR40,
VAR79,
VAR98,
VAR183,
VAR61,
VAR177,
VAR221,
VAR184,
VAR253,
VAR188,
VAR95,
VAR257,
VAR234,
VAR7,
VAR27,
VAR174,
VAR90,
VAR197,
VAR82,
VAR156,
VAR162,
VAR42,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tap/sky130_fd_sc_ls__tap.pp.symbol.v | 1,217 | module MODULE1 (
input VAR1 ,
input VAR2,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
monotone-RK/FACE | MCSoC-15/4-way_2-parallel/ise/ipcore_dir/dram/user_design/rtl/controller/mig_7series_v1_9_arb_select.v | 26,779 | module MODULE1 #
(
parameter VAR14 = 100,
parameter VAR116 = "VAR142",
parameter VAR117 = "1T",
parameter VAR21 = 11,
parameter VAR8 = 3,
parameter VAR166 = "8",
parameter VAR122 = 4,
parameter VAR82 = 5,
parameter VAR112 = 5,
parameter VAR161 = 31,
parameter VAR78 = 8,
parameter VAR4 = "VAR95",
parameter VAR164 = "VAR... | mit |
mcgodfrey/i2c-eeprom | i2c_master.v | 5,191 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR7,
input wire [7:0] VAR16,
input wire [6:0] VAR17,
input wire VAR12,
input wire [7:0] VAR11,
output reg [7:0] VAR3,
output reg VAR26,
output reg VAR4,
inout wire VAR9,
output wire VAR25
);
localparam VAR22 = 0;
localparam VAR28 = 1;
localparam VAR20 = 2;
l... | mit |
efabless/openlane | designs/BM64/src/BM64.v | 27,558 | module MODULE1 #(
parameter VAR30 = 256 )(
input VAR21, input VAR22,
input VAR10, input [(VAR30 - 1):0] VAR20, input [(VAR30 - 1):0] VAR7, output reg VAR3, output reg [((2*VAR30) - 1):0] VAR28 );
localparam VAR8 = ((VAR30 + 1)/4);
reg [4:0] VAR4; reg [4:0] VAR25; reg VAR12; reg [(VAR30 + 3):0] VAR1; wire [(VAR30 + 3):0... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/fifo_pacer.v | 1,279 | module MODULE1
(input clk,
input reset,
input [7:0] VAR6,
input enable,
input VAR13, output VAR11,
output VAR9, input VAR5,
output VAR2, VAR3);
wire VAR4;
VAR8 VAR7 (.VAR12(clk), .reset(reset), .enable(enable),
.VAR6(VAR6), .VAR14(1), .VAR10(VAR4));
wire VAR1 = VAR13 & VAR5;
assign VAR11 = VAR1 & VAR4;
assign VAR9 = VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1.blackbox.v | 1,323 | module MODULE1 (
VAR5,
VAR6
);
output VAR5;
input VAR6;
supply1 VAR4;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/cabac_mn_1p_16x64.v | 2,971 | module MODULE1(
clk ,
VAR5 ,
VAR8 ,
VAR16
);
parameter VAR24 = 'd0;
input clk ; input VAR5 ; input [5:0] VAR8 ;
output [15:0] VAR16 ;
VAR32 #(.VAR18(6), .VAR6(16))
VAR25(
.clk (clk ),
.VAR3 (~VAR5 ),
.VAR20 (~VAR5 ),
.VAR23 (VAR8 ),
.VAR29 (VAR16 )
);
generate
if(VAR24 == 'd0) begin: VAR4
VAR12 #(
.VAR22 ("VAR2.VAR17" ... | gpl-3.0 |
osrf/wandrr | firmware/motor_controller/fpga/crc_ccitt.v | 1,212 | module MODULE1
(input clk, input rst, input [7:0] VAR8, input VAR6, output [15:0] VAR7);
wire [15:0] VAR10;
wire [15:0] VAR9 = (rst ? VAR1 : VAR10);
VAR4 #(16) VAR5(.VAR2(clk), .rst(1'b0), .en(VAR6 | rst), .VAR8(VAR9), .VAR3(VAR7));
assign VAR10[0] = VAR7[8] ^ VAR7[12] ^ VAR8[0] ^ VAR8[4];
assign VAR10[1] = VAR7[9] ^ V... | apache-2.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/altera_avalon_st_handshake_clock_crosser.v | 7,761 | module MODULE1
parameter VAR14 = 8,
VAR28 = 8,
VAR5 = 0,
VAR1 = 0,
VAR45 = 1,
VAR18 = 0,
VAR11 = 1,
VAR12 = 2,
VAR38 = 2,
VAR10 = 1,
VAR6 = VAR14 / VAR28,
VAR31 = VAR40(VAR6)
)
(
input VAR33,
input VAR42,
input VAR43,
input VAR15,
output VAR25,
input VAR22,
input [VAR14 - 1 : 0] VAR17,
input [VAR45 - 1 : 0] VAR2,
input... | gpl-2.0 |
kyzhai/NUNY | src/hardware/lab3/synthesis/submodules/lab3_hps_0_hps_io.v | 10,876 | module MODULE1 (
output wire [14:0] VAR2, output wire [2:0] VAR23, output wire VAR44, output wire VAR51, output wire VAR46, output wire VAR26, output wire VAR67, output wire VAR60, output wire VAR38, output wire VAR32, inout wire [31:0] VAR64, inout wire [3:0] VAR47, inout wire [3:0] VAR34, output wire VAR48, output wi... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211o/sky130_fd_sc_ls__a211o.functional.v | 1,443 | module MODULE1 (
VAR6 ,
VAR10,
VAR3,
VAR9,
VAR5
);
output VAR6 ;
input VAR10;
input VAR3;
input VAR9;
input VAR5;
wire VAR8 ;
wire VAR2;
and VAR1 (VAR8 , VAR10, VAR3 );
or VAR7 (VAR2, VAR8, VAR5, VAR9);
buf VAR4 (VAR6 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41ai/sky130_fd_sc_ls__o41ai.functional.v | 1,475 | module MODULE1 (
VAR5 ,
VAR9,
VAR1,
VAR10,
VAR8,
VAR2
);
output VAR5 ;
input VAR9;
input VAR1;
input VAR10;
input VAR8;
input VAR2;
wire VAR7 ;
wire VAR4;
or VAR11 (VAR7 , VAR8, VAR10, VAR1, VAR9 );
nand VAR3 (VAR4, VAR2, VAR7 );
buf VAR6 (VAR5 , VAR4 );
endmodule | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/MySource/adaloop.v | 3,145 | module MODULE1(
input VAR11,
input rst,
output VAR48,
output VAR36,
output reg [15:0] VAR38,
output reg [15:0] VAR57,
input [13:0] VAR60,
input [13:0] VAR50,
input VAR40,
output VAR21,
output VAR66,
output VAR56,
output VAR2,
output [3:0] VAR13,
output VAR4
);
VAR52 VAR22(
.VAR26(VAR11),
.VAR53(~rst),
.VAR55(VAR37),
.V... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/phy/phy_clock_io.v | 4,866 | module MODULE1 #
(
parameter VAR15 = 100, parameter VAR9 = 2, parameter VAR8 = "VAR2", parameter VAR1 = "VAR13", parameter VAR6 = 300.0, parameter VAR5 = "VAR16" )
(
input VAR10, input clk, input rst, output [VAR9-1:0] VAR12, output [VAR9-1:0] VAR4 );
generate
genvar VAR3;
for (VAR3 = 0; VAR3 < VAR9; VAR3 = VAR3 + 1) b... | lgpl-3.0 |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/ip/camera_controller/config_controller/I2C_Controller.v | 2,607 | module MODULE1 (
input VAR2,
input VAR10,
input [31:0] VAR3, input VAR4, output VAR7, inout VAR5, output reg VAR6, output VAR12 );
reg VAR9;
reg VAR14;
reg [31:0]VAR11;
reg [6:0]VAR13;
assign VAR7 = VAR14 | ( ((VAR13 >= 4) & (VAR13 <= 39))? ~VAR2 : 1'b0);
assign VAR5 = VAR9 ? 1'VAR15 : 1'b0;
reg VAR1,VAR8,VAR16,VAR17;
... | gpl-3.0 |
JakeMercer/mac | MAC/rtl/mac/rx/rx_sm.v | 6,638 | module MODULE1 #(
parameter VAR24 = 3'h0,
parameter VAR51 = 3'h1,
parameter VAR15 = 3'h2,
parameter VAR41 = 3'h3,
parameter VAR53 = 3'h4,
parameter VAR37 = 3'h5,
parameter VAR9 = 12
)(
input reset,
input VAR40,
input VAR48,
input [7:0] VAR26,
input VAR12,
output wire [7:0] VAR25,
input wire VAR7,
input wire VAR43,
outp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdlclkp/sky130_fd_sc_lp__sdlclkp.functional.v | 1,984 | module MODULE1 (
VAR19,
VAR8 ,
VAR15,
VAR4
);
output VAR19;
input VAR8 ;
input VAR15;
input VAR4 ;
wire VAR18 ;
wire VAR11 ;
wire VAR17 ;
wire VAR10 ;
wire VAR6 ;
wire VAR14 ;
wire VAR5;
wire VAR2 ;
not VAR7 (VAR11 , VAR18 );
not VAR12 (VAR17 , VAR4 );
nor VAR9 (VAR2, VAR15, VAR8 );
VAR16 VAR3 VAR1 (VAR18 , VAR2, VAR17... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_pwrgood_pp_g/sky130_fd_sc_ls__udp_pwrgood_pp_g.symbol.v | 1,285 | module MODULE1 (
input VAR1 ,
output VAR3,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfsbp/sky130_fd_sc_lp__sdfsbp.blackbox.v | 1,455 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR9 ,
VAR5 ,
VAR7 ,
VAR10 ,
VAR11
);
output VAR6 ;
output VAR2 ;
input VAR9 ;
input VAR5 ;
input VAR7 ;
input VAR10 ;
input VAR11;
supply1 VAR3;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/cabac_neighbour_2p_12x128.v | 2,485 | module MODULE1(
clk ,
VAR18 ,
VAR7 ,
VAR3 ,
VAR2 ,
VAR14 ,
VAR1
);
input clk ; input VAR18 ; input [6:0] VAR7 ; input VAR3 ; input [6:0] VAR2 ; input [11:0] VAR14 ;
output [11:0] VAR1 ;
VAR9 #(.VAR13(7), .VAR16(12))
VAR11 (
.VAR10 ( clk ),
.VAR8 ( ~VAR18 ),
.VAR15 ( VAR7 ),
.VAR6 ( VAR1 ),
.VAR12 ( clk ),
.VAR4 ( ~VAR3... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221ai/sky130_fd_sc_hdll__o221ai.symbol.v | 1,410 | module MODULE1 (
input VAR6,
input VAR4,
input VAR7,
input VAR3,
input VAR10,
output VAR2
);
supply1 VAR1;
supply0 VAR5;
supply1 VAR9 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
drichmond/riffa | fpga/altera/de5/DE5QGen3x4If128/hdl/DE5QGen3x4If128.v | 17,194 | module MODULE1
parameter VAR164 = 4,
parameter VAR195 = 128,
parameter VAR88 = 256,
parameter VAR77 = 5
)
(
output [7:0] VAR155,
input VAR82,
input VAR173,
input [VAR164-1:0] VAR152,
output [VAR164-1:0] VAR89,
input VAR184
);
wire VAR131;
wire VAR85;
wire [3:0] VAR199;
wire [31:0] VAR64;
wire [52:0] VAR80;
wire [0:0] V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s.behavioral.v | 1,441 | module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR2;
supply0 VAR5;
supply1 VAR9 ;
supply0 VAR8 ;
wire VAR3;
buf VAR7 (VAR3, VAR4 );
buf VAR6 (VAR1 , VAR3 );
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_registers.v | 36,445 | module MODULE1( VAR233, VAR218, VAR195, VAR223, VAR206, VAR41, VAR142,
VAR107, VAR199, VAR258, VAR246, VAR86,
VAR257, VAR247, VAR198, VAR133, VAR115,
VAR280, VAR158, VAR37, VAR279, VAR57, VAR289,
VAR205, VAR7, VAR127, VAR272, VAR75,
VAR249, VAR153, VAR29, VAR62, VAR36, VAR162,
VAR256, VAR220, VAR160, VAR2,
VAR26, VAR15... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2b/sky130_fd_sc_hdll__nand2b.functional.pp.v | 1,956 | module MODULE1 (
VAR10 ,
VAR1 ,
VAR8 ,
VAR9,
VAR15,
VAR7 ,
VAR4
);
output VAR10 ;
input VAR1 ;
input VAR8 ;
input VAR9;
input VAR15;
input VAR7 ;
input VAR4 ;
wire VAR3 ;
wire VAR6 ;
wire VAR11;
not VAR5 (VAR3 , VAR8 );
or VAR2 (VAR6 , VAR3, VAR1 );
VAR13 VAR14 (VAR11, VAR6, VAR9, VAR15);
buf VAR12 (VAR10 , VAR11 );
en... | apache-2.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/db/ip/niosII_system/submodules/niosII_system_onchip_memory2_0.v | 3,064 | module MODULE1 (
address,
VAR26,
VAR17,
clk,
VAR9,
reset,
VAR28,
write,
VAR12,
VAR2
)
;
parameter VAR20 = "MODULE1.VAR10";
output [ 31: 0] VAR2;
input [ 11: 0] address;
input [ 3: 0] VAR26;
input VAR17;
input clk;
input VAR9;
input reset;
input VAR28;
input write;
input [ 31: 0] VAR12;
wire VAR22;
wire [ 31: 0] VAR2;
w... | apache-2.0 |
hoglet67/CoPro6502 | src/m32632/ICACHE_SM.v | 11,997 | module MODULE1 ( VAR90, VAR25, VAR102, VAR91, VAR41, VAR53, VAR73 , VAR96 , VAR91, VAR80, VAR5, VAR47, VAR74, VAR94, VAR83,
VAR75, VAR92, VAR26, VAR71, VAR63, VAR39, VAR6, VAR97 );
input VAR90;
input VAR25;
input VAR102;
input [23:0] VAR91; input [27:4] VAR41;
input [27:12] VAR53,VAR73;
input [1:0] VAR96;
input [23:0] ... | gpl-3.0 |
mithro/HDMI2USB | hdl/hdmi/chnlbond.v | 5,717 | module MODULE1 (
input wire clk,
input wire [9:0] VAR16,
input wire VAR31,
input wire VAR35,
input wire VAR23,
input wire VAR4,
input wire VAR32,
output reg VAR6,
output reg [9:0] VAR11
);
parameter VAR5 = 10'b1101010100;
parameter VAR25 = 10'b0010101011;
parameter VAR20 = 10'b0101010100;
parameter VAR7 = 10'b101010101... | bsd-2-clause |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.