repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v | 11,739 | module MODULE1 # (
parameter
VAR45 = 3,
VAR64 = 25,
VAR1 = 32,
VAR13 = 8,
VAR59 = 4,
VAR34 = 0
)
(
VAR17, VAR4,
VAR11, VAR5,
VAR56, VAR55, VAR46, VAR12, VAR8, VAR52, VAR41, VAR24, VAR33, VAR10,
VAR26, VAR14, VAR6, VAR31,
VAR30,
VAR9,
VAR3,
VAR62,
VAR40,
VAR22,
VAR7,
VAR65,
VAR32,
VAR66,
VAR15,
VAR54,
VAR38,
VAR42,
VAR1... | gpl-3.0 |
YosysHQ/yosys | techlibs/xilinx/lutrams_xcv_map.v | 3,209 | module MODULE2 (...);
parameter VAR22 = 0;
parameter VAR32 = 4;
output VAR9;
input VAR28;
input [VAR32-1:0] VAR20;
input VAR11;
input VAR31;
generate
case(VAR32)
4: VAR8
.VAR22(VAR22),
)
VAR36
(
.VAR13(VAR20[0]),
.VAR6(VAR20[1]),
.VAR14(VAR20[2]),
.VAR7(VAR20[3]),
.VAR35(VAR28),
.VAR29(VAR9),
.VAR3(VAR11),
.VAR37(VAR31... | isc |
trivoldus28/pulsarch-verilog | verif/env/iss/pli/jbus_mon/rtl/jbus_mon_wrapper.v | 5,190 | module MODULE1(
VAR26,
VAR16,
VAR10,
VAR28,
VAR44,
VAR24,
VAR27,
VAR4,
VAR8,
VAR47,
VAR33,
VAR6,
VAR25,
VAR41,
VAR45,
VAR32,
VAR50,
VAR20,
VAR42,
VAR12,
VAR1,
VAR48,
VAR51,
VAR18
);
input [5:0] VAR16;
input [5:0] VAR10;
input [5:0] VAR28;
input [5:0] VAR44;
input [5:0] VAR24;
input [5:0] VAR27;
input [5:0] VAR4;
inout ... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu9t5v0__aoi22_2.behavioral.pp.v | 2,375 | module MODULE1( VAR1, VAR6, VAR9, VAR3, VAR7, VAR2, VAR8 );
input VAR7, VAR3, VAR6, VAR1;
inout VAR2, VAR8;
output VAR9;
VAR4 VAR10(.VAR1(VAR1),.VAR6(VAR6),.VAR9(VAR9),.VAR3(VAR3),.VAR7(VAR7),.VAR2(VAR2),.VAR8(VAR8));
VAR4 VAR5(.VAR1(VAR1),.VAR6(VAR6),.VAR9(VAR9),.VAR3(VAR3),.VAR7(VAR7),.VAR2(VAR2),.VAR8(VAR8)); | apache-2.0 |
545/Atari7800 | Atari7800/Atari7800.srcs/sources_1/imports/NMOS/cpu_wrapper.v | 1,049 | module MODULE1( clk, reset, VAR8, VAR7, VAR13, VAR1, VAR12, VAR11, VAR9, VAR2);
input clk; input reset; output [15:0] VAR8; input [7:0] VAR7; output [7:0] VAR13; output VAR1; input VAR12; input VAR11; input VAR9; input VAR2;
wire VAR17;
wire VAR10;
reg VAR3;
wire [7:0] VAR5;
VAR4 VAR18(.clk(clk),.reset(reset),.VAR8(VAR... | gpl-2.0 |
ultraembedded/riscv | top_tcm_axi/src_v/dport_axi.v | 9,905 | module MODULE1
(
input VAR22
,input VAR47
,input [ 31:0] VAR53
,input [ 31:0] VAR55
,input VAR13
,input [ 3:0] VAR2
,input VAR26
,input [ 10:0] VAR46
,input VAR35
,input VAR31
,input VAR29
,input VAR14
,input VAR58
,input VAR6
,input [ 1:0] VAR25
,input VAR17
,input VAR8
,input [ 31:0] VAR48
,input [ 1:0] VAR30
,output... | bsd-3-clause |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/verilog/Block_Mat_exit1573_p.v | 17,185 | module MODULE1 (
VAR20,
VAR49,
VAR6,
VAR5,
VAR1,
VAR60,
VAR46,
VAR10,
VAR62,
VAR34,
VAR54,
VAR57,
VAR35,
VAR52,
VAR17,
VAR53,
VAR25,
VAR2,
VAR48,
VAR66,
VAR58,
VAR61,
VAR42,
VAR7,
VAR33,
VAR9,
VAR67,
VAR15,
VAR3,
VAR28,
VAR13,
VAR64,
VAR32,
VAR30,
VAR14,
VAR47,
VAR41,
VAR12,
VAR26,
VAR18,
VAR44,
VAR21,
VAR11,
VAR63,
VA... | mit |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/clib/c_select_1ofn.v | 268,455 | module MODULE1
(select, VAR2, VAR3);
parameter VAR4 = 4;
parameter VAR1 = 32;
input [0:VAR4-1] select;
input [0:VAR4*VAR1-1] VAR2;
output [0:VAR1-1] VAR3;
reg [0:VAR1-1] VAR3;
generate
if(VAR4 < 1)
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
be... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v | 6,841 | module MODULE1 (
VAR33, VAR23, VAR3, VAR18, VAR9,
VAR30, VAR1, VAR40, VAR34, VAR35, VAR7, VAR14, VAR17, VAR32, VAR26,
VAR15, VAR19, VAR16, VAR31, VAR39, VAR22
);
output [31:0] VAR33, VAR23;
output [31:0] VAR3;
input [5:0] VAR30;
input [4:0] VAR1, VAR40, VAR34, VAR35;
input [1:0] VAR7;
input [31:2] VAR14;
input [31:0] V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ebufn/sky130_fd_sc_ms__ebufn_1.v | 2,148 | module MODULE2 (
VAR8 ,
VAR9 ,
VAR6,
VAR3,
VAR4,
VAR5 ,
VAR7
);
output VAR8 ;
input VAR9 ;
input VAR6;
input VAR3;
input VAR4;
input VAR5 ;
input VAR7 ;
VAR2 VAR1 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR8 ,
VAR9 ,
VAR6
);
output VAR8 ;... | apache-2.0 |
hcabrera-/lancetfish | RTL/processing_element/des_engine/verif/source.v | 1,669 | module MODULE1 #(parameter VAR5 = 5)
(
input wire clk,
input wire VAR1,
output reg VAR2,
output reg [0:63] VAR3,
output reg [0:63] VAR8
);
task VAR6;
input [0:63] VAR4;
input [0:63] VAR9;
begin
if (VAR1)
wait(VAR1 == 0);
VAR3 = VAR4;
VAR8 = VAR9;
VAR2 = 1;
@(posedge clk);
VAR3 = {64{1'VAR7}};
VAR8 = {64{1'VAR7}};
VAR2 ... | gpl-3.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | Position/Integrador_Vel.v | 5,005 | module MODULE1(
input [15:0] VAR15,
input [15:0] VAR31,
input enable,
input rst,
input clk,
output [31:0] VAR16,
output reg VAR32
);
wire VAR28;
reg en;
reg [63:0] VAR17;
reg [63:0] VAR18;
wire [31:0] VAR5;
reg VAR11;
localparam VAR26 = 32'd20084;
localparam VAR29 = 11;
assign VAR16 = VAR17[63:32];
VAR20 VAR8(
.clk(clk... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s.symbol.v | 1,319 | module MODULE1 (
input VAR2,
output VAR1
);
supply1 VAR3;
supply0 VAR4;
endmodule | apache-2.0 |
CospanDesign/nysa-artemis-pcie-platform | artemis_pcie/slave/wb_artemis_pcie_platform/rtl/c/pcie_brams_s6.v | 7,937 | module MODULE1 #(
parameter VAR7 = 0,
parameter VAR4 = 1,
parameter VAR10 = 1,
parameter VAR11 = 1
) (
input VAR2,
input VAR12,
input VAR13,
input [11:0] VAR5,
input [35:0] VAR8,
input VAR14,
input VAR3,
input [11:0] VAR16,
output [35:0] VAR9
);
localparam VAR15 = (VAR10 > 1) ? 1 : 0;
localparam [6:0] VAR1 = ((VAR7 == ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31ai/sky130_fd_sc_ls__o31ai.pp.blackbox.v | 1,376 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR6 ,
VAR5 ,
VAR7 ,
VAR8,
VAR2,
VAR1 ,
VAR9
);
output VAR3 ;
input VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR7 ;
input VAR8;
input VAR2;
input VAR1 ;
input VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4/sky130_fd_sc_lp__and4_lp.v | 2,250 | module MODULE1 (
VAR10 ,
VAR11 ,
VAR1 ,
VAR2 ,
VAR6 ,
VAR9,
VAR8,
VAR5 ,
VAR7
);
output VAR10 ;
input VAR11 ;
input VAR1 ;
input VAR2 ;
input VAR6 ;
input VAR9;
input VAR8;
input VAR5 ;
input VAR7 ;
VAR3 VAR4 (
.VAR10(VAR10),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR5(VAR5),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32o/sky130_fd_sc_ms__a32o.pp.symbol.v | 1,431 | module MODULE1 (
input VAR10 ,
input VAR5 ,
input VAR8 ,
input VAR6 ,
input VAR4 ,
output VAR1 ,
input VAR3 ,
input VAR9,
input VAR7,
input VAR2
);
endmodule | apache-2.0 |
AmeerAbdelhadi/Multiported-RAM | mrram.v | 5,121 | module MODULE1
localparam VAR10 = VAR3(VAR17);
reg [VAR10-1:0] VAR8 [VAR15-1:0]; wire [VAR2-1:0] VAR7 [VAR15-1:0];
always @* begin
end
genvar VAR18;
generate
for (VAR18=0 ; VAR18<VAR15 ; VAR18=VAR18+1) begin: VAR5
VAR11 #( .VAR17 (VAR17 ), .VAR2 (VAR2 ), .VAR4 (VAR4 ), .VAR19 (VAR19 ), .VAR12 (VAR12 )) VAR1 ( .clk (clk... | bsd-3-clause |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/butterfly3_8.v | 2,072 | module MODULE1(
enable,
VAR11,
VAR14,
VAR5,
VAR10,
VAR7,
VAR12,
VAR13,
VAR9,
o0,
o1,
o2,
o3,
o4,
o5,
o6,
o7
);
input enable;
input signed [27:0] VAR11;
input signed [27:0] VAR14;
input signed [27:0] VAR5;
input signed [27:0] VAR10;
input signed [27:0] VAR7;
input signed [27:0] VAR12;
input signed [27:0] VAR13;
input si... | gpl-3.0 |
cpulabs/mist1032isa | src/mmu/mmu.v | 18,200 | module MODULE1(
input wire VAR105,
input wire VAR54,
input wire VAR124,
input wire VAR49,
input wire VAR17,
output wire VAR127,
input wire VAR73,
input wire [1:0] VAR90, input wire [2:0] VAR25, input wire [31:0] VAR91, input wire [13:0] VAR112, input wire [1:0] VAR93,
input wire [3:0] VAR32,
input wire VAR34, input wir... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdlclkp/sky130_fd_sc_ms__sdlclkp.symbol.v | 1,338 | module MODULE1 (
input VAR8 ,
input VAR2 ,
input VAR5,
output VAR7
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/cpu/spm.v | 6,327 | module MODULE1 (
input wire clk , input wire [VAR19] VAR22 , input wire VAR29 , input wire VAR15 , input wire [VAR30] VAR24 , output wire [VAR30] VAR17 , input wire [VAR19] VAR21 , input wire VAR20 , input wire VAR28 , input wire [VAR30] VAR16 , output wire [VAR30] VAR4 );
reg VAR6 ; reg VAR1 ;
always @(*) begin
if ((V... | apache-2.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/altera_avalon_sc_fifo.v | 32,190 | module MODULE1
parameter VAR61 = 1,
parameter VAR22 = 8,
parameter VAR6 = 16,
parameter VAR54 = 0,
parameter VAR10 = 0,
parameter VAR80 = 0,
parameter VAR8 = 0,
parameter VAR18 = 0,
parameter VAR50 = 0,
parameter VAR44 = 0,
parameter VAR83 = 3,
parameter VAR98 = 1,
parameter VAR66 = VAR61 * VAR22,
parameter VAR38 = VAR... | gpl-2.0 |
KorotkiyEugene/LAG_sv_syn_quartus | LAG_fifo_.v | 7,716 | typedef struct packed
{
logic VAR23, VAR32, VAR25, VAR18;
} VAR15;
module MODULE1 (VAR30, VAR6, VAR17, VAR11, VAR2, clk, VAR7);
parameter VAR10 = 8;
input VAR30, VAR6;
output VAR15 VAR2;
input VAR24 VAR17;
output VAR24 VAR11;
input clk, VAR7;
logic VAR16, VAR1;
VAR24 VAR12, VAR21;
MODULE2 #(.VAR10(VAR10))
VAR28 (VAR30,... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbn/sky130_fd_sc_hs__dfbbn.pp.symbol.v | 1,451 | module MODULE1 (
input VAR5 ,
output VAR7 ,
output VAR8 ,
input VAR2,
input VAR3 ,
input VAR6 ,
input VAR1 ,
input VAR4
);
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/models/DCM_SP.v | 33,403 | module MODULE1 (
VAR40, VAR35, VAR45, VAR74, VAR121, VAR82,
VAR15, VAR55, VAR109, VAR83, VAR130, VAR57,
VAR4, VAR88, VAR10, VAR43, VAR65, VAR70, VAR80);
parameter VAR23 = 2.0;
parameter integer VAR66 = 1;
parameter integer VAR41 = 4;
parameter VAR91 = "VAR8";
parameter VAR29 = 10.0; parameter VAR132 = "VAR107";
paramet... | gpl-2.0 |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_0_rank_mach.v | 12,347 | module MODULE1 #
(
parameter VAR49 = "8",
parameter VAR38 = 4,
parameter VAR18 = "VAR29",
parameter VAR54 = 40,
parameter VAR60 = 4,
parameter VAR19 = 4,
parameter VAR5 = 2,
parameter VAR37 = 5,
parameter VAR14 = 5,
parameter VAR12 = 2,
parameter VAR27 = 30,
parameter VAR22 = 8,
parameter VAR63 = 4,
parameter VAR34 = 4... | mit |
revaldinho/opc | copro/src/memory_controller.v | 5,397 | module MODULE1
(
VAR21,
VAR1,
VAR24,
VAR27,
VAR11,
VAR30,
VAR14,
VAR10,
VAR32,
VAR15,
VAR2,
VAR4,
VAR9,
VAR35
);
parameter VAR12 = 16;
parameter VAR8 = 16;
parameter VAR26 = 6;
localparam VAR31 = VAR34(VAR12) - 1; localparam VAR18 = VAR8 - VAR26;
localparam VAR25 = VAR12 + 1 + VAR18;
localparam VAR20 = 2 ** VAR26;
inpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfstp/sky130_fd_sc_hd__sdfstp.behavioral.pp.v | 2,802 | module MODULE1 (
VAR23 ,
VAR29 ,
VAR24 ,
VAR5 ,
VAR12 ,
VAR1,
VAR2 ,
VAR26 ,
VAR4 ,
VAR14
);
output VAR23 ;
input VAR29 ;
input VAR24 ;
input VAR5 ;
input VAR12 ;
input VAR1;
input VAR2 ;
input VAR26 ;
input VAR4 ;
input VAR14 ;
wire VAR21 ;
wire VAR16 ;
wire VAR6 ;
reg VAR9 ;
wire VAR11 ;
wire VAR18 ;
wire VAR25 ;
wir... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_link/bsg_link_ddr_upstream.v | 9,315 | module MODULE1
,parameter VAR55 = 8
,parameter VAR46 = 1
,parameter VAR20 = 6
,parameter VAR37 = 3
,parameter VAR39 = 0
,parameter VAR19 = 0
,parameter VAR45 = 0
,parameter VAR23 = 0
,localparam VAR29 = VAR55*2 + VAR39
,localparam VAR48 = VAR3/(VAR29*VAR46)
,localparam VAR56 = VAR55+1
)
( input VAR42
,input VAR2
,input... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31o/sky130_fd_sc_lp__a31o.functional.v | 1,434 | module MODULE1 (
VAR9 ,
VAR1,
VAR6,
VAR2,
VAR8
);
output VAR9 ;
input VAR1;
input VAR6;
input VAR2;
input VAR8;
wire VAR3 ;
wire VAR4;
and VAR10 (VAR3 , VAR2, VAR1, VAR6 );
or VAR7 (VAR4, VAR3, VAR8 );
buf VAR5 (VAR9 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311ai/sky130_fd_sc_lp__o311ai_1.v | 2,435 | module MODULE2 (
VAR9 ,
VAR4 ,
VAR3 ,
VAR8 ,
VAR2 ,
VAR12 ,
VAR6,
VAR7,
VAR1 ,
VAR5
);
output VAR9 ;
input VAR4 ;
input VAR3 ;
input VAR8 ;
input VAR2 ;
input VAR12 ;
input VAR6;
input VAR7;
input VAR1 ;
input VAR5 ;
VAR11 VAR10 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR6(VAR... | apache-2.0 |
efabless/openlane | designs/s44/src/lut.v | 1,094 | module MODULE1 #(
parameter VAR5=4, VAR8=1<<VAR5, VAR6=8
) (
input [VAR5-1:0] addr,
output out,
input VAR7,
input VAR3,
input [VAR6-1:0] VAR1,
output [VAR6-1:0] VAR2
);
reg [VAR8-1:0] VAR4 = 0;
assign out = VAR4[addr];
generate
genvar VAR9;
for (VAR9=1; VAR9<(VAR8/VAR6); VAR9=VAR9+1) begin
always @(posedge VAR7) begin
... | apache-2.0 |
thucoldwind/ucore_mips | CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/async.v | 7,485 | module MODULE4(
input clk,
input VAR44,
input [7:0] VAR24,
output VAR17,
output VAR2
);
parameter VAR42 = 12500000; parameter VAR29 = 115200;
generate
if(VAR42<VAR29*8 && (VAR42 % VAR29!=0)) MODULE1 VAR16("VAR7 VAR21 with VAR43 VAR29 VAR22");
endgenerate
wire VAR45 = 1'b1; else
wire VAR45;
MODULE2 #(VAR42, VAR29) VAR34... | unlicense |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/example_design/rtl/example_top.v | 25,208 | module MODULE1 #
(
parameter VAR85 = 32'h00000000,
parameter VAR110 = 32'h00ffffff,
parameter VAR180 = 32'hff000000,
parameter VAR120 = 0,
parameter VAR83 = 8'h11,
parameter VAR100 = 3'b000,
parameter VAR9 = 0,
parameter VAR67 = 0,
parameter VAR163 = 3,
parameter VAR35 = 10,
parameter VAR105 = 1,
parameter VAR31 = 16,
... | mit |
Progressive-Learning-Platform/progressive-learning-platform | reference/hw/verilog/cpu_if.v | 3,144 | module MODULE1(rst, clk, VAR18, VAR20, VAR16, VAR13,
VAR15, VAR19, VAR2, VAR6, VAR5, VAR8, int, VAR12, VAR9, VAR4);
input rst, clk, VAR18, int;
input VAR13;
input VAR15;
input [31:0] VAR19;
input [31:0] VAR2;
input VAR8;
output reg [31:0] VAR16;
output [31:0] VAR20;
input [31:0] VAR6;
output reg [31:0] VAR5;
output VAR... | gpl-3.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_cpu_s1_jtag_debug_module_sysclk.v | 6,946 | module MODULE1 (
clk,
VAR29,
VAR25,
VAR10,
VAR2,
VAR21,
VAR30,
VAR27,
VAR16,
VAR31,
VAR22,
VAR19,
VAR14,
VAR4,
VAR13,
VAR11,
VAR8,
VAR18,
VAR1
)
;
output [ 37: 0] VAR21;
output VAR30;
output VAR27;
output VAR16;
output VAR31;
output VAR22;
output VAR19;
output VAR14;
output VAR4;
output VAR13;
output VAR11;
output VAR8... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31a/sky130_fd_sc_hs__o31a.functional.v | 1,907 | module MODULE1 (
VAR15,
VAR4,
VAR3 ,
VAR7 ,
VAR9 ,
VAR8 ,
VAR2
);
input VAR15;
input VAR4;
output VAR3 ;
input VAR7 ;
input VAR9 ;
input VAR8 ;
input VAR2 ;
wire VAR2 VAR1 ;
wire VAR5 ;
wire VAR12;
or VAR10 (VAR1 , VAR9, VAR7, VAR8 );
and VAR14 (VAR5 , VAR1, VAR2 );
VAR11 VAR6 (VAR12, VAR5, VAR15, VAR4);
buf VAR13 (VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32a/sky130_fd_sc_lp__o32a_2.v | 2,428 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR1 ,
VAR5 ,
VAR6 ,
VAR8 ,
VAR9,
VAR10,
VAR4 ,
VAR12
);
output VAR11 ;
input VAR3 ;
input VAR1 ;
input VAR5 ;
input VAR6 ;
input VAR8 ;
input VAR9;
input VAR10;
input VAR4 ;
input VAR12 ;
VAR7 VAR2 (
.VAR11(VAR11),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(V... | apache-2.0 |
alexforencich/verilog-ethernet | example/HXT100G/fpga/rtl/eth_gth_phy_quad.v | 17,331 | module MODULE1 (
input wire VAR141,
input wire VAR120,
input wire VAR3,
input wire VAR51,
output wire VAR241,
input wire VAR6,
output wire VAR209,
input wire VAR256,
input wire VAR283,
output wire VAR46,
output wire VAR19,
input wire VAR28,
input wire VAR81,
output wire VAR115,
output wire VAR12,
input wire VAR257,
inp... | mit |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/hdl/mig_wrap_wrapper.v | 6,825 | module MODULE1
(VAR38,
VAR35,
VAR45,
VAR39,
VAR36,
VAR6,
VAR41,
VAR55,
VAR57,
VAR44,
VAR25,
VAR3,
VAR14,
VAR42,
VAR29,
VAR43,
VAR59,
VAR30,
VAR22,
VAR15,
VAR2,
VAR37,
VAR8,
VAR58,
VAR47,
VAR53,
VAR1,
VAR48,
VAR33,
VAR46,
VAR12,
VAR18,
VAR27,
VAR19,
VAR52,
VAR21,
VAR34,
VAR24,
VAR54,
VAR23,
VAR61,
VAR50,
VAR7,
VAR16,
VA... | mit |
DSDL2016/project2 | source/synthesizer/staff.v | 1,712 | module MODULE1(
input [7:0]VAR5,
output [15:0]VAR15,
output VAR23
);
assign VAR23=(VAR5==8'hf0)?0:1;
wire VAR12=(VAR5==8'h1c)?1:0; wire VAR10=(VAR5==8'h1b)?1:0; wire VAR20=(VAR5==8'h23)?1:0; wire VAR8=(VAR5==8'h2b)?1:0; wire VAR27=(VAR5==8'h34)?1:0; wire VAR24=(VAR5==8'h33)?1:0; wire VAR13=(VAR5==8'h3b)?1:0; wire VAR6=... | mit |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/acc_vadd_hls/solution1/syn/verilog/acc_vadd_hls.v | 16,294 | module MODULE1 (
VAR29,
VAR54,
VAR26,
VAR42,
VAR36,
VAR66,
VAR4,
VAR27,
VAR69,
VAR55,
VAR25,
VAR53,
VAR16,
VAR18,
VAR14,
VAR39,
VAR51,
VAR6,
VAR22,
VAR31,
VAR15,
VAR17,
VAR71,
VAR61,
VAR81,
VAR62,
VAR64,
VAR21,
VAR8
);
parameter VAR5 = 1'b1;
parameter VAR76 = 1'b0;
parameter VAR1 = 3'b000;
parameter VAR41 = 3'b1;
param... | bsd-3-clause |
rurume/openrisc_vision_hardware | ISE/uart_wb.v | 11,301 | module MODULE1 (clk, VAR25,
VAR19, VAR26, VAR2, VAR9, VAR1,
VAR12, VAR20, VAR8, VAR3, VAR4, VAR21, VAR14,
VAR5, VAR16 );
input clk;
input VAR25;
input VAR19;
input VAR26;
input VAR2;
input [3:0] VAR14;
input [VAR11-1:0] VAR1;
input [7:0] VAR20; output [7:0] VAR8;
reg [7:0] VAR8;
wire [7:0] VAR20;
reg [7:0] VAR23;
reg [... | gpl-2.0 |
jefflieu/recon | hw/recon_2/max1000/alt_ip/alt_ddr.v | 6,774 | module MODULE1 (
input wire VAR7, input wire [1:0] din, output wire [0:0] VAR10 );
VAR31 #(
.VAR24 ("output"),
.VAR5 (1),
.VAR21 ("VAR43"),
.VAR38 ("VAR8-VAR26"),
.VAR14 ("none"),
.VAR49 ("none"),
.VAR41 ("false"),
.VAR35 ("false"),
.VAR36 ("false"),
.VAR46 ("false"),
.VAR32 ("false"),
.VAR42 ("false"),
.VAR3 ("false")... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/example_design/rtl/traffic_gen/afifo.v | 6,181 | module MODULE1 #
(
parameter VAR7 = 100,
parameter VAR29 = 32,
parameter VAR23 = 16,
parameter VAR34 = 4,
parameter VAR27 = 1 )
(
input VAR33,
input rst,
input VAR28,
input [VAR29-1:0] VAR5,
input VAR10,
input VAR9,
output [VAR29-1:0] VAR26,
output reg VAR8,
output reg VAR19,
output reg VAR2
);
reg [VAR29-1:0] VAR17 [0... | lgpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x1_125/example_design/pci_exp_64b_app.v | 11,911 | module MODULE1 (
VAR19,
VAR58,
VAR47,
VAR71,
VAR12,
VAR13,
VAR52,
VAR35,
VAR39,
VAR69,
VAR59,
VAR31,
VAR44,
VAR53,
VAR11,
VAR14,
VAR45,
VAR64,
VAR74,
VAR46,
VAR49,
VAR22,
VAR38,
VAR9,
VAR56,
VAR18,
VAR30,
VAR41,
VAR16,
VAR67,
VAR25,
VAR17,
VAR10,
VAR34,
VAR68,
VAR55,
VAR29,
VAR70,
VAR62,
VAR21,
VAR32,
VAR73,
VAR63,
VAR... | lgpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/RAMB16_S4_altera_bb.v | 6,359 | module MODULE1 (
VAR1,
address,
VAR2,
VAR5,
VAR6,
VAR3,
VAR4);
input VAR1;
input [11:0] address;
input VAR2;
input VAR5;
input [3:0] VAR6;
input VAR3;
output [3:0] VAR4;
tri0 VAR1;
tri1 VAR2;
tri1 VAR5;
endmodule | mit |
SiLab-Bonn/basil | basil/firmware/modules/rrp_arbiter/rrp_arbiter.v | 2,728 | module MODULE1 #(
parameter VAR6 = 4
) (
input wire VAR3,
input wire VAR16,
input wire [VAR6-1:0] VAR20, input wire [VAR6-1:0] VAR15, input wire [VAR6*32-1:0] VAR2,
output wire[VAR6-1:0] VAR8,
input wire VAR17,
output wire VAR11,
output wire [31:0] VAR13
);
integer VAR1;
reg [VAR6-1:0] VAR4; reg [VAR6-1:0] select;
reg ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux4/sky130_fd_sc_hd__mux4.behavioral.pp.v | 1,983 | module MODULE1 (
VAR16 ,
VAR17 ,
VAR9 ,
VAR8 ,
VAR2 ,
VAR14 ,
VAR5 ,
VAR7,
VAR10,
VAR6 ,
VAR18
);
output VAR16 ;
input VAR17 ;
input VAR9 ;
input VAR8 ;
input VAR2 ;
input VAR14 ;
input VAR5 ;
input VAR7;
input VAR10;
input VAR6 ;
input VAR18 ;
wire VAR13 ;
wire VAR1;
VAR11 VAR4 (VAR13 , VAR17, VAR9, VAR8, VAR2, VAR14,... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/dsp_rx_glue.v | 3,577 | module MODULE1
parameter VAR7 = 0,
parameter VAR5 = 24
)
(
input VAR2, input reset, input VAR15, input enable,
input VAR14, input [7:0] VAR9, input [31:0] VAR4,
input [VAR5-1:0] VAR16,
input [VAR5-1:0] VAR1,
output [VAR5-1:0] VAR13,
output [VAR5-1:0] VAR10,
input [31:0] VAR3,
input VAR17, output VAR8,
output [31:0] VAR... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_sig_bot.v | 80,321 | module MODULE1(VAR165 ,VAR236 ,VAR92 ,
VAR166 ,VAR58 ,VAR119 ,VAR72 ,VAR262 ,VAR23 ,VAR364
,VAR100 ,VAR289 ,VAR237 ,VAR40 ,VAR183 ,VAR180 ,
VAR337 ,VAR256 ,VAR202 ,VAR229 ,
VAR70 ,VAR322 ,VAR205 ,VAR11
,VAR305 ,VAR185 ,VAR302 ,VAR257 ,
VAR270 ,VAR324 ,VAR394 ,VAR356 ,
VAR240 ,VAR316 ,VAR380 ,VAR113 ,VAR318 ,
VAR359 ,VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrbp/sky130_fd_sc_hs__sdfrbp.functional.v | 2,197 | module MODULE1 (
VAR10 ,
VAR3 ,
VAR13 ,
VAR1 ,
VAR5 ,
VAR18 ,
VAR7 ,
VAR12 ,
VAR20
);
input VAR10 ;
input VAR3 ;
output VAR13 ;
output VAR1 ;
input VAR5 ;
input VAR18 ;
input VAR7 ;
input VAR12 ;
input VAR20;
wire VAR15 ;
wire VAR8 ;
wire VAR4;
not VAR9 (VAR8 , VAR20 );
VAR19 VAR11 (VAR4, VAR18, VAR7, VAR12 );
VAR16 VA... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/phy_init.v | 123,767 | module MODULE1 #
(
parameter VAR63 = 100,
parameter VAR183 = 2, parameter VAR139 = 3333, parameter VAR251 = 2,
parameter VAR163 = 10,
parameter VAR207 = 1, parameter VAR186 = 64,
parameter VAR122 = 14,
parameter VAR213 = 1,
parameter VAR92 = 1, parameter VAR117 = "VAR75",
parameter VAR206 = "VAR84",
parameter VAR18 = 1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2/sky130_fd_sc_ms__nor2.symbol.v | 1,260 | module MODULE1 (
input VAR5,
input VAR7,
output VAR6
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dlatch_p/sky130_fd_sc_hdll__udp_dlatch_p.blackbox.v | 1,255 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR3
);
output VAR2 ;
input VAR1 ;
input VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2o/sky130_fd_sc_hd__a2bb2o.functional.pp.v | 2,231 | module MODULE1 (
VAR15 ,
VAR8,
VAR1,
VAR3 ,
VAR4 ,
VAR12,
VAR16,
VAR13 ,
VAR6
);
output VAR15 ;
input VAR8;
input VAR1;
input VAR3 ;
input VAR4 ;
input VAR12;
input VAR16;
input VAR13 ;
input VAR6 ;
wire VAR7 ;
wire VAR10 ;
wire VAR17 ;
wire VAR5;
and VAR2 (VAR7 , VAR3, VAR4 );
nor VAR19 (VAR10 , VAR8, VAR1 );
or VAR18... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/edk/pcores/iop_fpga_v1_00_a/hdl/verilog/sparc.v | 5,826 | module MODULE1 (
VAR28, VAR10, VAR3, VAR25,
VAR23, VAR38, VAR14,
VAR33, VAR31, VAR12,
VAR41, VAR37, VAR43,
VAR29, VAR16, VAR8, VAR15, VAR20,
VAR32, VAR18, VAR11,
VAR30, VAR2, VAR22,
VAR7, VAR13, VAR9,
VAR40, VAR1, VAR21,
VAR24, VAR39, VAR42,
VAR44, VAR35, VAR36, VAR6, VAR34,
VAR5, VAR19, VAR17, VAR27
);
output [4:0] VA... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_2.behavioral.v | 2,557 | module MODULE1( VAR4, VAR2, VAR6, VAR3 );
input VAR2, VAR4, VAR6;
output VAR3;
VAR7 VAR5(.VAR4(VAR4),.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3));
VAR7 VAR1(.VAR4(VAR4),.VAR2(VAR2),.VAR6(VAR6),.VAR3(VAR3)); | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/ip_top/mem_intfc.v | 39,881 | module MODULE1 #
(
parameter VAR222 = 100,
parameter VAR34 = 64,
parameter VAR111 = "VAR142",
parameter VAR124 = "0", parameter VAR6 = 3, parameter VAR140 = 2, parameter VAR231 = "8", parameter VAR190 = "VAR131", parameter VAR248 = 1, parameter VAR76 = 5,
parameter VAR48 = 12, parameter VAR50 = "VAR208", parameter VAR2... | lgpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/src_coregen/chipscope_icon_v1_03_a.v | 42,023 | module MODULE1 (
VAR18
);
inout [35 : 0] VAR18;
wire VAR23;
wire \VAR134/VAR123/VAR114.VAR43/VAR67 ;
wire \VAR134/VAR123/VAR48 ;
wire \VAR134/VAR123/VAR109/VAR124 ;
wire \VAR134/VAR123/VAR109/VAR111 ;
wire \VAR134/VAR123/VAR55/VAR157 ;
wire \VAR134/VAR123/VAR28/VAR151 ;
wire \VAR134/VAR123/VAR28/VAR157 ;
wire \VAR134/V... | mit |
mrehkopf/sd2snes | verilog/sd2snes_sgb/dec_table.v | 6,444 | module MODULE1 (
address,
VAR49,
VAR48);
input [7:0] address;
input VAR49;
output [15:0] VAR48;
tri1 VAR49;
wire [15:0] VAR14;
wire [15:0] VAR48 = VAR14[15:0];
VAR22 VAR11 (
.VAR32 (address),
.VAR40 (VAR49),
.VAR21 (VAR14),
.VAR52 (1'b0),
.VAR46 (1'b0),
.VAR33 (1'b1),
.VAR37 (1'b0),
.VAR6 (1'b0),
.VAR18 (1'b1),
.VAR30 ... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_4.functional.pp.v | 1,772 | module MODULE1( VAR20, VAR13, VAR16, VAR5, VAR7, VAR18, VAR9 );
input VAR13, VAR5, VAR16;
inout VAR18, VAR9;
output VAR7, VAR20;
wire VAR22;
and VAR25( VAR22, VAR13, VAR5 );
wire VAR12;
and VAR17( VAR12, VAR13, VAR16 );
wire VAR23;
and VAR29( VAR23, VAR5, VAR16 );
or VAR15( VAR7, VAR22, VAR12, VAR23 );
wire VAR2;
and V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp.functional.pp.v | 2,716 | module MODULE1 (
VAR9 ,
VAR13 ,
VAR11 ,
VAR2 ,
VAR21 ,
VAR10 ,
VAR16,
VAR26 ,
VAR15 ,
VAR27 ,
VAR17
);
output VAR9 ;
output VAR13 ;
input VAR11 ;
input VAR2 ;
input VAR21 ;
input VAR10 ;
input VAR16;
input VAR26 ;
input VAR15 ;
input VAR27 ;
input VAR17 ;
wire VAR20 ;
wire VAR4 ;
wire VAR14 ;
wire VAR19 ;
wire VAR25;
n... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvp/sky130_fd_sc_hdll__einvp_1.v | 2,146 | module MODULE2 (
VAR5 ,
VAR7 ,
VAR8 ,
VAR1,
VAR3,
VAR2 ,
VAR6
);
output VAR5 ;
input VAR7 ;
input VAR8 ;
input VAR1;
input VAR3;
input VAR2 ;
input VAR6 ;
VAR9 VAR4 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR5 ,
VAR7 ,
VAR8
);
output VAR5... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/c2i/rtl/c2i.v | 27,363 | module MODULE1 (
VAR97, VAR80, VAR128,
VAR115, VAR161,
VAR159, VAR82, VAR139, VAR68,
VAR32, VAR156, VAR87,
VAR4, VAR146, VAR28,
VAR62, VAR24, VAR91,
VAR138, VAR149, VAR88,
VAR5, VAR170, VAR123,
VAR153, VAR142, VAR8,
VAR60, VAR135, VAR78,
VAR43, VAR120, VAR111,
VAR74, VAR41, VAR72, VAR137,
VAR124, VAR23, VAR58, VAR81,
V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22ai/sky130_fd_sc_lp__o22ai.functional.v | 1,519 | module MODULE1 (
VAR4 ,
VAR12,
VAR5,
VAR11,
VAR8
);
output VAR4 ;
input VAR12;
input VAR5;
input VAR11;
input VAR8;
wire VAR3 ;
wire VAR7 ;
wire VAR10;
nor VAR1 (VAR3 , VAR11, VAR8 );
nor VAR6 (VAR7 , VAR12, VAR5 );
or VAR9 (VAR10, VAR7, VAR3);
buf VAR2 (VAR4 , VAR10 );
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/master_0/altera_jtag_dc_streaming/altera_avalon_st_jtag_interface.v | 2,383 | module MODULE1 (
clk,
VAR11,
VAR14,
VAR7,
VAR5,
VAR6,
VAR3,
VAR9,
VAR12
);
input clk;
input VAR11;
output [7:0] VAR7;
input VAR14;
output VAR5;
input [7:0] VAR6;
input VAR3;
output VAR9;
output VAR12;
parameter VAR18 = 0; parameter VAR19 = 0;
parameter VAR10 = 0;
parameter VAR8 = 0; parameter VAR15 = 50000;
wire clk;
w... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31oi/sky130_fd_sc_ls__a31oi.functional.v | 1,448 | module MODULE1 (
VAR6 ,
VAR8,
VAR4,
VAR5,
VAR1
);
output VAR6 ;
input VAR8;
input VAR4;
input VAR5;
input VAR1;
wire VAR3 ;
wire VAR7;
and VAR2 (VAR3 , VAR5, VAR8, VAR4 );
nor VAR9 (VAR7, VAR1, VAR3 );
buf VAR10 (VAR6 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2/sky130_fd_sc_hd__nand2.symbol.v | 1,266 | module MODULE1 (
input VAR3,
input VAR1,
output VAR7
);
supply1 VAR4;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
bluespec/Flute | builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkRISCV_MBox.v | 31,300 | module MODULE1(VAR5,
VAR32,
VAR165,
VAR73,
VAR76,
VAR23,
VAR85,
VAR104,
VAR105,
VAR64,
VAR130,
VAR118,
VAR80,
VAR108,
valid,
word);
input VAR5;
input VAR32;
input [3 : 0] VAR165;
input VAR73;
output VAR76;
input VAR23;
output VAR85;
input VAR104;
output VAR105;
input VAR64;
input [2 : 0] VAR130;
input [63 : 0] VAR118;
... | apache-2.0 |
yanhongwang/ColorImage | GammaCorrection/GammaCorrection.v | 7,913 | module MODULE2
(
input[ VAR5 - 1 : 0 ]VAR4,
output reg[ VAR5 - 1 : 0 ]VAR1
);
always@( VAR4 )
VAR1 = VAR2( VAR4 >> VAR6 );
function[ VAR5 - 1 : 0 ]VAR2;
input[ VAR5 - 1 : 0 ]VAR4;
begin
case( VAR4 )
0 : VAR2 = 0;
1 : VAR2 = 5404;
2 : VAR2 = 7383;
3 : VAR2 = 8860;
4 : VAR2 = 10085;
5 : VAR2 = 11150;
6 : VAR2 = 12104;
7 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux4/sky130_fd_sc_lp__mux4.behavioral.v | 1,688 | module MODULE1 (
VAR15 ,
VAR7,
VAR8,
VAR10,
VAR12,
VAR3,
VAR9
);
output VAR15 ;
input VAR7;
input VAR8;
input VAR10;
input VAR12;
input VAR3;
input VAR9;
supply1 VAR2;
supply0 VAR14;
supply1 VAR5 ;
supply0 VAR13 ;
wire VAR1;
VAR6 VAR11 (VAR1, VAR7, VAR8, VAR10, VAR12, VAR3, VAR9);
buf VAR4 (VAR15 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/conb/sky130_fd_sc_hd__conb.pp.blackbox.v | 1,255 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR4,
VAR1,
VAR5 ,
VAR3
);
output VAR2 ;
output VAR6 ;
input VAR4;
input VAR1;
input VAR5 ;
input VAR3 ;
endmodule | apache-2.0 |
apotocnik/redpitaya_guide | cores/axi_bram_reader_v1_0/bram_reader_v1_0_S00_AXI.v | 15,009 | module MODULE1 #
(
parameter integer VAR32 = 32,
parameter integer VAR6 = 13,
parameter integer VAR37 = 32,
parameter integer VAR9 = 15
)
(
output wire [VAR6-1:0] VAR33,
input wire [VAR32-1:0] VAR27,
input wire VAR34,
input wire VAR2,
input wire [VAR9-1 : 0] VAR35,
input wire [2 : 0] VAR28,
input wire VAR39,
output wir... | gpl-3.0 |
pollow/Single_Cycle_CPU | CPU_TOP.v | 17,662 | module MODULE1(
input VAR40,
input VAR24,
input [7:0]VAR10,
output [6:0]VAR27,
output [3:0]VAR16
);
wire [31:0]VAR23, VAR18, VAR7, VAR31, VAR19, VAR36, VAR38, VAR5, VAR6, VAR12;
wire [31:0]VAR13, VAR25, VAR32, VAR17, VAR35;
wire [4:0] VAR9;
wire [1:0] VAR33, VAR14;
wire VAR20, VAR29, VAR4, VAR11, VAR15, VAR34, VAR21, V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd1/sky130_fd_sc_ms__clkdlyinv3sd1.behavioral.pp.v | 1,867 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR1,
VAR3,
VAR4 ,
VAR5
);
output VAR2 ;
input VAR7 ;
input VAR1;
input VAR3;
input VAR4 ;
input VAR5 ;
wire VAR9 ;
wire VAR8;
not VAR11 (VAR9 , VAR7 );
VAR12 VAR10 (VAR8, VAR9, VAR1, VAR3);
buf VAR6 (VAR2 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4b/sky130_fd_sc_lp__and4b_lp.v | 2,308 | module MODULE2 (
VAR7 ,
VAR4 ,
VAR1 ,
VAR10 ,
VAR5 ,
VAR2,
VAR3,
VAR11 ,
VAR9
);
output VAR7 ;
input VAR4 ;
input VAR1 ;
input VAR10 ;
input VAR5 ;
input VAR2;
input VAR3;
input VAR11 ;
input VAR9 ;
VAR6 VAR8 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR11(VAR11),
.... | apache-2.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/top.v | 18,408 | module MODULE1(
input VAR210,
output VAR14,
input VAR8,
input VAR240,
input VAR284,
input VAR129,
input VAR272,
input VAR31,
input VAR215,
output VAR235,
output VAR295,
output VAR273,
output VAR83,
inout [7:0] VAR18,
input [15:0] VAR57,
output VAR47,
output VAR110,
output VAR128,
output VAR90,
output VAR260, output VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_nsr/sky130_fd_sc_lp__udp_dff_nsr.symbol.v | 1,408 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR1,
input VAR4 ,
input VAR3
);
endmodule | apache-2.0 |
velizarefremov/MIPS | Part 4/Verilog Code/regfileparam_behav.v | 1,327 | module MODULE1
parameter VAR11 = 4)
(output [VAR3-1:0] VAR7,
output [VAR3-1:0] VAR9,
output [VAR3-1:0] VAR12,
input [VAR11-1:0] VAR1, input [VAR11-1:0] VAR5, input [VAR11-1:0] VAR2, input [VAR3-1:0] VAR6,
input VAR4,
input clk, rst
);
integer VAR10;
reg [VAR3-1:0] VAR8 [2**VAR11-1:0];
always @(posedge clk, negedge rst)... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o32ai/sky130_fd_sc_hs__o32ai.pp.blackbox.v | 1,372 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR2 ,
VAR3 ,
VAR1 ,
VAR4 ,
VAR7,
VAR6
);
output VAR5 ;
input VAR8 ;
input VAR2 ;
input VAR3 ;
input VAR1 ;
input VAR4 ;
input VAR7;
input VAR6;
endmodule | apache-2.0 |
Jafet95/I-Proyecto-Laboratorio-de-Dise-o-Sistemas-Digitales | Registro_universal.v | 1,454 | module MODULE1
(
input wire VAR4, input wire VAR8, input wire clk, input wire reset, input wire VAR9, output wire VAR6, output wire VAR7 );
reg VAR3,VAR1,VAR2,VAR5;
always@(posedge clk, posedge reset)
begin
if(reset)
begin
VAR3 <= 0;
VAR1 <= 0;
end
else
begin
VAR3 <= VAR2;
VAR1 <= VAR5;
end
end
always@*
begin
case(VAR9... | apache-2.0 |
Microsoft/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/pcie_dma_engine/pcie_dma_wrapper.v | 32,235 | module MODULE1(
input clk,
input VAR286,
input rst,
output VAR88,
input [63:0] VAR251,
output VAR333,
input VAR38,
output reg VAR193,
input [63:0] VAR7,
output VAR147,
input VAR250,
input VAR175,
output VAR47,
output [2:0] VAR196,
output [27:6] VAR107,
output VAR130,
input VAR205,
input [1:0] VAR149,
output [1:0] VAR12... | bsd-2-clause |
mfkiwl/parallella-platform | hdl/debouncer.v | 1,720 | module MODULE1 (
VAR2,
clk, VAR4
);
parameter VAR1 = 20;
input clk; input VAR4; output VAR2;
wire VAR6;
wire VAR5;
reg [VAR1-1:0] counter;
wire VAR3;
VAR7 #(1) VAR7(.out (VAR5),
.in (VAR4),
.clk (clk),
.reset (1'b0));
always @ (posedge clk)
if(VAR5)
counter[VAR1-1:0]={(VAR1){1'b1}};
else if(VAR3)
counter[VAR1-1:0]=coun... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/einvn/sky130_fd_sc_hvl__einvn.behavioral.pp.v | 1,881 | module MODULE1 (
VAR10 ,
VAR11 ,
VAR5,
VAR7,
VAR4,
VAR3 ,
VAR8
);
output VAR10 ;
input VAR11 ;
input VAR5;
input VAR7;
input VAR4;
input VAR3 ;
input VAR8 ;
wire VAR2 ;
wire VAR12;
VAR9 VAR6 (VAR2 , VAR11, VAR7, VAR4 );
VAR9 VAR13 (VAR12, VAR5, VAR7, VAR4 );
notif0 VAR1 (VAR10 , VAR2, VAR12);
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_solo/nios_solo/synthesis/submodules/nios_solo_mm_interconnect_0_avalon_st_adapter.v | 6,152 | module MODULE1 #(
parameter VAR23 = 10,
parameter VAR11 = 0,
parameter VAR25 = 10,
parameter VAR16 = 0,
parameter VAR5 = 0,
parameter VAR21 = 0,
parameter VAR24 = 1,
parameter VAR3 = 1,
parameter VAR20 = 0,
parameter VAR7 = 10,
parameter VAR18 = 0,
parameter VAR12 = 1,
parameter VAR19 = 0,
parameter VAR2 = 1,
parameter... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/megafunctions/cpci_pci2net_16x60_bb.v | 6,045 | module MODULE1 (
VAR6,
VAR2,
VAR4,
VAR8,
VAR3,
VAR5,
VAR9,
VAR1,
VAR7,
VAR10);
input VAR6;
input VAR2;
input [59:0] VAR4;
input VAR8;
input VAR3;
output VAR5;
output VAR9;
output VAR1;
output [59:0] VAR7;
output [3:0] VAR10;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtn/sky130_fd_sc_lp__dfrtn.blackbox.v | 1,371 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR6 ,
VAR4
);
output VAR5 ;
input VAR7 ;
input VAR6 ;
input VAR4;
supply1 VAR2;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvn/sky130_fd_sc_ms__einvn.behavioral.v | 1,314 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR5
);
output VAR3 ;
input VAR8 ;
input VAR5;
supply1 VAR2;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR7 ;
notif0 VAR1 (VAR3 , VAR8, VAR5 );
endmodule | apache-2.0 |
gtaylormb/fpga_nes | hw/src/cpu/jp.v | 6,033 | module MODULE1
(
input wire clk, input wire rst, input wire wr, input wire [15:0] addr, input wire din, input wire VAR22, input wire VAR14, output wire VAR10, output wire VAR15, output reg [ 7:0] dout );
reg [7:0] VAR11, VAR19;
reg [7:0] VAR8, VAR18;
reg VAR21, VAR9;
reg VAR4, VAR24;
reg [8:0] VAR3, VAR6;
always @(pose... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_4.behavioral.pp.v | 1,868 | module MODULE1( VAR2, VAR1, VAR8, VAR4, VAR6, VAR7, VAR10 );
input VAR8, VAR1, VAR4, VAR6;
inout VAR7, VAR10;
output VAR2;
VAR3 VAR9(.VAR2(VAR2),.VAR1(VAR1),.VAR8(VAR8),.VAR4(VAR4),.VAR6(VAR6),.VAR7(VAR7),.VAR10(VAR10));
VAR3 VAR5(.VAR2(VAR2),.VAR1(VAR1),.VAR8(VAR8),.VAR4(VAR4),.VAR6(VAR6),.VAR7(VAR7),.VAR10(VAR10)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4bb/sky130_fd_sc_hd__nand4bb_4.v | 2,334 | module MODULE2 (
VAR1 ,
VAR7 ,
VAR2 ,
VAR9 ,
VAR5 ,
VAR8,
VAR6,
VAR11 ,
VAR3
);
output VAR1 ;
input VAR7 ;
input VAR2 ;
input VAR9 ;
input VAR5 ;
input VAR8;
input VAR6;
input VAR11 ;
input VAR3 ;
VAR10 VAR4 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.v | 2,334 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR7 ,
VAR5 ,
VAR8 ,
VAR10,
VAR6,
VAR1 ,
VAR4
);
output VAR9 ;
input VAR2 ;
input VAR7 ;
input VAR5 ;
input VAR8 ;
input VAR10;
input VAR6;
input VAR1 ;
input VAR4 ;
VAR3 VAR11 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR... | apache-2.0 |
secworks/chacha | src/rtl/chacha_core.v | 21,132 | module MODULE1(
input wire clk,
input wire VAR37,
input wire VAR94,
input wire VAR122,
input wire [255 : 0] VAR59,
input wire VAR86,
input wire [63 : 0] VAR22,
input wire [63 : 0] VAR128,
input wire [4 : 0] VAR41,
input wire [511 : 0] VAR95,
output wire ready,
output wire [511 : 0] VAR110,
output wire VAR75
);
localpar... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_1.behavioral.pp.v | 1,164 | module MODULE1( VAR5, VAR1, VAR7, VAR6 );
input VAR5;
inout VAR7, VAR6;
output VAR1;
VAR3 VAR2(.VAR5(VAR5),.VAR1(VAR1),.VAR7(VAR7),.VAR6(VAR6));
VAR3 VAR4(.VAR5(VAR5),.VAR1(VAR1),.VAR7(VAR7),.VAR6(VAR6)); | apache-2.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_random.v | 5,962 | module MODULE1 (VAR2, VAR12, VAR11, VAR13, VAR5, VAR9, VAR7,
VAR3, VAR1);
parameter VAR14 = 1;
input VAR2;
input VAR12;
input VAR11;
input VAR13;
input [3:0] VAR5;
input [15:0] VAR9;
input [9:0] VAR7;
output VAR3;
output VAR1;
wire VAR6;
reg [9:0] VAR4;
wire [9:0] VAR10;
reg [9:0] VAR8;
always @ (posedge VAR2 or posedg... | gpl-2.0 |
Narekmouse/Counter7SD | src/counter.v | 3,711 | module MODULE1(
VAR7,
reset,
VAR16,
VAR6,
VAR12
);
input VAR7;
input reset;
input VAR16;
input VAR6;
output reg [6:0] VAR12;
reg [6:0] VAR4;
parameter VAR11 = 7'b1111110; parameter VAR14 = 7'b0110000; parameter VAR13 = 7'b1101101; parameter VAR2 = 7'b1101101; parameter VAR1 = 7'b0110011; parameter VAR8 = 7'b1011011; pa... | gpl-3.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/acl_barrier.v | 7,178 | module MODULE1 (
VAR27,
VAR9,
VAR22,
VAR11,
VAR8,
VAR24,
VAR3,
VAR34,
VAR10
);
parameter VAR37=1024;
parameter VAR17=256; parameter VAR33=2; parameter VAR28 = 10;
localparam VAR4=VAR6(VAR33);
localparam VAR36 = VAR4 > 0 ? VAR4 : 1;
input VAR27;
input VAR9;
input VAR22;
input [VAR37-1:0] VAR11;
output VAR8;
output VAR24... | mit |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/riffa/reorder_queue_output.v | 10,557 | module MODULE1 #(
parameter VAR44 = 9'd128,
parameter VAR36 = 4'd12,
parameter VAR13 = 5, parameter VAR10 = 8, parameter VAR6 = 5, parameter VAR23 = 10, parameter VAR12 = VAR44/32,
parameter VAR28 = VAR30(VAR12),
parameter VAR3 = VAR30(VAR12+1),
parameter VAR1 = 2**VAR13
)
(
input VAR31, input VAR52, output [VAR23-1:0]... | mit |
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