repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32ai/sky130_fd_sc_ms__o32ai.functional.v | 1,547 | module MODULE1 (
VAR13 ,
VAR5,
VAR3,
VAR4,
VAR12,
VAR11
);
output VAR13 ;
input VAR5;
input VAR3;
input VAR4;
input VAR12;
input VAR11;
wire VAR2 ;
wire VAR10 ;
wire VAR1;
nor VAR9 (VAR2 , VAR4, VAR5, VAR3 );
nor VAR6 (VAR10 , VAR12, VAR11 );
or VAR8 (VAR1, VAR10, VAR2);
buf VAR7 (VAR13 , VAR1 );
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/neek/rtl/verilog/clkgen.v | 3,555 | module MODULE1
(
input VAR22,
input VAR3,
input VAR2,
output VAR20,
output VAR15,
output VAR16,
output VAR18,
output VAR7,
output VAR9
);
wire VAR17;
wire VAR6;
assign VAR6 = VAR3;
assign VAR17 = ~VAR6;
assign VAR20 = ~VAR6;
wire VAR23;
wire VAR13;
VAR21 VAR10 (
.VAR19 (VAR17),
.VAR11 (VAR22),
.VAR5 (VAR15),
.VAR1 (VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32o/sky130_fd_sc_lp__a32o_2.v | 2,469 | module MODULE1 (
VAR12 ,
VAR11 ,
VAR2 ,
VAR9 ,
VAR4 ,
VAR6 ,
VAR5,
VAR7,
VAR10 ,
VAR3
);
output VAR12 ;
input VAR11 ;
input VAR2 ;
input VAR9 ;
input VAR4 ;
input VAR6 ;
input VAR5;
input VAR7;
input VAR10 ;
input VAR3 ;
VAR1 VAR8 (
.VAR12(VAR12),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5... | apache-2.0 |
wyvernSemi/lm32fpga | HDL/rtl/wb_mux.v | 4,542 | module MODULE1 (VAR18,
VAR27,
VAR15,
VAR11,
VAR22,
VAR24,
VAR16,
VAR3,
VAR4,
VAR20,
VAR9,
VAR17,
VAR10,
VAR21,
VAR29,
VAR28,
VAR25,
VAR14,
VAR2,
VAR5,
VAR26,
VAR6,
VAR13,
VAR1,
VAR12,
VAR19
);
input VAR18;
input VAR27;
input VAR15;
input VAR11;
input VAR22;
input [3:0] VAR24;
input [31:0] VAR3;
input [31:0] VAR4; outpu... | gpl-3.0 |
Team-Jared/tera-computer | src/arithmetic.v | 3,288 | module MODULE2 (VAR1, VAR6);
output [7:0] VAR1;
input [7:0] VAR6;
assign VAR1 = VAR6 + 1;
endmodule
module MODULE1 (VAR8, VAR9, word, VAR5, VAR2, VAR3);
output [7:0] VAR8;
output VAR9;
input [7:0] word, VAR5, VAR2;
input VAR3;
reg [7:0] VAR12;
reg VAR10, VAR4;
reg [6:0] VAR11;
assign VAR8 = VAR12;
assign VAR9 = VAR10;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlclkp/sky130_fd_sc_ls__dlclkp_4.v | 2,154 | module MODULE1 (
VAR8,
VAR5,
VAR2 ,
VAR4,
VAR7,
VAR1 ,
VAR9
);
output VAR8;
input VAR5;
input VAR2 ;
input VAR4;
input VAR7;
input VAR1 ;
input VAR9 ;
VAR3 VAR6 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR8,
VAR5,
VAR2
);
output VAR8;
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2/sky130_fd_sc_lp__nand2.functional.v | 1,270 | module MODULE1 (
VAR3,
VAR2,
VAR1
);
output VAR3;
input VAR2;
input VAR1;
wire VAR5;
nand VAR4 (VAR5, VAR1, VAR2 );
buf VAR6 (VAR3 , VAR5 );
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0/bd_0/ip/ip_11/synth/bd_350b_slot_2_r_0.v | 4,588 | module MODULE1 (
VAR56,
VAR40,
VAR39,
dout
);
input wire [0 : 0] VAR56;
input wire [0 : 0] VAR40;
input wire [0 : 0] VAR39;
output wire [2 : 0] dout;
VAR64 #(
.VAR68(1),
.VAR50(1),
.VAR14(1),
.VAR28(1),
.VAR24(1),
.VAR5(1),
.VAR43(1),
.VAR16(1),
.VAR46(1),
.VAR49(1),
.VAR6(1),
.VAR12(1),
.VAR21(1),
.VAR31(1),
.VAR41(1)... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_4.functional.v | 1,676 | module MODULE1( VAR6, VAR21, VAR1, VAR5, VAR20, VAR9 );
input VAR20, VAR9, VAR21, VAR1, VAR5;
output VAR6;
wire VAR14;
not VAR17( VAR14, VAR20 );
wire VAR4;
not VAR15( VAR4, VAR9 );
wire VAR13;
and VAR3( VAR13, VAR14, VAR4 );
wire VAR18;
not VAR10( VAR18, VAR21 );
wire VAR8;
not VAR11( VAR8, VAR1 );
wire VAR16;
and VAR... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/user_logic.v | 7,481 | module MODULE1 (
VAR22,
VAR25,
VAR16,
VAR11,
VAR5,
VAR26,
VAR28,
VAR53,
VAR41,
VAR58,
VAR9,
VAR40,
VAR48,
VAR46,
VAR50,
VAR2,
VAR8,
VAR23,
VAR37,
VAR49,
VAR20,
VAR56,
VAR15,
VAR17,
VAR31,
VAR13,
VAR19,
VAR38,
VAR43);
parameter VAR27 = 32;
parameter VAR52 = 32;
input VAR22;
output VAR25;
output VAR16;
output VAR11;
outp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2b/sky130_fd_sc_hd__nand2b.behavioral.pp.v | 1,936 | module MODULE1 (
VAR7 ,
VAR11 ,
VAR13 ,
VAR6,
VAR1,
VAR12 ,
VAR2
);
output VAR7 ;
input VAR11 ;
input VAR13 ;
input VAR6;
input VAR1;
input VAR12 ;
input VAR2 ;
wire VAR4 ;
wire VAR5 ;
wire VAR8;
not VAR14 (VAR4 , VAR13 );
or VAR10 (VAR5 , VAR4, VAR11 );
VAR3 VAR15 (VAR8, VAR5, VAR6, VAR1);
buf VAR9 (VAR7 , VAR8 );
end... | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_custom_add.v | 1,572 | module MODULE1(VAR15, enable, VAR7, VAR13, VAR8, VAR14);
input VAR15, enable, VAR7;
input [31:0] VAR13;
input [31:0] VAR8;
output [31:0] VAR14;
VAR17 VAR3(
.VAR15(VAR15),
.VAR7(VAR7),
.VAR13(VAR13),
.VAR8(VAR8),
.VAR14(VAR14),
.VAR1(),
.VAR2(),
.VAR11(),
.VAR12(),
.enable(enable));
endmodule | mit |
rkrajnc/minimig-mist | bench/cpu_cache_sdram/tg68_ram.v | 1,472 | module MODULE1 #(
parameter VAR7 = 512
)(
input wire clk,
input wire VAR8,
input wire [ 32-1:0] VAR9,
input wire VAR13,
input wire VAR4,
input wire VAR1,
input wire [ 16-1:0] VAR2,
output wire [ 16-1:0] VAR6,
output wire VAR3
);
reg [8-1:0] VAR5 [0:VAR7-1];
reg [8-1:0] VAR11 [0:VAR7-1];
reg [16-1:0] VAR14 = 0;
reg VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfsbp/sky130_fd_sc_hs__sdfsbp.pp.symbol.v | 1,488 | module MODULE1 (
input VAR5 ,
output VAR2 ,
output VAR9 ,
input VAR8,
input VAR7 ,
input VAR3 ,
input VAR1 ,
input VAR4 ,
input VAR6
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.behavioral.pp.v | 1,561 | module MODULE1( VAR1, VAR7, VAR2, VAR8, VAR9, VAR5 );
input VAR2, VAR1, VAR8;
inout VAR9, VAR5;
output VAR7;
VAR3 VAR6(.VAR1(VAR1),.VAR7(VAR7),.VAR2(VAR2),.VAR8(VAR8),.VAR9(VAR9),.VAR5(VAR5));
VAR3 VAR4(.VAR1(VAR1),.VAR7(VAR7),.VAR2(VAR2),.VAR8(VAR8),.VAR9(VAR9),.VAR5(VAR5)); | apache-2.0 |
twlostow/dsi-shield | hdl/rtl/hpdmc/hpdmc_banktimer.v | 1,549 | module MODULE1(
input VAR4,
input VAR2,
input VAR1,
input [1:0] VAR5,
input read,
input write,
output reg VAR3
);
reg [2:0] counter;
always @(posedge VAR4) begin
if(VAR2) begin
counter <= 3'd0;
VAR3 <= 1'b1;
end else begin
if(read) begin
counter <= 3'd4;
VAR3 <= 1'b0;
end else if(write) begin
counter <= {1'b1, VAR5};
V... | lgpl-3.0 |
cpulabs/gci-std-display | rtl/display_controller/gci_std_display_device_special_memory.v | 1,227 | module MODULE1
parameter VAR5 = 32'h00000000,
parameter VAR7 = 32'h00000000,
parameter VAR6 = 32'h00000000
)(
input wire VAR12,
input wire VAR4,
input wire VAR3,
input wire VAR8,
input wire [7:0] VAR9,
input wire [31:0] VAR11,
output wire [31:0] VAR2
);
integer VAR1;
reg [31:0] VAR10[0:255];
always@(posedge VAR12 or ne... | bsd-2-clause |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_3/ff169405/src/d_serial_m_lfs_XOR.v | 3,008 | module MODULE1
(
input wire VAR2,
input wire [VAR7-1:0] VAR1,
output wire [VAR7-1:0] VAR5
);
parameter [0:168] VAR4 = 169'b1100011001001101001001011010010000001010100100010101010000111100111110110010110000100000001101100011000011111011010100011001110110100011110100100001001101010100010111001;
wire VAR8;
assign VAR8 = V... | gpl-3.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/sfp/triple_speed_ethernet-library/altera_tse_rgmii_module.v | 7,352 | module MODULE1 ( VAR2,
VAR41,
VAR54,
VAR20,
VAR31,
VAR5,
VAR3,
VAR49,
VAR44,
VAR33,
VAR21,
VAR39,
VAR17,
VAR42,
VAR28,
VAR37,
VAR53,
VAR35,
VAR29,
VAR36,
VAR27,
VAR9,
VAR48
)
;
output [ 3: 0] VAR42;
output [ 7: 0] VAR28;
output [ 3: 0] VAR37;
output VAR53;
output VAR35;
output VAR29;
output VAR36;
output VAR27;
output ... | apache-2.0 |
anderson1008/NOCulator | hring/hw/bless_mc/rcUC.v | 2,522 | module MODULE1(
VAR3,
VAR20
);
input [VAR10-1:0] VAR3;
output [VAR19-1:0] VAR20;
wire [2:0] VAR15, VAR16;
assign VAR15 = VAR3[VAR5];
assign VAR16 = VAR3[VAR8];
assign VAR20 [1] = VAR15 > VAR11;
assign VAR20 [3] = VAR15 < VAR11;
assign VAR20 [0] = (VAR16 > VAR18) && ~VAR20 [1] && ~VAR20 [3];
assign VAR20 [2] = (VAR16 < ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4bb/sky130_fd_sc_ls__and4bb_1.v | 2,323 | module MODULE2 (
VAR6 ,
VAR9 ,
VAR5 ,
VAR7 ,
VAR4 ,
VAR2,
VAR8,
VAR1 ,
VAR11
);
output VAR6 ;
input VAR9 ;
input VAR5 ;
input VAR7 ;
input VAR4 ;
input VAR2;
input VAR8;
input VAR1 ;
input VAR11 ;
VAR10 VAR3 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR11... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/ebufn/sky130_fd_sc_hdll__ebufn.blackbox.v | 1,286 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR3;
supply1 VAR5;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/in_switch.v | 18,617 | module MODULE1(
input clk,
input reset,
output [239:0] VAR79,
input [63:0] VAR3,
input [23:0] VAR29,
input VAR68,
input VAR124,
output reg VAR88,
input VAR33,
input [63:0] VAR39,
input [23:0] VAR118,
input VAR80,
input VAR19,
output reg VAR2,
input VAR6,
input [63:0] VAR114,
input [23:0] VAR87,
input VAR4,
input VAR103... | mit |
amrmorsey/Digital-Design-Project | sbox3.v | 3,546 | module MODULE1(
VAR2,
VAR1
);
input [6:1] VAR2;
output reg [4:1] VAR1;
wire [6:1] VAR3;
assign VAR3 = {VAR2[6], VAR2[1], VAR2[5 : 2]};
always @(VAR3)
begin
case (VAR3)
6'b000000: VAR1 <= 4'd10;
6'b000001: VAR1 <= 4'd0;
6'b000010: VAR1 <= 4'd9;
6'b000011: VAR1 <= 4'd14;
6'b000100: VAR1 <= 4'd6;
6'b000101: VAR1 <= 4'd3;
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor3/sky130_fd_sc_hdll__xnor3_4.v | 2,200 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR10 ,
VAR4 ,
VAR2,
VAR7,
VAR5 ,
VAR9
);
output VAR6 ;
input VAR1 ;
input VAR10 ;
input VAR4 ;
input VAR2;
input VAR7;
input VAR5 ;
input VAR9 ;
VAR3 VAR8 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
lsnow/mips32 | MEM_stage.v | 1,621 | module MODULE1(
clk, rst, VAR5, VAR10, VAR4, VAR1,
VAR13, VAR6, VAR11, VAR7,
VAR8, VAR12, VAR3, VAR9,VAR2);
input clk;
input rst;
input VAR5;
input VAR10;
input VAR4;
input VAR1;
input VAR13;
input [31:0] VAR6;
input [31:0] VAR7;
input [4:0] VAR11;
output reg VAR8;
output reg VAR12;
output reg [31:0] VAR2;
output reg [... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_36to18.v | 5,310 | module MODULE1(
rst,
VAR99,
VAR82,
din,
VAR29,
VAR58,
dout,
VAR43,
VAR53);
input rst;
input VAR99;
input VAR82;
input [35 : 0] din;
input VAR29;
input VAR58;
output [17 : 0] dout;
output VAR43;
output VAR53;
VAR36 #(
.VAR27(0),
.VAR12(0),
.VAR14(9),
.VAR94("VAR22"),
.VAR7(36),
.VAR57("0"),
.VAR1(18),
.VAR3(0),
.VAR15(1... | gpl-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/05MicroSD/Version_02/02 verilog/periferico_SD/peripheral_SD.v | 1,793 | module MODULE1(clk , reset , din , VAR10 , addr , rd , wr, dout, VAR7, VAR3, VAR8, VAR4 );
input clk;
input rst;
input [15:0]din;
input VAR10;
input [3:0]addr; input rd;
input wr;
output reg [15:0]dout;
input reset;
output VAR7;
input VAR8;
output VAR3;
output VAR4;
reg [5:0] VAR1;
reg [15:0] VAR11=0;reg enable=0;
wire... | gpl-3.0 |
cfangmeier/VFPIX-telescope-Code | utils/apc128_pattern_generator/step_curve_sub.v | 25,708 | module MODULE1
(
input clk,
input [15:0]VAR21,
output reg VAR17,
output VAR5,
output VAR16,
output VAR24,
output reg VAR27,
output reg VAR25,
output reg VAR13,
output reg VAR22,
output reg VAR12,
output reg VAR7,
output reg VAR2,
output reg VAR26,
output reg VAR10,
output reg VAR11,
output VAR20,
output [15:0]VAR8,
out... | gpl-2.0 |
bobnewgard/fcs | ver/uut_1_bytep.v | 2,369 | module MODULE1
(
output wire [31:0] VAR7,
output wire VAR5,
input wire [7:0] VAR12,
input wire VAR1,
input wire VAR8
);
reg [7:0] VAR3;
reg VAR11;
reg [7:0] VAR10;
reg VAR13;
reg [7:0] VAR4;
reg VAR2;
reg [7:0] VAR9;
reg VAR6;
always @ (posedge VAR8) begin
VAR3[7:0] <= VAR12[7:0];
VAR11 <= VAR1;
VAR10[7:0] <= VAR3[7:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2/sky130_fd_sc_lp__nand2_8.v | 2,097 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR3 ,
VAR6,
VAR1,
VAR7 ,
VAR4
);
output VAR5 ;
input VAR9 ;
input VAR3 ;
input VAR6;
input VAR1;
input VAR7 ;
input VAR4 ;
VAR2 VAR8 (
.VAR5(VAR5),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR5,
VAR9,
VAR3
);
output VAR5;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbn/sky130_fd_sc_ms__dlxbn.pp.symbol.v | 1,368 | module MODULE1 (
input VAR3 ,
output VAR6 ,
output VAR2 ,
input VAR1,
input VAR7 ,
input VAR5 ,
input VAR4 ,
input VAR8
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_dp_macb_r.v | 4,614 | module MODULE1(
VAR3, VAR27, VAR12,
VAR35, VAR19, VAR29,
VAR21, VAR5, VAR9,
VAR30, VAR10, VAR8, VAR32
);
output [129:0] VAR3; output VAR27;
output VAR12;
input VAR35; input VAR19; input VAR29; input VAR21; input VAR5;
input [129:0] VAR9; input [129:0] VAR30;
input VAR10;
input VAR8;
input VAR32;
wire VAR1;
wire [129:0]... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtn/sky130_fd_sc_ls__sdfrtn.behavioral.v | 2,952 | module MODULE1 (
VAR33 ,
VAR2 ,
VAR31 ,
VAR7 ,
VAR20 ,
VAR26
);
output VAR33 ;
input VAR2 ;
input VAR31 ;
input VAR7 ;
input VAR20 ;
input VAR26;
supply1 VAR19;
supply0 VAR4;
supply1 VAR12 ;
supply0 VAR3 ;
wire VAR32 ;
wire VAR9 ;
wire VAR6 ;
wire VAR18 ;
reg VAR30 ;
wire VAR5 ;
wire VAR10 ;
wire VAR17 ;
wire VAR13;
wi... | apache-2.0 |
parallella/oh | spi/hdl/spi_master_regs.v | 7,103 | module MODULE1 # (parameter VAR59 = 1, parameter VAR12 = 32, parameter VAR14 = 104 )
(
input clk, input VAR42, input VAR5, input [63:0] VAR29, input VAR27, output VAR23, output VAR49, output VAR41, output VAR57, output VAR8, output VAR58, output reg [7:0] VAR60, input [2:0] VAR32, input VAR39, input VAR33, input VAR2, ... | mit |
SeanZarzycki/openSPARC-FPU | project/src/fpu_mul.v | 18,286 | module MODULE1 (
VAR14,
VAR8,
VAR45,
VAR41,
VAR48,
VAR119,
VAR101,
VAR52,
VAR69,
VAR42,
VAR51,
VAR102,
VAR46,
VAR34,
VAR11,
VAR61,
VAR62,
VAR50,
VAR28,
VAR74,
VAR6,
VAR31,
VAR90,
VAR19,
VAR127,
VAR83,
VAR22,
VAR82,
VAR25,
VAR65,
VAR78,
VAR97,
VAR113,
VAR123,
VAR40,
VAR108,
VAR95
);
input [7:0] VAR14; input [1:0] VAR8; ... | gpl-3.0 |
jairov4/accel-oil | solution_spartan6/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/verilog/sample_iterator_next.v | 25,557 | module MODULE1 (
VAR52,
VAR92,
VAR13,
VAR3,
VAR117,
VAR31,
VAR110,
VAR58,
VAR78,
VAR42,
VAR87,
VAR118,
VAR115,
VAR111,
VAR19,
VAR127,
VAR48,
VAR41,
VAR114,
VAR51,
VAR128,
VAR26,
VAR69,
VAR119,
VAR100,
VAR83,
VAR96,
VAR129,
VAR6,
VAR75,
VAR93,
VAR10,
VAR18,
VAR132,
VAR104,
VAR49,
VAR66,
VAR112
);
input VAR52;
input VAR9... | lgpl-3.0 |
luebbers/reconos | support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/plb_tft_cntlr_ref_v1_00_c/hdl/verilog/dcr_if.v | 4,782 | module MODULE1(
clk, rst, VAR17, VAR3, VAR11, VAR9, VAR14, VAR6, VAR7, VAR2, VAR16 );
input clk;
input rst;
input [0:9] VAR17;
input [0:31] VAR3;
input VAR11;
input VAR9;
output VAR14;
output [0:31] VAR6;
output [0:10] VAR7;
output VAR2;
output VAR16;
wire [0:31] VAR6;
reg VAR14;
parameter VAR12 = 10'b0000000000;
param... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and2/sky130_fd_sc_hs__and2_4.v | 1,959 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR2 ,
VAR1,
VAR6
);
output VAR4 ;
input VAR3 ;
input VAR2 ;
input VAR1;
input VAR6;
VAR5 VAR7 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR4,
VAR3,
VAR2
);
output VAR4;
input VAR3;
input VAR2;
supply1 VAR1;
supply0 VAR6;
VAR5 VAR7 (
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso1p/sky130_fd_sc_hd__lpflow_inputiso1p.functional.pp.v | 1,769 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR2,
VAR8 ,
VAR3 ,
VAR1 ,
VAR5
);
output VAR7 ;
input VAR10 ;
input VAR2;
input VAR8 ;
input VAR3 ;
input VAR1 ;
input VAR5 ;
wire VAR9;
or VAR4 (VAR9, VAR10, VAR2 );
VAR6 VAR11 (VAR7 , VAR9, VAR8, VAR3);
endmodule | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/HDLNeuralNetwork/Registrodesplazamiento.v | 1,397 | module MODULE1 #(parameter VAR4 = 10)
(VAR15,reset,VAR1,VAR5,VAR8,VAR6,VAR9,VAR7,VAR14,VAR10,VAR11,VAR12,VAR3,VAR2);
input VAR15,reset,VAR1;
input signed [VAR4-1:0] VAR5;
output signed [VAR4-1:0] VAR8,VAR6,VAR9,VAR7,VAR14,VAR10,VAR11,VAR12,VAR3,VAR2;
reg [(VAR4*10)-1:0] VAR13 = 0;
always @(posedge VAR15) begin
if (rese... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111oi/sky130_fd_sc_hs__a2111oi.blackbox.v | 1,366 | module MODULE1 (
VAR3 ,
VAR1,
VAR6,
VAR4,
VAR8,
VAR2
);
output VAR3 ;
input VAR1;
input VAR6;
input VAR4;
input VAR8;
input VAR2;
supply1 VAR7;
supply0 VAR5;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/pb_pio.v | 1,834 | module MODULE1 (
address,
clk,
VAR2,
VAR1,
VAR5
)
;
output [ 31: 0] VAR5;
input [ 1: 0] address;
input clk;
input [ 3: 0] VAR2;
input VAR1;
wire VAR4;
wire [ 3: 0] VAR6;
wire [ 3: 0] VAR3;
reg [ 31: 0] VAR5;
assign VAR4 = 1;
assign VAR3 = {4 {(address == 0)}} & VAR6;
always @(posedge clk or negedge VAR1)
begin
if (VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21bai/sky130_fd_sc_hdll__o21bai_1.v | 2,345 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR7 ,
VAR9,
VAR3,
VAR8,
VAR2 ,
VAR4
);
output VAR1 ;
input VAR5 ;
input VAR7 ;
input VAR9;
input VAR3;
input VAR8;
input VAR2 ;
input VAR4 ;
VAR10 VAR6 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
V... | apache-2.0 |
wanahmadzainie/MELB1BKA | MEL1153/src/vm.v | 1,870 | module MODULE1(clk, rst, VAR4, VAR6, select, VAR32, VAR11, VAR1, VAR18,
VAR8, VAR24, VAR31, VAR22, VAR28, state);
input clk, rst;
input [9:0] VAR4, VAR11;
input [4:0] select;
input VAR6, VAR32, VAR1, VAR18;
output VAR8, VAR24, VAR31;
output [4:0] VAR22;
output [9:0] VAR28;
output [2:0] state;
wire VAR5, VAR19, VAR16, V... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0_0/synth/zynq_design_1_system_ila_0_0.v | 80,579 | module MODULE1 (
clk,
VAR14,
VAR8,
VAR19,
VAR7,
VAR2,
VAR17,
VAR1,
VAR15,
VAR10,
VAR11,
VAR6,
VAR18,
VAR13,
VAR20,
VAR4,
VAR16,
VAR9,
VAR12
);
input wire clk;
input wire [8 : 0] VAR14;
input wire VAR8;
input wire VAR19;
input wire [31 : 0] VAR7;
input wire [3 : 0] VAR2;
input wire VAR17;
input wire VAR1;
input wire [1 ... | mit |
mshr-h/fibonacci_verilog | fpga/mu500rx/displayik_7seg_16.v | 7,938 | module MODULE2
(
input wire VAR46,
input wire VAR50,
input wire [15:0] VAR6,
input wire [15:0] VAR2,
input wire [15:0] VAR7,
input wire [15:0] VAR27,
input wire [15:0] VAR4,
input wire [15:0] VAR40,
input wire [15:0] VAR41,
input wire [15:0] VAR38,
input wire [15:0] VAR31,
input wire [15:0] VAR33,
input wire [15:0] VAR... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_common/src/v/bsg_dff_reset_half.v | 1,433 | module MODULE1
(input VAR9
, input VAR3
, input [VAR10-1:0] VAR2
, output logic [VAR10-1:0] VAR1
, output logic [VAR10-1:0] VAR5
);
logic [VAR10-1:0] VAR7;
VAR8 @(posedge VAR9)
if (VAR3)
VAR7 <= '0;
else
VAR7 <= VAR2;
logic [VAR10-1:0] VAR4;
VAR8 @(negedge VAR9)
if (VAR3)
VAR4 <= '0;
else
VAR4 <= VAR7;
logic [VAR10-1:0... | bsd-3-clause |
monotone-RK/FACE | IEICE-Trans/4-way_2-tree/src/ip_pcie/source/PCIeGen2x8If128_rxeq_scan.v | 14,867 | module MODULE1 #
(
parameter VAR15 = "VAR9", parameter VAR39 = "VAR1", parameter VAR41 = 1, parameter VAR42 = 22'd3125000, parameter VAR3 = 22'd2083333 )
(
input VAR8,
input VAR18,
input [ 1:0] VAR4,
input [ 2:0] VAR24,
input VAR10,
input [ 3:0] VAR38,
input [17:0] VAR20,
input VAR28,
input [ 5:0] VAR6,
input [ 5:0] VA... | mit |
lucasrangit/Robertsons_Multiplier | robsmult.v | 7,754 | module MODULE1 #(parameter VAR5 = 8)
(
input clk,
input reset,
input [VAR5-1:0] VAR31,
input [VAR5-1:0] VAR14,
output [VAR5*2-1:0] VAR34, output VAR9 );
wire VAR1, VAR22, VAR16, VAR27, VAR3, VAR26, VAR13, VAR21, VAR18, VAR23, VAR4, VAR20, VAR33, VAR15, VAR6;
wire VAR28, VAR30, VAR17;
MODULE3 MODULE1(clk, reset, VAR28, ... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10-old/mmio_if/synthesis/submodules/mmio_if_hps_0.v | 7,936 | module MODULE1 #(
parameter VAR40 = 0,
parameter VAR17 = 0
) (
output wire VAR22, input wire VAR53, output wire [11:0] VAR25, output wire [20:0] VAR50, output wire [3:0] VAR54, output wire [2:0] VAR9, output wire [1:0] VAR32, output wire [1:0] VAR52, output wire [3:0] VAR36, output wire [2:0] VAR24, output wire VAR11, ... | gpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_02/MicrofonoFIFO/fifo.v | 3,511 | module MODULE1(VAR18,VAR28,VAR8,VAR19,VAR29,VAR27, VAR23,VAR1,VAR13,VAR17,VAR12,VAR4);
input VAR18; input VAR28; input [(VAR16-1):0] VAR8; input VAR19; input VAR29; input VAR27;
output [(VAR16-1):0] VAR23; output VAR1; output VAR13; output VAR17; output VAR4; output VAR12; reg VAR1;
reg VAR4;
reg VAR13;
reg VAR17;
reg ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41a/sky130_fd_sc_hs__o41a_2.v | 2,284 | module MODULE2 (
VAR7 ,
VAR1 ,
VAR3 ,
VAR4 ,
VAR2 ,
VAR5 ,
VAR9,
VAR6
);
output VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR4 ;
input VAR2 ;
input VAR5 ;
input VAR9;
input VAR6;
VAR10 VAR8 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE2 ... | apache-2.0 |
ridecore/ridecore | src/fpga/rs_reqgen.v | 1,359 | module MODULE1
(
input wire [VAR18-1:0] VAR4,
input wire [VAR18-1:0] VAR2,
output wire VAR17,
output wire VAR13,
output wire [1:0] VAR7,
output wire VAR6,
output wire VAR14,
output wire [1:0] VAR5,
output wire VAR9,
output wire VAR11,
output wire [1:0] VAR1,
output wire VAR20,
output wire VAR3,
output wire [1:0] VAR10
... | bsd-3-clause |
spesialstyrker/boula | gen/PCIe/source/pcie_bram_top_v6.v | 5,909 | module MODULE1
parameter VAR25 = 0,
parameter VAR14 = 31,
parameter VAR31 = 24,
parameter VAR6 = 1,
parameter VAR12 = 2,
parameter VAR2 = 1,
parameter VAR21 = 'h1FFF,
parameter VAR22 = 1,
parameter VAR19 = 2,
parameter VAR28 = 1
)
(
input VAR11,
input VAR15,
input VAR27,
input [12:0] VAR23,
input [71:0] VAR10,
input VA... | gpl-2.0 |
Madh93/scpu | modules/stack.v | 1,729 | module MODULE1(VAR3, reset, VAR9, VAR5,
VAR7, VAR1, VAR4, VAR6);
inout [9:0] VAR3;
input VAR9, VAR5, reset;
output VAR1, VAR4, VAR6;
output [1:0] VAR7;
reg VAR1, VAR4, VAR6;
reg [1:0] VAR7;
reg [9:0] MODULE1 [3:0];
reg [9:0] VAR8;
wire [9:0] #(0) VAR3 = VAR8;
always @(posedge VAR9 or posedge VAR5 or posedge reset)
begi... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/mcm_0.v | 4,786 | module MODULE1(
clk,
rst,
VAR31,
VAR15,
VAR30,
VAR12,
VAR14,
o0,
o1,
o2,
o3
);
input clk;
input rst;
input VAR31;
input signed [18:0] VAR15;
input signed [18:0] VAR30;
input signed [18:0] VAR12;
input signed [18:0] VAR14;
output reg signed [27:0] o0;
output reg signed [27:0] o1;
output reg signed [27:0] o2;
output reg ... | gpl-3.0 |
red0bear/CRCAHB | rtl/crc_control_unit.v | 8,642 | module MODULE1
(
output reg [1:0] VAR38,
output VAR10,
output VAR19,
output VAR31,
output VAR6,
output VAR22,
output VAR7,
output VAR5,
output VAR2,
output VAR11,
input [1:0] VAR28,
input write,
input VAR33,
input clk,
input VAR4
);
localparam VAR9 = 2'b00;
localparam VAR3 = 2'b01;
localparam VAR35 = 2'b10;
localparam ... | gpl-3.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/cpu/cpu.v | 14,693 | module MODULE1 (
input wire clk,
input wire VAR20,
input wire reset,
input wire [VAR112] VAR36,
input wire VAR68,
input wire VAR30,
output wire VAR22,
output wire [VAR122] VAR115,
output wire VAR28,
output wire VAR113,
output wire [VAR112] VAR73,
input wire [VAR112] VAR114,
input wire VAR44,
input wire VAR81,
output wi... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/extramfifo/icon.v | 40,286 | module MODULE1 (
VAR36
);
inout [35 : 0] VAR36;
wire VAR45;
wire \VAR110/VAR140/VAR126.VAR162/VAR122 ;
wire \VAR110/VAR140/VAR116/VAR53 ;
wire \VAR110/VAR140/VAR116/VAR3 ;
wire \VAR110/VAR140/VAR167/VAR118 ;
wire \VAR110/VAR140/VAR104/VAR148 ;
wire \VAR110/VAR140/VAR104/VAR118 ;
wire \VAR110/VAR140/VAR104/VAR174 ;
wire... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab3/fir_prj/solution2/syn/verilog/fir_mul_32s_32s_3bkb.v | 1,298 | module MODULE2(clk, VAR9, VAR3, VAR13, VAR4);
input clk;
input VAR9;
input signed [32 - 1 : 0] VAR3; input signed [32 - 1 : 0] VAR13; output[32 - 1 : 0] VAR4;
reg signed [32 - 1 : 0] VAR4;
wire signed [32 - 1 : 0] VAR2;
assign VAR2 = (VAR3) * (VAR13);
always @ (posedge clk) begin
if (VAR9) begin
VAR4 <= VAR2;
end
end
e... | mit |
The-OpenROAD-Project/asap7 | asap7sc7p5t_28/Verilog/asap7sc7p5t_OA_SRAM_TT_201020.v | 197,703 | module MODULE1 (VAR8, VAR7, VAR5, VAR10, VAR1);
output VAR8;
input VAR7, VAR5, VAR10, VAR1;
wire VAR6, VAR2, VAR9;
wire VAR11, VAR3, VAR4;
not (VAR11, VAR1);
not (VAR9, VAR10);
and (VAR3, VAR9, VAR11);
not (VAR2, VAR5);
not (VAR6, VAR7);
and (VAR4, VAR6, VAR2, VAR11);
or (VAR8, VAR4, VAR3); | bsd-3-clause |
mda-ut/Tempest | fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/ADC_CTRL.v | 4,412 | module MODULE1 (
VAR4,
VAR7,
VAR17,
VAR11,
VAR14,
VAR22,
VAR16,
VAR8,
VAR23,
VAR9,
VAR3,
VAR15,
VAR6,
VAR20,
VAR2,
VAR13
);
input VAR4;
input VAR7;
input VAR17;
input VAR11;
output VAR14;
output VAR22;
output VAR16;
input VAR8;
output reg [11:0] VAR23;
output reg [11:0] VAR9;
output reg [11:0] VAR3;
output reg [11:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41ai/sky130_fd_sc_lp__o41ai.functional.pp.v | 2,059 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR1 ,
VAR10 ,
VAR17 ,
VAR4 ,
VAR3,
VAR12,
VAR6 ,
VAR15
);
output VAR9 ;
input VAR2 ;
input VAR1 ;
input VAR10 ;
input VAR17 ;
input VAR4 ;
input VAR3;
input VAR12;
input VAR6 ;
input VAR15 ;
wire VAR16 ;
wire VAR13 ;
wire VAR14;
or VAR5 (VAR16 , VAR17, VAR10, VAR1, VAR2 );
nand VAR8 (VAR... | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_maccontrol.v | 11,602 | module MODULE1 (VAR42, VAR31, VAR41, VAR37, VAR1, VAR32, VAR5, VAR39,
VAR48, VAR24, VAR9, VAR11, VAR52, VAR54, VAR27, VAR7,
VAR23, VAR30, VAR26, VAR25, VAR50, VAR49,
VAR22, VAR51, VAR53, VAR3, VAR15, VAR17, VAR13, VAR28,
VAR33, VAR4, VAR45, VAR12, VAR16,
VAR36, VAR38, VAR56, VAR18, VAR19
);
input VAR42; input VAR31; in... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/example_design/PIO_TO_CTRL.v | 3,605 | module MODULE1 #(
parameter VAR2 = 1
) (
input clk,
input VAR5,
input VAR4,
input VAR1,
input VAR3,
output reg VAR7
);
reg VAR6;
always @ ( posedge clk ) begin
if (!VAR5 )
begin
end
else
begin
if (!VAR6 && VAR4)
end
else if (VAR1)
end
end
always @ ( posedge clk ) begin
if (!VAR5 )
begin
end
else
begin
if ( VAR3 && !VAR... | lgpl-3.0 |
Marcoslz22/Tercer_Proyecto | Decodificador_VGA.v | 10,971 | module MODULE1(
input clk,
input [7:0] VAR1,
input [7:0] VAR3,
input [7:0] VAR5,
output reg [7:0] VAR4,
output reg [7:0] VAR6,
output reg [7:0] VAR2
);
always @(posedge clk)
begin
case (VAR1)
8'd00: VAR4 = 8'b00000000;
8'd01: VAR4 = 8'b00000001;
8'd02: VAR4 = 8'b00000010;
8'd03: VAR4 = 8'b00000011;
8'd04: VAR4 = 8'b000... | mit |
ultraembedded/altor32 | rtl/cpu/altor32_exec.v | 48,602 | module MODULE1
(
input VAR252 ,
input VAR67 ,
input VAR279 ,
input VAR266 ,
output reg VAR70 ,
output reg VAR278 ,
output reg VAR80 ,
output reg VAR31 ,
output VAR88 ,
output [31:0] VAR262 ,
output VAR226 ,
input [31:0] VAR260 ,
input [31:0] VAR185 ,
input VAR251 ,
input [4:0] VAR149 ,
input [31:0] VAR215 ,
input [4:0]... | lgpl-3.0 |
olajep/oh | src/adi/hdl/library/util_axis_fifo/address_sync.v | 3,331 | module MODULE1 #(
parameter VAR11 = 4
) (
input clk,
input VAR9,
input VAR4,
output reg VAR2,
output reg [VAR11-1:0] VAR12,
output [VAR11:0] VAR5,
output reg VAR6,
input VAR8,
output reg VAR10,
output reg [VAR11-1:0] VAR3,
output [VAR11:0] VAR7
);
localparam VAR15 = {1'b1,{VAR11{1'b0}}};
reg [VAR11:0] VAR1 = VAR15;
reg... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/bw_clk_cl_ccx_cmp.v | 2,619 | module MODULE1(VAR16 ,VAR7 ,VAR12 ,VAR8 ,VAR9 ,
VAR10,VAR4 ,VAR20 ,VAR2, VAR11,VAR21 ,VAR15 ,VAR5 ,
VAR14 );
output VAR16 ;
input VAR7 ;
input VAR12 ;
input [1:0] VAR8 ;
input VAR20 ;
output VAR9 ;
output VAR10 ;
output VAR4 ;
input VAR2 ;
input VAR11 ;
input VAR21 ;
input VAR15 ;
input VAR5 ;
input VAR14 ;
wire VAR3 ;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.blackbox.v | 1,437 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR3 ,
VAR7 ,
VAR1,
VAR5 ,
VAR4
);
output VAR6 ;
input VAR2 ;
input VAR3 ;
input VAR7 ;
input VAR1;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
bgelb/digilite_zl | rtl/zl_sys_pll.v | 3,513 | module MODULE1
(
input VAR33,
input VAR93,
output VAR111,
output VAR100,
output VAR108
);
wire [4:0] VAR67;
assign VAR111 = VAR67[0];
assign VAR100 = VAR67[1];
VAR89 #
(
.VAR32("VAR107"),
.VAR26(1),
.VAR17(50),
.VAR65(1),
.VAR46("0"),
.VAR22(25),
.VAR34(50),
.VAR98(2),
.VAR82("0"),
.VAR75("VAR27"),
.VAR20(20000),
.VAR6... | bsd-2-clause |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/cpu_0_mult_cell.v | 6,198 | module MODULE1 (
VAR52,
VAR32,
clk,
VAR12,
VAR10
)
;
output [ 31: 0] VAR10;
input [ 31: 0] VAR52;
input [ 31: 0] VAR32;
input clk;
input VAR12;
wire [ 31: 0] VAR10;
wire [ 31: 0] VAR35;
wire [ 15: 0] VAR40;
wire VAR17;
assign VAR17 = ~VAR12;
VAR42 VAR11
(
.VAR41 (VAR17),
.VAR31 (clk),
.VAR13 (VAR52[15 : 0]),
.VAR3 (VAR... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_solo/nios_solo/synthesis/nios_solo.v | 35,998 | module MODULE1 (
input wire VAR170, input wire VAR19, input wire VAR176, input wire [7:0] VAR67, output wire VAR29, output wire [7:0] VAR51, output wire VAR70, output wire [19:0] VAR77, input wire VAR114, input wire VAR76, input wire [7:0] VAR148, output wire VAR79, output wire [7:0] VAR156, output wire VAR72, output w... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkinv/sky130_fd_sc_hs__clkinv.blackbox.v | 1,194 | module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
supply1 VAR3;
supply0 VAR4;
endmodule | apache-2.0 |
neale/CS-program | 474-VLSI/Lab_6/db/sclk_altpll.v | 4,519 | module MODULE1
(
VAR1,
clk,
VAR3,
VAR4) ;
input VAR1;
output [4:0] clk;
input [1:0] VAR3;
output VAR4;
tri0 VAR1;
tri0 [1:0] VAR3;
reg VAR7;
wire [4:0] VAR2;
wire VAR6;
wire VAR5; | unlicense |
rkrajnc/minimig-de1 | rtl/or1200/or1200_ic_top.v | 8,092 | module MODULE1(
clk, rst,
VAR72, VAR26, VAR45, VAR22, VAR58, VAR21, VAR13,
VAR37, VAR2, VAR4,
VAR19,
VAR23, VAR62, VAR46,
VAR12, VAR5,
VAR44, VAR9, VAR67, VAR33, VAR40,
VAR20, VAR18, VAR11,
VAR1, VAR48, VAR51
);
parameter VAR59 = VAR38;
input clk;
input rst;
output [VAR59-1:0] VAR72;
output [31:0] VAR26;
output VAR45;
... | gpl-3.0 |
olgirard/openmsp430 | fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v | 37,512 | module MODULE1 (
VAR46, VAR71, VAR58, VAR48, VAR22, VAR24, VAR68, VAR35, VAR156, VAR75, VAR74, VAR148, VAR99, VAR101, VAR123, VAR77, VAR175, VAR17, VAR6, VAR43, VAR174, VAR2, VAR95, VAR160, VAR41, VAR45, VAR28, VAR98, VAR136,
VAR47, VAR9, VAR54, VAR134, VAR171, VAR32, VAR114, VAR8, VAR7, irq, VAR109, VAR31, VAR27, VAR9... | bsd-3-clause |
alexforencich/verilog-ethernet | example/VCU118/fpga_25g/rtl/fpga.v | 35,496 | module MODULE1 (
input wire VAR274,
input wire VAR388,
input wire reset,
input wire VAR85,
input wire VAR424,
input wire VAR194,
input wire VAR12,
input wire VAR268,
input wire [3:0] VAR250,
output wire [7:0] VAR437,
inout wire VAR351,
inout wire VAR429,
output wire VAR288,
output wire VAR36,
input wire VAR386,
input w... | mit |
kigawas/MipsCPU | CPU/shifter.v | 2,348 | module MODULE1(
input [31:0] VAR9, input [31:0] VAR5, input VAR2,input VAR12,output [31:0] VAR6,output VAR1,
output VAR8,
output VAR4,
output VAR15
);
reg [31:0] VAR7;
reg VAR14;
reg VAR3;
reg VAR11;
reg VAR10;
reg [4:0] VAR13;
assign VAR1 = VAR14;
assign VAR8 = VAR3;
assign VAR4 = VAR11;
assign VAR15 = VAR10;
assign V... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/dest_axi_stream.v | 4,949 | module MODULE1 (
input VAR6,
input VAR31,
input enable,
output VAR35,
input VAR8,
output VAR36,
output VAR7,
input [VAR11-1:0] VAR41,
output [VAR11-1:0] VAR20,
output [VAR11-1:0] VAR42,
input VAR17,
input VAR22,
input VAR12,
output VAR46,
output [VAR16-1:0] VAR14,
output VAR3,
output VAR26,
input VAR19,
input [VAR16-1:... | gpl-3.0 |
mindrobots/P8X32A_Emulation | P8X32A_BeMicroCV/cog_ram.v | 1,257 | module MODULE1
(
input clk,
input VAR6,
input VAR5,
input [8:0] VAR2,
input [31:0] VAR3,
output reg [31:0] VAR1
);
reg [511:0] [31:0] VAR4;
always @(posedge clk)
begin
if (VAR6 && VAR5)
VAR4[VAR2] <= VAR3;
if (VAR6)
VAR1 <= VAR4[VAR2];
end
endmodule | gpl-3.0 |
mcgodfrey/i2c-eeprom | src/cclk_detector.v | 1,033 | module MODULE1 #(
parameter VAR2 = 50000000
)(
input clk,
input rst,
input VAR7,
output ready
);
parameter VAR3 = VAR8(VAR2/50000);
reg [VAR3-1:0] VAR5, VAR6;
reg VAR4, VAR1;
assign ready = VAR1;
always @(VAR6 or VAR7) begin
VAR4 = 1'b0;
if (VAR7 == 1'b0) begin VAR5 = 1'b0;
end else if (VAR6 != {VAR3{1'b1}}) begin
VAR5... | mit |
oblivioncth/DE0-Verilog-Processor | src/Bit_OP_16bit.v | 1,061 | module MODULE1(VAR1, VAR2, VAR4, VAR3);
input[15:0] VAR2;
input[3:0] VAR4;
input VAR3;
output reg[15:0] VAR1;
always @(VAR2) begin
case (VAR4[3:0])
4'b0000: begin VAR1 = {VAR2[15:1],VAR3}; end
4'b0001: begin VAR1 = {VAR2[15:2],VAR3,VAR2[0]}; end
4'b0010: begin VAR1 = {VAR2[15:3],VAR3,VAR2[1:0]}; end
4'b0011: begin VAR1... | mit |
esonghori/TinyGarbled | circuit_synthesis/knns_td/k_nns_seq_td.v | 2,898 | module MODULE1
(
parameter VAR30 = 32,
parameter VAR41 = 10
)
(
clk,
rst,
VAR14,
VAR24,
VAR36
);
function integer VAR38;
input [31:0] VAR19;
reg [31:0] VAR9;
begin
VAR9 = VAR19;
for (VAR38=0; VAR9>0; VAR38=VAR38+1)
VAR9 = VAR9>>1;
end
endfunction
localparam VAR13 = VAR38(VAR30);
input clk;
input rst;
input [2*VAR30-1:0... | gpl-3.0 |
orbancedric/DeepGate | src/core/parameterized_RAM.v | 2,606 | module MODULE1 #(
parameter VAR15 = 10,
parameter VAR17 = 2,
parameter VAR11 = 5
)(
input VAR1,
input VAR5,
input VAR2,
input [7:0] VAR8,
output reg [7:0] VAR10 = 0,
output wire VAR12,
output wire VAR16
);
reg [7:0] VAR4 [VAR15*VAR17*2 - 1'b1: 0];
reg [VAR3(VAR15*VAR17*2 - 1'b1) - 1'b1:0] VAR9 = 0;
reg [VAR3(VAR15*VAR1... | gpl-3.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v | 35,319 | module MODULE1 (
output wire VAR216, input wire VAR137, output wire VAR7, output wire [31:0] VAR14, output wire VAR177, input wire [0:0] VAR124, input wire [31:0] VAR72, input wire [10:0] VAR166, input wire VAR129, input wire VAR169, input wire [3:0] VAR205, input wire VAR41, output wire VAR172, output wire VAR223, inp... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_sao_cal_offset.v | 3,836 | module MODULE1(
VAR10 ,
VAR7 ,
VAR8 ,
VAR14 ,
VAR18
);
parameter VAR9 = 128 ;
parameter VAR17 = 8 ;
parameter VAR13 = 20 ;
parameter VAR2 = 25 ;
input signed [VAR13-1:0] VAR10 ;
input [ 12 :0] VAR7 ;
input VAR8 ;
output signed [ 2 :0] VAR14 ;
output signed [ VAR2-1:0] VAR18 ;
reg signed [VAR13-1:0] VAR4 ;
reg [ 12 :0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufinv/sky130_fd_sc_ms__bufinv.symbol.v | 1,272 | module MODULE1 (
input VAR1,
output VAR3
);
supply1 VAR5;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
aaiijmrtt/JUCSEsem2 | VeryLargeScaleIntegration/module.v | 2,314 | module MODULE3(in, out);
input wire[3: 0] in;
output wire[3: 0] out;
assign out[0] = in[0];
assign out[1] = in[1] ^ in[0];
assign out[2] = in[2] ^ in[1] ^ in[0];
assign out[3] = in[3] ^ in[2] ^ in[1] ^ in[0];
endmodule
module MODULE2(in, out);
input wire[4: 0] in;
output wire[5: 0] out;
reg[3: 0] VAR3;
reg[1: 0] VAR2;
... | mit |
SymbiFlow/fpga-tool-perf | third_party/daisho-usb3/usb3_lfsr.v | 4,695 | module MODULE1 (
input wire VAR5,
input wire VAR2,
input wire [31:0] VAR7,
input wire VAR10,
input wire VAR6,
input wire [15:0] VAR9,
output reg [31:0] VAR11,
output reg [31:0] VAR1
);
reg [15:0] VAR3, VAR4;
reg [31:0] VAR8;
always @(*) begin
VAR4[0] = VAR3[0] ^ VAR3[6] ^ VAR3[8] ^ VAR3[10];
VAR4[1] = VAR3[1] ^ VAR3[7]... | isc |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/Add.v | 1,814 | module MODULE1(
input VAR7,
input [35:0] VAR9,
input [35:0] VAR12,
input [31:0] VAR16,
input VAR4,
output reg VAR14,
output reg [31:0] VAR8,
output reg [27:0] VAR15
);
parameter VAR10 = 1'b0,
VAR11 = 1'b1;
wire VAR3;
wire [7:0] VAR6;
wire [26:0] VAR1;
wire VAR2;
wire [7:0] VAR5;
wire [26:0] VAR13;
assign VAR3 = VAR12[3... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_if.v | 7,049 | module MODULE1(
clk, rst,
VAR9, VAR2, VAR4, VAR20, VAR1,
VAR14, VAR6, VAR10, VAR8,
VAR13, VAR7, VAR18, VAR15,
VAR16, VAR21, VAR3
);
input clk;
input rst;
input [31:0] VAR9;
input VAR2;
input VAR4;
input [31:0] VAR20;
input [3:0] VAR1;
input VAR14;
output [31:0] VAR6;
output [31:0] VAR10;
input VAR8;
output VAR13;
input... | apache-2.0 |
nikhilghanathe/HLS-for-EMTF | verilog/sp_mux_128to1_sel7_12_1.v | 19,002 | module MODULE1 #(
parameter
VAR332 = 0,
VAR54 = 1,
VAR13 = 32,
VAR12 = 32,
VAR82 = 32,
VAR56 = 32,
VAR137 = 32,
VAR83 = 32,
VAR322 = 32,
VAR5 = 32,
VAR14 = 32,
VAR44 = 32,
VAR283 = 32,
VAR156 = 32,
VAR62 = 32,
VAR234 = 32,
VAR110 = 32,
VAR267 = 32,
VAR254 = 32,
VAR321 = 32,
VAR222 = 32,
VAR292 = 32,
VAR350 = 32,
VAR139... | apache-2.0 |
makestuff/swled | templates/fx2all/verilog/top_level.v | 4,317 | module
MODULE1(
input wire VAR17, output wire[1:0] VAR9, inout wire[7:0] VAR43,
output wire VAR21, output wire VAR2, input wire VAR8,
output wire VAR14, input wire VAR24, output wire VAR20,
output wire[7:0] VAR40, output wire[3:0] VAR7, output wire[7:0] VAR34, input wire[7:0] VAR32 );
wire[6:0] VAR5;
wire[7:0] VAR12; w... | gpl-3.0 |
lucasbrasilino/secret_flow | src/secret_flow.v | 7,235 | module MODULE1
parameter VAR41 = 64,
parameter VAR13 = VAR41/8,
parameter VAR3 = 2
)
(
output reg [VAR41-1:0] VAR28,
output reg [VAR13-1:0] VAR24,
output reg VAR38,
input VAR61,
input [VAR41-1:0] VAR37,
input [VAR13-1:0] VAR34,
input VAR59,
output VAR12,
input VAR31,
input VAR29,
input VAR36,
input [VAR19-1:0] VAR32,
i... | bsd-3-clause |
jossCr/Lab_Digitales | ProyectoCorto2/Codigo1.v | 8,936 | module MODULE1(clk, VAR37, VAR46, VAR3, VAR45
);
input clk;
input VAR46, VAR37;
output [7:0]VAR3;
output reg VAR45;
reg [7:0] VAR47;
reg VAR17;
reg [2:0] VAR9=0;
reg [7:0] VAR35=0;
reg [7:0] VAR48;
reg VAR20;
localparam [2:0]
VAR2 = 3'b000,
VAR28 = 3'b001,
VAR18 = 3'b010,
VAR5 = 3'b011,
VAR10 = 3'b100;
always @ (posedg... | gpl-2.0 |
jotego/jt51 | syn/xilinx/ym09/hdl/system_bus.v | 7,511 | module MODULE1(
input wire clk,
input wire rst,
output reg [ 7:0] VAR2,
input wire [ 7:0] VAR47,
input wire VAR58,
input wire VAR61,
input wire [ 7:0] VAR59,
input wire [15:0] address,
output wire VAR33,
input wire [ 7:0] VAR14,
output reg VAR52,
output reg [ 7:0] VAR35,
input VAR9,
output reg VAR51,
output reg VAR37,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.blackbox.v | 1,319 | module MODULE1 (
VAR4,
VAR1 ,
VAR2 ,
VAR3
);
output VAR4;
input VAR1 ;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
esonghori/TinyGarbled | circuit_synthesis/a23/a23_register_bank.v | 10,520 | module MODULE1 (
input VAR56,
input VAR4,
input [3:0] VAR23,
input [3:0] VAR50,
input [3:0] VAR16,
input VAR6,
input [14:0] VAR9,
input [23:0] VAR53, input [31:0] VAR17,
input [3:0] VAR15,
output [31:0] VAR18,
output reg [31:0] VAR51,
output reg [31:0] VAR35,
output [31:0] VAR13,
output [31:0] VAR32
);
reg [31:0] VAR47... | gpl-3.0 |
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