repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/rw_manager_ac_ROM_no_ifdef_params.v | 10,167 | module MODULE1 (
VAR13,
VAR8,
VAR18,
VAR6,
VAR28,
VAR55);
parameter VAR20 = "VAR12.VAR27";
input VAR13;
input [31:0] VAR8;
input [5:0] VAR18;
input [5:0] VAR6;
input VAR28;
output [31:0] VAR55;
tri1 VAR13;
tri0 VAR28;
wire [31:0] VAR26;
wire [31:0] VAR55 = VAR26[31:0];
VAR49 VAR2 (
.VAR16 (VAR6),
.VAR9 (VAR13),
.VAR35 ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2/sky130_fd_sc_lp__nor2.functional.pp.v | 1,783 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR7 ,
VAR8,
VAR3,
VAR12 ,
VAR9
);
output VAR5 ;
input VAR1 ;
input VAR7 ;
input VAR8;
input VAR3;
input VAR12 ;
input VAR9 ;
wire VAR6 ;
wire VAR13;
nor VAR10 (VAR6 , VAR1, VAR7 );
VAR11 VAR4 (VAR13, VAR6, VAR8, VAR3);
buf VAR2 (VAR5 , VAR13 );
endmodule | apache-2.0 |
PerezFederico/UART_Arquitectura | TX.v | 2,429 | module MODULE1
parameter VAR11 = 'b00010,
parameter VAR13 = 'b00100,
parameter VAR9 = 'b01000,
parameter VAR4 = 'b10000)
(input clk,
input VAR8,
input [7:0]din,
input VAR14,
output reg VAR7,
output reg VAR3);
reg [4:0] state = VAR10;
reg [4:0] VAR6 = VAR10;
reg VAR1 = 0;
integer VAR15 = 0;
reg VAR12 = 1;
integer VAR5 =... | gpl-3.0 |
ncos/Xilinx-Verilog | GYRACC/src/GYRO/display_clk.v | 2,099 | module MODULE1(
clk,
VAR4,
VAR1
);
input clk;
input VAR4;
output VAR1;
parameter [15:0] VAR3 = 16'b1011011100110101;
reg [15:0] VAR2;
always @(posedge clk)
begin
if (VAR4 == 1'b1)
VAR2 <= {16{1'b0}};
end
else
if (VAR2 == VAR3)
VAR2 <= {16{1'b0}};
else
VAR2 <= VAR2 + 1'b1;
end
assign VAR1 = VAR2[15];
endmodule | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/triple_speed_ethernet-library/altera_tse_lvds_reset_sequencer.v | 4,447 | module MODULE1 (
clk,
reset,
VAR12,
VAR7,
VAR8,
VAR11,
VAR9
);
input clk;
input reset;
input VAR12;
output VAR7;
output VAR8;
output VAR11;
output VAR9;
reg VAR7;
reg VAR8;
reg VAR11;
reg VAR9;
wire VAR20;
reg VAR16;
reg VAR1;
reg VAR4;
reg VAR15;
reg [2:0] VAR2;
reg [2:0] state;
reg [2:0] VAR17;
parameter [2:0] VAR3 =... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxbp/sky130_fd_sc_hs__sdfxbp.blackbox.v | 1,341 | module MODULE1 (
VAR2,
VAR5 ,
VAR6 ,
VAR1,
VAR7,
VAR3
);
input VAR2;
input VAR5 ;
output VAR6 ;
output VAR1;
input VAR7;
input VAR3;
supply1 VAR4;
supply0 VAR8;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/master_0/altera_jtag_dc_streaming/altera_avalon_st_pipeline_base.v | 4,716 | module MODULE1 (
clk,
reset,
VAR1,
VAR5,
VAR2,
VAR8,
VAR3,
VAR6
);
parameter VAR14 = 1;
parameter VAR11 = 8;
parameter VAR16 = 1;
localparam VAR15 = VAR14 * VAR11;
input clk;
input reset;
output VAR1;
input VAR5;
input [VAR15-1:0] VAR2;
input VAR8;
output VAR3;
output [VAR15-1:0] VAR6;
reg VAR9;
reg VAR10;
reg [VAR15-1... | mit |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/I2C/bit_ctr2l_tst.v | 1,579 | module MODULE1;
reg clk;
reg VAR3;
reg rst;
reg en;
reg VAR14;
reg VAR4;
reg VAR8;
reg VAR11;
wire VAR9;
wire VAR2;
wire VAR15;
wire VAR7;
reg VAR6, VAR1, VAR5;
assign VAR7 = VAR5? 1'VAR12 : VAR1;
VAR13 VAR10 (
.clk(clk),
.VAR3(VAR3),
.rst(rst),
.en(en),
.VAR14(VAR14),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR9(VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtp/sky130_fd_sc_hd__dfrtp_2.v | 2,329 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR2 ,
VAR8,
VAR9 ,
VAR3 ,
VAR10 ,
VAR6
);
output VAR7 ;
input VAR5 ;
input VAR2 ;
input VAR8;
input VAR9 ;
input VAR3 ;
input VAR10 ;
input VAR6 ;
VAR1 VAR4 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR6(VAR6)
);
endmodule
module MODU... | apache-2.0 |
gajjanag/6111_Project | src/move_cursor.v | 5,710 | module MODULE1(input clk,
input VAR11,
input VAR15,
input VAR23,
input VAR21,
input VAR24,
input[1:0] VAR18,
input[9:0] VAR29,
input[8:0] VAR14,
input[9:0] VAR6,
input[8:0] VAR25,
input[9:0] VAR12,
input[8:0] VAR10,
input[9:0] VAR22,
input[8:0] VAR1,
output reg[9:0] VAR3,
output reg[8:0] VAR2,
output reg[9:0] VAR13,
ou... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invlp/sky130_fd_sc_lp__invlp_2.v | 2,025 | module MODULE2 (
VAR4 ,
VAR8 ,
VAR5,
VAR2,
VAR3 ,
VAR1
);
output VAR4 ;
input VAR8 ;
input VAR5;
input VAR2;
input VAR3 ;
input VAR1 ;
VAR6 VAR7 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR4,
VAR8
);
output VAR4;
input VAR8;
supply1 VAR5;
supply0 VAR2;... | apache-2.0 |
infiniteNOP/nopCPU | cpu.v | 1,252 | module MODULE1(input clk, reset, interrupt,
input [7:0] VAR14, VAR18,
output [7:0] VAR20, VAR7, VAR19,
output VAR25);
wire [1:0] VAR9, VAR5, VAR3;
wire [7:0] VAR13, VAR21, VAR16, VAR24;
wire [7:0] VAR22;
wire [3:0] VAR10;
VAR23 VAR4(clk, reset, VAR2, VAR1, VAR13, VAR20);
VAR6 VAR17(VAR9, VAR5, VAR3,
VAR21, clk, VAR11,
... | lgpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/source/LOAGDA_St_N16_M4_P4.v | 2,811 | module MODULE1(
input [15:0] VAR49,
input [15:0] VAR27,
output [16:0] VAR70
);
wire [4:0] VAR60, VAR18, VAR69, VAR48;
wire VAR73,VAR92,VAR95,VAR66,VAR94,VAR50,VAR43,VAR28;
wire VAR100,VAR84,VAR79,VAR77,VAR97;
wire VAR11, VAR53;
wire VAR54;
and VAR96(VAR66,VAR49[3],VAR27[3]);
and VAR5(VAR95,VAR49[2],VAR27[2]);
and VAR46... | gpl-3.0 |
cafe-alpha/wascafe | v13/wasca_10m08sc_20191205_abus_divide/wasca/synthesis/submodules/wasca_nios2_gen2_0_cpu_debug_slave_sysclk.v | 6,123 | module MODULE1 (
clk,
VAR2,
VAR22,
VAR9,
VAR12,
VAR18,
VAR29,
VAR1,
VAR7,
VAR23,
VAR21,
VAR25,
VAR13,
VAR24,
VAR10,
VAR6
)
;
output [ 37: 0] VAR18;
output VAR29;
output VAR1;
output VAR7;
output VAR23;
output VAR21;
output VAR25;
output VAR13;
output VAR24;
output VAR10;
output VAR6;
input clk;
input [ 1: 0] VAR2;
inpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tap/sky130_fd_sc_lp__tap_1.v | 1,877 | module MODULE2 (
VAR2,
VAR3,
VAR6 ,
VAR4
);
input VAR2;
input VAR3;
input VAR6 ;
input VAR4 ;
VAR1 VAR5 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE2 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR4 ;
VAR1 VAR5 ();
endmodule | apache-2.0 |
osecpu/fpga | ireg.v | 1,392 | module MODULE1(clk, VAR5, VAR1, VAR6, VAR2, VAR4, VAR9, VAR8);
input clk, VAR8;
input [5:0] VAR5, VAR1, VAR6;
input [31:0] VAR9;
output reg [31:0] VAR2, VAR4;
wire [5:0] VAR3;
reg [31:0] VAR7[63:0];
assign VAR3 = (VAR8 == 1) ? VAR6 : VAR5;
always @ (posedge clk)
begin
if(VAR8 == 1) begin
VAR7[VAR3] <= VAR9;
end
else be... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o221ai/sky130_fd_sc_hd__o221ai_2.v | 2,457 | module MODULE1 (
VAR7 ,
VAR11 ,
VAR8 ,
VAR3 ,
VAR5 ,
VAR9 ,
VAR2,
VAR1,
VAR10 ,
VAR12
);
output VAR7 ;
input VAR11 ;
input VAR8 ;
input VAR3 ;
input VAR5 ;
input VAR9 ;
input VAR2;
input VAR1;
input VAR10 ;
input VAR12 ;
VAR4 VAR6 (
.VAR7(VAR7),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR2(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxbp/sky130_fd_sc_ls__dfxbp.blackbox.v | 1,295 | module MODULE1 (
VAR2 ,
VAR7,
VAR4,
VAR8
);
output VAR2 ;
output VAR7;
input VAR4;
input VAR8 ;
supply1 VAR6;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/daq_firmware.v | 7,331 | module MODULE1(
input wire [4:0] VAR72,
output wire [2:0] VAR20,
inout wire [31:0] VAR61,
inout wire VAR66,
input wire VAR90,
output wire [1:0] VAR24,
output wire [1:0] VAR74,
output wire [ 12: 0] VAR86,
output wire [ 2: 0] VAR68,
output wire VAR69,
output wire [ 0: 0] VAR1,
inout wire [ 0: 0] VAR41,
inout wire [ 0: 0]... | gpl-2.0 |
svofski/mahponk | src/quad.v | 1,164 | module MODULE1(clk, reset, VAR11, VAR10, VAR12);
parameter VAR8=0;
parameter VAR13 = 0;
input clk, reset, VAR11, VAR10;
output [9:0] VAR12;
reg [2:0] VAR5, VAR6;
always @(posedge clk) VAR5 <= {VAR5[1:0], VAR11};
always @(posedge clk) VAR6 <= {VAR6[1:0], VAR10};
wire VAR7 = VAR5[1] ^ VAR5[2] ^ VAR6[1] ^ VAR6[2];
wire VA... | bsd-2-clause |
freecores/orsoc_graphics_accelerator | rtl/verilog/gfx/gfx_line.v | 9,232 | module MODULE1(VAR13, VAR5,
VAR8, VAR22, VAR34, VAR15,
VAR9, VAR18,
VAR4, VAR12, VAR6, VAR26, VAR2
);
parameter VAR32 = 16;
parameter VAR16 = 16;
input VAR13;
input VAR5;
input signed [VAR32-1:-VAR16] VAR8;
input signed [VAR32-1:-VAR16] VAR34;
input signed [VAR32-1:-VAR16] VAR22;
input signed [VAR32-1:-VAR16] VAR15;
in... | gpl-3.0 |
mdsalman729/flexpret_project | fpga/atlys/4tf-16i-16d/dspm_bram.v | 1,699 | module MODULE1(input clk,
input [11:0] VAR11,
input VAR21,
output[31:0] VAR14,
input VAR7,
input VAR10,
input VAR16,
input VAR23,
input [31:0] VAR15,
input [11:0] VAR1,
input VAR8,
output[31:0] VAR22,
input VAR5,
input VAR4,
input VAR17,
input VAR18,
input [31:0] VAR20
);
wire [7:0] VAR13;
wire [7:0] VAR6;
assign VAR13... | bsd-3-clause |
tdaede/daala_zynq | daala_idct4_mmap_1.0/hdl/daala_idct4_mmap_v1_0.v | 2,215 | module MODULE1 #
(
parameter integer VAR28 = 32,
parameter integer VAR46 = 4
)
(
input wire VAR15,
input wire VAR41,
input wire [VAR46-1 : 0] VAR47,
input wire [2 : 0] VAR34,
input wire VAR35,
output wire VAR10,
input wire [VAR28-1 : 0] VAR44,
input wire [(VAR28/8)-1 : 0] VAR5,
input wire VAR40,
output wire VAR6,
outpu... | bsd-2-clause |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/hb/ram32_2sum.v | 1,199 | module MODULE1 (input VAR1, input write,
input [4:0] VAR2, input [15:0] VAR4,
input [4:0] VAR3, input [4:0] VAR5,
output reg [15:0] sum);
reg [15:0] VAR7 [0:31];
wire [16:0] VAR6;
always @(posedge VAR1)
if(write)
VAR7[VAR2] <= VAR4;
assign VAR6 = VAR7[VAR3] + VAR7[VAR5];
always @(posedge VAR1)
sum <= VAR6[16:1] + (VAR6... | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_1c_2p_f_v1_00_a/hdl/verilog/cf_spi.v | 6,638 | module MODULE1 (
VAR1,
VAR16,
VAR24,
VAR6,
VAR21,
VAR4,
VAR9,
VAR5,
VAR8,
VAR2,
VAR15,
VAR22,
VAR10,
VAR3,
VAR12);
output VAR1;
output VAR16;
output VAR24;
output VAR6;
input VAR21;
input VAR4;
input VAR9;
input VAR5;
input VAR8;
input [31:0] VAR2;
input [15:0] VAR15;
output [ 7:0] VAR22;
output VAR10;
output [ 7:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s.functional.pp.v | 1,865 | module MODULE1 (
VAR10 ,
VAR9 ,
VAR5,
VAR2,
VAR11 ,
VAR6
);
output VAR10 ;
input VAR9 ;
input VAR5;
input VAR2;
input VAR11 ;
input VAR6 ;
wire VAR3 ;
wire VAR4;
buf VAR8 (VAR3 , VAR9 );
VAR7 VAR1 (VAR4, VAR3, VAR5, VAR2);
buf VAR12 (VAR10 , VAR4 );
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/chris.uart.ok/Qsys/soc_design/synthesis/submodules/altera_up_rs232_counters.v | 5,450 | module MODULE1 (
clk,
reset,
VAR10,
VAR6,
VAR4,
VAR3
);
parameter VAR9 = 9; parameter VAR5 = 433;
parameter VAR8 = 216;
parameter VAR7 = 11;
input clk;
input reset;
input VAR10;
output reg VAR6;
output reg VAR4;
output reg VAR3;
reg [(VAR9-1):0] VAR1;
reg [ 3: 0] VAR2;
always @(posedge clk)
begin
if (reset)
VAR1 <= {VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/probec_p/sky130_fd_sc_hdll__probec_p.symbol.v | 1,290 | module MODULE1 (
input VAR5,
output VAR6
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_regfile_reg1.v | 1,930 | module MODULE1 (
address,
clk,
VAR6,
VAR5,
VAR1
)
;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input clk;
input [ 31: 0] VAR6;
input VAR5;
wire VAR2;
wire [ 31: 0] VAR4;
wire [ 31: 0] VAR3;
reg [ 31: 0] VAR1;
assign VAR2 = 1;
assign VAR3 = {32 {(address == 0)}} & VAR4;
always @(posedge clk or negedge VAR5)
begin
if (... | gpl-3.0 |
makestuff/swled | templates/fx2min/verilog/top_level.v | 3,855 | module
MODULE1(
input wire VAR32, output wire VAR33, inout wire[7:0] VAR31,
output wire VAR5, input wire VAR9,
output wire VAR3, input wire VAR28, output wire VAR29,
output wire[7:0] VAR8, output wire[3:0] VAR18, output wire[7:0] VAR16, input wire[7:0] VAR26 );
wire[6:0] VAR22;
wire[7:0] VAR35; wire VAR36; wire VAR20;
... | gpl-3.0 |
ILoveSpeccy/Aeon-Lite | cores/radio-86rk/src/rk_video.v | 1,931 | module MODULE1(
input VAR4,
output VAR15,
output VAR6,
output VAR24,
output [3:0] VAR1,
output [3:0] VAR23,
output [3:0] VAR9,
input[3:0] VAR5,
input[6:0] VAR22,
input VAR16,
input VAR8,
input VAR11,
input VAR7
);
reg[1:0] state;
reg[9:0] VAR3;
reg[9:0] VAR10;
reg[2:0] VAR12;
reg[5:0] VAR18;
wire[7:0] VAR21;
assign VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buf/sky130_fd_sc_lp__buf.blackbox.v | 1,202 | module MODULE1 (
VAR2,
VAR1
);
output VAR2;
input VAR1;
supply1 VAR6;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
mateuszokulanis/OM_FIREWALL | src/eth_mac_l2.v | 8,355 | module MODULE1(
input VAR42,
input VAR47,
output reg VAR44,
output reg [7:0] VAR53,
output reg [7:0] VAR24,
output reg VAR51,
input [7:0] VAR1,
input VAR28,
input [7:0] VAR3,
input [7:0] VAR25,
input VAR50,
output reg VAR57,
output reg VAR34,
output reg [7:0] VAR60,
output reg [7:0] VAR46,
output reg VAR31,
input [7:0]... | mit |
hcabrera-/atto | rtl/atto.v | 5,698 | module MODULE1 #(parameter VAR15 = 2, parameter VAR34 = 2)
(
input wire VAR33,
input wire VAR18,
input wire [47:0] VAR41,
input wire [1:0] VAR32,
input wire [47:0] VAR11,
input wire [1:0] VAR2,
input wire [47:0] VAR55,
input wire [1:0] VAR59,
output wire [47:0] VAR57,
output wire [1:0] VAR29,
output wire [47:0] VAR36,
... | gpl-3.0 |
nyaxt/dmix | nkmdhpa_t.v | 6,534 | module MODULE1;
reg rst;
reg clk;
parameter VAR17 = 40;
VAR11 clk = 0;
always #(VAR17/2) clk = ~clk;
reg VAR13;
reg VAR18;
parameter VAR20 = 80;
reg VAR14;
reg VAR4;
parameter VAR22 = 40; VAR9 VAR28(
.rst(rst),
.VAR8(clk),
.VAR10(VAR13),
.VAR25(VAR18),
.VAR21(VAR14),
.VAR3(VAR4));
task VAR15;
input VAR2;
begin
VAR13 = ... | mit |
DougFirErickson/parallella-hw | fpga/src/elink/hdl/erx_io.v | 12,768 | module MODULE1 (
VAR92, VAR110, VAR114, VAR52,
VAR55, VAR84, VAR32, VAR71,
reset, VAR104, VAR47, VAR111, VAR82,
VAR14, VAR115, VAR83, VAR26, VAR88,
VAR103, VAR91
);
parameter VAR11 = "VAR22";
input reset;
input VAR104, VAR47; input VAR111, VAR82; input [7:0] VAR14, VAR115; output VAR92,VAR110; output VAR114,VAR52;
outp... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_2.functional.v | 1,585 | module MODULE1( VAR5, VAR11, VAR1, VAR13 );
input VAR11, VAR5, VAR1;
output VAR13;
wire VAR4;
not VAR14( VAR4, VAR1 );
wire VAR8;
and VAR2( VAR8, VAR4, VAR11, VAR5 );
wire VAR17;
not VAR7( VAR17, VAR5 );
wire VAR12;
and VAR15( VAR12, VAR17, VAR11, VAR1 );
wire VAR6;
not VAR9( VAR6, VAR11 );
wire VAR18;
and VAR16( VAR18... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/bandwidth/DRAM/src/dramcon.v | 8,931 | module MODULE1(input wire VAR31,
input wire VAR71,
input wire VAR69,
input wire [1:0] VAR52, input wire [31:0] VAR70, input wire [31:0] VAR16, input wire [VAR75-1:0] VAR68, output wire VAR55, output reg [VAR75-1:0] VAR8, output reg VAR35, output wire VAR39, output wire VAR58, output wire VAR17, inout wire [VAR78] VAR80... | mit |
Jside/pdp1 | pdp1_sbs.v | 1,917 | module MODULE1(VAR4, VAR10,
VAR2, VAR7,
VAR13, VAR3, VAR12,
VAR1, VAR11, VAR5, VAR6, VAR15, VAR9);
input VAR4;
input VAR10;
output reg VAR2;
input VAR7;
input VAR13;
input [0:10] VAR3;
output [0:5] VAR12;
input VAR1;
input VAR11;
input VAR5;
input VAR6;
input VAR15;
input VAR9;
reg VAR8;
wire VAR14;
assign VAR12 = {VAR... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | processor/instrmem.v | 2,228 | module MODULE1 (VAR1,VAR2,VAR3);
output [0:31] VAR2;
input [0:31] VAR1;
input VAR3;
reg [0:31] VAR2;
reg [0:31] MODULE1 [0:255]; reg [0:7] VAR4;
begin
begin
begin | mit |
andrewandrepowell/zybo_petalinux | zybo_petalinux_gpio_sysfs/zybo_petalinux_1.srcs/sources_1/bd/block_design/ip/block_design_xlconcat_0_0/synth/block_design_xlconcat_0_0.v | 4,545 | module MODULE1 (
VAR64,
VAR45,
VAR14,
dout
);
input wire [3 : 0] VAR64;
input wire [3 : 0] VAR45;
input wire [0 : 0] VAR14;
output wire [8 : 0] dout;
VAR53 #(
.VAR44(4),
.VAR46(4),
.VAR58(1),
.VAR55(1),
.VAR16(1),
.VAR50(1),
.VAR49(1),
.VAR40(1),
.VAR66(1),
.VAR37(1),
.VAR5(1),
.VAR23(1),
.VAR18(1),
.VAR34(1),
.VAR48(1... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/serialInterfaceEngine/updateCRC5.v | 4,162 | module MODULE1 (VAR1, VAR2, VAR7, VAR3, VAR4, ready, clk, rst);
input VAR1;
input VAR7;
input VAR3;
input [7:0] VAR4;
input clk;
input rst;
output [4:0] VAR2;
output ready;
wire VAR1;
wire VAR7;
wire VAR3;
wire [7:0] VAR4;
wire clk;
wire rst;
reg [4:0] VAR2;
reg ready;
reg VAR8;
reg [7:0] VAR9;
reg [3:0] VAR6;
reg [3:0... | gpl-3.0 |
davidkoltak/tawas-core | ip/rcn/rtl/rcn_debug_lsa.v | 4,203 | module MODULE1
(
input VAR35,
input VAR7,
input [68:0] VAR43,
output [68:0] VAR29,
output reg [7:0] VAR34,
input VAR38,
input VAR9,
input [31:0] VAR28
);
parameter VAR37 = 1; parameter VAR10 = 1;
parameter VAR5 = 0;
parameter VAR11 = 8'd0;
wire VAR20;
wire VAR15;
wire [23:0] VAR33;
wire [31:0] VAR18;
reg [31:0] VAR12;
... | mit |
combinatorylogic/soc | backends/c2/hw/rtl/soundctl.v | 2,106 | module MODULE1(input rst,
input VAR27,
input [15:0] VAR6,
input VAR7,
output VAR8,
input VAR14,
output [15:0] VAR12,
output VAR21,
input VAR10);
VAR4#(.VAR16(4),.VAR19(16))
VAR18(.VAR3 (VAR14),
.VAR11 (VAR27),
.VAR22 (~rst),
.VAR20 (~rst),
.VAR29 (VAR7),
.VAR15 (VAR6),
.VAR2 (VAR10),
.VAR1 (VAR12),
.VAR23 (VAR21),
.VAR... | mit |
twlostow/dsi-shield | hdl/rtl/framebuffer/framebuffer.v | 4,733 | module MODULE1
parameter VAR26 = 26
) (
input VAR10,
input VAR11,
input VAR22,
output reg VAR15,
output reg [47:0] VAR5,
output VAR27,
input VAR4,
output [VAR26-1:0] VAR2,
output reg VAR6,
output VAR25,
output [3:0] VAR9,
input [31:0] VAR23,
input VAR19,
input VAR17,
input VAR24,
input [VAR26-1:0] VAR12,
input [VAR26-1... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/ff_dram_sc_bank1.v | 25,507 | module MODULE1(
VAR14, VAR25,
VAR28, VAR8,
VAR15, VAR30,
VAR9, VAR36,
VAR6, VAR38, VAR22,
VAR39, VAR42,
VAR32, VAR26,
VAR16, VAR33,
VAR1, VAR47, VAR40,
VAR44, VAR51, VAR11,
VAR50, VAR24,
VAR29, VAR43, VAR3,
VAR7, VAR5, VAR12,
VAR20, VAR2, VAR31,
VAR46, VAR10,
VAR52, VAR35,
VAR41, VAR13, VAR4, VAR18
);
input [127:0] VAR... | gpl-2.0 |
manu3193/GatoTDD | Pruebas_Controlador_Gato.v | 3,591 | module MODULE1;
reg clk;
reg VAR1;
reg VAR14;
reg VAR13;
reg VAR9;
reg VAR5;
reg VAR6;
reg VAR2;
wire [3:0] VAR15;
wire [3:0] VAR12;
wire [3:0] VAR7;
wire [1:0] VAR8;
wire [1:0] VAR4;
wire [1:0] VAR18;
wire [2:0] state;
wire VAR10;
wire VAR11;
wire VAR3;
wire VAR17;
wire VAR19;
VAR20 VAR16 (
.clk(clk),
.VAR1(VAR1),
.VA... | mit |
CospanDesign/nysa-sdio-device | rtl/control/sdio_card_control.v | 23,273 | module MODULE1 #(
parameter VAR149 = 1,
parameter VAR73 = 0,
parameter VAR101 = 0,
parameter VAR69 = 24'hFFF0,
parameter VAR124 = 8,
parameter VAR93 = 0
)(
input VAR50,
input rst,
output reg VAR106,
output reg VAR14,
output reg VAR96,
output reg VAR55,
output reg VAR81,
output reg VAR29,
output reg [17:0] VAR94,
output... | mit |
monotone-RK/FACE | IEICE-Trans/4-way_2-tree/src/riffa/tx_hdr_fifo.v | 7,726 | module MODULE1(
parameter VAR55 = 128,
parameter VAR21 = 1,
parameter VAR5 = 1,
parameter VAR35 = "VAR59"
)
(
input VAR45,
input VAR17,
input VAR44,
input [(VAR55)-1:0] VAR11,
input [VAR4-1:0] VAR49,
input [VAR26-1:0] VAR28,
input [VAR34-1:0] VAR18,
input VAR24,
output VAR20,
output VAR52,
output [(VAR55)-1:0] VAR13,
o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor2/sky130_fd_sc_hdll__xor2.behavioral.v | 1,389 | module MODULE1 (
VAR2,
VAR1,
VAR7
);
output VAR2;
input VAR1;
input VAR7;
supply1 VAR6;
supply0 VAR10;
supply1 VAR5 ;
supply0 VAR4 ;
wire VAR9;
xor VAR8 (VAR9, VAR7, VAR1 );
buf VAR3 (VAR2 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2/sky130_fd_sc_ms__and2_2.v | 2,086 | module MODULE2 (
VAR8 ,
VAR7 ,
VAR9 ,
VAR3,
VAR4,
VAR1 ,
VAR5
);
output VAR8 ;
input VAR7 ;
input VAR9 ;
input VAR3;
input VAR4;
input VAR1 ;
input VAR5 ;
VAR6 VAR2 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR8,
VAR7,
VAR9
);
output VAR8;
... | apache-2.0 |
PeterMagnusson/modexp | src/rtl/blockmem2rptr1w.v | 4,670 | module MODULE1(
input wire clk,
input wire VAR16,
input wire [07 : 0] VAR2,
output wire [31 : 0] VAR14,
output wire [31 : 0] VAR5,
input wire rst,
input wire VAR9,
input wire wr,
input wire [07 : 0] VAR10,
input wire [31 : 0] VAR4
);
reg [31 : 0] VAR7 [0 : 255];
reg [31 : 0] VAR1;
reg [31 : 0] VAR6;
reg [7 : 0] VAR3;
r... | bsd-2-clause |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/vfabric_bypass_reg.v | 1,542 | module MODULE1(VAR9, VAR3,
VAR5,
VAR8,
VAR11, VAR6, VAR10,
VAR2, VAR1, VAR7);
parameter VAR4 = 32;
input VAR9;
input VAR3;
input VAR5;
input [VAR4-1:0] VAR8;
input [VAR4-1:0] VAR11;
input VAR6;
output VAR10;
output [VAR4-1:0] VAR2;
output VAR1;
input VAR7;
assign VAR2 = VAR5 ? VAR8 : VAR11;
assign VAR1 = VAR6;
assign V... | mit |
chebykinn/university | io/lab3/v-src/Timer.v | 2,510 | module MODULE1(VAR14,VAR1,VAR12,VAR16,VAR5,VAR9,VAR13,VAR10);
input VAR14;
input VAR1;
input [12:0] VAR12;
input [31:0] VAR16;
output [31:0] VAR5;
input VAR9;
input [3:0] VAR13;
output [31:0] VAR10;
reg [31:0] VAR5;
reg [31:0] VAR10;
reg [31:0] VAR15;
reg [31:0] VAR3;
reg [31:0] VAR8;
reg [31:0] VAR7;
reg [31:0] VAR6;
... | mit |
Jside/nova1 | nova_ram.v | 2,119 | module MODULE1(VAR14, VAR7, VAR5, VAR11, VAR19, VAR16);
parameter VAR1 = 16;
parameter VAR10 = 1 << VAR1;
parameter VAR3 = VAR10-1;
input VAR14;
input VAR7;
input [0:15] VAR5;
input VAR11;
input [0:15] VAR19;
output [0:15] VAR16;
reg [0:15] VAR6[0:VAR10];
wire [0:VAR1-1] VAR17;
integer VAR2;
assign VAR17 = VAR5[0:VAR1-... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_var.v | 1,176 | module MODULE1 #
(parameter VAR24(VAR20)
,parameter VAR24(VAR22)
,parameter VAR24(VAR5)
,parameter VAR18 = VAR20 / VAR22
,parameter VAR1=VAR21(VAR5))
(input VAR10
,input VAR7
,input [VAR20-1:0] VAR19
,input [VAR20-1:0] VAR4
,input [VAR1-1:0] VAR6
,input VAR8
,input VAR3
,output [VAR20-1:0] VAR13);
VAR17 @(posedge VAR10... | bsd-3-clause |
drichmond/riffa | fpga/xilinx/adm7V3/ADM7V3_Gen3x4If128/hdl/ADM7V3_Gen3x4If128.v | 26,201 | module MODULE1
parameter VAR17 = 4,
parameter VAR107 = 128,
parameter VAR127 = 256,
parameter VAR48 = 6)
(output [(VAR17 - 1) : 0] VAR75,
output [(VAR17 - 1) : 0] VAR183,
input [(VAR17 - 1) : 0] VAR212,
input [(VAR17 - 1) : 0] VAR54,
output [5:0] VAR208,
input VAR80,
input VAR182,
input VAR191
);
wire VAR98;
wire VAR33... | bsd-3-clause |
frisnit/fpga-noise | verilog/vga.v | 2,606 | module MODULE1(clk, VAR2, VAR3, VAR18, VAR8, VAR17, VAR21, VAR7, VAR15);
parameter VAR4 = 640;
parameter VAR16 = 16;
parameter VAR6 = 96;
parameter VAR10 = 48;
parameter VAR14 = 480;
parameter VAR11 = 11;
parameter VAR12 = 2;
parameter VAR5 = 31;
input clk;
input [7:0] VAR2;
output VAR3, VAR18;
output [9:0] VAR7, VAR15... | mit |
gbraad/minimig-de1 | lib/models/mt48lc4m16.v | 56,423 | module MODULE1
(
VAR52 ,
VAR112 ,
VAR91 ,
VAR3 ,
VAR80 ,
VAR76 ,
VAR114 ,
VAR56 ,
VAR135 ,
VAR187 ,
VAR64 ,
VAR117 ,
VAR7 ,
VAR81 ,
VAR9 ,
VAR73 ,
VAR33 ,
VAR53 ,
VAR124 ,
VAR138 ,
VAR38 ,
VAR174 ,
VAR142 ,
VAR125 ,
VAR131 ,
VAR107 ,
VAR23 ,
VAR55 ,
VAR147 ,
VAR185 ,
VAR129 ,
VAR32 ,
VAR172 ,
VAR19 ,
VAR61 ,
VAR157 ,
V... | gpl-3.0 |
MarcoVogt/basil | firmware/modules/fei4_rx/fei4_rx_core.v | 4,222 | module MODULE1
parameter VAR25 = 10,
parameter VAR9 = 0,
parameter VAR37 = 32
)
(
input wire VAR44,
input wire VAR54,
input wire VAR23,
input wire VAR40,
output wire VAR15,
output wire VAR55,
output wire VAR57,
input wire VAR60,
input wire VAR24,
output wire VAR5,
output wire [31:0] VAR6,
output wire VAR29,
output wire... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfxbp/sky130_fd_sc_hvl__dfxbp.blackbox.v | 1,299 | module MODULE1 (
VAR2 ,
VAR7,
VAR6,
VAR5
);
output VAR2 ;
output VAR7;
input VAR6;
input VAR5 ;
supply1 VAR3;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4b/sky130_fd_sc_ms__nor4b.behavioral.pp.v | 1,988 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR12 ,
VAR6 ,
VAR4 ,
VAR5,
VAR7,
VAR17 ,
VAR13
);
output VAR8 ;
input VAR10 ;
input VAR12 ;
input VAR6 ;
input VAR4 ;
input VAR5;
input VAR7;
input VAR17 ;
input VAR13 ;
wire VAR11 ;
wire VAR9 ;
wire VAR2;
not VAR14 (VAR11 , VAR4 );
nor VAR1 (VAR9 , VAR10, VAR12, VAR6, VAR11 );
VAR3 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvp/sky130_fd_sc_hs__einvp_2.v | 2,002 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR7 ,
VAR5,
VAR2
);
input VAR3 ;
input VAR6 ;
output VAR7 ;
input VAR5;
input VAR2;
VAR4 VAR1 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR3 ,
VAR6,
VAR7
);
input VAR3 ;
input VAR6;
output VAR7 ;
supply1 VAR5;
supply0 VAR2;
VAR4 VAR1 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkinv/sky130_fd_sc_ms__clkinv.pp.blackbox.v | 1,251 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR1,
VAR2,
VAR3 ,
VAR6
);
output VAR4 ;
input VAR5 ;
input VAR1;
input VAR2;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
ElegantLin/My-CPU | project_4/project_4.srcs/sources_1/imports/Chapter11/if_id.v | 2,685 | module MODULE1(
input wire clk,
input wire rst,
input wire[5:0] VAR9,
input wire VAR2,
input wire[VAR11] VAR6,
input wire[VAR12] VAR8,
output reg[VAR11] VAR10,
output reg[VAR12] VAR5
);
always @ (posedge clk) begin
if (rst == VAR4) begin
VAR10 <= VAR7;
VAR5 <= VAR7;
end else if(VAR2 == 1'b1 ) begin
VAR10 <= VAR7;
VAR5 ... | gpl-3.0 |
zhangry868/MultiCycleCPU | Multiple_Cycles_CPU/MIPS_Shifter.v | 1,359 | module MODULE2(
input [31:0] VAR10,VAR18,VAR3,VAR11,
input [1:0] VAR4,
output [31:0]VAR17
);
assign VAR17 = (VAR4[1] == 1'b0)?((VAR4[0] == 1'b0)?(VAR10):(VAR18)):((VAR4[0] == 1'b0)?(VAR3):(VAR11));
endmodule
module MODULE1(
input[31:0] VAR6,
input [4:0] VAR5,
input [1:0] VAR4,
output [31:0]VAR2
);
wire[31:0] VAR13,VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4/sky130_fd_sc_hdll__nor4.pp.symbol.v | 1,338 | module MODULE1 (
input VAR1 ,
input VAR3 ,
input VAR2 ,
input VAR7 ,
output VAR4 ,
input VAR8 ,
input VAR6,
input VAR9,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dlatch_lp/sky130_fd_sc_hd__udp_dlatch_lp.blackbox.v | 1,253 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR2
);
output VAR3 ;
input VAR1 ;
input VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4bb/sky130_fd_sc_ls__nand4bb.functional.pp.v | 2,000 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR10 ,
VAR12 ,
VAR2 ,
VAR1,
VAR11,
VAR9 ,
VAR15
);
output VAR8 ;
input VAR7 ;
input VAR10 ;
input VAR12 ;
input VAR2 ;
input VAR1;
input VAR11;
input VAR9 ;
input VAR15 ;
wire VAR13 ;
wire VAR4 ;
wire VAR17;
nand VAR5 (VAR13 , VAR2, VAR12 );
or VAR16 (VAR4 , VAR10, VAR7, VAR13 );
VAR3 VA... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/jtag_interface/src/jtag_bus.v | 7,609 | module MODULE1
parameter VAR47 = 27,
parameter VAR36 = 32
)
(
input VAR24,
input VAR52,
input [VAR47-1:0] VAR43,
input [VAR36-1:0] VAR15,
output wire [VAR36-1:0] VAR14,
output VAR13, input VAR49,
output wire VAR29,
output [VAR47-1:0] VAR18,
output [VAR36-1:0] VAR28,
input wire [VAR36-1:0] VAR3,
input VAR16,
input reset... | mit |
DigitalLogicSummerTerm2015/mips-cpu-pipeline | ppcpu/alu.v | 1,101 | module MODULE1(
input [31:0] VAR23,
input [31:0] VAR12,
input [5:0] VAR20,
input VAR7,
output reg [31:0] VAR14
);
wire VAR11, VAR16, VAR18;
wire [31:0] VAR6, VAR10, VAR13, VAR2;
VAR21 VAR15(.VAR14 (VAR11),
.VAR8 (VAR16),
.VAR22 (VAR18),
.dout(VAR6),
.VAR23 (VAR23),
.VAR12 (VAR12),
.VAR19(VAR20[0]),
.VAR7(VAR7));
VAR3 V... | mit |
makestuff/swled | templates/epp/verilog/top_level.v | 3,516 | module
MODULE1(
input wire VAR34,
inout wire[7:0] VAR21, input wire VAR17, input wire VAR15, input wire VAR13, output wire VAR7,
output wire[7:0] VAR24, output wire[3:0] VAR18, output wire[7:0] VAR5, input wire[7:0] VAR35 );
wire[6:0] VAR22;
wire[7:0] VAR23; wire VAR25; wire VAR27;
wire[7:0] VAR3; wire VAR28; wire VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/maj3/sky130_fd_sc_hs__maj3.pp.symbol.v | 1,257 | module MODULE1 (
input VAR6 ,
input VAR1 ,
input VAR3 ,
output VAR2 ,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbn/sky130_fd_sc_hs__dfbbn.functional.pp.v | 2,401 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR7 ,
VAR15 ,
VAR17 ,
VAR11,
VAR14 ,
VAR21
);
output VAR8 ;
output VAR1 ;
input VAR7 ;
input VAR15 ;
input VAR17 ;
input VAR11;
input VAR14 ;
input VAR21 ;
wire VAR2 ;
wire VAR20 ;
wire VAR18 ;
wire VAR13 ;
wire VAR12 ;
wire VAR4;
wire VAR6 ;
not VAR10 (VAR2 , VAR11 );
not VAR5 (VAR20 , ... | apache-2.0 |
ultraembedded/altor32 | fpga/papilio_xc3s250e/top.v | 7,455 | module MODULE1
(
input clk ,
input VAR78 ,
output VAR87 ,
inout [15:0] VAR58 ,
inout [15:0] VAR83 ,
inout [15:0] VAR37 ,
output VAR102 ,
output VAR105 ,
input VAR49 ,
output VAR124
);
parameter VAR16 = 32000;
parameter VAR99 = 32000;
parameter VAR36 = 115200;
reg reset = 1'b1;
reg VAR104 = 1'b1;
wire [31:0] VAR92;
wire... | lgpl-3.0 |
sh-chris110/chris | FPGA/Math/Qsys/nios_design/synthesis/submodules/nios_design_nios2_gen2_0_cpu_debug_slave_tck.v | 8,393 | module MODULE1 (
VAR27,
VAR38,
VAR19,
VAR13,
VAR9,
VAR29,
VAR4,
VAR11,
VAR2,
VAR25,
VAR32,
VAR3,
VAR16,
VAR36,
VAR22,
VAR10,
VAR39,
VAR31,
VAR30,
VAR33,
VAR40,
VAR37,
VAR34,
VAR20,
VAR5,
VAR12,
VAR17,
VAR28,
VAR21,
VAR26,
VAR15
)
;
output [ 1: 0] VAR17;
output VAR28;
output [ 37: 0] VAR21;
output VAR26;
output VAR15;
i... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd2/sky130_fd_sc_hdll__dlygate4sd2.behavioral.v | 1,413 | module MODULE1 (
VAR4,
VAR9
);
output VAR4;
input VAR9;
supply1 VAR2;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR7 ;
wire VAR1;
buf VAR5 (VAR1, VAR9 );
buf VAR6 (VAR4 , VAR1 );
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/yf32/control.v | 32,496 | module MODULE1 (VAR72, VAR60, VAR78, VAR71, VAR52, VAR10,
VAR43, VAR41, VAR48, VAR3, VAR75,
VAR31, VAR11, VAR19, VAR33);
input [31:0] VAR72;
input VAR60;
output [ 5:0] VAR78;
output [ 5:0] VAR71;
output [ 5:0] VAR52;
output [15:0] VAR10;
output [ 3:0] VAR43;
output [ 1:0] VAR41;
output [ 3:0] VAR48;
output [ 2:0] VAR3;... | mit |
walkthetalk/fsref | ip/axis_relay/src/axis_relay.v | 3,039 | module MODULE1 #
(
parameter integer VAR13 = 8,
parameter integer VAR15 = 0,
parameter integer VAR5 = 0
) (
input wire clk,
input wire VAR7,
input wire VAR9,
input wire [VAR13-1:0] VAR18 ,
input wire VAR6 ,
input wire VAR20 ,
output wire VAR8,
output wire VAR16,
output wire [VAR13-1:0] VAR2 ,
output wire VAR14 ,
output... | gpl-3.0 |
kevintownsend/R3 | verilog/instdec.v | 2,616 | module MODULE1 (
input [31:0] VAR14,
input [63:0] VAR11,
input VAR3,
output VAR10,
output [4:0] VAR8,
output VAR1,
output VAR15,
output [17:0] VAR2,
output VAR6
);
reg VAR4, VAR13, VAR12, VAR5;
reg [4:0] VAR7;
reg [17:0] VAR9;
always @* begin
VAR4 = 'b0;
VAR7 = 'b0;
VAR13 = 'b0;
VAR12 = 'b0;
VAR9 = 'b0;
VAR5 = 'b0;
cas... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/buslvds/buslvds.v | 1,690 | module MODULE1(
VAR24,
VAR16,
din,
VAR19,
VAR18
);
input wire VAR24;
input wire VAR16;
output wire din;
inout wire VAR19;
inout wire VAR18;
wire VAR9;
wire VAR10;
wire [0:0] VAR6;
wire VAR17;
wire VAR7;
wire VAR23;
VAR5 VAR15(
.VAR2(VAR24),
.VAR11(VAR16),
.VAR13(VAR7),
.VAR8(VAR23),
.VAR9(VAR9),
.VAR10(VAR10));
assign ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.v | 2,160 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR4,
VAR2,
VAR6 ,
VAR1
);
output VAR7 ;
input VAR5 ;
input VAR4;
input VAR2;
input VAR6 ;
input VAR1 ;
VAR8 VAR3 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR7,
VAR5
);
output VAR7;
input VAR5;
supply1 VAR4;
supply0 VAR2;... | apache-2.0 |
everskar2013/PentiumX | Hardware/Code/alu.v | 2,653 | module MODULE1(
VAR20,
VAR14,
VAR3,
VAR9,
VAR23,
VAR16,
VAR24
);
input wire [31: 0] VAR20, VAR14;
input wire [ 3: 0] VAR3;
input wire [ 4: 0] VAR9;
output reg [31: 0] VAR23;
output wire VAR16;
output wire VAR24;
wire [31: 0] VAR15, VAR11, VAR5, VAR13, VAR2, VAR25,
VAR6, VAR10, VAR22, VAR17, VAR1, VAR26, VAR21, VAR19, V... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/yf32/pipeline.v | 6,613 | module MODULE1 (clk, reset, VAR39, VAR11, VAR5, VAR40, VAR15, VAR30,
VAR22, VAR37, VAR16, VAR33, VAR13,
VAR19, VAR28, VAR1, VAR8, VAR34, VAR23,
VAR31, VAR14, VAR3, VAR35, VAR27, VAR7,
VAR36);
input clk;
input reset;
input [31:0] VAR39;
input [31:0] VAR5;
input [ 3:0] VAR15;
input [ 1:0] VAR22;
input [ 3:0] VAR16;
input... | mit |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/CvtColor_1_sectorncg.v | 1,246 | module MODULE1 (
VAR1, VAR5, VAR7, clk);
parameter VAR2 = 2;
parameter VAR6 = 3;
parameter VAR3 = 6;
input[VAR6-1:0] VAR1;
input VAR5;
output reg[VAR2-1:0] VAR7;
input clk;
reg [VAR2-1:0] VAR4[0:VAR3-1];
begin
begin | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nfc-substrate/bch_shared_kes-1.0.0/ChannelArbiter.v | 8,139 | module MODULE1
(
VAR4 ,
VAR13 ,
VAR16 ,
VAR15 ,
VAR20 ,
VAR6 ,
VAR2
);
input VAR4 ;
input VAR13 ;
input [3:0] VAR16 ;
input [3:0] VAR15 ;
output [3:0] VAR20 ;
output [1:0] VAR6 ;
input VAR2 ;
reg [3:0] VAR17 ;
reg [3:0] VAR12 ;
reg [3:0] VAR11 ;
reg [3:0] VAR3 ;
reg [3:0] VAR1 ;
reg [1:0] VAR5 ;
localparam VAR10 = 5'b0... | gpl-3.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_int_mult32s_s5.v | 2,852 | module MODULE1 (
enable,
VAR13,
VAR6,
VAR3,
VAR9);
parameter VAR16 = 32;
parameter VAR5 = 32;
localparam VAR8 = VAR16 < 32 ? VAR16 + 1 : VAR16;
localparam VAR1 = VAR5 < 32 ? VAR5 + 1 : VAR5;
input enable;
input VAR13;
input [VAR8 - 1 : 0] VAR6;
input [VAR1 - 1 : 0] VAR3;
output reg [31:0] VAR9;
reg [VAR8 - 1 : 0] VAR15... | mit |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/mega/ram_16x75k.v | 7,544 | module MODULE1 (
address,
VAR40,
VAR4,
VAR56,
VAR25,
VAR24,
VAR37);
input [16:0] address;
input [1:0] VAR40;
input VAR4;
input VAR56;
input [15:0] VAR25;
input VAR24;
output [15:0] VAR37;
tri1 [1:0] VAR40;
tri1 VAR4;
tri1 VAR56;
wire [15:0] VAR36;
wire [15:0] VAR37 = VAR36[15:0];
VAR6 VAR23 (
.VAR16 (address),
.VAR13 (... | bsd-3-clause |
aabdelfattah/alhaitham-hardware | alt_div.v | 4,184 | module MODULE1 (
VAR13,
VAR21,
VAR11,
VAR9);
input [31:0] VAR13;
input [31:0] VAR21;
output [31:0] VAR11;
output [31:0] VAR9;
wire [31:0] VAR10;
wire [31:0] VAR20;
wire [31:0] VAR11 = VAR10[31:0];
wire [31:0] VAR9 = VAR20[31:0];
VAR17 VAR19 (
.VAR13 (VAR13),
.VAR21 (VAR21),
.VAR11 (VAR10),
.VAR9 (VAR20),
.VAR1 (1'b0),
... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_logic_analyzer/rtl/wb_logic_analyzer.v | 14,664 | module MODULE1 # (
parameter VAR53 = 10,
parameter VAR46 = 115200
) (
input clk,
input rst,
input VAR2,
input VAR7,
input [3:0] VAR125,
input [31:0] VAR41,
input VAR102,
output reg VAR80,
output reg [31:0] VAR73,
input [31:0] VAR11,
output reg VAR5,
input VAR40,
input [VAR51 - 1:0] VAR110,
input VAR45,
input VAR100,
ou... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_2.functional.pp.v | 1,066 | module MODULE1( VAR10, VAR6, VAR9, VAR3, VAR4 );
input VAR9, VAR10;
inout VAR3, VAR4;
output VAR6;
wire VAR7;
not VAR5( VAR7, VAR9 );
wire VAR2;
not VAR1( VAR2, VAR10 );
and VAR8( VAR6, VAR7, VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tap/sky130_fd_sc_ls__tap.functional.pp.v | 1,189 | module MODULE1 (
VAR4,
VAR2,
VAR3 ,
VAR1
);
input VAR4;
input VAR2;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.behavioral.v | 1,495 | module MODULE1( VAR6, VAR4, VAR1, VAR5 );
input VAR1, VAR6, VAR5;
output VAR4;
VAR7 VAR2(.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1),.VAR5(VAR5));
VAR7 VAR3(.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32oi/sky130_fd_sc_ms__a32oi.pp.symbol.v | 1,440 | module MODULE1 (
input VAR3 ,
input VAR10 ,
input VAR2 ,
input VAR5 ,
input VAR4 ,
output VAR7 ,
input VAR6 ,
input VAR8,
input VAR1,
input VAR9
);
endmodule | apache-2.0 |
drichmond/riffa | fpga/altera/de5/DE5QGen1x8If64_CLK/hdl/DE5QGen1x8If64_CLK.v | 30,947 | module MODULE1
parameter VAR147 = 8,
parameter VAR19 = 64,
parameter VAR91 = 256,
parameter VAR60 = 5
)
(
output [7:0] VAR226,
input VAR185,
input VAR23,
input [VAR147-1:0] VAR143,
output [VAR147-1:0] VAR33,
input VAR21
);
wire VAR95;
wire VAR12;
wire [3:0] VAR225;
wire [31:0] VAR11;
wire [52:0] VAR108;
wire [0:0] VAR1... | bsd-3-clause |
donnaware/AGC | rtl/de0/modules/ng_TPG.v | 3,176 | module MODULE1(
input VAR5, input VAR12, input VAR18, input VAR4, input VAR2, input VAR28, input VAR15, input VAR1, input VAR19, input VAR21, input VAR26, input VAR7, output reg [3:0] VAR11, output VAR24 );
wire VAR9 = !(!VAR18 | !(VAR4 | !VAR2)); wire VAR6 = !(!VAR28 & VAR2); wire VAR8 = !(!(VAR15 & !VAR19) & VAR1); w... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_qpll_drp.v | 20,767 | module MODULE1 #
(
parameter VAR18 = "VAR60", parameter VAR72 = "3.0", parameter VAR28 = "VAR22", parameter VAR46 = 0, parameter VAR24 = 2'd3, parameter VAR43 = 3'd6
)
(
input VAR75,
input VAR45,
input VAR65,
input VAR15,
input VAR16,
input VAR21,
input [15:0] VAR66,
input VAR54,
output [ 7:0] VAR74,
output VAR83,
outp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbn/sky130_fd_sc_lp__sdfbbn.pp.blackbox.v | 1,558 | module MODULE1 (
VAR10 ,
VAR4 ,
VAR12 ,
VAR2 ,
VAR11 ,
VAR5 ,
VAR3 ,
VAR6,
VAR8 ,
VAR9 ,
VAR1 ,
VAR7
);
output VAR10 ;
output VAR4 ;
input VAR12 ;
input VAR2 ;
input VAR11 ;
input VAR5 ;
input VAR3 ;
input VAR6;
input VAR8 ;
input VAR9 ;
input VAR1 ;
input VAR7 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_counter_set_down.v | 1,533 | module MODULE1 #(parameter VAR16(VAR15), parameter VAR13='0, parameter VAR11=0)
(input VAR7
, input VAR4
, input VAR9
, input [VAR15-1:0] VAR14
, input VAR8
, output [VAR15-1:0] VAR5
);
logic [VAR15-1:0] VAR1, VAR2;
VAR3 @(posedge VAR7)
if (VAR4)
VAR1 <= VAR15 ' (VAR13);
else
VAR1 <= VAR2;
if (VAR11)
begin: VAR6
VAR12
... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o.functional.pp.v | 2,253 | module MODULE1 (
VAR4 ,
VAR12,
VAR18,
VAR10 ,
VAR3 ,
VAR6,
VAR17,
VAR14 ,
VAR2
);
output VAR4 ;
input VAR12;
input VAR18;
input VAR10 ;
input VAR3 ;
input VAR6;
input VAR17;
input VAR14 ;
input VAR2 ;
wire VAR5 ;
wire VAR1 ;
wire VAR7 ;
wire VAR16;
and VAR13 (VAR5 , VAR10, VAR3 );
nor VAR8 (VAR1 , VAR12, VAR18 );
or VA... | apache-2.0 |
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