repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
cafe-alpha/wascafe | v13/wasca_10m08sc_20191205_abus_divide/wasca/synthesis/submodules/wasca_onchip_memory2_1.v | 2,887 | module MODULE1 (
address,
VAR31,
VAR8,
clk,
VAR12,
reset,
VAR15,
write,
VAR14,
VAR20
)
;
output [ 31: 0] VAR20;
input [ 9: 0] address;
input [ 3: 0] VAR31;
input VAR8;
input clk;
input VAR12;
input reset;
input VAR15;
input write;
input [ 31: 0] VAR14;
wire VAR9;
wire [ 31: 0] VAR20;
wire VAR5;
assign VAR5 = VAR8 & wri... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor2/sky130_fd_sc_hvl__nor2.pp.symbol.v | 1,267 | module MODULE1 (
input VAR7 ,
input VAR2 ,
output VAR6 ,
input VAR3 ,
input VAR5,
input VAR4,
input VAR1
);
endmodule | apache-2.0 |
plindstroem/oh | memory/hdl/fifo_empty_block.v | 2,675 | module MODULE1 (
VAR4, VAR6, VAR10,
reset, VAR1, VAR5, VAR2
);
parameter VAR11 = 2;
input reset;
input VAR1;
input [VAR11:0] VAR5; input VAR2;
output VAR4;
output [VAR11-1:0] VAR6;
output [VAR11:0] VAR10;
reg [VAR11:0] VAR10;
reg [VAR11:0] VAR9;
reg VAR4;
wire VAR7;
wire [VAR11:0] VAR3;
wire [VAR11:0] VAR8;
always @(po... | gpl-3.0 |
takeshineshiro/fpga_linear_128 | LOG_Table.v | 6,539 | module MODULE1 (
address,
VAR36,
VAR20);
input [12:0] address;
input VAR36;
output [7:0] VAR20;
wire [7:0] VAR34;
wire [7:0] VAR20 = VAR34[7:0];
VAR44 VAR43 (
.VAR9 (VAR36),
.VAR41 (address),
.VAR51 (VAR34),
.VAR1 (1'b0),
.VAR23 (1'b0),
.VAR50 (1'b1),
.VAR10 (1'b0),
.VAR47 (1'b0),
.VAR12 (1'b1),
.VAR40 (1'b1),
.VAR45 (... | mit |
tugrulyatagan/RISC-processor | xilinx_processor/ALU_16.v | 2,678 | module MODULE1(
input VAR4,
input [15:0] VAR32,
input [15:0] VAR25,
input [7:0] VAR30,
output [15:0] VAR24,
output reg VAR29,
output reg VAR33,
output reg VAR8,
output reg VAR28
);
wire [3:0] VAR23, VAR26;
assign VAR23 = VAR30[3:0];
assign VAR26 = VAR30[7:4];
reg [15:0] VAR17;
wire [15:0] VAR14, VAR3, VAR13;
wire VAR6,... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/dma_queue/cpu_dma_queue_regs.v | 3,256 | module MODULE1
parameter VAR15 = 125000
)
(
input VAR8,
input VAR20,
input VAR13,
input [VAR2-1:0] VAR6,
input [VAR5-1:0] VAR11,
output reg [VAR5-1:0] VAR9,
output reg VAR7,
input reset,
input clk
);
function integer VAR14;
input integer VAR19;
begin
VAR14=0;
while(2**VAR14<VAR19) begin
VAR14=VAR14+1;
end
end
endfuncti... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3b/sky130_fd_sc_hs__and3b.behavioral.pp.v | 1,888 | module MODULE1 (
VAR13,
VAR11,
VAR14 ,
VAR10 ,
VAR1 ,
VAR3
);
input VAR13;
input VAR11;
output VAR14 ;
input VAR10 ;
input VAR1 ;
input VAR3 ;
wire VAR6 ;
wire VAR8 ;
wire VAR4;
not VAR12 (VAR6 , VAR10 );
and VAR9 (VAR8 , VAR3, VAR6, VAR1 );
VAR5 VAR2 (VAR4, VAR8, VAR13, VAR11);
buf VAR7 (VAR14 , VAR4 );
endmodule | apache-2.0 |
jotego/jt12 | hdl/deprecated/jt12_mod6.v | 1,195 | module MODULE1
(
input [2:0] in, input [2:0] sum,
output reg [2:0] out );
reg [3:0] VAR1;
always @(*) begin
VAR1 <= in+sum;
case( VAR1 )
4'd6: out <= 3'd0;
4'd7: out <= 3'd1;
4'd8: out <= 3'd2;
4'd9: out <= 3'd3;
4'ha: out <= 3'd4;
4'hb: out <= 3'd5;
4'hc: out <= 3'd0;
4'he: out <= 3'd1;
4'hf: out <= 3'd2;
default: out... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32o/sky130_fd_sc_ms__a32o.behavioral.pp.v | 2,224 | module MODULE1 (
VAR5 ,
VAR17 ,
VAR15 ,
VAR7 ,
VAR9 ,
VAR6 ,
VAR3,
VAR12,
VAR16 ,
VAR13
);
output VAR5 ;
input VAR17 ;
input VAR15 ;
input VAR7 ;
input VAR9 ;
input VAR6 ;
input VAR3;
input VAR12;
input VAR16 ;
input VAR13 ;
wire VAR2 ;
wire VAR11 ;
wire VAR20 ;
wire VAR1;
and VAR4 (VAR2 , VAR7, VAR17, VAR15 );
and VAR... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/dram/rtl/dram_ucb.v | 8,670 | module MODULE1(
VAR70, VAR31, VAR40,
VAR24, VAR46, VAR33, VAR79,
VAR55, VAR72, VAR105,
VAR48,
clk, VAR44, VAR7,
VAR61, VAR58, VAR106, VAR45,
VAR20, VAR95, VAR69,
VAR73, VAR76, VAR96, VAR75,
VAR88, VAR2
);
output VAR70;
output VAR31;
output VAR40;
output VAR24;
output [31:0] VAR46;
output [63:0] VAR33;
output [3:0] VAR7... | gpl-2.0 |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_AWSF1/mkGPR_RegFile.v | 6,921 | module MODULE1(VAR34,
VAR72,
VAR51,
VAR6,
VAR43,
VAR56,
VAR4,
VAR1,
VAR40,
VAR32,
VAR71,
VAR63,
VAR54,
VAR29,
VAR11);
input VAR34;
input VAR72;
input VAR51;
output VAR6;
input VAR43;
output VAR56;
input [4 : 0] VAR4;
output [63 : 0] VAR1;
input [4 : 0] VAR40;
output [63 : 0] VAR32;
input [4 : 0] VAR71;
output [63 : 0] ... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/dram/rtl/dram_ecc_gen.v | 15,878 | module MODULE1 (
VAR21,
VAR30,
VAR63
);
input [127:0] VAR21;
output [111:0] VAR30;
output [15:0] VAR63;
wire [3:0] VAR61;
wire [3:0] VAR16;
wire [3:0] VAR68;
wire [3:0] VAR4;
wire [3:0] VAR11;
wire [3:0] VAR12;
wire [3:0] VAR1;
wire [3:0] VAR59;
wire [3:0] VAR20;
wire [3:0] VAR14;
wire [3:0] VAR36;
wire [3:0] VAR3;
wir... | gpl-2.0 |
YosysHQ/yosys | techlibs/fabulous/regfile_map.v | 1,431 | module \VAR32 (...);
parameter VAR40 = "";
localparam [0:0] VAR18 = VAR40[15:8] == "VAR13";
localparam [0:0] VAR21 = VAR40[23:16] == "VAR13";
localparam VAR36 = 4;
localparam VAR49 = 5;
input [VAR36-1:0] VAR14;
input [VAR49-1:0] VAR8;
input VAR51;
output [VAR36-1:0] VAR3;
input [VAR49-1:0] VAR28;
output [VAR36-1:0] VAR... | isc |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4/sky130_fd_sc_lp__and4.behavioral.v | 1,392 | module MODULE1 (
VAR7,
VAR2,
VAR6,
VAR11,
VAR4
);
output VAR7;
input VAR2;
input VAR6;
input VAR11;
input VAR4;
supply1 VAR12;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR9 ;
wire VAR3;
and VAR1 (VAR3, VAR2, VAR6, VAR11, VAR4 );
buf VAR10 (VAR7 , VAR3 );
endmodule | apache-2.0 |
Franderg/CE-4301-Arqui1 | Processor/InstructionMem.v | 2,394 | module MODULE1(VAR7,clk,VAR2,VAR3,VAR8,VAR9,VAR11,VAR6,VAR10,VAR4);
input clk;
input [31:0] VAR7;
output [4:0] VAR2;
output [4:0] VAR3, VAR8, VAR9;
output reg [31:0] VAR10;
output [31:0] VAR4;
output [16:0] VAR11;
output [31:0] VAR6;
reg [0:0] VAR1;
reg [31:0] VAR5 [0:127]; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkinv/sky130_fd_sc_hs__clkinv.pp.blackbox.v | 1,198 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR1,
VAR4
);
output VAR3 ;
input VAR2 ;
input VAR1;
input VAR4;
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_mm_interconnect_0_avalon_st_adapter_010.v | 6,185 | module MODULE1 #(
parameter VAR6 = 130,
parameter VAR20 = 0,
parameter VAR12 = 130,
parameter VAR3 = 0,
parameter VAR14 = 0,
parameter VAR5 = 0,
parameter VAR8 = 1,
parameter VAR13 = 1,
parameter VAR23 = 0,
parameter VAR19 = 130,
parameter VAR2 = 0,
parameter VAR16 = 1,
parameter VAR9 = 0,
parameter VAR11 = 1,
paramete... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21boi/sky130_fd_sc_lp__a21boi_2.v | 2,332 | module MODULE2 (
VAR1 ,
VAR8 ,
VAR10 ,
VAR2,
VAR4,
VAR6,
VAR9 ,
VAR7
);
output VAR1 ;
input VAR8 ;
input VAR10 ;
input VAR2;
input VAR4;
input VAR6;
input VAR9 ;
input VAR7 ;
VAR3 VAR5 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR7(VAR7)
);
endmodule
module MODULE2 ... | apache-2.0 |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/mi_nios/synthesis/submodules/mi_nios_sysid.v | 1,446 | module MODULE1 (
address,
VAR2,
VAR3,
VAR1
)
;
output [ 31: 0] VAR1;
input address;
input VAR2;
input VAR3;
wire [ 31: 0] VAR1;
assign VAR1 = address ? 1432137269 : 0;
endmodule | mit |
monotone-RK/FACE | IEICE-Trans/8-way/src/riffa/rxc_engine_128.v | 19,769 | module MODULE1
parameter VAR114=10)
( input VAR143,
input VAR60, input VAR42, output VAR77,
input [VAR100-1:0] VAR22,
input VAR130,
input VAR78,
input [VAR5-1:0] VAR88,
input VAR35,
input [VAR5-1:0] VAR134,
input [VAR63-1:0] VAR62,
output [VAR100-1:0] VAR21,
output VAR116,
output [(VAR100/32)-1:0] VAR94,
output VAR7,
o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3b/sky130_fd_sc_ls__nand3b.pp.blackbox.v | 1,320 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR7 ,
VAR2 ,
VAR1,
VAR6,
VAR8 ,
VAR5
);
output VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR2 ;
input VAR1;
input VAR6;
input VAR8 ;
input VAR5 ;
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_057.v | 1,616 | module MODULE2 (
VAR7,
VAR8
);
input [31:0] VAR7;
output [31:0]
VAR8;
wire [31:0]
VAR3,
VAR4,
VAR12,
VAR6,
VAR1,
VAR10,
VAR16,
VAR11,
VAR15,
VAR5,
VAR9;
assign VAR3 = VAR7;
assign VAR10 = VAR1 << 3;
assign VAR16 = VAR1 + VAR10;
assign VAR1 = VAR12 - VAR6;
assign VAR4 = VAR3 << 11;
assign VAR12 = VAR3 + VAR4;
assign VAR... | mit |
asicguy/gplgpu | hdl/vga/pixel_panning.v | 4,451 | module MODULE1
(
input din,
input clk, input VAR9, input [3:0] VAR2, input VAR6,
input VAR7,
input VAR10,
output dout,
output VAR8
);
reg [8:0] VAR5;
reg [7:0] VAR1;
wire [7:0] VAR4;
wire [7:0] VAR3;
assign VAR4[7] = VAR1[7] ? din : VAR5[8];
assign VAR4[6] = VAR1[6] ? din : VAR5[7];
assign VAR4[5] = VAR1[5] ? din : VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2/sky130_fd_sc_lp__and2.symbol.v | 1,260 | module MODULE1 (
input VAR2,
input VAR3,
output VAR1
);
supply1 VAR6;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_example_top_33.v | 7,066 | module MODULE1 (
VAR63,
VAR8,
VAR1,
VAR51,
VAR13,
VAR26,
VAR2,
VAR58,
VAR15,
VAR57,
VAR18,
VAR17,
VAR36,
VAR68,
VAR16,
VAR39,
VAR4,
VAR66,
VAR61,
VAR7,
VAR21
)
;
output [ 12: 0] VAR1;
output [ 2: 0] VAR51;
output VAR13;
output [ 0: 0] VAR26;
inout [ 0: 0] VAR2;
inout [ 0: 0] VAR58;
output [ 0: 0] VAR15;
output [ 7: 0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s.pp.blackbox.v | 1,342 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR5,
VAR3,
VAR1 ,
VAR6
);
output VAR4 ;
input VAR2 ;
input VAR5;
input VAR3;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
YosysHQ/yosys | techlibs/xilinx/lutrams_xc5v_map.v | 19,522 | module MODULE6 (...);
parameter VAR19 = 0;
parameter VAR37 = 5;
parameter VAR6 = 8;
parameter VAR86 = 0;
output [VAR6-1:0] VAR35;
input [VAR6-1:0] VAR9;
input [VAR37-1:0] VAR106;
input VAR41;
input VAR73;
function [(1 << VAR37)-1:0] VAR3;
input integer VAR65;
integer VAR60;
for (VAR60 = 0; VAR60 < (1 << VAR37); VAR60 =... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlrtp/sky130_fd_sc_hvl__dlrtp.pp.symbol.v | 1,438 | module MODULE1 (
input VAR8 ,
output VAR6 ,
input VAR5,
input VAR4 ,
input VAR3 ,
input VAR2 ,
input VAR1 ,
input VAR7
);
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/redundant/ovl_unchange.v | 2,137 | module MODULE1 (VAR16, reset, enable, VAR12, VAR18, VAR6);
parameter VAR25 = VAR14;
parameter VAR22 = 1;
parameter VAR15 = 1;
parameter VAR4 = VAR9;
parameter VAR7 = VAR10;
parameter VAR11 = VAR3;
parameter VAR23 = VAR13;
parameter VAR2 = VAR19;
parameter VAR1 = VAR21;
parameter VAR24 = VAR8;
input VAR16, reset, enable... | mit |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_vdivops.v | 2,512 | module MODULE1(
input VAR11,
input VAR1,
output VAR7,
input VAR24,
output VAR30,
input signed [17:0] VAR29,
input signed [17:0] VAR21,
input signed [17:0] VAR26,
input signed [17:0] VAR20,
input signed [17:0] VAR12,
input signed [17:0] VAR25,
input signed [17:0] VAR8,
input signed [17:0] VAR3,
input signed [11:0] VAR2,... | lgpl-3.0 |
asicguy/gplgpu | hdl/hbi/hbi_yuv2rgb.v | 7,114 | module MODULE1
(
input VAR35, input [31:0] VAR30, input [2:0] VAR4, input [9:0] VAR12, input [9:0] VAR24, input [9:0] VAR18, input [9:0] VAR19, input VAR31, input select,
output reg [31:0] VAR8,
output reg [7:0] VAR13, output reg [7:0] VAR21 );
reg [10:0] VAR26;
reg [10:0] VAR2, VAR10, VAR20;
reg [10:0] VAR6, VAR22, VA... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/Altera/audio_clock/audio_clock_0002.v | 2,075 | module MODULE1(
input wire VAR62,
input wire rst,
output wire VAR53,
output wire VAR58
);
VAR37 #(
.VAR56("true"),
.VAR41("50.0 VAR17"),
.VAR11("VAR52"),
.VAR64(1),
.VAR72("3.072000 VAR17"),
.VAR7("0 VAR68"),
.VAR33(50),
.VAR13("0 VAR17"),
.VAR35("0 VAR68"),
.VAR44(50),
.VAR9("0 VAR17"),
.VAR61("0 VAR68"),
.VAR21(50),
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2b/sky130_fd_sc_hd__or2b_2.v | 2,127 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR2 ,
VAR1,
VAR5,
VAR3 ,
VAR4
);
output VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR1;
input VAR5;
input VAR3 ;
input VAR4 ;
VAR8 VAR9 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR6 ,
VAR7 ,
VAR2
);
output VAR6... | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/playback_driver.v | 6,758 | module MODULE1();
parameter VAR4=157;
parameter VAR5=130;
parameter VAR1=1;
reg [256*8-1:0] VAR3;
reg [256*8-1:0] VAR2;
begin
end else
begin | gpl-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_fsm.v | 6,274 | module MODULE1 #(
parameter integer VAR1 = 1,
parameter integer VAR4 = 0
)
(
input wire clk ,
input wire reset ,
output reg VAR3 ,
input wire VAR7 ,
output wire VAR6 ,
input wire VAR10 ,
output wire VAR2 ,
input wire VAR8 ,
input wire VAR5 ,
output wire VAR9
);
assign VAR6 = (VAR7 & VAR5);
assign VAR2 = (~VAR10 & VAR6)... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.functional.pp.v | 1,751 | module MODULE1( VAR11, VAR10, VAR19, VAR26, VAR4, VAR17, VAR18, VAR9, VAR24 );
input VAR26, VAR19, VAR11, VAR4, VAR10, VAR18, VAR9, VAR24;
output VAR17;
not VAR5( VAR25, VAR4 );
wire VAR27;
not VAR20( VAR27, VAR19 );
wire VAR15;
not VAR8( VAR15, VAR11 );
wire VAR28;
and VAR6( VAR28, VAR27, VAR15 );
wire VAR13;
not VAR2... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController4L/src/pcie_hcmd_sq_arb.v | 12,546 | module MODULE1 # (
parameter VAR35 = 128,
parameter VAR53 = 36
)
(
input VAR27,
input VAR32,
input [8:0] VAR9,
input [8:0] VAR18,
input [7:0] VAR1,
input [7:0] VAR22,
input [7:0] VAR52,
input [7:0] VAR41,
input [7:0] VAR42,
input [7:0] VAR10,
input [7:0] VAR31,
input [7:0] VAR50,
input [7:0] VAR61,
input [VAR53-1:2] VA... | gpl-3.0 |
bgamari/timetag-fpga | reg_manager.v | 2,217 | module MODULE1(
clk,
VAR2, VAR13,
VAR3, VAR1, VAR7, VAR6,
VAR10, VAR4, VAR8
);
input clk;
input VAR2;
input [7:0] VAR13;
output [7:0] VAR3;
output VAR1;
input VAR7;
output VAR6;
output [15:0] VAR10;
inout [31:0] VAR4;
output VAR8;
reg [15:0] addr;
reg [31:0] VAR12;
reg [4:0] state;
reg VAR11;
VAR9 state = 0;
always @(p... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2/sky130_fd_sc_hs__nor2.pp.blackbox.v | 1,207 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR5 ,
VAR3,
VAR1
);
output VAR4 ;
input VAR2 ;
input VAR5 ;
input VAR3;
input VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4b/sky130_fd_sc_hs__nand4b_1.v | 2,184 | module MODULE2 (
VAR6 ,
VAR8 ,
VAR7 ,
VAR5 ,
VAR4 ,
VAR3,
VAR9
);
output VAR6 ;
input VAR8 ;
input VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR3;
input VAR9;
VAR1 VAR2 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR6 ,
VAR8,
VAR7 ,
VAR5 ,
VAR4
... | apache-2.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab09/lab09/Code/CPU/MDPath_IO.v | 1,112 | module MODULE1(input clk,
input reset,
input VAR17, input VAR2,
input VAR9,
input[1:0] VAR4,
input VAR8,
input[1:0]VAR18,
input VAR11,
input[1:0]VAR19,
input[1:0]VAR5,
input VAR16,
input VAR3,
input VAR12,
input[2:0]VAR6,
output[31:0]VAR1,
input[31:0]VAR13,
output[31:0]VAR14,
output[31:0]VAR15,
output[31:0]VAR7,
output... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nand2/sky130_fd_sc_hvl__nand2.pp.symbol.v | 1,273 | module MODULE1 (
input VAR5 ,
input VAR6 ,
output VAR3 ,
input VAR1 ,
input VAR4,
input VAR2,
input VAR7
);
endmodule | apache-2.0 |
zhijian-liu/mips-cpu | src/cpu/cpu.v | 17,260 | module MODULE1(
input VAR122 ,
input reset ,
output [31:0] VAR88 ,
input [31:0] VAR26 ,
output VAR86 ,
output [31:0] VAR38 ,
input [31:0] VAR3 ,
output VAR99 ,
output [31:0] VAR35,
output [ 3:0] VAR85 ,
output [31:0] VAR133
);
wire [ 5:0] VAR113;
wire VAR8 ;
wire [ 4:0] VAR130;
wire [31:0] VAR145 ;
wire VAR28 ;
wire [ ... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/example_design/PIO.v | 5,986 | module MODULE1 #(
parameter VAR10 = 64,
parameter VAR14 = VAR10 / 8, parameter VAR18 = 1
)(
input VAR15,
input VAR28,
input VAR26,
input VAR3,
output [VAR10-1:0] VAR2,
output [VAR14-1:0] VAR1,
output VAR16,
output VAR24,
output VAR23,
input [VAR10-1:0] VAR12,
input [VAR14-1:0] VAR8,
input VAR21,
input VAR6,
output VAR1... | lgpl-3.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/wb_bfm/wb_bfm_transactor.v | 5,499 | module MODULE1
parameter VAR10 = 32,
parameter VAR23 = 0,
parameter VAR20 = 5,
parameter VAR18 = 0,
parameter VAR7 = 32'hffffffff)
(input VAR13,
input VAR11,
output [VAR15-1:0] VAR16,
output [VAR10-1:0] VAR3,
output [3:0] VAR2,
output VAR5,
output VAR21,
output VAR19,
output [2:0] VAR17,
output [1:0] VAR9,
input [VAR10... | gpl-2.0 |
marqs85/ossc | ip/i2c_opencores/i2c_opencores.v | 2,172 | module MODULE1
(
VAR3, VAR13, VAR17, VAR7, VAR1,
VAR15, VAR8, VAR21, VAR16,
VAR11, VAR18, VAR12
);
parameter VAR23 = 0;
input VAR3; input VAR13;
input [2:0] VAR17; input [7:0] VAR7; output [7:0] VAR1; input VAR15; input VAR8; output VAR21; output VAR16;
inout VAR11; inout VAR18;
input VAR12;
wire VAR19; wire VAR4;
wire... | gpl-3.0 |
olajep/oh | src/common/hdl/oh_csa92.v | 2,377 | module MODULE1 #( parameter VAR15 = 1)
( input [VAR15-1:0] VAR31, input [VAR15-1:0] VAR12, input [VAR15-1:0] VAR25, input [VAR15-1:0] VAR7, input [VAR15-1:0] VAR16, input [VAR15-1:0] VAR11, input [VAR15-1:0] VAR8, input [VAR15-1:0] VAR26, input [VAR15-1:0] VAR27, input [VAR15-1:0] VAR9, input [VAR15-1:0] VAR1, input [V... | mit |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_4/hdl/verilog/feedforward_mux_4to1_sel2_32_1.v | 1,213 | module MODULE1 #(
parameter
VAR13 = 0,
VAR3 = 1,
VAR14 = 32,
VAR5 = 32,
VAR10 = 32,
VAR2 = 32,
VAR9 = 32,
VAR12 = 32
)(
input [31 : 0] VAR15,
input [31 : 0] VAR8,
input [31 : 0] VAR16,
input [31 : 0] VAR1,
input [1 : 0] VAR6,
output [31 : 0] dout);
wire [1 : 0] sel;
wire [31 : 0] VAR7;
wire [31 : 0] VAR4;
wire [31 : 0]... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/s3_dqs_iob.v | 3,728 | module MODULE1(
clk,
VAR13,
VAR20,
VAR30,
VAR6,
VAR21
);
input clk;
input VAR13;
input VAR20;
input VAR30;
inout VAR6;
output VAR21;
parameter VAR26 = 1'b1;
parameter VAR1 = 1'b0;
wire VAR9;
wire VAR2;
wire VAR23;
wire VAR5;
assign VAR23 = ~VAR30;
assign VAR5 = (VAR20 == 1'b1) ? 1'b0 : 1'b1;
VAR31 VAR32 (
.VAR8(VAR23),... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxbp/sky130_fd_sc_ls__sedfxbp.behavioral.v | 2,734 | module MODULE1 (
VAR9 ,
VAR1,
VAR14,
VAR25 ,
VAR7 ,
VAR18,
VAR27
);
output VAR9 ;
output VAR1;
input VAR14;
input VAR25 ;
input VAR7 ;
input VAR18;
input VAR27;
supply1 VAR19;
supply0 VAR28;
supply1 VAR22 ;
supply0 VAR29 ;
wire VAR3 ;
reg VAR10 ;
wire VAR12 ;
wire VAR21 ;
wire VAR11;
wire VAR2;
wire VAR8;
wire VAR30 ;
... | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/profile_sink.v | 3,966 | module MODULE1 (
VAR23,
VAR1);
parameter VAR12 = 1;
parameter VAR4 = 128;
input [VAR4-1:0] VAR23;
output VAR1;
wire VAR19;
wire VAR1 = VAR19;
VAR14 VAR5 (
.VAR23 (VAR23),
.VAR1 (VAR19)
,
.VAR6 (),
.VAR11 (),
.VAR30 (),
.VAR17 (),
.VAR25 (),
.VAR32 (),
.VAR15 (),
.VAR26 (),
.VAR9 (),
.VAR27 (),
.VAR31 (),
.VAR21 (),
.VA... | mit |
somethingnew2-0/CS552-CPU | RoadRunner/off_by_one.tar.gz_extracted/ID.v | 2,991 | module MODULE1(VAR16, VAR31, VAR21, VAR26, VAR25, VAR30, VAR14, VAR1, VAR29, VAR12, VAR3, VAR2, VAR5, VAR15, VAR20, VAR28, VAR13, VAR7, VAR23, VAR24, VAR11, VAR9);
input [15:0] VAR16;
output [11:0] VAR31;
output [3:0] VAR21, VAR26, VAR25, VAR30;
output [2:0] VAR14, VAR1;
output VAR29, VAR12, VAR3, VAR2, VAR5, VAR15, VA... | mit |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_filter_block.v | 2,663 | module MODULE1
parameter VAR19 = 1, parameter VAR17 = 4, parameter VAR14 = 14, parameter VAR11 = 10
)
(
input VAR5,
input VAR15 ,
input [32-1:0] VAR13,
input signed [VAR14-1:0] VAR8,
output signed [VAR14-1:0] VAR16
);
wire signed [VAR14-1:0] VAR3[VAR19-1:0];
wire signed [VAR14-1:0] VAR7[VAR19-1:0];
assign VAR3[0] = VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221a/sky130_fd_sc_lp__o221a.blackbox.v | 1,395 | module MODULE1 (
VAR2 ,
VAR6,
VAR9,
VAR8,
VAR7,
VAR1
);
output VAR2 ;
input VAR6;
input VAR9;
input VAR8;
input VAR7;
input VAR1;
supply1 VAR3;
supply0 VAR4;
supply1 VAR10 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fahcon/sky130_fd_sc_ls__fahcon.pp.blackbox.v | 1,396 | module MODULE1 (
VAR9,
VAR1 ,
VAR6 ,
VAR5 ,
VAR2 ,
VAR3 ,
VAR7 ,
VAR4 ,
VAR8
);
output VAR9;
output VAR1 ;
input VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR3 ;
input VAR7 ;
input VAR4 ;
input VAR8 ;
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/mig_7series_v1_8_iodelay_ctrl.v | 9,075 | module MODULE1 #
(
parameter VAR23 = 100,
parameter VAR26 = "VAR27",
parameter VAR25 = "VAR45",
parameter VAR33 = "VAR45",
parameter VAR40 = 1,
parameter VAR6 = "VAR37"
)
(
input VAR2,
input VAR4,
input VAR21,
input VAR28,
output VAR22,
output VAR3
);
localparam VAR41 = 15;
wire VAR29;
wire VAR19;
wire VAR31;
reg [VAR4... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3/sky130_fd_sc_hs__nand3.symbol.v | 1,244 | module MODULE1 (
input VAR4,
input VAR3,
input VAR1,
output VAR5
);
supply1 VAR2;
supply0 VAR6;
endmodule | apache-2.0 |
tmeissner/cryptocores | cbctdes/rtl/verilog/des.v | 10,850 | module MODULE1
(
input VAR37, input VAR59, input VAR15, input [0:63] VAR47, input [0:63] VAR48, input VAR51, output reg [0:63] VAR70, output VAR80 );
reg [0:18] valid;
reg [0:17] VAR13;
reg [0:27] VAR32;
reg [0:27] VAR68;
reg [0:27] VAR11;
reg [0:27] VAR56;
reg [0:27] VAR86;
reg [0:27] VAR96;
reg [0:27] VAR28;
reg [0:2... | gpl-2.0 |
kyzhai/NUNY | src/hardware/zero_new2.v | 6,400 | module MODULE1 (
address,
VAR2,
VAR21);
input [9:0] address;
input VAR2;
output [11:0] VAR21;
tri1 VAR2;
wire [11:0] VAR8;
wire [11:0] VAR21 = VAR8[11:0];
VAR9 VAR52 (
.VAR1 (address),
.VAR29 (VAR2),
.VAR5 (VAR8),
.VAR37 (1'b0),
.VAR6 (1'b0),
.VAR34 (1'b1),
.VAR7 (1'b0),
.VAR49 (1'b0),
.VAR10 (1'b1),
.VAR45 (1'b1),
.VA... | gpl-2.0 |
alexforencich/xfcp | lib/eth/example/VCU108/fpga_1g/rtl/fpga.v | 9,745 | module MODULE1 (
input wire VAR141,
input wire VAR76,
input wire reset,
input wire VAR149,
input wire VAR29,
input wire VAR85,
input wire VAR43,
input wire VAR108,
input wire [3:0] VAR86,
output wire [7:0] VAR14,
input wire VAR79,
input wire VAR167,
output wire VAR154,
output wire VAR26,
input wire VAR155,
input wire V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_ps_pp_pkg_s/sky130_fd_sc_hs__udp_dff_ps_pp_pkg_s.symbol.v | 1,498 | module MODULE1 (
input VAR6 ,
output VAR7 ,
input VAR5 ,
input VAR3 ,
input VAR4,
input VAR1 ,
input VAR2 ,
input VAR8
);
endmodule | apache-2.0 |
MCDELTAT/CSE311 | lab1/right_barrel_shifter.v | 1,053 | module MODULE1(
input [7:0] din,
input [2:0] VAR1,
output reg [7:0] dout
);
always @* begin
case (VAR1)
0 : dout = din;
1 : dout = {din[0], din[7:1]}; 2 : dout = {din[1:0], din[7:2]};
3 : dout = {din[2:0], din[7:3]};
4 : dout = {din[3:0], din[7:4]};
5 : dout = {din[4:0], din[7:5]};
6 : dout = {din[5:0], din[7:6]};
7 : ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21bo/sky130_fd_sc_hdll__a21bo.blackbox.v | 1,391 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR6 ,
VAR1
);
output VAR2 ;
input VAR5 ;
input VAR6 ;
input VAR1;
supply1 VAR3;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21bo/sky130_fd_sc_ms__a21bo.behavioral.v | 1,579 | module MODULE1 (
VAR12 ,
VAR2 ,
VAR6 ,
VAR5
);
output VAR12 ;
input VAR2 ;
input VAR6 ;
input VAR5;
supply1 VAR10;
supply0 VAR13;
supply1 VAR7 ;
supply0 VAR9 ;
wire VAR1 ;
wire VAR8;
nand VAR4 (VAR1 , VAR6, VAR2 );
nand VAR11 (VAR8, VAR5, VAR1);
buf VAR3 (VAR12 , VAR8 );
endmodule | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_i2c_lcd/zybo_petalinux_i2c_lcd.srcs/sources_1/bd/block_design/ipshared/xilinx.com/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_axi_slave.v | 37,590 | module MODULE1 (
VAR23,
VAR133,
VAR126,
VAR12,
VAR148,
VAR127,
VAR170,
VAR153,
VAR37,
VAR44,
VAR139,
VAR82,
VAR149,
VAR31,
VAR100,
VAR116,
VAR167,
VAR174,
VAR59,
VAR1,
VAR47,
VAR84,
VAR38,
VAR83,
VAR45,
VAR17,
VAR20,
VAR60,
VAR137,
VAR168,
VAR57,
VAR85,
VAR119,
VAR154,
VAR147,
VAR163,
VAR53,
VAR55,
VAR178,
VAR114,
VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.v | 2,587 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR8 ,
VAR10 ,
VAR3 ,
VAR5,
VAR11 ,
VAR6 ,
VAR2 ,
VAR12
);
output VAR4 ;
input VAR1 ;
input VAR8 ;
input VAR10 ;
input VAR3 ;
input VAR5;
input VAR11 ;
input VAR6 ;
input VAR2 ;
input VAR12 ;
VAR9 VAR7 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/support_memory_if.v | 1,846 | module MODULE1 (
input clk,
input [7:0] VAR14, input [15:0] VAR15,
input [7:0] VAR11,
output [7:0] VAR16,
input VAR2,
input VAR5,
input [15:0] VAR3,
input [7:0] VAR10,
input VAR13
);
wire VAR8 = (VAR15[15:8] >= VAR14);
wire [15:0] VAR12;
wire [7:0] VAR1;
wire wr;
assign VAR12 = (VAR5) ? VAR3 : VAR15;
assign VAR1 = (VAR... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/HardFloat/source/RISCV/HardFloat_specialize.v | 2,287 | module
MODULE1#(parameter VAR3 = 1) (
input VAR1,
input VAR2,
input VAR4,
output [(VAR3 - 1):0] out
);
wire VAR5 = VAR2 || !VAR4;
assign out = {VAR1 ^ VAR5, {(VAR3 - 1){VAR5}}};
endmodule | bsd-3-clause |
Jawanga/ece385final | finalproject/synthesis/finalproject.v | 49,639 | module MODULE1 (
input wire VAR139, output wire [7:0] VAR295, input wire VAR274, output wire VAR283, output wire [12:0] VAR344, output wire [1:0] VAR3, output wire VAR197, output wire VAR149, output wire VAR140, inout wire [31:0] VAR236, output wire [3:0] VAR144, output wire VAR176, output wire VAR268, inout wire [15:0... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_tag/bsg_tag_client_unsync.v | 2,992 | module MODULE1
import VAR23::VAR11;
(
input VAR11 VAR14
,output [VAR16-1:0] VAR4
);
logic VAR20, VAR19;
VAR31 @(posedge VAR14.clk)
begin
VAR20 <= VAR14.VAR32;
VAR19 <= VAR14.VAR9;
end
wire VAR26 = VAR20;
wire VAR6 = ~VAR20 & ~VAR19;
logic [VAR16-1:0] VAR30, VAR22, VAR2;
if (VAR16 > 1)
begin : VAR12
assign VAR2 = { VAR1... | bsd-3-clause |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_fp_mul_fast_double.v | 37,708 | module MODULE1
(
VAR18,
VAR88,
VAR59,
VAR4,
VAR19) ;
input VAR18;
input VAR88;
input [63:0] VAR59;
input [63:0] VAR4;
output [63:0] VAR19;
tri1 VAR18;
reg VAR28;
reg VAR82;
reg VAR49;
reg VAR29;
reg VAR34;
reg VAR6;
reg VAR5;
reg VAR73;
reg [12:0] VAR57;
reg [12:0] VAR61;
reg [12:0] VAR30;
reg VAR36;
reg VAR70;
reg VAR... | mit |
mrehkopf/sd2snes | verilog/sd2snes_mini/mcu_cmd.v | 3,366 | module MODULE1(
input clk,
input VAR22,
input VAR5,
input [7:0] VAR8,
input [7:0] VAR14,
output reg VAR12 = 0,
output reg VAR15 = 0,
input VAR21,
output [7:0] VAR1,
input [7:0] VAR3,
output [7:0] VAR20,
input [31:0] VAR16,
input [2:0] VAR6,
output [23:0] VAR11,
output [23:0] VAR9,
output [23:0] VAR7
);
reg [7:0] VAR19;... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_1.behavioral.pp.v | 1,167 | module MODULE1( VAR6, VAR2, VAR7, VAR5 );
input VAR6;
inout VAR7, VAR5;
output VAR2;
VAR3 VAR4(.VAR6(VAR6),.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5));
VAR3 VAR1(.VAR6(VAR6),.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5)); | apache-2.0 |
Elphel/x393_sata | wrapper/GTXE2_GPL.v | 124,713 | module MODULE2(
input wire [2:0] VAR2,
input wire VAR42,
input wire VAR46,
input wire VAR18,
input wire VAR8,
input wire VAR37,
input wire VAR34,
input wire VAR14,
output wire VAR23
);
assign VAR23 = VAR2 == 3'b000 ? 1'b0 : VAR2 == 3'b001 ? VAR42
: VAR2 == 3'b010 ? VAR46
: VAR2 == 3'b011 ? VAR18
: VAR2 == 3'b100 ? VAR8... | gpl-3.0 |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/hdl/fmrv32im_artya7.v | 15,674 | module MODULE2
(VAR83,
VAR104,
VAR95,
VAR64,
VAR134,
VAR61);
input VAR83;
input [31:0]VAR104;
output [31:0]VAR95;
output [31:0]VAR64;
input VAR134;
output VAR61;
wire VAR178;
wire [0:0]VAR8;
wire [31:0]VAR224;
wire [3:0]VAR201;
wire [2:0]VAR239;
wire VAR180;
wire VAR103;
wire [31:0]VAR127;
wire [3:0]VAR90;
wire [2:0]VA... | mit |
shaform/ArkanoidOnVerilog | word.v | 3,430 | module MODULE1(
input [4:0] VAR1, VAR3,
input [1:0] select,
output MODULE1
);
reg [19:0] VAR2;
always @(VAR1,VAR3,select,VAR2[19:0])
begin
case (select)
2'b00: case(VAR1) 5'b00000: VAR2 = 20'b00000000000000000000;
5'b00001: VAR2 = 20'b00000111111111100000;
5'b00010: VAR2 = 20'b00011000000000011000;
5'b00011: VAR2 = 20'... | gpl-3.0 |
cafe-alpha/wascafe | v13/wasca_10m08sc_20191205_abus_divide/wasca/wasca_bb.v | 2,144 | module MODULE1 (
VAR19,
VAR15,
VAR20,
VAR12,
VAR9,
VAR13,
VAR29,
VAR18,
VAR27,
VAR22,
VAR16,
VAR26,
VAR5,
VAR28,
VAR17,
VAR4,
VAR24,
VAR23,
VAR8,
VAR2,
VAR25,
VAR1,
VAR7,
VAR6,
VAR21,
VAR3,
VAR11,
VAR14,
VAR10);
input [9:0] VAR19;
input [2:0] VAR15;
input VAR20;
input [1:0] VAR12;
output VAR9;
output VAR13;
inout [15:0... | gpl-2.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Proyectos Funcionales Francis Jeffrey/CORDICO/CORDICO.srcs/sources_1/new/CORDIC_Arch3.v | 20,545 | module MODULE1 #(parameter VAR39 = 32, parameter VAR139 = 8, parameter VAR150 = 23, parameter VAR124=26, parameter VAR33 = 5)/*#(parameter VAR39 = 64, parameter VAR139 = 11, parameter VAR150 = 52, parameter VAR124 = 55, parameter VAR33 = 6) (
input wire clk, input wire rst, input wire VAR89, input wire VAR91, input wir... | gpl-3.0 |
kactus2/ipxactexamplelib | tut.fi/peripheral.logic/wb_dual_master/1.0/wb_master.v | 6,846 | module MODULE1 #(
parameter VAR14 = 0, parameter VAR3 = 16, parameter VAR20 = 16, parameter VAR10 = 16, parameter VAR1 = 1
)(
input clk, input rst, input VAR21, output reg VAR16,
output reg VAR8, output reg VAR7, input VAR18, output reg VAR11, output reg [VAR3-1:0] VAR12, input [VAR3-1:0] VAR6, output reg [VAR20-1:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregrbp/sky130_fd_sc_lp__sregrbp.behavioral.pp.v | 2,885 | module MODULE1 (
VAR7 ,
VAR22 ,
VAR3 ,
VAR31 ,
VAR30 ,
VAR10 ,
VAR32,
VAR2 ,
VAR15 ,
VAR12 ,
VAR11
);
output VAR7 ;
output VAR22 ;
input VAR3 ;
input VAR31 ;
input VAR30 ;
input VAR10 ;
input VAR32;
input VAR2 ;
input VAR15 ;
input VAR12 ;
input VAR11 ;
wire VAR6 ;
wire reset ;
wire VAR9 ;
reg VAR14 ;
wire VAR24 ;
wire... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/enet_if/v7_emac_controller.v | 1,892 | module MODULE1
(
input VAR18,
input VAR16,
output VAR9,
input VAR26, input VAR10, output VAR8, output VAR7, input VAR15, input VAR23,
output VAR12,
output VAR22,
input VAR4,
output VAR29,
output VAR1,
output VAR13,
output VAR2,
output VAR14,
output [7:0] VAR19,
output VAR20,
input VAR28,
output VAR6,
output VAR24,
outp... | mit |
lvd2/ngs | fpga/obsolete/fpgaE_dma/dma/dma_zx_old.v | 3,397 | module MODULE1(
input clk,
input VAR5,
input VAR22;
input VAR27;
output reg VAR11;
input [7:0] VAR10;
output reg [7:0] VAR24;
output reg VAR1;
input [7:0] din; output reg [7:0] dout;
input VAR26; input VAR2;
input [1:0] VAR21;
output reg [20:0] VAR25;
output reg [7:0] VAR28;
input [7:0] VAR18;
output reg VAR16;
output ... | gpl-3.0 |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_register_file.v | 21,356 | module MODULE1 (
VAR15, VAR31, VAR27, VAR7, VAR103, VAR131, VAR94, VAR115, VAR8, VAR72,
VAR48, VAR39, VAR135, VAR40, VAR61, VAR111, VAR124, VAR60, VAR107, VAR73, VAR86, VAR21, VAR132, VAR19, VAR89, VAR17, VAR9 );
output VAR15; output VAR31; output VAR27; output [15:0] VAR7; output VAR103; output [15:0] VAR131; output [... | bsd-3-clause |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/e69044ca/hdl/processing_system7_bfm_v2_0_axi_slave.v | 37,655 | module MODULE1 (
VAR173,
VAR54,
VAR41,
VAR144,
VAR15,
VAR169,
VAR113,
VAR138,
VAR86,
VAR112,
VAR6,
VAR176,
VAR63,
VAR123,
VAR11,
VAR163,
VAR32,
VAR162,
VAR92,
VAR104,
VAR31,
VAR27,
VAR135,
VAR154,
VAR35,
VAR153,
VAR96,
VAR148,
VAR45,
VAR105,
VAR91,
VAR73,
VAR83,
VAR108,
VAR133,
VAR57,
VAR29,
VAR26,
VAR39,
VAR106,
VAR12... | gpl-3.0 |
asicguy/gplgpu | hdl/vga/sm_graphic_crt.v | 5,897 | module MODULE1
(
input VAR17,
input VAR8,
input VAR24,
input VAR32,
input VAR21,
input VAR14,
input VAR10,
input VAR19,
input [7:0] VAR16,
input VAR13,
output VAR9,
output VAR12,
output VAR1,
output [30:0] VAR28
);
reg [2:0] VAR20;
reg [2:0] VAR4;
reg [3:0] VAR26;
reg VAR5;
reg VAR25, VAR31;
reg VAR30, VAR6;
reg [4:0] ... | gpl-3.0 |
lee-dohm/atom-linguist | samples/Verilog/pipeline_registers.v | 3,287 | module MODULE1
(
input clk,
input VAR2,
input [VAR5-1:0] VAR8,
output reg [VAR5-1:0] VAR3
);
parameter
VAR5 = 10,
VAR7 = 5;
generate
genvar VAR6;
if (VAR7 == 0) begin
always @ *
VAR3 = VAR8;
end
else if (VAR7 == 1) begin
always @ (posedge clk or negedge VAR2)
VAR3 <= (!VAR2) ? 0 : VAR8;
end
else begin
reg [VAR5*(VAR7-1... | mit |
ptracton/wb_soc_template | rtl/uart16550/rtl/verilog/uart_debug_if.v | 5,944 | module MODULE1 (
VAR13,
VAR4, VAR6, VAR3, VAR11, VAR5, VAR12, VAR14,
VAR7, VAR9, VAR10, VAR2, VAR1
) ;
input [VAR15-1:0] VAR4;
output [31:0] VAR13;
input [3:0] VAR6;
input [3:0] VAR3;
input [1:0] VAR11; input [4:0] VAR5;
input [7:0] VAR12;
input [7:0] VAR14;
input [7:0] VAR7;
input [VAR8-1:0] VAR9;
input [VAR8-1:0] VAR... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/ip_top/memc_ui_top.v | 32,382 | module MODULE1 #
(
parameter VAR154 = 200,
parameter VAR199 = "VAR141",
parameter VAR85 = "VAR141",
parameter VAR95 = "VAR5",
parameter VAR162 = 2,
parameter VAR192 = "VAR138",
parameter VAR17 = 1,
parameter VAR98 = 6,
parameter VAR148 = 3,
parameter VAR107 = 1,
parameter VAR103 = 3,
parameter VAR2 = 1,
parameter VAR31... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkbuf/sky130_fd_sc_hdll__clkbuf_1.v | 2,050 | module MODULE2 (
VAR7 ,
VAR3 ,
VAR6,
VAR8,
VAR5 ,
VAR2
);
output VAR7 ;
input VAR3 ;
input VAR6;
input VAR8;
input VAR5 ;
input VAR2 ;
VAR4 VAR1 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR7,
VAR3
);
output VAR7;
input VAR3;
supply1 VAR6;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/inv/sky130_fd_sc_hs__inv.blackbox.v | 1,168 | module MODULE1 (
VAR4,
VAR3
);
output VAR4;
input VAR3;
supply1 VAR1;
supply0 VAR2;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_4.functional.pp.v | 1,611 | module MODULE1( VAR2, VAR20, VAR12, VAR8, VAR15, VAR3, VAR1 );
input VAR12, VAR20, VAR8, VAR15;
inout VAR3, VAR1;
output VAR2;
wire VAR5;
not VAR17( VAR5, VAR12 );
wire VAR11;
not VAR18( VAR11, VAR8 );
wire VAR13;
not VAR4( VAR13, VAR15 );
wire VAR14;
and VAR19( VAR14, VAR5, VAR11, VAR13 );
wire VAR9;
not VAR6( VAR9, V... | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/axi_hdmi_tx/axi_hdmi_tx_core.v | 17,947 | module MODULE1 (
VAR10,
VAR27,
VAR118,
VAR97,
VAR39,
VAR67,
VAR83,
VAR80,
VAR65,
VAR100,
VAR45,
VAR123,
VAR7,
VAR115,
VAR30,
VAR138,
VAR21,
VAR120,
VAR24,
VAR87,
VAR25,
VAR119,
VAR23,
VAR31,
VAR72,
VAR38,
VAR55,
VAR130,
VAR139,
VAR36,
VAR59,
VAR105,
VAR116,
VAR6,
VAR75,
VAR104,
VAR52,
VAR89,
VAR95,
VAR125);
parameter V... | lgpl-3.0 |
ellore/processor | microprocessor.v | 4,143 | module MODULE1(VAR18,clk,VAR69,VAR89,VAR118,VAR21,VAR56,
VAR64,VAR34,VAR75,VAR32,VAR26,VAR114,VAR77
);
input[7:0] VAR18;
input clk;
output[7:0] VAR69;
output[15:0] VAR89;
output VAR118;
output[7:0] VAR21;
output[7:0] VAR56;
output[7:0] VAR64;
output[7:0] VAR34,VAR32,VAR26;
output[15:0] VAR75;
output VAR114,VAR77;
wire ... | mit |
liuyenting/CA-Project | src/GeneralControl.v | 2,853 | module MODULE1 (
input [5:0] VAR10,
input [5:0] VAR2,
input VAR7,
output reg [1:0] VAR1,
output reg [4:0] VAR12,
output reg [1:0] VAR8,
output reg [1:0] VAR4
);
always @ (*)
begin
case (VAR10)
begin
case (VAR2)
begin
VAR1 <= { 1'b0, 1'b0 };
VAR12 <= { VAR3, 1'b0, 1'b1 };
VAR8 <= { 1'b0, 1'b0 };
VAR4 <= { 1'b1, 1'b1 };
... | gpl-3.0 |
domahony/ButtonCount | ButtonCount.v | 1,769 | module MODULE1(input clk, input VAR15, output[7:0] VAR6, output[7:0] VAR7,
output VAR24);
wire VAR4, VAR9, VAR8;
VAR22 VAR1(
.clk (clk),
.VAR15 (VAR15),
.VAR4 (VAR4),
.VAR9 (VAR9),
.VAR8 (VAR8));
reg[3:0] d0 = 3'd0;
reg[3:0] d1 = 3'd0;
reg[3:0] d2 = 3'd0;
reg[3:0] d3 = 3'd0;
reg[3:0] d4 = 3'd0;
reg[3:0] d5 = 3'd0;
reg[... | mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_processing_system7_0_0/hdl/processing_system7_bfm_v2_0_ocmc.v | 4,023 | module MODULE1(
VAR6,
VAR35,
VAR12,
VAR24,
VAR18,
VAR59,
VAR10,
VAR1,
VAR49,
VAR5,
VAR54,
VAR13,
VAR50,
VAR70,
VAR52,
VAR51,
VAR60,
VAR3,
VAR66,
VAR4,
VAR61,
VAR46,
VAR48,
VAR15,
VAR38,
VAR2
);
input VAR6;
input VAR35;
output VAR12;
input VAR24;
input VAR18;
output VAR59;
input[VAR45-1:0] VAR10;
input[VAR21-1:0] VAR1;
... | mit |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/ecc/mig_7series_v4_0_fi_xor.v | 5,555 | module MODULE1 #
(
parameter integer VAR3 = 72,
parameter integer VAR1 = 9,
parameter integer VAR7 = 4
)
(
input wire clk ,
input wire [2*VAR7*VAR3-1:0] VAR8 ,
output wire [2*VAR7*VAR3-1:0] VAR12 ,
input wire VAR9 ,
input wire [VAR1-1:0] VAR6 ,
input wire [VAR3-1:0] VAR2
);
localparam VAR10 = VAR3 / VAR1;
reg [VAR3-1:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211ai/sky130_fd_sc_hs__o211ai.blackbox.v | 1,332 | module MODULE1 (
VAR5 ,
VAR6,
VAR1,
VAR2,
VAR4
);
output VAR5 ;
input VAR6;
input VAR1;
input VAR2;
input VAR4;
supply1 VAR7;
supply0 VAR3;
endmodule | apache-2.0 |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CORESPI/4.2.116/bfm_ahbtoapb.v | 6,292 | module MODULE1 (VAR20, VAR15, VAR28, VAR31, VAR19, VAR39, VAR41, VAR26, VAR2, VAR18, VAR10, VAR16, VAR27, VAR38, VAR23, VAR13, VAR30, VAR24, VAR33, VAR17, VAR12, VAR21, VAR5);
parameter VAR3 = 1;
input VAR20;
input VAR15;
input VAR28;
input VAR31;
input[31:0] VAR19;
input[31:0] VAR39;
output[31:0] VAR41;
wire[31:0] VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_2.functional.pp.v | 1,692 | module MODULE1( VAR11, VAR2, VAR13, VAR1, VAR20, VAR23, VAR17, VAR12 );
input VAR13, VAR2, VAR11, VAR23, VAR20;
inout VAR17, VAR12;
output VAR1;
wire VAR19;
not VAR21( VAR19, VAR13 );
wire VAR4;
not VAR22( VAR4, VAR2 );
wire VAR6;
not VAR16( VAR6, VAR11 );
wire VAR10;
and VAR3( VAR10, VAR19, VAR4, VAR6 );
wire VAR8;
no... | apache-2.0 |
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