repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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GLADICOS/SPACEWIRESYSTEMC | rtl/DEBUG_VERILOG/write_axi_8bit.v | 1,724 | module MODULE1(
input VAR1,
input VAR5,
input VAR2,
input [7:0] VAR4,
output reg [7:0] VAR3
);
always@(posedge VAR5 or negedge VAR2 )
begin
if(!VAR2)
begin
VAR3 <= 8'd0;
end
else
begin
if(VAR1)
VAR3 <= VAR4;
end
else
VAR3 <= VAR3;
end
end
endmodule | gpl-3.0 |
mlohstroh/bubble-pushers | control.v | 2,077 | module MODULE1(VAR1, VAR4, VAR7, VAR5, VAR6, VAR9, VAR2, VAR3, VAR10, VAR8) ;
input [5:0] VAR4;
input [5:0] VAR1;
output [0:0] VAR7, VAR5, VAR6, VAR2, VAR3, VAR10, VAR8;
output [1:0] VAR9;
reg [0:0] VAR7, VAR5, VAR6, VAR2, VAR3, VAR10, VAR8;
reg [1:0] VAR9;
always @(*) begin
case(VAR1)
6'b000010: begin
VAR8 = 1;
VAR10 ... | gpl-3.0 |
cwilkens/fpga-hero | MusicHero.v | 20,573 | module MODULE1(clk, VAR69, VAR91, VAR21, VAR22, VAR6,
VAR80, VAR104, VAR53, VAR16, VAR37,
VAR13, VAR105, VAR48, VAR74, VAR98,
VAR72, VAR9, VAR101, VAR64, VAR75, VAR28, VAR56, VAR33, VAR55, VAR3, VAR58, VAR47);
input clk;
output VAR69; output VAR91; output [7:0] VAR21;
input VAR80;
output VAR104;
output VAR53;
output VA... | mit |
borti4938/sd2snes | verilog/sd2snes_sa1/msu.v | 5,888 | module MODULE1(
input VAR15,
input enable,
input [13:0] VAR5,
input [7:0] VAR25,
input VAR43,
input [2:0] VAR17,
input [7:0] VAR6,
output [7:0] VAR22,
input VAR24,
input VAR19,
input VAR28,
output [7:0] VAR41,
output [7:0] VAR11,
output VAR33,
output [31:0] VAR13,
output [15:0] VAR10,
input [5:0] VAR34,
input [5:0] VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2/sky130_fd_sc_ls__and2.blackbox.v | 1,233 | module MODULE1 (
VAR6,
VAR3,
VAR5
);
output VAR6;
input VAR3;
input VAR5;
supply1 VAR2;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/uart/example/Arty/fpga/rtl/sync_reset.v | 1,615 | module MODULE1 #(
parameter VAR3=2 )(
input wire clk,
input wire rst,
output wire VAR1
);
reg [VAR3-1:0] VAR2 = {VAR3{1'b1}};
assign VAR1 = VAR2[VAR3-1];
always @(posedge clk or posedge rst) begin
if (rst)
VAR2 <= {VAR3{1'b1}};
end
else
VAR2 <= {VAR2[VAR3-2:0], 1'b0};
end
endmodule | mit |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_core/altera_tse_rgmii_out1.v | 5,262 | module MODULE1 (
VAR2,
VAR15,
VAR10,
VAR18,
VAR14);
input VAR2;
input VAR15;
input VAR10;
input VAR18;
output VAR14;
wire [0:0] VAR6;
wire [0:0] VAR4 = VAR6[0:0];
wire VAR14 = VAR4;
wire VAR12 = VAR15;
wire VAR21 = VAR12;
wire VAR9 = VAR10;
wire VAR8 = VAR9;
VAR24 VAR3 (
.VAR18 (VAR18),
.VAR15 (VAR21),
.VAR2 (VAR2),
.V... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/example_design/pcie_app_v6.v | 9,600 | module MODULE1#(
parameter VAR10 = 64,
parameter VAR82 = VAR10 / 8 )(
input VAR22,
input VAR60,
input VAR59,
input [5:0] VAR19,
input VAR51,
input VAR88,
output VAR21,
input VAR49,
output [VAR10-1:0] VAR86,
output [VAR82-1:0] VAR7,
output [3:0] VAR81,
output VAR65,
output VAR53,
output VAR58,
input [VAR10-1:0] VAR18,
i... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtp/sky130_fd_sc_hs__dlrtp_2.v | 2,220 | module MODULE2 (
VAR2,
VAR7 ,
VAR4 ,
VAR5 ,
VAR6 ,
VAR8
);
input VAR2;
input VAR7 ;
input VAR4 ;
output VAR5 ;
input VAR6 ;
input VAR8 ;
VAR1 VAR3 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR2,
VAR7 ,
VAR4 ,
VAR5
);
input VAR2;
input VAR7 ;
input VAR4 ... | apache-2.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/mega/ram_16x16k.v | 7,646 | module MODULE1 (
address,
VAR13,
VAR57,
VAR60,
VAR39,
VAR47,
VAR4);
input [13:0] address;
input [1:0] VAR13;
input VAR57;
input VAR60;
input [15:0] VAR39;
input VAR47;
output [15:0] VAR4;
tri1 [1:0] VAR13;
tri1 VAR57;
tri1 VAR60;
wire [15:0] VAR15;
wire [15:0] VAR4 = VAR15[15:0];
VAR19 VAR22 (
.VAR14 (address),
.VAR55 ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211oi/sky130_fd_sc_hdll__a211oi.behavioral.v | 1,561 | module MODULE1 (
VAR13 ,
VAR9,
VAR14,
VAR8,
VAR5
);
output VAR13 ;
input VAR9;
input VAR14;
input VAR8;
input VAR5;
supply1 VAR10;
supply0 VAR11;
supply1 VAR1 ;
supply0 VAR12 ;
wire VAR2 ;
wire VAR7;
and VAR6 (VAR2 , VAR9, VAR14 );
nor VAR4 (VAR7, VAR2, VAR8, VAR5);
buf VAR3 (VAR13 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvn/sky130_fd_sc_hd__einvn.pp.symbol.v | 1,329 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR7,
input VAR5 ,
input VAR6,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
BoolLi/Pollard-s-p-1-algorithm | GCD.v | 2,308 | module MODULE1(input [31:0] VAR7, input [31:0] VAR8, input reset, input clk, output reg [31:0] VAR11, output reg VAR12
);
reg [31:0] VAR3;
reg [31:0] VAR6;
reg [31:0] VAR1;
reg [31:0] VAR4;
reg [31:0] VAR2;
reg [31:0] VAR5;
reg [31:0] VAR9;
reg VAR10; | mit |
jefg89/proyecto_final_prototipado | ProyectoFinal/SOC/synthesis/submodules/SOC_sysid_qsys_0.v | 1,405 | module MODULE1 (
address,
VAR3,
VAR2,
VAR1
)
;
output [ 31: 0] VAR1;
input address;
input VAR3;
input VAR2;
wire [ 31: 0] VAR1;
assign VAR1 = address ? 1417708661 : 0;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311o/sky130_fd_sc_ms__a311o.symbol.v | 1,387 | module MODULE1 (
input VAR3,
input VAR8,
input VAR6,
input VAR10,
input VAR4,
output VAR1
);
supply1 VAR9;
supply0 VAR2;
supply1 VAR7 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2i/sky130_fd_sc_lp__mux2i_0.v | 2,214 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR7 ,
VAR4 ,
VAR5,
VAR10,
VAR6 ,
VAR3
);
output VAR9 ;
input VAR2 ;
input VAR7 ;
input VAR4 ;
input VAR5;
input VAR10;
input VAR6 ;
input VAR3 ;
VAR1 VAR8 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
alexforencich/verilog-ethernet | rtl/eth_mac_1g_rgmii.v | 7,009 | module MODULE1 #
(
parameter VAR31 = "VAR2",
parameter VAR75 = "VAR4",
parameter VAR45 = "VAR19",
parameter VAR64 = "VAR29",
parameter VAR68 = 1,
parameter VAR55 = 64
)
(
input wire VAR51,
input wire VAR54,
input wire VAR30,
output wire VAR65,
output wire VAR22,
output wire VAR12,
output wire VAR3,
input wire [7:0] VAR... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_clock_crosser.v | 4,874 | module MODULE1(
VAR19,
VAR21,
VAR31,
VAR3,
VAR14,
VAR17,
VAR27,
VAR11,
VAR9,
VAR23
);
parameter VAR1 = 1;
parameter VAR28 = 8;
parameter VAR10 = 2;
parameter VAR6 = 2;
parameter VAR32 = 1;
localparam VAR16 = VAR1 * VAR28;
input VAR19;
input VAR21;
output VAR31;
input VAR3;
input [VAR16-1:0] VAR14;
input VAR17;
input VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2i/sky130_fd_sc_hdll__mux2i.functional.v | 1,574 | module MODULE1 (
VAR4 ,
VAR6,
VAR5,
VAR1
);
output VAR4 ;
input VAR6;
input VAR5;
input VAR1 ;
wire VAR7;
VAR3 VAR8 (VAR7, VAR6, VAR5, VAR1 );
buf VAR2 (VAR4 , VAR7);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p.blackbox.v | 1,334 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR8
);
output VAR3 ;
input VAR2 ;
input VAR8;
supply1 VAR9;
supply1 VAR4 ;
supply0 VAR5 ;
supply1 VAR7;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_mux_2to1_n/sky130_fd_sc_ls__udp_mux_2to1_n.symbol.v | 1,289 | module MODULE1 (
input VAR1,
input VAR3,
output VAR2 ,
input VAR4
);
endmodule | apache-2.0 |
Cognoscan/BoostLogic | verilog/src/transmitters/Tx8b10b.v | 11,660 | module MODULE1 #(
parameter VAR20 = 10'b0011111010, parameter VAR21 = 10'b1100000101, parameter VAR5 = 1'b1, parameter VAR17 = 4 )
(
input clk, input rst, input en, input [7:0] VAR13, input VAR23, output VAR1, output VAR15, output VAR14, output VAR8 );
wire [7:0] VAR3;
reg [3:0] VAR19;
reg [1:9] VAR2;
reg VAR9;
reg VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4b/sky130_fd_sc_hs__nor4b_4.v | 2,175 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR4 ,
VAR7 ,
VAR5 ,
VAR6,
VAR9
);
output VAR1 ;
input VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR5 ;
input VAR6;
input VAR9;
VAR2 VAR8 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR1 ,
VAR3 ,
VAR4 ,
VAR7 ,
VAR5... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregrbp/sky130_fd_sc_lp__sregrbp.symbol.v | 1,413 | module MODULE1 (
input VAR2 ,
output VAR4 ,
output VAR9 ,
input VAR5,
input VAR10 ,
input VAR7 ,
input VAR3
);
supply1 VAR8;
supply0 VAR11;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/system.v | 40,393 | module MODULE1 (
input wire VAR117, input wire VAR26, output wire VAR202, output wire [14:0] VAR224, output wire [2:0] VAR57, output wire VAR27, output wire VAR103, output wire VAR115, output wire VAR114, output wire VAR43, output wire VAR52, output wire VAR145, output wire VAR82, inout wire [31:0] VAR74, inout wire [3... | mit |
wgml/sysrek | arithm/ipcore_dir/sum2.v | 22,104 | module MODULE1 (
clk, VAR62, VAR107, VAR181, VAR56
);
input clk;
input VAR62;
output [14 : 0] VAR107;
input [10 : 0] VAR181;
input [13 : 0] VAR56;
wire \VAR151/VAR241 ;
wire \VAR151/VAR212 ;
wire \VAR151/VAR192 ;
wire \VAR151/VAR248 ;
wire \VAR151/VAR213 ;
wire \VAR151/VAR78 ;
wire \VAR151/VAR126 ;
wire \VAR151/VAR222 ... | gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/FIFO_pixelq_op_img_rows_V_channel.v | 2,999 | module MODULE1 (
clk,
VAR4,
VAR8,
VAR12,
VAR15);
parameter VAR5 = 32'd12;
parameter VAR26 = 32'd2;
parameter VAR22 = 32'd3;
input clk;
input [VAR5-1:0] VAR4;
input VAR8;
input [VAR26-1:0] VAR12;
output [VAR5-1:0] VAR15;
reg[VAR5-1:0] VAR7 [0:VAR22-1];
integer VAR14;
always @ (posedge clk)
begin
if (VAR8)
begin
for (VAR... | gpl-2.0 |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_clk_wiz_0_0/bd_clk_wiz_0_0.v | 4,183 | module MODULE1
(
output VAR2,
output VAR6,
output VAR5,
input VAR1,
input VAR4
);
VAR7 VAR3
(
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux4/sky130_fd_sc_ls__mux4_1.v | 2,444 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR10 ,
VAR8 ,
VAR11 ,
VAR5 ,
VAR7 ,
VAR12,
VAR4,
VAR13 ,
VAR1
);
output VAR6 ;
input VAR2 ;
input VAR10 ;
input VAR8 ;
input VAR11 ;
input VAR5 ;
input VAR7 ;
input VAR12;
input VAR4;
input VAR13 ;
input VAR1 ;
VAR9 VAR3 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR11(VAR1... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GeAr_N9_R4_P1_syn.v | 1,669 | module MODULE1 ( VAR14, VAR8, VAR20 );
input [8:0] VAR14;
input [8:0] VAR8;
output [9:0] VAR20;
wire VAR23, VAR19, VAR12, VAR40, VAR10,
VAR25, VAR38, VAR13, VAR3;
VAR34 VAR18 ( .VAR28(VAR8[5]), .VAR37(VAR14[5]), .VAR5(VAR23), .VAR16(
VAR19), .VAR17(VAR20[5]) );
VAR34 VAR24 ( .VAR28(VAR8[6]), .VAR37(VAR14[6]), .VAR5(VAR... | gpl-3.0 |
borti4938/sd2snes | verilog/sd2snes_obc1/address.v | 4,117 | module MODULE1(
input VAR8,
input [15:0] VAR22, input [2:0] VAR13, input [23:0] VAR14, input [7:0] VAR10, input VAR24, output [23:0] VAR17, output VAR6, output VAR3, output VAR2, output VAR5, input [23:0] VAR23,
input [23:0] VAR9,
output VAR7,
output VAR25,
output VAR26,
output VAR1,
output VAR11,
output VAR18,
output ... | gpl-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_light/rtl/spw_light.v | 11,480 | module MODULE1(
input VAR22,
input [1:0] VAR60,
input VAR89,
input VAR82,
output VAR21,
output VAR70,
output [7:0] VAR26
);
wire VAR71;
wire VAR24;
wire VAR20;
wire VAR87;
wire VAR99;
wire VAR49;
wire VAR47;
wire [7:0] VAR62;
wire VAR83;
wire [1:0] VAR41;
wire [5:0] VAR4;
wire VAR61;
wire VAR84;
wire [7:0] VAR6;
wire V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_1.functional.v | 1,746 | module MODULE1( VAR22, VAR4, VAR6, VAR16, VAR2 );
input VAR4, VAR16, VAR6;
output VAR2, VAR22;
wire VAR13;
and VAR20( VAR13, VAR4, VAR16 );
wire VAR14;
and VAR21( VAR14, VAR4, VAR6 );
wire VAR23;
and VAR11( VAR23, VAR16, VAR6 );
or VAR25( VAR2, VAR13, VAR14, VAR23 );
wire VAR18;
and VAR17( VAR18, VAR4, VAR16, VAR6 );
w... | apache-2.0 |
rafalmiel/fpga | tron/bigram.v | 10,828 | module MODULE1 (
VAR34,
VAR38,
VAR2,
VAR42,
VAR49,
VAR21,
VAR3,
VAR40,
VAR9,
VAR5);
input [16:0] VAR34;
input [16:0] VAR38;
input [2:0] VAR2;
input [2:0] VAR42;
input VAR49;
input VAR21;
input VAR3;
input VAR40;
output [2:0] VAR9;
output [2:0] VAR5;
tri1 VAR49;
tri0 VAR3;
tri0 VAR40;
wire [2:0] VAR4;
wire [2:0] VAR25;
... | gpl-2.0 |
camsoupa/cc3000 | cc3000fpga/component/work/cc3000fpga_MSS/mss_tshell.v | 11,663 | module MODULE1
(
VAR110,
VAR206,
VAR129,
VAR26,
VAR158,
VAR116,
VAR144,
VAR185,
VAR166,
VAR188,
VAR10,
VAR8,
VAR27,
VAR101,
VAR79,
VAR191,
VAR210,
VAR201,
VAR65,
VAR76,
VAR136,
VAR60,
VAR100,
VAR119,
VAR106,
VAR90,
VAR126,
VAR31,
VAR1,
VAR184,
VAR5,
VAR7,
VAR182,
VAR142,
VAR165,
VAR68,
VAR4,
VAR128,
VAR88,
VAR180,
VAR9... | mit |
Mahdi89/eTeak | SELF_files/SRLOR_H.v | 1,115 | module MODULE1(
output VAR13,
input VAR3,
input VAR11,
input rst
);
wire VAR4;
wire VAR7;
wire VAR11;
wire VAR13 ;
VAR6 VAR5 (VAR11, VAR11, ~rst);
VAR6 VAR2 (VAR4, VAR11, VAR3);
VAR6 VAR10 (VAR7, VAR11, ~VAR3);
VAR12 VAR1 (VAR13, VAR4, VAR13);
VAR8 VAR9 (VAR13, VAR13, VAR7, rst);
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o211ai/sky130_fd_sc_hdll__o211ai.symbol.v | 1,383 | module MODULE1 (
input VAR4,
input VAR1,
input VAR6,
input VAR5,
output VAR7
);
supply1 VAR3;
supply0 VAR2;
supply1 VAR9 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211a/sky130_fd_sc_lp__o211a.pp.blackbox.v | 1,389 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR8 ,
VAR2 ,
VAR7 ,
VAR9,
VAR5,
VAR6 ,
VAR4
);
output VAR3 ;
input VAR1 ;
input VAR8 ;
input VAR2 ;
input VAR7 ;
input VAR9;
input VAR5;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_pm.v | 9,400 | module MODULE1(
clk, rst, VAR1, VAR4, VAR16, VAR11, VAR13,
VAR29, VAR26, VAR14, VAR6, VAR15,
VAR24, VAR20, VAR18, VAR23, VAR12
);
input clk; input rst; input VAR1; input VAR4; input [31:0] VAR16; input [31:0] VAR11; output [31:0] VAR13;
input VAR26; output [3:0] VAR29; output VAR14; output VAR6; output VAR15; output VA... | gpl-2.0 |
alexforencich/verilog-ethernet | rtl/arp.v | 17,937 | module MODULE1 #
(
parameter VAR10 = 8,
parameter VAR71 = (VAR10>8),
parameter VAR37 = (VAR10/8),
parameter VAR16 = 9,
parameter VAR139 = 4,
parameter VAR85 = 125000000*2,
parameter VAR29 = 125000000*30
)
(
input wire clk,
input wire rst,
input wire VAR73,
output wire VAR111,
input wire [47:0] VAR47,
input wire [47:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrbp/sky130_fd_sc_lp__sdfrbp.behavioral.v | 2,996 | module MODULE1 (
VAR32 ,
VAR6 ,
VAR27 ,
VAR13 ,
VAR25 ,
VAR18 ,
VAR29
);
output VAR32 ;
output VAR6 ;
input VAR27 ;
input VAR13 ;
input VAR25 ;
input VAR18 ;
input VAR29;
supply1 VAR33;
supply0 VAR16;
supply1 VAR24 ;
supply0 VAR7 ;
wire VAR2 ;
wire VAR1 ;
wire VAR15 ;
reg VAR20 ;
wire VAR30 ;
wire VAR9 ;
wire VAR31 ;
w... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/prcfg/qpsk/prcfg_dac.v | 5,556 | module MODULE1(
clk,
VAR20,
VAR24,
VAR25,
VAR19,
VAR23,
VAR17,
VAR10,
VAR5,
VAR9,
VAR4
);
parameter VAR15 = 0;
parameter VAR22 = 32;
localparam VAR18 = 2;
localparam VAR13 = 8'hA2;
input clk;
input [31:0] VAR20;
output [31:0] VAR24;
output VAR25;
input [(VAR22-1):0] VAR19;
input VAR23;
input VAR17;
input VAR10;
output ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311ai/sky130_fd_sc_ms__o311ai.pp.symbol.v | 1,387 | module MODULE1 (
input VAR7 ,
input VAR6 ,
input VAR1 ,
input VAR8 ,
input VAR2 ,
output VAR4 ,
input VAR3 ,
input VAR5,
input VAR10,
input VAR9
);
endmodule | apache-2.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/NIOS_Sys_nios2_qsys_0_jtag_debug_module_wrapper.v | 10,649 | module MODULE1 (
VAR35,
VAR41,
clk,
VAR36,
VAR12,
VAR43,
VAR21,
VAR18,
VAR34,
VAR3,
VAR50,
VAR47,
VAR29,
VAR2,
VAR8,
VAR58,
VAR24,
VAR37,
VAR33,
VAR39,
VAR57,
VAR26,
VAR15,
VAR27,
VAR4,
VAR23,
VAR48,
VAR38,
VAR16,
VAR17,
VAR30,
VAR14,
VAR6,
VAR10,
VAR46,
VAR20
)
;
output [ 37: 0] VAR57;
output VAR26;
output VAR15;
outp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21a/sky130_fd_sc_hd__o21a.symbol.v | 1,341 | module MODULE1 (
input VAR2,
input VAR6,
input VAR7,
output VAR4
);
supply1 VAR1;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
aj-michael/Digital-Systems | Lab4-Part2-RAMwithHyperTerminalDisplay/bbfifo_16x8.v | 7,921 | module MODULE1(
input [7:0] VAR18,
output [7:0] VAR59,
input reset,
input write,
input read,
output VAR42,
output VAR11,
output VAR29,
input clk);
wire [3:0] VAR6;
wire [3:0] VAR47;
wire [3:0] VAR14;
wire [2:0] VAR3;
wire VAR50;
wire VAR2;
wire VAR30;
wire VAR17;
wire VAR56;
genvar VAR5 ;
generate
for (VAR5 = 0; VAR5 <... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32ai/sky130_fd_sc_hd__o32ai.pp.symbol.v | 1,398 | module MODULE1 (
input VAR8 ,
input VAR3 ,
input VAR9 ,
input VAR7 ,
input VAR4 ,
output VAR10 ,
input VAR2 ,
input VAR6,
input VAR5,
input VAR1
);
endmodule | apache-2.0 |
mindrobots/P8X32A_Emulation | P8X32A_DE2_115/cog.v | 17,857 | module MODULE1
(
input VAR56,
input VAR53, input VAR62,
input VAR15,
input VAR24, input [27:0] VAR104,
input VAR75,
input VAR63, output VAR108,
output VAR13,
output VAR50,
output [1:0] VAR83,
output [15:0] VAR110,
output [31:0] VAR101,
input [31:0] VAR66,
input VAR42,
input VAR22,
input [31:0] VAR91,
input [7:0] VAR6, ... | gpl-3.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/io/uart/rtl/uart_tx.v | 2,864 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR9, input wire [VAR19] VAR2, output wire VAR11, output reg VAR12,
output reg VAR18 );
reg [VAR1] state; reg [VAR21] VAR8; reg [VAR24] VAR17; reg [VAR19] VAR14;
assign VAR11 = (state == VAR3) ? VAR6 : VAR10;
always @(posedge clk or VAR13 reset) begin
if (re... | apache-2.0 |
davidjabon/Verilog | PWM/pwm.v | 1,681 | module MODULE1 #(VAR1 = 1000)(
input clk,
input enable,
input [31:0] VAR3,
output out
);
reg VAR2=1'b0;
reg [31:0] counter = 32'b0;
always @(posedge clk)
begin
if (enable == 1'b1)
begin
if (counter < VAR3)
begin
VAR2 <= 1'b1;
counter <= counter + 32'b1;
end
else
begin
if (counter < (VAR1-1))
begin
VAR2 <= 1'b0;
counter... | gpl-2.0 |
iori-yja/ball_detector | cameradrv.v | 1,755 | module MODULE1 (
input clk,
input VAR1,
input [7:0] VAR2,
input VAR5,
output reg write,
output reg [15:0] VAR13,
output reg [9:0] VAR15
);
reg VAR6;
reg [7:0] VAR3;
reg VAR16;
always @(posedge clk)
begin
if (write) begin
write <= 1'b0;
end
if (!VAR5) begin
VAR6 <= 1'b1;
VAR16 <= 1'b0;
write <= 1'b0;
VAR15<= 0;
end else... | mit |
alexforencich/verilog-ethernet | rtl/eth_phy_10g_rx_if.v | 7,800 | module MODULE1 #
(
parameter VAR22 = 64,
parameter VAR9 = 2,
parameter VAR8 = 0,
parameter VAR1 = 0,
parameter VAR18 = 0,
parameter VAR11 = 0,
parameter VAR15 = 1,
parameter VAR12 = 8,
parameter VAR2 = 125000/6.4
)
(
input wire clk,
input wire rst,
output wire [VAR22-1:0] VAR20,
output wire [VAR9-1:0] VAR16,
input wire... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/master_0/altera_jtag_avalon_master/master_0_master_0.v | 15,530 | module MODULE1 #(
parameter VAR36 = 0,
parameter VAR5 = 50000,
parameter VAR14 = 2
) (
input wire VAR26, input wire VAR1, output wire [31:0] VAR45, input wire [31:0] VAR13, output wire VAR2, output wire VAR17, output wire [31:0] VAR15, input wire VAR10, input wire VAR9, output wire [3:0] VAR12, output wire VAR20 );
wir... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_rst_ps7_0_100M_1/zynq_design_1_rst_ps7_0_100M_1_stub.v | 1,914 | module MODULE1(VAR10, VAR2, VAR4,
VAR7, VAR9, VAR1, VAR3, VAR5,
VAR6, VAR8)
;
input VAR10;
input VAR2;
input VAR4;
input VAR7;
input VAR9;
output VAR1;
output [0:0]VAR3;
output [0:0]VAR5;
output [0:0]VAR6;
output [0:0]VAR8;
endmodule | mit |
qeedquan/fpga | de2-115/nios_lights/lights/synthesis/submodules/lights_LEDs.v | 2,097 | module MODULE1 (
address,
VAR8,
clk,
VAR5,
VAR4,
VAR1,
VAR6,
VAR2
)
;
output [ 7: 0] VAR6;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input VAR8;
input clk;
input VAR5;
input VAR4;
input [ 31: 0] VAR1;
wire VAR9;
reg [ 7: 0] VAR7;
wire [ 7: 0] VAR6;
wire [ 7: 0] VAR3;
wire [ 31: 0] VAR2;
assign VAR9 = 1;
assign VAR3 ... | mit |
ptracton/wb_soc_template | rtl/wb_ram/rtl/verilog/wb_ram_xilinx_bank.v | 3,126 | module MODULE1 (
dout,
clk, rst, VAR23, din, VAR18, VAR43, VAR56
) ;
input clk;
input rst;
input [3:0] VAR23;
input [31:0] din;
input [15:0] VAR18;
input [15:0] VAR43;
input wire VAR56;
output wire [31:0] dout;
wire [14:0] address = (|VAR23 & VAR56) ? VAR18 : VAR43;
wire [3:0] enable = {4{VAR56}};
VAR30 VAR1(
.VAR11(do... | mit |
TalentlessAlpaca/Automated_Vacuum_Cleaner | Position/Div_tst.v | 1,322 | module MODULE1;
reg clk;
reg rst;
reg VAR3;
reg [63:0] VAR4;
reg [63:0] VAR7;
wire [63:0] VAR2;
wire VAR6;
VAR5 VAR1 (
.clk(clk),
.rst(rst),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR6(VAR6)
); | mit |
cornell-zhang/datuner | designs/vtr/mkPktMerge.v | 40,761 | module MODULE4(VAR63,
VAR51,
VAR97,
VAR102,
VAR76,
VAR67,
VAR79,
VAR45,
VAR109,
VAR31,
VAR14);
input VAR63;
input VAR51;
input [152 : 0] VAR97;
input VAR102;
output VAR76;
input [152 : 0] VAR67;
input VAR79;
output VAR45;
input VAR109;
output [152 : 0] VAR31;
output VAR14;
wire [152 : 0] VAR31;
wire VAR76, VAR45, VAR14... | bsd-3-clause |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/verilog/start_for_CvtColokbM.v | 3,003 | module MODULE2 (
clk,
VAR19,
VAR17,
VAR25,
VAR15);
parameter VAR18 = 32'd1;
parameter VAR12 = 32'd3;
parameter VAR8 = 32'd5;
input clk;
input [VAR18-1:0] VAR19;
input VAR17;
input [VAR12-1:0] VAR25;
output [VAR18-1:0] VAR15;
reg[VAR18-1:0] VAR1 [0:VAR8-1];
integer VAR4;
always @ (posedge clk)
begin
if (VAR17)
begin
for... | mit |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_01/02 verilog/Pruebas/Fifo/fifo120bits/fifo.v | 3,834 | module MODULE1 # (parameter VAR27 = 15, VAR23 = 8)(
input reset, clk,
input rd, wr,
input [VAR23-1:0] din,
output [VAR23-1:0] dout,
output VAR3,
output VAR1,
output reg VAR13
);
wire VAR11;
VAR6 VAR7(.clk(clk), .reset(reset),.VAR4(VAR11));
wire VAR2;
wire VAR12;
reg VAR18, VAR14;
reg [VAR23-1:0] out;
VAR25 VAR13 = 0;
r... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_2.behavioral.pp.v | 3,847 | module MODULE1( VAR32, VAR30, VAR8, VAR10, VAR7, VAR31 );
input VAR32, VAR30, VAR8;
inout VAR7, VAR31;
output VAR10;
reg VAR21;
VAR34 VAR28(.VAR32(VAR32),.VAR30(VAR30),.VAR8(VAR8),.VAR10(VAR10),.VAR7(VAR7),.VAR31(VAR31),.VAR21(VAR21));
VAR34 VAR5(.VAR32(VAR32),.VAR30(VAR30),.VAR8(VAR8),.VAR10(VAR10),.VAR7(VAR7),.VAR31(... | apache-2.0 |
d16-processor/d16 | verilog/src/core.v | 11,918 | module MODULE1(input clk,input VAR41, output [7:0] VAR13, input VAR66, output VAR21,
output VAR5, output [3:0] VAR39, input [3:0] VAR67,
output [31:0] VAR6,
output [23:0] VAR40,
output VAR79,
output VAR63,
input [31:0] VAR93,
input VAR96,
input VAR36
);
wire [15:0] VAR7; wire [7:0] VAR4; wire [3:0] VAR28; wire [VAR101:... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_1.functional.pp.v | 1,611 | module MODULE1( VAR12, VAR5, VAR4, VAR6, VAR21, VAR7 );
input VAR5, VAR12, VAR4;
inout VAR21, VAR7;
output VAR6;
wire VAR18;
not VAR15( VAR18, VAR4 );
wire VAR16;
and VAR1( VAR16, VAR18, VAR5, VAR12 );
wire VAR9;
not VAR11( VAR9, VAR12 );
wire VAR20;
and VAR3( VAR20, VAR9, VAR5, VAR4 );
wire VAR19;
not VAR14( VAR19, VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2/sky130_fd_sc_lp__and2_2.v | 2,086 | module MODULE2 (
VAR7 ,
VAR2 ,
VAR4 ,
VAR9,
VAR6,
VAR8 ,
VAR1
);
output VAR7 ;
input VAR2 ;
input VAR4 ;
input VAR9;
input VAR6;
input VAR8 ;
input VAR1 ;
VAR3 VAR5 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR7,
VAR2,
VAR4
);
output VAR7;
... | apache-2.0 |
archlabo/Frix | fpga/nexys4/rtl/clock/clk_wiz_0.v | 4,138 | module MODULE1
(
input VAR5,
output VAR2,
output VAR1,
output VAR3
);
VAR6 VAR4
(
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21oi/sky130_fd_sc_lp__a21oi_2.v | 2,261 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR3 ,
VAR1 ,
VAR7,
VAR2,
VAR10 ,
VAR8
);
output VAR4 ;
input VAR9 ;
input VAR3 ;
input VAR1 ;
input VAR7;
input VAR2;
input VAR10 ;
input VAR8 ;
VAR6 VAR5 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
rbarzic/async_logic | reset_generator.v | 1,056 | module MODULE1 (
VAR4,
clk, VAR2
);
input clk;
input VAR2; output VAR4;
reg VAR3; reg VAR1;
always @(negedge clk or negedge VAR2) begin
if(VAR2 == 1'b0) begin
VAR3 <= 1'h0;
VAR1 <= 1'h0;
end
else begin
VAR3 <= 1'b1; VAR1 <= VAR3;
end
end
assign VAR4 = VAR1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222o/sky130_fd_sc_hs__a222o.functional.v | 2,281 | module MODULE1 (
VAR15 ,
VAR7 ,
VAR8 ,
VAR20 ,
VAR5 ,
VAR16 ,
VAR2 ,
VAR10,
VAR17
);
output VAR15 ;
input VAR7 ;
input VAR8 ;
input VAR20 ;
input VAR5 ;
input VAR16 ;
input VAR2 ;
input VAR10;
input VAR17;
wire VAR5 VAR21 ;
wire VAR5 VAR11 ;
wire VAR5 VAR13 ;
wire VAR14 ;
wire VAR12;
and VAR3 (VAR21 , VAR20, VAR5 );
an... | apache-2.0 |
bigeagle/riffa | fpga/riffa_hdl/rx_port_32.v | 15,824 | module MODULE1 #(
parameter VAR65 = 9'd32,
parameter VAR164 = 1024,
parameter VAR46 = 512,
parameter VAR10 = 2, parameter VAR51 = VAR114((VAR65/32)+1),
parameter VAR4 = VAR114((2**VAR114(VAR164))+1),
parameter VAR191 = VAR114((2**VAR114(VAR46))+1)
)
(
input VAR64,
input VAR128,
input [2:0] VAR41,
output VAR30, input [3... | bsd-3-clause |
gajjanag/6111_Project | src/divider.v | 2,094 | module MODULE1 #(parameter VAR3 = 8)
(input clk, VAR12, VAR5,
input [VAR3-1:0] VAR2,
input [VAR3-1:0] MODULE1,
output reg [VAR3-1:0] VAR13,
output [VAR3-1:0] VAR1,
output ready);
reg [VAR3-1:0] VAR14;
reg [VAR3*2-1:0] VAR9, VAR10, VAR7;
reg VAR11;
assign VAR1 = (!VAR11) ?
VAR9[VAR3-1:0] : ~VAR9[VAR3-1:0] + 1'b1;
reg [6... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3b/sky130_fd_sc_hs__or3b.behavioral.pp.v | 1,880 | module MODULE1 (
VAR5,
VAR11,
VAR10 ,
VAR13 ,
VAR2 ,
VAR7
);
input VAR5;
input VAR11;
output VAR10 ;
input VAR13 ;
input VAR2 ;
input VAR7 ;
wire VAR4 ;
wire VAR3 ;
wire VAR14;
not VAR12 (VAR4 , VAR7 );
or VAR1 (VAR3 , VAR2, VAR13, VAR4 );
VAR8 VAR9 (VAR14, VAR3, VAR5, VAR11);
buf VAR6 (VAR10 , VAR14 );
endmodule | apache-2.0 |
ptracton/wb_soc_template | behvioral/wb_bfm/wb_bfm_slave.v | 2,671 | module MODULE1
parameter VAR10 = 32,
parameter VAR9 = 0)
(input VAR7,
input VAR6,
input [VAR10-1:0] VAR31,
input [VAR2-1:0] VAR25,
input [3:0] VAR30,
input VAR34,
input VAR5,
input VAR12,
input [2:0] VAR22,
input [1:0] VAR36,
output reg [VAR2-1:0] VAR21,
output reg VAR14,
output reg VAR11,
output reg VAR13);
localparam... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_p0_reset_sync.v | 1,947 | module MODULE1(
VAR4,
clk,
VAR7
);
parameter VAR3 = 4;
parameter VAR1 = 1;
input VAR4;
input clk;
output [VAR1-1:0] VAR7;
reg [VAR3+VAR1-2:0] VAR6 ;
generate
genvar VAR5;
for (VAR5=0; VAR5<VAR3+VAR1-1; VAR5=VAR5+1)
begin: VAR2
always @(posedge clk or negedge VAR4)
begin
if (~VAR4)
VAR6[VAR5] <= 1'b0;
end
else
begin
if ... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | source/hardware/low-level-nfc/llnfc-ddr200mt-1.0.0/NPCG_Toggle_way_CE_timer.v | 7,926 | module MODULE1
(
parameter VAR2 = 8
)
(
VAR22 ,
VAR15 ,
VAR23 ,
VAR30 ,
VAR1 ,
VAR13 ,
VAR11
);
input VAR22 ;
input VAR15 ;
input [VAR2 - 1:0] VAR23 ;
input VAR30 ;
input VAR1 ;
input [VAR2 - 1:0] VAR13 ;
output VAR11 ;
wire VAR37 ;
wire VAR33 ;
wire VAR32 ;
wire VAR28 ;
wire VAR17 ;
wire VAR14 ;
wire VAR40 ;
wire VAR3... | gpl-3.0 |
kDaniu/miaow | src/verilog/rtl/fetch/fetch.v | 4,833 | module MODULE1(
VAR7,
VAR56,
VAR70,
VAR42,
VAR21,
VAR34,
VAR65,
VAR17,
VAR50,
VAR35,
VAR49,
VAR26,
VAR67,
VAR39,
VAR63,
VAR68,
VAR47,
VAR46,
VAR20,
VAR22,
VAR41,
VAR43,
VAR14,
VAR32,
VAR29,
VAR45,
VAR66,
VAR48,
VAR15,
VAR4,
VAR36,
VAR16,
VAR12,
VAR55,
VAR13,
VAR69,
VAR25,
clk,
rst
);
input clk;
input rst;
input VAR7, V... | bsd-3-clause |
skyfex/svo-raycaster | orlink/hw/ngc/orlink_ltw_fifo.v | 13,388 | module MODULE1(
rst,
VAR114,
VAR20,
din,
VAR324,
VAR342,
dout,
VAR160,
VAR39
);
input rst;
input VAR114;
input VAR20;
input [7 : 0] din;
input VAR324;
input VAR342;
output [31 : 0] dout;
output VAR160;
output VAR39;
VAR182 #(
.VAR253(0),
.VAR234(0),
.VAR194(0),
.VAR335(0),
.VAR357(0),
.VAR130(0),
.VAR269(0),
.VAR339(32... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_mc_speed/delay_30_degrees.v | 7,793 | module MODULE1
(
input VAR15,
input VAR12,
input [31:0] VAR4, input [2:0] VAR17, output reg [2:0] VAR16 );
localparam VAR1 = 32'h1000000;
localparam VAR3 = 6'b000001;
localparam VAR5 = 6'b000010;
localparam VAR13 = 6'b000100;
localparam VAR2 = 6'b001000;
localparam VAR8 = 6'b010000;
localparam VAR10 = 6'b100000;
reg [5... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3.functional.v | 1,309 | module MODULE1 (
VAR2,
VAR4
);
output VAR2;
input VAR4;
wire VAR1;
buf VAR3 (VAR1, VAR4 );
buf VAR5 (VAR2 , VAR1 );
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_5/ab882192/src/CRC_serial_m_lfs_XOR.v | 2,681 | module MODULE1
parameter VAR5 = 64
)
(
VAR3 ,
VAR4 ,
VAR2
);
input VAR3 ;
input [VAR5-1:0] VAR4 ;
output [VAR5-1:0] VAR2 ;
localparam [0:64] VAR6 = 65'b11001001011011000101011110010101110101111000011100001111010000101;
wire VAR1;
assign VAR1 = VAR3 ^ VAR4[VAR5-1];
assign VAR2[0] = VAR1;
genvar VAR7;
generate
for (VAR7=... | gpl-3.0 |
AmeerAbdelhadi/Switched-Multiported-RAM | mrram_swt.v | 7,331 | module MODULE1
localparam VAR22 = VAR26+VAR1 ; localparam VAR27 = VAR20(VAR7);
reg [VAR27-1:0] VAR5 [VAR22-1:0]; wire [VAR4-1:0] VAR25 [VAR22-1:0];
always @* begin
end
genvar VAR24;
generate
for (VAR24=0 ; VAR24<VAR1 ; VAR24=VAR24+1) begin: VAR3
if (VAR24<(VAR1-VAR26)) begin
VAR16 #( .VAR7 (VAR7 ), .VAR4 (VAR4 ), .VAR9... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_c0.v | 19,504 | module MODULE1 (
input wire VAR61, input wire VAR138, input wire VAR40, output wire VAR41, output wire VAR142, output wire VAR116, output wire [25:0] VAR8, output wire [5:0] VAR7, output wire [1:0] VAR139, output wire [1:0] VAR76, output wire [1:0] VAR42, output wire [1:0] VAR46, output wire [1:0] VAR27, output wire [1... | lgpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/models/ODDR2.v | 3,801 | module MODULE1 (VAR8, VAR7, VAR17, VAR10, VAR4, VAR18, VAR5, VAR14);
output VAR8;
input VAR7;
input VAR17;
input VAR10;
input VAR4;
input VAR18;
tri0 VAR15 = VAR1.VAR15;
input VAR5;
input VAR14;
parameter VAR16 = "VAR19";
parameter VAR11 = 1'b0;
parameter VAR9 = "VAR2";
reg VAR3, VAR13, VAR6;
buf VAR12 (VAR8, VAR3); | gpl-2.0 |
alexforencich/verilog-ethernet | rtl/eth_mac_10g.v | 7,596 | module MODULE1 #
(
parameter VAR46 = 64,
parameter VAR26 = (VAR46/8),
parameter VAR6 = (VAR46/8),
parameter VAR42 = 1,
parameter VAR38 = 1,
parameter VAR12 = 64,
parameter VAR28 = 4'h6,
parameter VAR2 = 16'h6666,
parameter VAR3 = 0,
parameter VAR1 = 96,
parameter VAR11 = VAR3,
parameter VAR10 = 16,
parameter VAR36 = 0,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2b/sky130_fd_sc_hdll__nor2b.functional.pp.v | 1,989 | module MODULE1 (
VAR2 ,
VAR10 ,
VAR11 ,
VAR4,
VAR13,
VAR5 ,
VAR12
);
output VAR2 ;
input VAR10 ;
input VAR11 ;
input VAR4;
input VAR13;
input VAR5 ;
input VAR12 ;
wire VAR8 ;
wire VAR9 ;
wire VAR15;
not VAR14 (VAR8 , VAR10 );
and VAR3 (VAR9 , VAR8, VAR11 );
VAR7 VAR6 (VAR15, VAR9, VAR4, VAR13);
buf VAR1 (VAR2 , VAR15 )... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2b/sky130_fd_sc_ls__or2b.functional.v | 1,346 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR1
);
output VAR8 ;
input VAR7 ;
input VAR1;
wire VAR4 ;
wire VAR2;
not VAR3 (VAR4 , VAR1 );
or VAR5 (VAR2, VAR4, VAR7 );
buf VAR6 (VAR8 , VAR2 );
endmodule | apache-2.0 |
cfangmeier/VFPIX-telescope-Code | utils/apc128_pattern_generator/counter_group.v | 1,984 | module MODULE1
(
input VAR4,
input VAR13,
input VAR21,
input VAR26,
input wire [15:0]VAR18,
input wire [15:0]VAR9,
input wire [15:0]VAR29,
input wire [15:0]VAR2,
input wire [15:0]VAR32,
input wire [15:0]VAR31,
input wire [15:0]VAR23,
input wire [15:0]VAR30,
output wire [15:0]VAR34,
output wire [15:0]VAR12,
output wire ... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/packet_generator32.v | 1,469 | module MODULE1
(input clk, input reset, input VAR1,
input [127:0] VAR21,
output [35:0] VAR9, output VAR4, input VAR11);
wire [7:0] VAR17;
wire VAR6, VAR18, VAR13, VAR10;
VAR19 VAR7
(.clk(clk), .reset(reset), .VAR1(VAR1),
.VAR9(VAR17), .VAR16(VAR6), .VAR15(VAR18),
.VAR21(VAR21),
.VAR4(VAR13), .VAR11(~VAR10));
VAR22 VAR2... | gpl-2.0 |
skarpenko/ultiparc | rtl/src/cpu/uparc_writeback.v | 2,573 | module MODULE1(
clk,
VAR2,
VAR1,
VAR12,
VAR4,
VAR5,
VAR6,
VAR10,
VAR8,
VAR11,
VAR7
);
input wire clk;
input wire VAR2;
input wire VAR1;
input wire VAR12;
input wire VAR4;
input wire VAR5;
input wire VAR6;
input wire [VAR13-1:0] VAR10;
input wire [VAR9-1:0] VAR8;
output reg [VAR13-1:0] VAR11;
output reg [VAR9-1:0] VAR7;... | bsd-2-clause |
yugr/primogen | boards/icestick/src/blink.v | 1,448 | module MODULE1 (
input VAR8,
output [4:0] VAR7);
localparam VAR1 = 4;
localparam VAR10 = 1 << VAR1;
localparam VAR12 = VAR10 - 1;
wire VAR11, VAR16;
wire [VAR12:0] VAR3;
reg VAR14;
reg [31:0] VAR9;
reg MODULE1;
wire rst;
wire VAR18;
wire clk;
wire VAR20;
localparam VAR6 = 16;
VAR17 #(.VAR6(VAR6)) VAR4 (.VAR8(VAR8), .cl... | mit |
SymbiFlow/yosys | techlibs/xilinx/arith_map.v | 4,575 | module MODULE1(
module 80xilinxlcu (VAR35, VAR11, VAR24, VAR33);
parameter VAR18 = 2;
input [VAR18-1:0] VAR35, VAR11;
input VAR24;
output [VAR18-1:0] VAR33;
wire VAR9 = VAR18 <= 2;
genvar VAR38;
generate if (VAR39 == 4) begin
wire [VAR18-1:0] VAR5 = {VAR33, VAR24};
wire [VAR18-1:0] VAR8 = VAR35 & ~VAR11;
generate for (... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2/sky130_fd_sc_hdll__nor2.symbol.v | 1,268 | module MODULE1 (
input VAR7,
input VAR6,
output VAR2
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21oi/sky130_fd_sc_lp__a21oi.functional.v | 1,420 | module MODULE1 (
VAR6 ,
VAR7,
VAR1,
VAR4
);
output VAR6 ;
input VAR7;
input VAR1;
input VAR4;
wire VAR2 ;
wire VAR3;
and VAR8 (VAR2 , VAR7, VAR1 );
nor VAR5 (VAR3, VAR4, VAR2 );
buf VAR9 (VAR6 , VAR3 );
endmodule | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Lab4/lab_pong/VGA_Control.v | 3,136 | module MODULE1(VAR3, reset, VAR5, VAR2, VAR1, VAR6);
input VAR3, reset;
output reg VAR1, VAR6;
output [9:0] VAR5;
output [8:0] VAR2;
reg [9:0] VAR7, VAR4;
begin
begin
begin
end
begin
begin
end
begin
begin
begin
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtp/sky130_fd_sc_ms__dfrtp_2.v | 2,329 | module MODULE2 (
VAR8 ,
VAR10 ,
VAR2 ,
VAR7,
VAR6 ,
VAR9 ,
VAR1 ,
VAR5
);
output VAR8 ;
input VAR10 ;
input VAR2 ;
input VAR7;
input VAR6 ;
input VAR9 ;
input VAR1 ;
input VAR5 ;
VAR3 VAR4 (
.VAR8(VAR8),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODU... | apache-2.0 |
aj-michael/Digital-Systems | Pong/Phase1/ipcore_dir/Clock50MHz.v | 5,519 | module MODULE1
( input VAR6,
output VAR31
);
VAR5 VAR47
(.VAR33 (VAR23),
.VAR49 (VAR6));
wire VAR40;
wire VAR16;
wire [7:0] VAR43;
wire VAR19;
wire VAR21;
wire VAR8;
VAR17
.VAR3 (1),
.VAR9 (4),
.VAR18 ("VAR27"),
.VAR32 (10.0),
.VAR2 ("VAR4"),
.VAR24 ("1X"),
.VAR14 ("VAR15"),
.VAR30 (0),
.VAR28 ("VAR27"))
VAR20
(.VAR42 ... | mit |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/pixelq_op.v | 39,700 | module MODULE1 (
VAR166,
VAR208,
VAR43,
VAR264,
VAR136,
VAR278,
VAR234,
VAR83,
VAR90,
VAR134,
VAR12,
VAR59,
VAR254,
VAR117,
VAR123,
VAR116,
VAR84,
VAR82,
VAR167,
VAR118,
VAR263,
VAR262,
VAR211,
VAR34,
VAR36,
VAR122,
VAR196,
VAR3,
VAR81,
VAR210,
VAR193,
VAR146,
VAR158,
VAR130,
VAR188,
VAR200,
VAR236,
VAR177,
VAR53,
VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkbuf/sky130_fd_sc_hd__clkbuf.pp.symbol.v | 1,262 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR5 ,
input VAR6,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/clk_gen/clk_gen.v | 3,913 | module MODULE1
(
input VAR2,
output VAR4,
input reset
);
VAR3 VAR1
(
.VAR2(VAR2),
.VAR4(VAR4),
.reset(reset)
);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrbp/sky130_fd_sc_hd__dlrbp_1.v | 2,474 | module MODULE1 (
VAR6 ,
VAR11 ,
VAR9,
VAR2 ,
VAR8 ,
VAR5 ,
VAR7 ,
VAR10 ,
VAR1
);
output VAR6 ;
output VAR11 ;
input VAR9;
input VAR2 ;
input VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR10 ;
input VAR1 ;
VAR4 VAR3 (
.VAR6(VAR6),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR10(VAR10)... | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_except.v | 21,168 | module MODULE1
(
clk, rst,
VAR119, VAR60, VAR27, VAR55, VAR117, VAR8,
VAR83, VAR135, VAR112, VAR47, VAR85, VAR99,
VAR57, VAR73, VAR87, VAR26, VAR46, VAR78,
VAR9, VAR59, VAR18, VAR81, VAR123, VAR121, VAR30,
VAR44, VAR42, VAR65, VAR21, VAR84,
VAR37, VAR50, VAR111, VAR4, VAR88, VAR31,
VAR35, VAR12, VAR68, VAR79, VAR103, V... | mit |
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