repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfstp/sky130_fd_sc_lp__dfstp_2.v | 2,273 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR8 ,
VAR2,
VAR3 ,
VAR5 ,
VAR6 ,
VAR1
);
output VAR9 ;
input VAR7 ;
input VAR8 ;
input VAR2;
input VAR3 ;
input VAR5 ;
input VAR6 ;
input VAR1 ;
VAR4 VAR10 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbp/sky130_fd_sc_hd__sdfbbp.pp.symbol.v | 1,579 | module MODULE1 (
input VAR5 ,
output VAR8 ,
output VAR3 ,
input VAR10,
input VAR11 ,
input VAR9 ,
input VAR6 ,
input VAR2 ,
input VAR4 ,
input VAR1 ,
input VAR7 ,
input VAR12
);
endmodule | apache-2.0 |
alexforencich/xfcp | rtl/xfcp_mod_drp.v | 3,793 | module MODULE1 #
(
parameter VAR8 = 16'h0001,
parameter VAR12 = "VAR49",
parameter VAR42 = 0,
parameter VAR35 = "",
parameter VAR28 = 10
)
(
input wire clk,
input wire rst,
input wire [7:0] VAR9,
input wire VAR50,
output wire VAR19,
input wire VAR38,
input wire VAR31,
output wire [7:0] VAR37,
output wire VAR30,
input w... | mit |
kigawas/MipsCPU | CPU/addsub32.v | 2,815 | module MODULE1(
input [31:0] VAR10,
input [31:0] VAR11,
input VAR8,
input VAR4,
output [31:0]VAR7,
output VAR12,
output VAR13,
output VAR1,
output VAR14
);
reg [31:0]VAR6;
reg VAR3;
reg VAR9;
reg VAR5;
reg VAR2;
assign VAR7 = VAR6;
assign VAR12 = VAR3;
assign VAR13 = VAR9;
assign VAR14 = VAR2;
assign VAR1 = VAR5;
alway... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1.pp.symbol.v | 1,289 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtn/sky130_fd_sc_lp__dlxtn.functional.pp.v | 1,893 | module MODULE1 (
VAR14 ,
VAR3 ,
VAR10,
VAR16 ,
VAR2 ,
VAR4 ,
VAR9
);
output VAR14 ;
input VAR3 ;
input VAR10;
input VAR16 ;
input VAR2 ;
input VAR4 ;
input VAR9 ;
wire VAR5 ;
wire VAR1 ;
wire VAR7;
wire VAR11 ;
VAR12 VAR15 VAR13 (VAR1 , VAR3, VAR5, , VAR16, VAR2);
not VAR8 (VAR5 , VAR10 );
buf VAR6 (VAR14 , VAR1 );
end... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_dtcm_ctrl.v | 13,167 | module MODULE1(
output VAR109,
input VAR50,
input VAR46, output VAR28, input [VAR4-1:0] VAR86, input VAR57, input [32-1:0] VAR10,
input [4-1:0] VAR3,
output VAR119, input VAR130, output VAR6, output [32-1:0] VAR12,
input [ 4-1:0] VAR16,
output VAR134, input VAR87, output VAR88, output [32-1:0] VAR102,
output VAR53,
out... | apache-2.0 |
secworks/fpga_entropy | src/rtl/fpga_entropy.v | 8,672 | module MODULE1(
input wire clk,
input wire VAR26,
input wire VAR3,
input wire VAR35,
input wire [7 : 0] address,
input wire [31 : 0] VAR1,
output wire [31 : 0] VAR33,
output wire VAR38,
output wire [7 : 0] VAR2
);
parameter VAR7 = 8'h00;
parameter VAR30 = 8'h01;
parameter VAR36 = 8'h02;
parameter VAR11 = 8'h10;
paramet... | bsd-2-clause |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_109.v | 1,554 | module MODULE2 (
VAR1,
VAR10
);
input [31:0] VAR1;
output [31:0]
VAR10;
wire [31:0]
VAR5,
VAR7,
VAR8,
VAR4,
VAR14,
VAR3,
VAR9,
VAR13,
VAR6,
VAR12;
assign VAR5 = VAR1;
assign VAR8 = VAR7 - VAR5;
assign VAR7 = VAR5 << 10;
assign VAR9 = VAR8 + VAR3;
assign VAR3 = VAR14 << 4;
assign VAR6 = VAR13 - VAR9;
assign VAR13 = VAR9... | mit |
ehab93/MIPS-Processor | synthesis/synth.v | 61,408 | module MODULE2(VAR174, VAR185, VAR215, VAR82);
input VAR174;
input VAR185;
input VAR215;
output VAR82;
wire VAR93;
wire VAR139;
wire VAR73;
assign VAR82 = VAR93 | VAR139;
assign VAR139 = VAR174 & VAR215;
assign VAR93 = VAR185 & VAR73;
assign VAR73 = ~VAR215;
endmodule
module MODULE3(VAR205, clk, VAR217, VAR144, VAR128)... | mit |
sorgelig/ZX_Spectrum-128K_MIST | sys/mist_io.v | 14,128 | module MODULE1 #(parameter VAR14=0, parameter VAR17=100)
(
input [(8*VAR14)-1:0] VAR63,
input VAR36,
input VAR2,
input VAR67,
input VAR37,
output VAR15,
input VAR72,
output reg [7:0] VAR13,
output reg [7:0] VAR49,
output reg [15:0] VAR16,
output reg [15:0] VAR9,
output [1:0] VAR96,
output [1:0] VAR83,
output VAR95,
out... | gpl-2.0 |
silent-observer/RCPU | CPU/source/alu.v | 1,984 | module MODULE1(
input wire[VAR14-1:0] VAR17,
input wire[VAR14-1:0] VAR23,
input wire[VAR14-1:0] VAR21,
input wire[3:0] VAR7,
input wire VAR12,
input wire VAR9,
output reg[VAR14-1:0] VAR22,
output reg[VAR14-1:0] VAR16,
output reg VAR13,
output reg VAR19,
output reg VAR18,
output reg VAR2 );
parameter VAR14 = 16;
reg[2*V... | mit |
elegabriel/myzju | junior1/CA/LAB/lab5/code/alt_ctl.v | 1,681 | module MODULE1(VAR3,VAR1,VAR2
);
input [5:0] VAR3,VAR1;
output reg [4:0] VAR2;
always @*
begin
case(VAR3)
6'b000000 : begin case(VAR1) 6'b100000 : VAR2 = 0; 6'b100001 : VAR2 = 1; 6'b100010 : VAR2 = 2; 6'b100011 : VAR2 = 3; 6'b100100 : VAR2 = 4; 6'b100101 : VAR2 = 5; 6'b100110 : VAR2 = 6; 6'b100111 : VAR2 = 7; 6'b101010... | gpl-2.0 |
DreamIP/GPStudio | support/process/histogram/hdl/histogram.v | 10,629 | module MODULE1(
VAR71,
VAR34,
VAR46,
VAR15,
VAR45,
VAR4,
VAR67,
VAR5,
VAR66,
VAR21,
VAR70,
VAR37,
VAR60,
VAR48,
VAR57,
VAR69
);
parameter VAR19 = 16;
parameter VAR77 = 8;
parameter VAR39 = 16;
parameter VAR64 = 50000000;
parameter VAR24 = 2048;
localparam VAR41 = VAR80(VAR24);
input VAR71;
input VAR34;
input VAR4;
inpu... | gpl-3.0 |
CospanDesign/nysa-artemis-pcie-platform | artemis_pcie/slave/wb_artemis_pcie_platform/rtl/c/axi_basic_rx.v | 8,699 | module MODULE1 #(
parameter VAR7 = 128, parameter VAR37 = "VAR33", parameter VAR30 = "VAR2", parameter VAR1 = "VAR2", parameter VAR26 = 1,
parameter VAR5 = (VAR7 == 128) ? 2 : 1, parameter VAR25 = VAR7 / 8 ) (
output [VAR7-1:0] VAR6, output VAR9, input VAR11, output [VAR25-1:0] VAR31, output VAR3, output [21:0] VAR29,
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211ai/sky130_fd_sc_hd__o211ai.functional.pp.v | 2,048 | module MODULE1 (
VAR5 ,
VAR15 ,
VAR7 ,
VAR10 ,
VAR12 ,
VAR14,
VAR4,
VAR2 ,
VAR17
);
output VAR5 ;
input VAR15 ;
input VAR7 ;
input VAR10 ;
input VAR12 ;
input VAR14;
input VAR4;
input VAR2 ;
input VAR17 ;
wire VAR8 ;
wire VAR3 ;
wire VAR1;
or VAR11 (VAR8 , VAR7, VAR15 );
nand VAR9 (VAR3 , VAR12, VAR8, VAR10 );
VAR16 VA... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pipe_reset.v | 22,159 | module MODULE1 #
(
parameter VAR46 = "VAR16", parameter VAR42 = "VAR75",
parameter VAR38 = "VAR74", parameter VAR25 = "VAR45", parameter VAR53 = "VAR16", parameter VAR18 = 1, parameter VAR35 = 6'd63, parameter VAR34 = 1
)
(
input VAR52,
input VAR13,
input VAR36,
input VAR26,
input [VAR18-1:0] VAR23,
input [VAR18-1:0] V... | gpl-3.0 |
pavel-demin/red-pitaya-notes | cores/axi_cfg_register_v1_0/axi_cfg_register.v | 6,763 | module MODULE1 #
(
parameter integer VAR65 = 1024,
parameter integer VAR8 = 32,
parameter integer VAR10 = 16
)
(
input wire VAR66,
input wire VAR24,
output wire [VAR65-1:0] VAR58,
input wire [VAR10-1:0] VAR36, input wire VAR51, output wire VAR13, input wire [VAR8-1:0] VAR68, input wire [VAR8/8-1:0] VAR6, input wire VAR... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_impctl_pulldown.v | 6,265 | module MODULE1(VAR63 ,VAR18 ,VAR8
,VAR40 ,VAR5 ,VAR44 ,VAR37 ,VAR28 ,
VAR33 ,VAR32 ,VAR21 ,VAR7 ,VAR67 ,VAR87 ,VAR31 ,VAR66
,VAR45 ,VAR13 ,VAR84 );
output [7:0] VAR28 ;
output [7:0] VAR13 ;
input [7:0] VAR7 ;
output VAR44 ;
output VAR33 ;
output VAR84 ;
input VAR63 ;
input VAR18 ;
input VAR8 ;
input VAR40 ;
input VAR5 ... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1.behavioral.v | 3,689 | module MODULE1( VAR27, VAR12, VAR13, VAR11 );
input VAR27, VAR12, VAR13;
output VAR11;
reg VAR25;
VAR23 VAR8(.VAR27(VAR27),.VAR12(VAR12),.VAR13(VAR13),.VAR11(VAR11),.VAR25(VAR25));
VAR23 VAR20(.VAR27(VAR27),.VAR12(VAR12),.VAR13(VAR13),.VAR11(VAR11),.VAR25(VAR25));
not VAR14(VAR32,VAR12);
and VAR28(VAR26,VAR13,VAR32);
a... | apache-2.0 |
tmolteno/TART | hardware/FPGA/zynq/tart_1.0/hdl/correlator/correlate_cos_sin_DSP.v | 3,791 | module MODULE1
parameter VAR21 = VAR46+VAR3,
parameter VAR53 = 0, parameter VAR47 = 3)
(
input clk,
input VAR43,
input en,
input VAR52,
input VAR42,
input VAR57,
input VAR37,
input VAR36,
input [VAR3:0] VAR20,
input [VAR3:0] VAR5,
output [VAR3:0] VAR19,
output [VAR3:0] VAR17
);
wire [6:0] VAR24 = 7'b0110011;
wire [3:0]... | lgpl-3.0 |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/acc_vadd_hls/project/project.srcs/sources_1/imports/verilog/acc_vadd_hls.v | 10,460 | module MODULE1 (
VAR26,
VAR24,
VAR31,
VAR27,
VAR45,
VAR12,
VAR53,
VAR1,
VAR38,
VAR21,
VAR64,
VAR20,
VAR60,
VAR16,
VAR6,
VAR18,
VAR54,
VAR25,
VAR63,
VAR44,
VAR66,
VAR33,
VAR34,
VAR35,
VAR58,
VAR67,
VAR49,
VAR41,
VAR13
);
parameter VAR3 = 1'b1;
parameter VAR37 = 1'b0;
parameter VAR8 = 3'b000;
parameter VAR17 = 3'b1;
para... | bsd-3-clause |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/CPU/controlunit2.v | 3,531 | module MODULE1 (output reg VAR4, VAR7, VAR10, VAR14, VAR11, VAR13, VAR12, VAR17,VAR22,VAR21,VAR16,VAR19,VAR9,output reg[4:0] VAR20, output reg[3:0] VAR18, input VAR23, VAR1,VAR3, input [31:0] VAR24,input [3:0] VAR5);
reg [4:0] VAR6, VAR15;
task VAR2;
input [17:0] VAR8;
fork
{VAR18,VAR4, VAR7, VAR10, VAR14,VAR20, VAR11,... | apache-2.0 |
mballance/wb_dma | rtl/wb_dma_wb_mast.v | 5,960 | module MODULE1(clk, rst,
VAR22, VAR19, VAR12, VAR24, VAR4, VAR15,
VAR10, VAR9, VAR18, VAR23,
VAR13, VAR2, VAR3, VAR16, VAR8, VAR7,
VAR20, VAR17,
VAR1, VAR5, VAR14
);
input clk, rst;
input [31:0] VAR22;
output [31:0] VAR19;
output [31:0] VAR12;
output [3:0] VAR24;
output VAR4;
output VAR15;
output VAR10;
input VAR9;
inp... | apache-2.0 |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/altera_up_video_fb_color_rom.v | 7,314 | module MODULE1 (
clk,
VAR43,
VAR9,
VAR28,
VAR47,
VAR18
);
input clk;
input VAR43;
input [ 3: 0] VAR9;
output [ 9: 0] VAR28;
output [ 9: 0] VAR47;
output [ 9: 0] VAR18;
wire [29: 0] VAR22;
assign VAR28 = VAR22[29:20];
assign VAR47 = VAR22[19:10];
assign VAR18 = VAR22[ 9: 0];
VAR46 VAR45 (
.VAR41 (clk),
.VAR27 (VAR43),
.... | gpl-2.0 |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_align.v | 2,529 | module MODULE1
(VAR7, VAR6, VAR2);
parameter VAR5 = 32;
parameter VAR4 = 32;
parameter VAR8 = 0;
input [0:VAR5-1] VAR7;
input [0:VAR4-1] VAR6;
output [0:VAR4-1] VAR2;
wire [0:VAR4-1] VAR2;
genvar VAR1;
generate
for(VAR1 = 0; VAR1 < VAR4; VAR1 = VAR1 + 1)
begin:VAR3
if((VAR1 < VAR8) || (VAR1 >= (VAR8 + VAR5)))
assign VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkinv/sky130_fd_sc_hd__clkinv.pp.blackbox.v | 1,251 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR3,
VAR1,
VAR5 ,
VAR4
);
output VAR2 ;
input VAR6 ;
input VAR3;
input VAR1;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp.behavioral.pp.v | 1,814 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR6,
VAR1,
VAR3 ,
VAR12
);
output VAR7 ;
input VAR10 ;
input VAR6;
input VAR1;
input VAR3 ;
input VAR12 ;
wire VAR4 ;
wire VAR9;
not VAR8 (VAR4 , VAR10 );
VAR2 VAR11 (VAR9, VAR4, VAR6, VAR1);
buf VAR5 (VAR7 , VAR9 );
endmodule | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_base/upd77c25_datram.v | 10,727 | module MODULE1 (
VAR56,
VAR25,
VAR7,
VAR20,
VAR47,
VAR23,
VAR2,
VAR53,
VAR59);
input [9:0] VAR56;
input [10:0] VAR25;
input VAR7;
input [15:0] VAR20;
input [7:0] VAR47;
input VAR23;
input VAR2;
output [15:0] VAR53;
output [7:0] VAR59;
tri1 VAR7;
tri0 VAR23;
tri0 VAR2;
wire [15:0] VAR1;
wire [7:0] VAR43;
wire [15:0] VAR... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab2/fir_prj/solution1/impl/verilog/fir_shift_reg.v | 1,428 | module MODULE1 (VAR2, VAR9, VAR3, VAR1, VAR8, clk);
parameter VAR7 = 32;
parameter VAR5 = 4;
parameter VAR4 = 11;
input[VAR5-1:0] VAR2;
input VAR9;
input[VAR7-1:0] VAR3;
input VAR1;
output reg[VAR7-1:0] VAR8;
input clk;
reg [VAR7-1:0] VAR6[0:VAR4-1];
begin
begin
begin
end | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32oi/sky130_fd_sc_lp__a32oi.functional.pp.v | 2,238 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR10 ,
VAR18 ,
VAR6 ,
VAR8 ,
VAR14,
VAR19,
VAR3 ,
VAR17
);
output VAR9 ;
input VAR1 ;
input VAR10 ;
input VAR18 ;
input VAR6 ;
input VAR8 ;
input VAR14;
input VAR19;
input VAR3 ;
input VAR17 ;
wire VAR15 ;
wire VAR2 ;
wire VAR16 ;
wire VAR13;
nand VAR11 (VAR15 , VAR10, VAR1, VAR18 );
nan... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_pe_pp_pg/sky130_fd_sc_hs__udp_dff_pe_pp_pg.symbol.v | 1,447 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR4,
input VAR3 ,
input VAR5 ,
input VAR6
);
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_014.v | 1,513 | module MODULE2 (
VAR7,
VAR5
);
input [31:0] VAR7;
output [31:0]
VAR5;
wire [31:0]
VAR1,
VAR10,
VAR9,
VAR14,
VAR3,
VAR12,
VAR2,
VAR11,
VAR8;
assign VAR1 = VAR7;
assign VAR3 = VAR9 - VAR14;
assign VAR10 = VAR1 << 4;
assign VAR11 = VAR1 << 14;
assign VAR9 = VAR1 + VAR10;
assign VAR8 = VAR2 + VAR11;
assign VAR14 = VAR1 << ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/einvp/sky130_fd_sc_hvl__einvp.pp.symbol.v | 1,333 | module MODULE1 (
input VAR7 ,
output VAR1 ,
input VAR2 ,
input VAR5 ,
input VAR3,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor3/sky130_fd_sc_hdll__xor3.blackbox.v | 1,297 | module MODULE1 (
VAR4,
VAR1,
VAR7,
VAR2
);
output VAR4;
input VAR1;
input VAR7;
input VAR2;
supply1 VAR5;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
ptracton/Picoblaze | Picoblaze/UART_and_PicoTerm/ATLYS_design/uart6_atlys.v | 14,929 | module MODULE1 (
input VAR6,
output VAR44,
output [7:0] VAR51,
input [7:0] VAR52,
input VAR15,
input clk );
wire [11:0] address;
wire [17:0] VAR53;
wire VAR40;
reg [7:0] VAR57;
wire [7:0] VAR20;
wire [7:0] VAR11;
wire VAR10;
wire VAR45;
wire VAR30;
reg interrupt;
wire VAR37;
wire VAR41;
wire VAR17;
wire VAR19;
wire [7:... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_common/src/v/bsg_parallel_in_serial_out_passthrough_dynamic.v | 7,876 | module MODULE1
,parameter VAR21(VAR28)
,parameter VAR3 = VAR15(VAR28)
)
(input VAR18
,input VAR43
,input VAR17
,input [VAR28-1:0][VAR13-1:0] VAR41
,output VAR29
,output VAR35
,output [VAR13-1:0] VAR31
,input VAR44
,output VAR30
,input [VAR3-1:0] VAR37
);
if (VAR28 == 1)
begin : VAR47
assign VAR35 = VAR17;
assign VAR31 ... | bsd-3-clause |
alexforencich/verilog-mersenne | rtl/axis_mt19937.v | 7,805 | module MODULE1
(
input wire clk,
input wire rst,
output wire [31:0] VAR26,
output wire VAR43,
input wire VAR30,
output wire VAR11,
input wire [31:0] VAR4,
input wire VAR21
);
localparam [1:0]
VAR33 = 2'd0,
VAR15 = 2'd1;
reg [1:0] VAR18 = VAR33, VAR20;
reg [31:0] VAR41 [623:0];
reg [31:0] VAR7 = 0, VAR28;
reg [9:0] VAR1... | mit |
alankarkotwal/lca-processor | pipeline/decode.v | 8,720 | module MODULE3(VAR31, VAR15, VAR35, VAR29, VAR37, VAR7, VAR38, VAR36, VAR34, VAR19, VAR8, VAR11, VAR10, VAR14, VAR12, VAR2, VAR5);
output [15:0] VAR29, VAR36, VAR34;
output reg [2:0] VAR37, VAR7, VAR38, VAR14;
output reg VAR31;
integer VAR18;
output reg VAR19, VAR8, VAR11, VAR10, VAR12, VAR2;
output reg [3:0] VAR5;
inp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.v | 2,325 | module MODULE1 (
VAR11 ,
VAR7 ,
VAR3 ,
VAR4 ,
VAR1 ,
VAR8,
VAR9,
VAR10 ,
VAR2
);
output VAR11 ;
input VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR1 ;
input VAR8;
input VAR9;
input VAR10 ;
input VAR2 ;
VAR5 VAR6 (
.VAR11(VAR11),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR10(VAR10),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4bb/sky130_fd_sc_lp__nor4bb.symbol.v | 1,333 | module MODULE1 (
input VAR6 ,
input VAR7 ,
input VAR1,
input VAR5,
output VAR2
);
supply1 VAR8;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21a/sky130_fd_sc_hdll__o21a.pp.blackbox.v | 1,359 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR3 ,
VAR5 ,
VAR1,
VAR7,
VAR2 ,
VAR8
);
output VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR1;
input VAR7;
input VAR2 ;
input VAR8 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/wb_ram/rtl/verilog/wb_ram.v | 1,495 | module MODULE1
parameter VAR14 = 256,
parameter VAR26 = VAR6(VAR14),
parameter VAR23 = "")
(input VAR17,
input VAR13,
input [VAR26-1:0] VAR1,
input [VAR16-1:0] VAR20,
input [3:0] VAR3,
input VAR4,
input [1:0] VAR8,
input [2:0] VAR29,
input VAR21,
input VAR22,
output reg VAR10,
output VAR7,
output [VAR16-1:0] VAR28);
re... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31oi/sky130_fd_sc_ls__a31oi_4.v | 2,350 | module MODULE2 (
VAR8 ,
VAR5 ,
VAR9 ,
VAR10 ,
VAR4 ,
VAR2,
VAR7,
VAR3 ,
VAR6
);
output VAR8 ;
input VAR5 ;
input VAR9 ;
input VAR10 ;
input VAR4 ;
input VAR2;
input VAR7;
input VAR3 ;
input VAR6 ;
VAR11 VAR1 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR... | apache-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/SpecialAdd.v | 4,559 | module MODULE1(
input [31:0] VAR16,
input [31:0] VAR8,
input reset,
input VAR6,
output reg VAR10 = 1'b0,
output reg [7:0] VAR7,
output reg [35:0] VAR14,
output reg [35:0] VAR4,
output reg [31:0] VAR9
);
wire VAR1;
wire [7:0] VAR3;
wire [26:0] VAR15;
wire VAR2;
wire [7:0] VAR5;
wire [26:0] VAR11;
assign VAR2 = VAR16[31]... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p.symbol.v | 1,374 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR1
);
supply1 VAR4;
supply1 VAR7 ;
supply0 VAR9 ;
supply1 VAR3;
supply1 VAR2 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
cybero/Verilog | src/PicoBlaze (kcpsm6)/rtl/picoblaze_toggle.v | 1,951 | module MODULE1(
input VAR13,
input VAR16,
output VAR4
);
wire VAR12 = VAR16;
wire [11:0] address;
wire [17:0] VAR2;
wire VAR6;
wire [7:0] VAR24;
wire [7:0] VAR25;
reg [7:0] VAR10;
wire VAR17;
wire VAR19;
wire VAR15;
wire interrupt;
wire VAR11;
wire VAR1;
wire VAR3 = VAR13;
wire VAR22;
wire VAR21 = VAR13;
VAR23 #(
.VAR9... | mit |
rurume/openrisc_vision_hardware | ISE/OpenRISC_Interface.v | 16,103 | module MODULE1(
input VAR74,
input VAR20,
output reg VAR5,
input [15:0] VAR62,
input VAR72,
output reg VAR42,
output reg [15:0] VAR38,
input VAR43,
output reg VAR7,
output reg[7:0] VAR3, output reg[7:0] VAR77, output reg[7:0] VAR50, output reg[15:0] VAR65, output [31:0] VAR63,
input [31:0] VAR37,
input [31:0] VAR54,
in... | gpl-2.0 |
jhoward321/pacman | usb_system/synthesis/submodules/usb_system_cpu_jtag_debug_module_wrapper.v | 10,038 | module MODULE1 (
VAR30,
VAR60,
clk,
VAR43,
VAR6,
VAR17,
VAR34,
VAR59,
VAR27,
VAR24,
VAR33,
VAR36,
VAR35,
VAR25,
VAR54,
VAR1,
VAR5,
VAR19,
VAR20,
VAR12,
VAR53,
VAR18,
VAR41,
VAR29,
VAR2,
VAR8,
VAR3,
VAR13,
VAR52,
VAR7,
VAR45,
VAR44,
VAR23,
VAR55,
VAR21,
VAR48
)
;
output [ 37: 0] VAR53;
output VAR18;
output VAR41;
output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfstp/sky130_fd_sc_hs__dfstp.blackbox.v | 1,283 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR6 ,
VAR4
);
input VAR2 ;
input VAR1 ;
output VAR6 ;
input VAR4;
supply1 VAR3;
supply0 VAR5;
endmodule | apache-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_02_a/hdl/verilog/user_logic.v | 20,191 | module MODULE1
(
VAR104,
VAR24,
VAR60,
VAR54,
VAR75,
VAR26,
VAR118,
VAR25,
VAR68,
VAR12,
VAR3,
VAR21,
VAR108,
VAR18,
VAR45,
VAR35,
VAR65,
VAR39,
VAR48,
VAR49,
VAR61,
VAR37,
VAR41,
VAR56,
VAR90,
VAR105,
VAR107,
VAR1,
VAR22,
VAR88,
VAR27,
VAR46,
VAR94,
VAR20,
VAR116,
VAR86,
VAR19,
VAR13,
VAR113,
VAR47,
VAR66,
VAR83,
VAR1... | bsd-2-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v | 1,816 | module MODULE1
, parameter VAR4 = VAR20(VAR7)
, parameter VAR22=0
, parameter VAR17(VAR8 )
, parameter VAR1 = VAR8>>3
)
( input VAR25
,input VAR13
,input VAR16
,input VAR21
,input [VAR4-1:0] VAR19
,input [VAR9(VAR8, 1):0] VAR2
,input [VAR9(VAR1, 1):0] VAR24
,output [VAR9(VAR8, 1):0] VAR3
);
genvar VAR18;
if (VAR8 == 0)... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4/sky130_fd_sc_ls__nand4.pp.blackbox.v | 1,320 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR4 ,
VAR7 ,
VAR3 ,
VAR9,
VAR2,
VAR8 ,
VAR6
);
output VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR7 ;
input VAR3 ;
input VAR9;
input VAR2;
input VAR8 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4b/sky130_fd_sc_hdll__or4b.pp.symbol.v | 1,326 | module MODULE1 (
input VAR2 ,
input VAR5 ,
input VAR7 ,
input VAR1 ,
output VAR6 ,
input VAR8 ,
input VAR4,
input VAR3,
input VAR9
);
endmodule | apache-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/twiddle_ram.v | 9,498 | module MODULE1 (
VAR7,
VAR14,
VAR45,
VAR48,
VAR22,
VAR44);
input VAR7;
input [31:0] VAR14;
input [6:0] VAR45;
input [6:0] VAR48;
input VAR22;
output [31:0] VAR44;
tri1 VAR7;
tri0 VAR22;
wire [31:0] VAR23;
wire [31:0] VAR44 = VAR23[31:0];
VAR40 VAR16 (
.VAR51 (VAR48),
.VAR29 (VAR7),
.VAR47 (VAR14),
.VAR15 (VAR22),
.VAR5... | gpl-3.0 |
chriz2600/DreamcastHDMI | Core/source/adv7513/I2C.v | 2,740 | module MODULE1(
input clk,
input reset,
input [6:0] VAR29,
input [7:0] VAR27,
input [7:0] VAR28,
input enable,
input VAR4,
inout VAR24,
inout VAR23,
output reg [7:0] VAR10,
output reg VAR30,
output VAR13,
input [31:0] VAR12
);
reg VAR17;
reg [6:0] VAR9;
reg VAR11;
reg [7:0] VAR31;
reg VAR14;
reg [7:0] VAR22;
VAR18 VAR1... | mit |
Marcoslz22/Tercer_Proyecto | MUX_DECO.v | 2,519 | module MODULE1(
input wire [7:0]VAR7,
input wire [7:0]VAR5,
input wire [7:0] VAR9,
input wire [7:0] VAR8,
input wire [7:0]VAR6,
input wire [7:0]VAR4,
input wire [7:0]VAR3,
input wire VAR10,
input wire VAR1,
input wire VAR2,
output reg [7:0]VAR11
);
always @(VAR7, VAR10, VAR1,VAR2)
case (VAR7)
8'b00000000: VAR11 = 8'h00... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2.pp.blackbox.v | 1,309 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR5,
VAR3,
VAR1 ,
VAR6
);
output VAR2 ;
input VAR4 ;
input VAR5;
input VAR3;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
sergev/vak-opensource | hardware/verilator/t.v | 1,675 | module MODULE1 (
VAR10,
clk, VAR6, VAR5
);
input clk;
input VAR6;
input VAR5;
output VAR10;
wire [20:0] VAR4;
wire VAR10 = &VAR4;
assign VAR4[0] = 1'b1;
assign VAR4[1] = 1'b1;
assign VAR4[2] = 1'b1;
assign VAR4[3] = 1'b1;
assign VAR4[4] = 1'b1;
assign VAR4[5] = 1'b1;
VAR1 VAR1
(.VAR10 (VAR4[6]),
.clk (clk),
.VAR6 (VAR6... | apache-2.0 |
rkrajnc/minimig-de1 | rtl/or1200/or1200_cfgr.v | 9,466 | module MODULE1(
VAR48, VAR78
);
input [31:0] VAR48; output [31:0] VAR78;
reg [31:0] VAR78;
always @(VAR48)
if (~|VAR48[31:4])
case(VAR48[3:0]) VAR128: begin
VAR78[VAR126] = VAR123;
VAR78[VAR120] = VAR117;
VAR78[VAR70] = VAR134;
VAR78[VAR61] = VAR64;
end
VAR78[VAR24] = VAR112;
VAR78[VAR96] = VAR79;
VAR78[VAR130] = VAR13... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31ai/sky130_fd_sc_ls__o31ai.behavioral.pp.v | 2,027 | module MODULE1 (
VAR13 ,
VAR7 ,
VAR4 ,
VAR17 ,
VAR1 ,
VAR2,
VAR9,
VAR8 ,
VAR14
);
output VAR13 ;
input VAR7 ;
input VAR4 ;
input VAR17 ;
input VAR1 ;
input VAR2;
input VAR9;
input VAR8 ;
input VAR14 ;
wire VAR12 ;
wire VAR15 ;
wire VAR10;
or VAR11 (VAR12 , VAR4, VAR7, VAR17 );
nand VAR5 (VAR15 , VAR1, VAR12 );
VAR16 VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso0n/sky130_fd_sc_hdll__inputiso0n.functional.pp.v | 1,776 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR5,
VAR11 ,
VAR6 ,
VAR3 ,
VAR10
);
output VAR9 ;
input VAR7 ;
input VAR5;
input VAR11 ;
input VAR6 ;
input VAR3 ;
input VAR10 ;
wire VAR4;
and VAR2 (VAR4, VAR7, VAR5 );
VAR8 VAR1 (VAR9 , VAR4, VAR11, VAR6);
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/redundant/ovl_handshake.v | 1,578 | module MODULE1 (VAR11, reset, enable, req, ack, VAR18);
parameter VAR24 = VAR2;
parameter VAR10 = 0;
parameter VAR14 = 0;
parameter VAR23 = 0;
parameter VAR22 = 0;
parameter VAR25 = 0;
parameter VAR4 = VAR12;
parameter VAR9 = VAR7;
parameter VAR16 = VAR1;
parameter VAR3 = VAR5;
parameter VAR6 = VAR8;
parameter VAR21 = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inv/sky130_fd_sc_hdll__inv_16.v | 2,017 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR7,
VAR2,
VAR8 ,
VAR4
);
output VAR6 ;
input VAR1 ;
input VAR7;
input VAR2;
input VAR8 ;
input VAR4 ;
VAR5 VAR3 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR6,
VAR1
);
output VAR6;
input VAR1;
supply1 VAR7;
supply0 VAR2;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/inv/sky130_fd_sc_ls__inv_2.v | 1,995 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR1,
VAR2,
VAR4 ,
VAR6
);
output VAR7 ;
input VAR5 ;
input VAR1;
input VAR2;
input VAR4 ;
input VAR6 ;
VAR8 VAR3 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR7,
VAR5
);
output VAR7;
input VAR5;
supply1 VAR1;
supply0 VAR2;... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/nios_mm_interconnect_0_avalon_st_adapter_003.v | 6,149 | module MODULE1 #(
parameter VAR10 = 10,
parameter VAR9 = 0,
parameter VAR3 = 10,
parameter VAR16 = 0,
parameter VAR7 = 0,
parameter VAR2 = 0,
parameter VAR13 = 1,
parameter VAR24 = 1,
parameter VAR18 = 0,
parameter VAR1 = 10,
parameter VAR4 = 0,
parameter VAR25 = 1,
parameter VAR22 = 0,
parameter VAR23 = 1,
parameter V... | gpl-3.0 |
gajjanag/6111_Project | src/ntsc2zbt.v | 2,796 | module MODULE1(clk, VAR21, VAR32, VAR14, din, VAR38, VAR30, VAR39, VAR16);
input clk; input VAR21; input [2:0] VAR32;
input VAR14;
input [29:0] din;
input VAR16;
output reg [16:0] VAR38;
output reg [11:0] VAR30;
output VAR39; parameter VAR4 = 10'd0;
parameter VAR40 = 10'd0;
reg [9:0] VAR23 = 0;
reg [9:0] VAR19 = 0;
reg... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtp/sky130_fd_sc_ls__sdfrtp.behavioral.v | 2,843 | module MODULE1 (
VAR17 ,
VAR2 ,
VAR7 ,
VAR30 ,
VAR14 ,
VAR19
);
output VAR17 ;
input VAR2 ;
input VAR7 ;
input VAR30 ;
input VAR14 ;
input VAR19;
supply1 VAR29;
supply0 VAR21;
supply1 VAR28 ;
supply0 VAR4 ;
wire VAR15 ;
wire VAR25 ;
wire VAR8 ;
reg VAR11 ;
wire VAR6 ;
wire VAR9 ;
wire VAR10 ;
wire VAR23;
wire VAR5 ;
wi... | apache-2.0 |
petrmikheev/miksys | verilog/RAM512x16_1R1W_bb.v | 7,524 | module MODULE1 (
VAR4,
VAR2,
VAR5,
VAR1,
VAR3,
VAR6);
input VAR4;
input [15:0] VAR2;
input [8:0] VAR5;
input [8:0] VAR1;
input VAR3;
output [15:0] VAR6;
tri1 VAR4;
tri0 VAR3;
endmodule | gpl-3.0 |
yanhongwang/ColorImage | AutoLevel/AutoLevel.v | 2,674 | module MODULE1( VAR13, VAR7, VAR8, VAR16, VAR14, VAR5 );
input[ VAR1 - 1 : 0 ]VAR13;
input[ VAR1 - 1 : 0 ]VAR7;
input[ VAR1 - 1 : 0 ]VAR8;
output wire[ VAR1 - 1 : 0 ]VAR16;
output wire[ VAR1 - 1 : 0 ]VAR14;
output wire[ VAR1 - 1 : 0 ]VAR5;
reg[ VAR1 - 1 : 0 ]VAR2;
reg[ VAR1 - 1 : 0 ]VAR15;
reg[ VAR1 - 1 : 0 ]VAR10;
alw... | mit |
liuyenting/CA-Project | src/IDEX_Reg.v | 1,760 | module MODULE1 (
input clk,
input VAR32,
input VAR33,
input [5-1:0] VAR28,
output [5-1:0] VAR20,
input [2-1:0] VAR30,
output [2-1:0] VAR2,
input [2-1:0] VAR21,
output [2-1:0] VAR22,
input [32-1:0] VAR10,
output [32-1:0] VAR25,
input [32-1:0] VAR19,
output [32-1:0] VAR27,
input [32-1:0] VAR34,
output [32-1:0] VAR26,
inp... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/tx_control.v | 5,696 | module MODULE1
(input clk, input rst,
input VAR62, input [7:0] VAR69, input [31:0] VAR70,
input [31:0] VAR35,
output VAR16,
input [31:0] VAR44,
input [3:0] VAR2,
input VAR6,
output VAR40,
output [31:0] VAR3,
output VAR59,
input VAR47,
output [15:0] VAR72,
output VAR5,
output VAR26,
output [31:0] VAR55
);
wire VAR4 = VA... | gpl-2.0 |
cr88192/bgbtech_bjx1core | srvcore/MemTLB.v | 5,728 | parameter[2:0] VAR8 = 3'h00; parameter[2:0] VAR6 = 3'h01; parameter[2:0] VAR34 = 3'h02; parameter[2:0] VAR36 = 3'h03; parameter[2:0] VAR14 = 3'h04;
module MODULE1(
clk,
reset,
VAR5,
VAR22,
VAR24,
VAR41,
VAR40
);
input clk;
input reset;
input[2:0] VAR5;
input[2:0] VAR22;
input[63:0] VAR24;
output[63:0] VAR41;
output[7:0... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/ime/ime_top.v | 150,174 | module MODULE1 (
clk ,
VAR101 ,
VAR126 ,
VAR185 ,
VAR18 ,
VAR103 ,
VAR148 ,
VAR275 ,
VAR307 ,
VAR254 ,
VAR21 ,
VAR124 ,
VAR210 ,
VAR191 ,
VAR224 ,
VAR343 ,
VAR33 ,
VAR265
);
parameter VAR248 = 0 ,
VAR285 = 1 ,
VAR140 = 2 ,
VAR19 = 3 ,
VAR187 = 4 ,
VAR114 = 5 ;
input clk ; input VAR101 ;
input [VAR330-1 : 0] VAR126 ; in... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_011bits.v | 1,917 | module MODULE2 (
clk,
VAR29, VAR13, VAR23, VAR34, VAR31, VAR32, VAR8, VAR3,
sum,
);
input clk;
input [VAR14+0-1:0] VAR29, VAR13, VAR23, VAR34, VAR31, VAR32, VAR8, VAR3;
output [VAR14 :0] sum;
reg [VAR14 :0] sum;
wire [VAR14+3-1:0] VAR22;
wire [VAR14+2-1:0] VAR17, VAR18;
wire [VAR14+1-1:0] VAR1, VAR21, VAR33, VAR30;
reg... | mit |
nishtahir/arty-blaze | src/bd/system/ip/system_auto_cc_1/system_auto_cc_1_stub.v | 3,466 | module MODULE1(VAR1, VAR29, VAR39,
VAR19, VAR33, VAR36, VAR13, VAR24, VAR21,
VAR20, VAR3, VAR42, VAR22, VAR23, VAR35,
VAR37, VAR6, VAR14, VAR15, VAR30, VAR26,
VAR31, VAR27, VAR34, VAR12, VAR11, VAR7,
VAR9, VAR41, VAR40, VAR17, VAR2, VAR18,
VAR8, VAR28, VAR32, VAR25, VAR4, VAR10,
VAR16, VAR5, VAR38)
;
input VAR1;
input ... | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/spi_slave_rx.v | 2,267 | module MODULE1
(input clk,
input VAR28,
input VAR23,
input VAR26,
output VAR2,
output [7:0] VAR34,
output VAR29,
output VAR5);
assign VAR2 = 1'b0;
wire VAR13, VAR32, VAR35;
sync #(3, 3) VAR36
(.clk(clk), .in({VAR23, VAR26, ~VAR28}), .out({VAR13, VAR32, VAR35}));
wire VAR11;
VAR1 VAR8(.VAR18(clk), .rst(1'b0), .en(1'b1),... | apache-2.0 |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/hps_sdram_p0_acv_hard_io_pads.v | 11,398 | module MODULE1(
VAR117,
VAR108,
VAR149,
VAR18,
VAR130,
VAR26,
VAR112,
VAR104,
VAR73,
VAR145,
VAR89,
VAR55,
VAR99,
VAR81,
VAR12,
VAR124,
VAR22,
VAR151,
VAR85,
VAR32,
VAR144,
VAR2,
VAR129,
VAR90,
VAR57,
VAR4,
VAR17,
VAR30,
VAR109,
VAR111,
VAR10,
VAR38,
VAR64,
VAR103,
VAR119,
VAR86,
VAR116,
VAR152,
VAR37,
VAR39,
VAR136,
V... | epl-1.0 |
open-fpga-nvm/open-nvm-source | fpga/NAND/uart_tx.v | 3,769 | module MODULE1(
input clk,
input rst,
input VAR11,
input [7:0] VAR2,
output VAR3,
output VAR10
);
reg [9:0] VAR4;
reg [3:0] VAR8;
wire VAR6;
reg [1:0] VAR9;
assign VAR3 = (VAR9 == VAR7) ? 1'b1 : 1'b0;
assign VAR10 = (VAR9 == VAR1) ? VAR6 : 1'b1;
assign VAR6 =( (VAR8 == 0) ? 1'b0 :
( (VAR8 == 1) ? VAR2[0] :
( (VAR8 == 2... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2.pp.symbol.v | 1,234 | module MODULE1 (
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.cache/ip/0187b43a68f9861e/design_1_axi_intc_0_0_stub.v | 2,290 | module MODULE1(VAR5, VAR20, VAR17,
VAR19, VAR11, VAR2, VAR18, VAR1, VAR3,
VAR6, VAR10, VAR12, VAR14, VAR8, VAR7,
VAR15, VAR16, VAR4, VAR13, VAR9, irq)
;
input VAR5;
input VAR20;
input [8:0]VAR17;
input VAR19;
output VAR11;
input [31:0]VAR2;
input [3:0]VAR18;
input VAR1;
output VAR3;
output [1:0]VAR6;
output VAR10;
inpu... | mit |
hcabrera-/lancetfish | RTL/router/rtl/selector.v | 8,623 | module MODULE1 #(
parameter VAR6 = VAR14
)
(
input wire [3:0] VAR2,
input wire VAR24,
input wire [3:0] VAR4,
output reg [3:0] VAR9
);
wire [3:0] VAR15;
assign VAR15 = (VAR24) ? {4{1'b0}} :
VAR2 & VAR4;
always @
if (VAR6 == VAR22)
begin
VAR28[127-:32] = (VAR9[VAR10]) ?
"VAR12+, " : " ";
VAR28[95-:32] = (VAR9[VAR13]) ?
"... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22o/sky130_fd_sc_hdll__a22o.functional.pp.v | 2,173 | module MODULE1 (
VAR10 ,
VAR11 ,
VAR15 ,
VAR13 ,
VAR14 ,
VAR18,
VAR12,
VAR9 ,
VAR2
);
output VAR10 ;
input VAR11 ;
input VAR15 ;
input VAR13 ;
input VAR14 ;
input VAR18;
input VAR12;
input VAR9 ;
input VAR2 ;
wire VAR3 ;
wire VAR1 ;
wire VAR19 ;
wire VAR6;
and VAR5 (VAR3 , VAR13, VAR14 );
and VAR8 (VAR1 , VAR11, VAR15 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32ai/sky130_fd_sc_ms__o32ai.pp.symbol.v | 1,398 | module MODULE1 (
input VAR7 ,
input VAR5 ,
input VAR4 ,
input VAR6 ,
input VAR2 ,
output VAR10 ,
input VAR8 ,
input VAR3,
input VAR9,
input VAR1
);
endmodule | apache-2.0 |
alonso193/proyecto1 | sintetizado/DMAblock.v | 210,002 | module \VAR15\MODULE3\VAR63=32 (VAR100, VAR28, VAR45, VAR27, VAR52, VAR24);
wire [8:0] 000;
wire [31:0] 001;
wire 002;
wire 003;
wire 004;
wire 005;
wire 006;
wire 007;
wire 008;
wire 009;
wire 010;
wire 011;
wire 012;
wire 013;
wire 014;
wire 015;
wire 016;
wire 017;
wire 018;
wire 019;
wire 020;
wire 021;
wire 022;
w... | gpl-3.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/manage_md/NET_MAGIC_CTRL.v | 8,654 | module MODULE1(
clk,
VAR19,
VAR10, VAR54, VAR45, VAR47,
VAR22, VAR1, VAR11,
VAR42, VAR31, VAR40,
VAR44,
VAR17,
VAR48,
VAR51,
VAR29,
VAR53,
VAR7,
VAR21,
VAR49,
VAR13,
VAR2,
VAR50,
VAR6,
VAR4,
valid,
VAR33,
VAR24,
VAR9,
VAR12,
VAR57,
VAR37,
VAR14
);
input [47:0] VAR37;
input [31:0] VAR14;
input clk;
input VAR19;
output V... | apache-2.0 |
miguelgarcia/sase2017-hls-video | hdmi_in_hls/repo/sase/hdl/verilog/my_video_filter.v | 83,566 | module MODULE1 (
VAR287,
VAR276,
VAR76,
VAR90,
VAR110,
VAR7,
VAR416,
VAR211,
VAR170,
VAR344,
VAR304,
VAR10,
VAR275,
VAR220,
VAR22,
VAR57,
VAR84,
VAR124,
VAR266,
VAR227,
VAR259,
VAR315,
VAR364,
VAR282,
VAR252,
VAR162,
VAR74,
VAR367,
VAR72,
VAR232,
VAR346,
VAR58,
VAR400,
VAR134,
VAR362,
VAR8,
VAR119,
interrupt
);
paramet... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_dff_reset_en.v | 2,549 | if (VAR2 && VAR5==VAR15) \
begin: VAR8 \
VAR4 VAR1(.VAR14 \
,.VAR6 \
,.VAR10 \
,.VAR11(~VAR13) \
,.VAR12); \
end
module MODULE1 #(VAR5=-1, VAR2=1)
(input VAR14
,input VAR13
,input [VAR5-1:0] VAR6
,input VAR10
,output [VAR5-1:0] VAR12
);
else VAR9(32)
else VAR9(31)
else VAR9(30)
else VAR9(29)
else VAR9(28)
else VAR9(27)... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invlp/sky130_fd_sc_lp__invlp.behavioral.pp.v | 1,768 | module MODULE1 (
VAR1 ,
VAR11 ,
VAR5,
VAR6,
VAR4 ,
VAR12
);
output VAR1 ;
input VAR11 ;
input VAR5;
input VAR6;
input VAR4 ;
input VAR12 ;
wire VAR2 ;
wire VAR7;
not VAR3 (VAR2 , VAR11 );
VAR8 VAR10 (VAR7, VAR2, VAR5, VAR6);
buf VAR9 (VAR1 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbp/sky130_fd_sc_ms__sdfbbp.symbol.v | 1,572 | module MODULE1 (
input VAR1 ,
output VAR9 ,
output VAR3 ,
input VAR4,
input VAR8 ,
input VAR2 ,
input VAR10 ,
input VAR5
);
supply1 VAR11;
supply0 VAR7;
supply1 VAR12 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
Xilinx/PYNQ | boards/ip/audio_direct_1.1/src/audio_direct.v | 1,089 | module MODULE1(
input wire VAR8,
input wire VAR10,
input wire VAR4,
output wire VAR11,
output wire VAR14,
output wire VAR3,
output wire VAR9
);
wire VAR5;
wire [15:0] VAR6;
reg VAR2;
reg [15:0] VAR1;
assign VAR9 = VAR2;
VAR12 VAR13 (
.clk(VAR8),
.en(VAR10),
.dout(VAR6),
.VAR11(VAR11),
.VAR7(VAR4)
);
always @(posedge VA... | bsd-3-clause |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_s_w_channel.v | 29,386 | module MODULE1 #(
parameter VAR17 = 32'hffffffff,
parameter VAR22 = 32'h00000000,
parameter VAR71 = 1 ,
parameter VAR120 = 32 ,
parameter VAR216 = 8 ,
parameter VAR7 = 1 ,
parameter VAR84 = 0 ,
parameter VAR87 = 1 ,
parameter VAR177 = 0
) (
input VAR1 ,
input VAR205 ,
input [VAR71-1:0] VAR69 ,
input [31:0] VAR68 ,
inpu... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_4.behavioral.v | 1,410 | module MODULE1( VAR6, VAR4, VAR5 );
input VAR4, VAR6;
output VAR5;
VAR1 VAR3(.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5));
VAR1 VAR2(.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5)); | apache-2.0 |
ckdur/mriscv_vivado_arty | mriscv_vivado.srcs/sources_1/ip/ddr3/ddr3/example_design/rtl/traffic_gen/mig_7series_v4_0_read_posted_fifo.v | 7,842 | module MODULE1 #
(
parameter VAR12 = 100,
parameter VAR7 = "VAR11",
parameter VAR10 = 4,
parameter VAR44 = 4,
parameter VAR37 = 32,
parameter VAR39 = 6
)
(
input VAR43,
input VAR24,
output reg VAR4,
input VAR46,
input VAR42,
input VAR30,
input VAR9,
input [VAR37-1:0] VAR47,
input [VAR39-1:0] VAR5,
input [2:0] VAR6,
inp... | mit |
alexforencich/verilog-i2c | rtl/i2c_master.v | 30,518 | module MODULE1 (
input wire clk,
input wire rst,
input wire [6:0] VAR44,
input wire VAR70,
input wire VAR82,
input wire VAR22,
input wire VAR60,
input wire VAR6,
input wire VAR94,
output wire VAR10,
input wire [7:0] VAR43,
input wire VAR52,
output wire VAR98,
input wire VAR102,
output wire [7:0] VAR72,
output wire VAR3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50.behavioral.v | 1,439 | module MODULE1 (
VAR8,
VAR2
);
output VAR8;
input VAR2;
supply1 VAR7;
supply0 VAR6;
supply1 VAR9 ;
supply0 VAR4 ;
wire VAR3;
buf VAR5 (VAR3, VAR2 );
buf VAR1 (VAR8 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd/sky130_fd_sc_hs__tapvgnd.behavioral.pp.v | 1,179 | module MODULE1 (
VAR1,
VAR2
);
input VAR1;
input VAR2;
endmodule | apache-2.0 |
jairov4/accel-oil | solution_spartan6/syn/verilog/nfa_accept_samples_generic_hw_add_14ns_14ns_14_4.v | 5,914 | module MODULE1(clk, reset, VAR1, VAR27, VAR37, VAR13);
input clk;
input reset;
input VAR1;
input [14 - 1 : 0] VAR27;
input [14 - 1 : 0] VAR37;
output [14 - 1 : 0] VAR13;
wire [14 - 1 : 0] VAR15;
wire [14 - 1 : 0] VAR19;
wire [4 - 1 : 0] VAR7;
wire [4 - 1 : 0] VAR32;
wire [8 - 1 : 4] VAR14;
wire [8 - 1 : 4] VAR6;
wire [... | lgpl-3.0 |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/AXIvideo2Mat.v | 43,829 | module MODULE1 (
VAR10,
VAR1,
VAR127,
VAR49,
VAR75,
VAR167,
VAR157,
VAR143,
VAR4,
VAR23,
VAR131,
VAR103,
VAR151,
VAR25,
VAR154,
VAR107,
VAR83,
VAR105,
VAR126,
VAR148,
VAR91,
VAR73,
VAR85,
VAR161,
VAR78,
VAR33,
VAR34,
VAR41,
VAR171,
VAR141,
VAR84,
VAR79,
VAR88,
VAR97,
VAR146,
VAR116,
VAR27,
VAR39,
VAR106,
VAR71
);
param... | mit |
cafe-alpha/wascafe | v13/r07c_de10_20201010_abus3/wasca/synthesis/submodules/wasca_mm_interconnect_0_avalon_st_adapter_005.v | 6,152 | module MODULE1 #(
parameter VAR17 = 10,
parameter VAR5 = 0,
parameter VAR19 = 10,
parameter VAR13 = 0,
parameter VAR2 = 0,
parameter VAR8 = 0,
parameter VAR11 = 1,
parameter VAR16 = 1,
parameter VAR21 = 0,
parameter VAR25 = 10,
parameter VAR24 = 0,
parameter VAR14 = 1,
parameter VAR10 = 0,
parameter VAR7 = 1,
parameter... | gpl-2.0 |
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