repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
asicguy/gplgpu | hdl/dlp/pp_sync.v | 2,438 | module MODULE1
(
input VAR4, input VAR6, input VAR1,
output VAR2 );
reg VAR5;
reg VAR3;
always @(posedge VAR4 or negedge VAR6) begin
if(!VAR6) VAR5 <= 1'b0;
end
else VAR5 <= VAR1;
end
always @(posedge VAR4 or negedge VAR6) begin
if(!VAR6) VAR3 <= 1'b0;
end
else VAR3 <= VAR5;
end
assign VAR2 = VAR3 ^ VAR5;
endmodule | gpl-3.0 |
bluespec/Flute | src_SSITH_P2/Verilog_RTL/mkDebug_Module.v | 48,578 | module MODULE1(VAR187,
VAR249,
VAR231,
VAR165,
VAR222,
VAR114,
VAR131,
VAR101,
VAR6,
VAR215,
VAR32,
VAR192,
VAR33,
VAR52,
VAR211,
VAR241,
VAR4,
VAR206,
VAR55,
VAR185,
VAR75,
VAR41,
VAR122,
VAR175,
VAR239,
VAR102,
VAR22,
VAR263,
VAR90,
VAR70,
VAR257,
VAR89,
VAR115,
VAR111,
VAR106,
VAR178,
VAR182,
VAR12,
VAR220,
VAR116,
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvn/sky130_fd_sc_ls__einvn_1.v | 2,150 | module MODULE2 (
VAR1 ,
VAR6 ,
VAR7,
VAR9,
VAR5,
VAR4 ,
VAR3
);
output VAR1 ;
input VAR6 ;
input VAR7;
input VAR9;
input VAR5;
input VAR4 ;
input VAR3 ;
VAR2 VAR8 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR1 ,
VAR6 ,
VAR7
);
output VAR1 ;... | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/rli/info_gather.v | 19,772 | module MODULE1(
clk,
reset,
VAR15,
VAR34,
VAR56,
VAR51,
VAR46,
VAR27,
VAR3,
VAR19,
VAR9,
VAR4,
VAR21,
VAR53,
VAR52,
VAR7,
VAR16,
VAR2
);
input clk;
input reset;
input VAR15;
input [138:0]VAR34;
output [7:0]VAR56;
input VAR51;
input VAR46;
output VAR27;
output [138:0]VAR3;
input [7:0]VAR19;
output VAR9;
output VAR4;
out... | apache-2.0 |
esonghori/TinyGarble | circuit_synthesis/syn_lib/COUNT.v | 1,341 | module MODULE1
parameter VAR2=7
)
(
VAR22,
VAR9
);
function integer VAR24;
input [31:0] VAR21;
reg [31:0] VAR17;
begin
VAR17 = VAR21;
for (VAR24=0; VAR17>0; VAR24=VAR24+1)
VAR17 = VAR17>>1;
end
endfunction
localparam VAR23 = VAR24(VAR2);
localparam VAR5 = VAR24(VAR2 - 2**(VAR23-1));
input [VAR2-1:0] VAR22;
output [VAR2... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/ip_repo/led_controller_1.0/hdl/led_controller_v1_0_S00_AXI.v | 14,118 | module MODULE1 #
(
parameter integer VAR2 = 32,
parameter integer VAR34 = 4
)
(
output wire[7:0] VAR31,
input wire VAR30,
input wire VAR38,
input wire [VAR34-1 : 0] VAR16,
input wire [2 : 0] VAR12,
input wire VAR13,
output wire VAR37,
input wire [VAR2-1 : 0] VAR23,
input wire [(VAR2/8)-1 : 0] VAR44,
input wire VAR21,
o... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/pre_i/md_ram.v | 2,249 | module MODULE1 (
clk ,
VAR17 ,
VAR6 ,
VAR15 ,
rd ,
VAR11 ,
VAR14
);
input clk ;
input [31:0] VAR17 ;
input [3:0] VAR6 ;
input VAR15 ;
input rd ;
input [3:0] VAR11 ;
output [31:0] VAR14 ;
VAR9 #(.VAR8(4), .VAR1(32))
VAR10 (
.VAR4 ( clk ),
.VAR7 ( ~rd ),
.VAR18 ( VAR11 ),
.VAR2 ( VAR14 ),
.VAR16 ( clk ),
.VAR5 ( ~VAR15 )... | gpl-3.0 |
Mahdi89/eTeak | runtime/verilog/amust018Teak.v | 17,859 | module MODULE45 (VAR40, VAR24, VAR25);
output VAR40;
input VAR24, VAR25;
and #(VAR60, VAR60) VAR84 (VAR40, VAR24, VAR25);
endmodule
module MODULE9 (VAR40, VAR24, VAR25);
output VAR40;
input VAR24, VAR25;
and #(VAR60, VAR60) VAR84 (VAR40, VAR24, VAR25);
endmodule
module MODULE14 (VAR40, VAR24, VAR25);
output VAR40;
inpu... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfxbp/sky130_fd_sc_hd__sdfxbp.symbol.v | 1,434 | module MODULE1 (
input VAR7 ,
output VAR5 ,
output VAR8,
input VAR4,
input VAR1,
input VAR3
);
supply1 VAR9;
supply0 VAR10;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41oi/sky130_fd_sc_lp__a41oi_4.v | 2,439 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR2 ,
VAR10 ,
VAR3 ,
VAR7 ,
VAR6,
VAR12,
VAR9 ,
VAR4
);
output VAR5 ;
input VAR8 ;
input VAR2 ;
input VAR10 ;
input VAR3 ;
input VAR7 ;
input VAR6;
input VAR12;
input VAR9 ;
input VAR4 ;
VAR11 VAR1 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VA... | apache-2.0 |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/clk_adc/clk_adc_stub.v | 1,196 | module MODULE1(VAR3, VAR2, VAR1, VAR4)
;
input VAR3;
input VAR2;
output VAR1;
output VAR4;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtp/sky130_fd_sc_hd__dlrtp_2.v | 2,362 | module MODULE2 (
VAR9 ,
VAR2,
VAR8 ,
VAR7 ,
VAR10 ,
VAR4 ,
VAR1 ,
VAR3
);
output VAR9 ;
input VAR2;
input VAR8 ;
input VAR7 ;
input VAR10 ;
input VAR4 ;
input VAR1 ;
input VAR3 ;
VAR6 VAR5 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and2/sky130_fd_sc_hd__and2.symbol.v | 1,260 | module MODULE1 (
input VAR3,
input VAR1,
output VAR7
);
supply1 VAR6;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_2.functional.v | 1,264 | module MODULE1( VAR1, VAR3, VAR9, VAR4 );
input VAR4, VAR9, VAR1;
output VAR3;
wire VAR10;
not VAR5( VAR10, VAR4 );
wire VAR8;
not VAR13( VAR8, VAR9 );
wire VAR6;
and VAR11( VAR6, VAR10, VAR8 );
wire VAR7;
not VAR2( VAR7, VAR1 );
or VAR12( VAR3, VAR6, VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32oi/sky130_fd_sc_hd__a32oi.blackbox.v | 1,434 | module MODULE1 (
VAR9 ,
VAR10,
VAR1,
VAR2,
VAR7,
VAR3
);
output VAR9 ;
input VAR10;
input VAR1;
input VAR2;
input VAR7;
input VAR3;
supply1 VAR5;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
twlostow/dsi-shield | hdl/rtl/hpdmc/spartan6/hpdmc_iobuf16.v | 2,078 | module MODULE1 (
input [15:0] VAR21,
input [15:0] VAR14,
output [15:0] VAR13,
inout [15:0] VAR10
);
VAR17 VAR5(
.VAR21(VAR21[0]),
.VAR14(VAR14[0]),
.VAR13(VAR13[0]),
.VAR10(VAR10[0])
);
VAR17 VAR16(
.VAR21(VAR21[1]),
.VAR14(VAR14[1]),
.VAR13(VAR13[1]),
.VAR10(VAR10[1])
);
VAR17 VAR3(
.VAR21(VAR21[2]),
.VAR14(VAR14[2]),... | lgpl-3.0 |
SymbiFlow/yosys | techlibs/xilinx/mux_map.v | 2,496 | module \VAR15 (VAR4, VAR16, VAR10);
parameter VAR1 = 0;
parameter VAR13 = 0;
parameter VAR3 = 1;
parameter VAR6 = 1;
parameter VAR7 = 1;
input [VAR3-1:0] VAR4;
input [VAR6-1:0] VAR16;
output [VAR7-1:0] VAR10;
parameter [VAR6-1:0] VAR2 = 0;
parameter [VAR6-1:0] VAR5 = 0;
generate
if (VAR13) begin
if (VAR2[VAR6-1] && (VA... | isc |
Gurint/EPC-Gen2-RFID-Tag-Baseband-Processor | miller_enc.v | 2,817 | module MODULE1
(
output VAR23,
output VAR17,
input VAR21,
input VAR5,
input VAR8,
input VAR20,
input VAR19, input VAR6,
input VAR22,
input VAR10
);
parameter VAR11 = 2'b00;
parameter VAR14 = 2'b01;
parameter VAR9 = 2'b10;
reg [1:0]VAR26;
reg [1:0]VAR13;
wire VAR15;
wire VAR16;
wire VAR25;
wire VAR7;
wire VAR24;
reg [5:... | mit |
vvk/sysrek | skin_color_segm/src/tx/convert_30to15_fifo.v | 6,695 | module MODULE1(
input wire rst, input wire clk, input wire VAR105, input wire [29:0] VAR86, output wire [14:0] VAR75);
wire [3:0] VAR36; reg [3:0] VAR70; wire [3:0] VAR108; reg [3:0] VAR73; wire [29:0] VAR18;
parameter VAR80 = 4'b0000;
parameter VAR104 = 4'b0001;
parameter VAR67 = 4'b0010;
parameter VAR40 = 4'b0011;
pa... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Introduction/lab1/fir_prj/solution1/impl/ip/hdl/verilog/fir.v | 8,179 | module MODULE1 (
VAR8,
VAR13,
VAR16,
VAR1,
VAR18,
VAR37,
VAR17,
VAR20,
VAR33,
VAR27,
VAR6,
VAR42
);
parameter VAR39 = 5'd1;
parameter VAR12 = 5'd2;
parameter VAR24 = 5'd4;
parameter VAR43 = 5'd8;
parameter VAR32 = 5'd16;
input VAR8;
input VAR13;
input VAR16;
output VAR1;
output VAR18;
output VAR37;
output [31:0] VAR17;... | mit |
zhaoyang10/mips-cpu | verilog/control.v | 1,133 | module MODULE1(
input wire [5:0] VAR13,
output wire VAR12, VAR16, VAR5,
output wire [1:0] VAR2,
output wire [1:0] VAR8,
output wire VAR6, VAR1, VAR17);
reg VAR10, VAR14, VAR4, VAR11, VAR3, VAR9;
always @(*) begin
VAR10 <= 1'b0;
VAR14 <= 1'b0;
VAR4 <= 1'b0;
VAR11 <= 1'b0;
VAR3 <= 1'b0;
VAR9 <= 1'b0;
case (VAR13)
6'b1000... | gpl-3.0 |
pavel-demin/red-pitaya-notes | cores/gpio_debouncer_v1_0/gpio_debouncer.v | 1,172 | module MODULE1 #
(
parameter integer VAR2 = 8,
parameter integer VAR15 = 22
)
(
input wire VAR12,
inout wire [VAR2-1:0] VAR11,
output wire [VAR2-1:0] VAR7,
output wire [VAR2-1:0] VAR16
);
reg [VAR2-1:0] VAR9 [2:0];
reg [VAR15-1:0] VAR13 [VAR2-1:0];
wire [VAR2-1:0] VAR4;
genvar VAR5;
generate
for(VAR5 = 0; VAR5 < VAR2; ... | mit |
hakehuang/pycpld | ips/ip/pwm_capture/pwm_capture.v | 4,194 | module MODULE1(
VAR16,clk,VAR17,enable,VAR14,VAR23,VAR13,VAR3,VAR8
);
input VAR16;
input clk;
input VAR17;
input enable;
input VAR13;
input VAR3;
input VAR8;
output VAR14;
output[7:0] VAR23;
reg ready;
reg[31:0] counter;
reg[31:0] VAR2;
reg[31:0] VAR22;
reg[31:0] VAR18;
reg[31:0] VAR15;
reg[31:0] VAR21;
reg VAR11;
reg ... | mit |
LSaldyt/qnp | output/vs/opt_var12_multi.v | 13,404 | module MODULE1(VAR4, VAR5, VAR8, VAR2, VAR12, VAR9, VAR1, VAR10, VAR11, VAR3, VAR6, VAR7, valid);
wire 000;
wire 001;
wire 002;
wire 003;
wire 004;
wire 005;
wire 006;
wire 007;
wire 008;
wire 009;
wire 010;
wire 011;
wire 012;
wire 013;
wire 014;
wire 015;
wire 016;
wire 017;
wire 018;
wire 019;
wire 020;
wire 021;
wi... | mit |
pwwu/FPGA | VGAbased/final/vga_game_text_top_ya.v | 3,893 | module MODULE1
(
input wire clk, reset,
input wire [1:0] VAR15,
output wire VAR16, VAR29,
output wire [2:0] VAR27
);
localparam [1:0]
VAR8 = 2'b00,
VAR2 = 2'b01,
VAR21 = 2'b10,
VAR3 = 2'b11;
reg [1:0] VAR22, VAR28;
wire [9:0] VAR1, VAR6;
wire VAR11, VAR23;
wire [3:0] VAR4;
wire [2:0] VAR19;
reg [2:0] VAR18, VAR17;
wire... | mit |
joaocarlos/udlx-verilog | rtl/pipeline/registers/mem_wb_reg.v | 3,186 | module MODULE1
parameter VAR15 = 32,
parameter VAR10 = 32,
parameter VAR16 = 5
)
(
input clk,
input VAR1,
input en,
input VAR3,
input [VAR15-1:0] VAR18,
input [VAR15-1:0] VAR17,
input [VAR16-1:0] VAR4,
input [VAR16-1:0] VAR12,
input VAR6,
input VAR19,
input [VAR10-1:0] VAR14,
output reg VAR13,
output reg [VAR15-1:0] VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2.blackbox.v | 1,368 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR2
);
output VAR5 ;
input VAR7 ;
input VAR2;
supply1 VAR4;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
Xilinx/PYNQ | boards/ip/boolean_generator_1.1/src/boolean_input.v | 1,079 | module MODULE1 # (parameter VAR6 = 24)
(
input [24:0] sel,
input [VAR6-1:0] VAR8,
output [4:0] VAR4
);
genvar VAR5;
generate
for (VAR5=0; VAR5 < 5; VAR5=VAR5+1)
begin: VAR3
VAR1 #(VAR6) VAR7(
.sel(sel[5*VAR5+4:5*VAR5]),
.VAR9(VAR8),
.VAR2(VAR4[VAR5]));
end
endgenerate
endmodule | bsd-3-clause |
hoangt/NOCulator | hring/hw/buffered/src/c_fifo_ctrl.v | 5,492 | module MODULE1
(clk, reset, VAR26, VAR33, VAR37, VAR18, VAR21, VAR14,
VAR34, VAR27, VAR24);
parameter VAR17 = 3;
parameter VAR12 = 0;
parameter VAR5 = 8;
localparam [0:VAR17-1] VAR30 = VAR12;
localparam [0:VAR17-1] VAR29 = VAR12 + VAR5 - 1;
parameter VAR8 = VAR31;
input clk;
input reset;
input VAR26;
input VAR33;
outpu... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_adc_1c_v1_00_a/hdl/verilog/cf_spi.v | 6,697 | module MODULE1 (
VAR1,
VAR6,
VAR12,
VAR4,
VAR13,
VAR11,
VAR23,
VAR22,
VAR5,
VAR19,
VAR8,
VAR17,
VAR7,
VAR15,
VAR14);
output VAR1;
output VAR6;
output VAR12;
output VAR4;
output VAR13;
input VAR11;
input VAR23;
input VAR22;
input VAR5;
input VAR19;
input [23:0] VAR8;
output [ 7:0] VAR17;
output VAR7;
output [63:0] VAR15... | mit |
svofski/mahponk | src/scorecopymux.v | 3,932 | module MODULE1 (
VAR12,
VAR8,
VAR19,
VAR5,
sel,
VAR10);
input [3:0] VAR12;
input [3:0] VAR8;
input [3:0] VAR19;
input [3:0] VAR5;
input [1:0] sel;
output [3:0] VAR10;
wire [3:0] VAR4;
wire [3:0] VAR2 = VAR5[3:0];
wire [3:0] VAR22 = VAR8[3:0];
wire [3:0] VAR20 = VAR12[3:0];
wire [3:0] VAR10 = VAR4[3:0];
wire [3:0] VAR15... | bsd-2-clause |
minosys-jp/FPGA | Zybo/fillbox/HDL/fillbox_act.v | 6,636 | module MODULE1 (
input wire [27:0] VAR9,
input wire [9:0] VAR10,
input wire [9:0] VAR8,
input wire VAR3,
output wire VAR20,
input wire clk,
input wire VAR25,
output reg [27:0] VAR26,
output reg VAR21,
output reg [7:0] VAR1,
output reg [3:0] VAR15
);
parameter VAR16 = 2'h0,
VAR19 = 2'h1,
VAR24 = 2'h2;
localparam VAR6 = ... | bsd-2-clause |
cr88192/bgbtech_bjx1core | bjx1core32/ArithAlu.v | 2,670 | module MODULE1(
clk,
VAR5,
VAR1,
VAR29,
VAR30,
VAR12,
VAR13
);
input clk;
input[4:0] VAR5;
input[31:0] VAR1;
input[31:0] VAR29;
output[31:0] VAR30;
input[3:0] VAR12;
output[3:0] VAR13;
parameter[4:0] VAR28 = 5'h00;
parameter[4:0] VAR24 = 5'h01;
parameter[4:0] VAR15 = 5'h02;
parameter[4:0] VAR21 = 5'h03;
parameter[4:0] ... | mit |
keith-epidev/VHDL-lib | top/lab_3/part_1/ip/dds/dds_stub.v | 1,185 | module MODULE1(VAR1, VAR2, VAR3)
;
input VAR1;
output VAR2;
output [15:0]VAR3;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufbuf/sky130_fd_sc_hs__bufbuf_16.v | 1,909 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR6,
VAR3
);
output VAR5 ;
input VAR1 ;
input VAR6;
input VAR3;
VAR4 VAR2 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR5,
VAR1
);
output VAR5;
input VAR1;
supply1 VAR6;
supply0 VAR3;
VAR4 VAR2 (
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule | apache-2.0 |
ILoveSpeccy/Aeon-Lite | cores/radio-86rk/src/k580wg75.v | 5,027 | module MODULE1(
input clk,
input VAR57,
input VAR30,
input[7:0] VAR51,
input VAR16,
input VAR37,
input VAR25,
input VAR22,
input VAR10,
input[7:0] VAR52,
output reg VAR55,
output reg irq,
output[7:0] VAR50,
output[3:0] VAR48,
output reg[6:0] VAR38,
output VAR18,
output VAR61,
output VAR43,
output VAR3,
output[1:0] VAR2... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/ppu/ppu_vga.v | 9,343 | module MODULE1
(
input VAR31, input VAR7,
output VAR36, output VAR27, output [2:0] VAR16, output [2:0] VAR30, output [1:0] VAR21,
input [5:0] VAR28,
output [9:0] VAR19, output [9:0] VAR35, output [9:0] VAR37, output VAR32, output VAR6 );
localparam [9:0] VAR22 = 10'h280,
VAR24 = 10'h1E0;
localparam [9:0] VAR25 = 10'h10... | mit |
chaohu/Daily-Learning | Verilog/lab5/lab5_2/lab5_2_1/lab5_2_1.srcs/sources_1/new/lab5_2_1.v | 1,656 | module MODULE1(
input in,reset,clk,
output reg VAR3
);
reg [1:0] state,VAR1;
parameter VAR2 = 0,VAR4 = 1,VAR5 = 2,VAR6 = 3;
always @(posedge clk or posedge reset)
if(reset)
state = VAR2;
else
state = VAR1;
always @(state)
begin
case(state)
VAR2: VAR3 = 0;
VAR4: VAR3 = 0;
VAR5: VAR3 = 0;
VAR6: VAR3 = 1;
endcase
end
alwa... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtp/sky130_fd_sc_ms__dfrtp.symbol.v | 1,395 | module MODULE1 (
input VAR1 ,
output VAR3 ,
input VAR2,
input VAR8
);
supply1 VAR6;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2.symbol.v | 1,357 | module MODULE1 (
input VAR3,
output VAR4
);
supply1 VAR1;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/tx_fct_send.v | 4,354 | module MODULE1(
input VAR5,
input VAR8,
input VAR3,
input VAR2,
input VAR9,
output reg [2:0] VAR10
);
reg [2:0] VAR11;
reg VAR1;
reg [2:0] VAR12;
reg [2:0] VAR7;
reg [2:0] VAR6;
reg [2:0] VAR4;
always@
begin
VAR4 = VAR6;
case(VAR6)
3'd0:
begin
VAR4 = 3'd2;
end
3'd1:
begin
if(VAR11 == 3'd7)
begin
VAR4 = 3'd2;
end
else
V... | gpl-3.0 |
bigeagle/riffa | fpga/riffa_hdl/tx_port_32.v | 7,591 | module MODULE1 #(
parameter VAR33 = 9'd32,
parameter VAR59 = 512,
parameter VAR82 = VAR18((2**VAR18(VAR59))+1)
)
(
input VAR3,
input VAR87,
input [2:0] VAR92,
output VAR75, input VAR96, output [31:0] VAR27, output [31:0] VAR36, output [31:0] VAR26, output VAR40, input VAR79,
input [VAR33-1:0] VAR71, input VAR95, output... | bsd-3-clause |
praveendath92/DDR2_Interface_Xilinx_XUPV5 | source/ddr2_idelay_ctrl.v | 3,561 | module MODULE1 #
(
parameter VAR10 = "VAR3"
)
(
input VAR5,
input VAR7,
output VAR8
);
VAR1 VAR9
(
.VAR6(VAR8),
.VAR4(VAR5),
.VAR2(VAR7)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41oi/sky130_fd_sc_ls__a41oi_4.v | 2,439 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR9 ,
VAR11 ,
VAR5 ,
VAR3 ,
VAR10,
VAR7,
VAR4 ,
VAR2
);
output VAR6 ;
input VAR1 ;
input VAR9 ;
input VAR11 ;
input VAR5 ;
input VAR3 ;
input VAR10;
input VAR7;
input VAR4 ;
input VAR2 ;
VAR8 VAR12 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR10(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrtp/sky130_fd_sc_hd__sdfrtp.functional.v | 1,972 | module MODULE1 (
VAR7 ,
VAR13 ,
VAR5 ,
VAR3 ,
VAR10 ,
VAR8
);
output VAR7 ;
input VAR13 ;
input VAR5 ;
input VAR3 ;
input VAR10 ;
input VAR8;
wire VAR4 ;
wire VAR1 ;
wire VAR2;
not VAR11 (VAR1 , VAR8 );
VAR6 VAR14 (VAR2, VAR5, VAR3, VAR10 );
VAR15 VAR12 VAR9 (VAR4 , VAR2, VAR13, VAR1);
buf VAR16 (VAR7 , VAR4 );
endmodu... | apache-2.0 |
jairov4/accel-oil | solution_virtex5_plb/syn/verilog/nfa_accept_samples_generic_hw_start_indices.v | 1,478 | module MODULE1 (VAR4, VAR1, VAR13, VAR5, VAR8, clk);
parameter VAR10 = 32;
parameter VAR6 = 4;
parameter VAR7 = 16;
input[VAR6-1:0] VAR4;
input VAR1;
input[VAR10-1:0] VAR13;
input VAR5;
output reg[VAR10-1:0] VAR8;
input clk;
reg [VAR10-1:0] VAR12[VAR7-1:0];
always @(posedge clk)
begin
if (VAR1)
begin
if (VAR5)
begin
VA... | lgpl-3.0 |
sam-falvo/verilog-foundations | memory/async_bridge.v | 3,513 | module MODULE1(
input VAR9,
input VAR19,
input VAR8,
input VAR15,
input VAR13,
input [1:0] VAR2,
input [19:1] VAR7,
input [15:0] VAR16,
output VAR18,
output [15:0] VAR21,
output VAR5,
output VAR23,
output VAR4,
output VAR14,
output VAR20,
output VAR6,
output [19:1] VAR22,
output [15:0] VAR17,
input [15:0] VAR12
);
reg ... | mpl-2.0 |
lokisz/openzcore | pippo-0.9/rtl/verilog/pippo_bpu.v | 6,333 | module MODULE1(
clk, rst,
VAR24, VAR27, VAR20,
VAR3, VAR16, VAR2,
VAR18,
VAR13, VAR7,
VAR22, VAR17, VAR26,
VAR19, VAR25, VAR1
);
input clk;
input rst;
input [4:0] VAR24;
input [4:0] VAR27;
input [4:0] VAR20;
input [29:0] VAR3;
input [29:0] VAR16;
input [29:0] VAR2;
input [31:0] VAR18;
input VAR22;
input VAR17;
output [... | gpl-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_avlmm_pr_freeze_bridge_0/altera_avlmm_pr_freeze_bridge_171/synth/ghrd_10as066n2_avlmm_pr_freeze_bridge_0_altera_avlmm_pr_freeze_bridge_171_bb3qwvq.v | 9,392 | module MODULE1 #(
parameter VAR6 = 0,
parameter VAR21 = 0
) (
input wire VAR14, input wire VAR33, output wire VAR27, input wire VAR4, output wire VAR18, input wire VAR23, output wire VAR15, output wire [9:0] VAR7, output wire [3:0] VAR26, output wire [31:0] VAR32, input wire [31:0] VAR13, output wire [2:0] VAR12, input... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_mem/bsg_mem_2r1w_sync.v | 3,136 | module MODULE1 #(parameter VAR19(VAR8)
, parameter VAR19(VAR10)
, parameter VAR2=0
, parameter VAR15=VAR20(VAR10)
, parameter VAR14=0
)
(input VAR3
, input VAR12
, input VAR18
, input [VAR15-1:0] VAR17
, input [VAR8-1:0] VAR1
, input VAR16
, input [VAR15-1:0] VAR6
, output logic [VAR8-1:0] VAR5
, input VAR11
, input [V... | bsd-3-clause |
LSaldyt/qnp | output/vs/opt_var21_multi.v | 35,884 | module MODULE1(VAR10, VAR3, VAR18, VAR16, VAR1, VAR14, VAR15, VAR7, VAR13, VAR17, VAR12, VAR19, VAR9, VAR20, VAR8, VAR5, VAR21, VAR4, VAR2, VAR11, VAR6, valid);
wire 0000;
wire 0001;
wire 0002;
wire 0003;
wire 0004;
wire 0005;
wire 0006;
wire 0007;
wire 0008;
wire 0009;
wire 0010;
wire 0011;
wire 0012;
wire 0013;
wire ... | mit |
jas0n1ee/THU-DSD | FB/ip/Binary_VGA_Controller/hdl/VGA_OSD_RAM.v | 1,422 | module MODULE1 ( VAR6,
VAR8,
VAR17,
VAR11,
VAR4,
VAR7,
VAR9,
VAR23,
VAR10,
VAR28,
VAR1,
VAR26,
VAR15,
VAR14,
VAR25,
VAR5 );
output reg [9:0] VAR6;
output reg [9:0] VAR8;
output reg [9:0] VAR17;
input [18:0] VAR11;
input VAR4;
input [18:0] VAR9;
input VAR7;
input VAR23;
input VAR10;
input [9:0] VAR28;
input [9:0] VAR1;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21ba/sky130_fd_sc_hdll__o21ba.pp.blackbox.v | 1,398 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR4 ,
VAR3,
VAR6,
VAR2,
VAR1 ,
VAR5
);
output VAR8 ;
input VAR7 ;
input VAR4 ;
input VAR3;
input VAR6;
input VAR2;
input VAR1 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux4/sky130_fd_sc_hs__mux4.pp.blackbox.v | 1,323 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR5 ,
VAR4 ,
VAR9 ,
VAR1 ,
VAR6 ,
VAR2,
VAR8
);
output VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR2;
input VAR8;
endmodule | apache-2.0 |
vvk/sysrek | skin_color_segm/ipcore_dir/sub8.v | 8,597 | module MODULE1 (
clk, VAR88, VAR22, VAR70, VAR1
);
input clk;
input VAR88;
input [7 : 0] VAR22;
input [7 : 0] VAR70;
output [7 : 0] VAR1;
wire \VAR69/VAR51 ;
wire \VAR69/VAR56 ;
wire \VAR69/VAR34 ;
wire \VAR69/VAR9 ;
wire \VAR69/VAR35 ;
wire \VAR69/VAR99 ;
wire \VAR69/VAR87 ;
wire \VAR69/VAR26 ;
wire \VAR69/VAR96 ;
wir... | gpl-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_pic.v | 7,397 | module MODULE1(
clk, rst, VAR19, VAR5, VAR4, VAR16, VAR3,
VAR12, VAR1,
VAR10
);
input clk; input rst; input VAR19; input VAR5; input [31:0] VAR4; input [31:0] VAR16; output [31:0] VAR3; output VAR12; output VAR1;
input [VAR20-1:0] VAR10;
reg [VAR20-1:2] VAR18; else
wire [VAR20-1:2] VAR18; VAR7
reg [VAR20-1:0] VAR11; el... | gpl-3.0 |
eecsninja/duinocube-core | common/sprite_reg_decoder.v | 4,104 | module MODULE1(VAR13,
VAR10,
VAR9,
VAR20,
VAR5,
VAR7,
VAR49,
VAR14,
VAR27,
VAR35,
VAR41,
VAR38,
VAR17,
VAR31,
VAR32,
VAR47,
VAR45,
VAR6,
VAR52,
VAR29);
input [VAR19-1:0] VAR13;
output VAR10;
output VAR9;
output VAR20;
output VAR5;
output VAR7;
output VAR49;
output VAR14;
output VAR27;
output VAR35;
output [VAR43-1:0] V... | gpl-3.0 |
MartinMosbeck/NoCMonitor | buildCONNECT4x4/mkRouterOutputArbitersRoundRobin.v | 37,365 | module MODULE1(VAR9,
VAR137,
VAR117,
VAR15,
VAR217,
VAR172,
VAR147,
VAR96,
VAR66,
VAR167,
VAR50,
VAR211,
VAR12,
VAR58,
VAR3,
VAR146,
VAR57);
input VAR9;
input VAR137;
input [4 : 0] VAR117;
output [4 : 0] VAR15;
input VAR217;
input [4 : 0] VAR172;
output [4 : 0] VAR147;
input VAR96;
input [4 : 0] VAR66;
output [4 : 0] V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111o/sky130_fd_sc_hs__a2111o.blackbox.v | 1,358 | module MODULE1 (
VAR5 ,
VAR7,
VAR4,
VAR6,
VAR2,
VAR1
);
output VAR5 ;
input VAR7;
input VAR4;
input VAR6;
input VAR2;
input VAR1;
supply1 VAR3;
supply0 VAR8;
endmodule | apache-2.0 |
andres-erbsen/sha3-verilog-mirror | low_throughput_core/rtl/padder.v | 3,078 | module MODULE1(clk, reset, in, VAR14, VAR6, VAR10, VAR11, out, VAR4, VAR3);
input clk, reset;
input [31:0] in;
input VAR14, VAR6;
input [1:0] VAR10;
output VAR11;
output reg [575:0] out;
output VAR4;
input VAR3;
reg state;
reg VAR2;
reg [17:0] VAR9;
wire [31:0] VAR5;
reg [31:0] VAR13;
wire VAR8,
VAR7;
assign VAR11 = VA... | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ip/design_1_auto_us_1/synth/design_1_auto_us_1.v | 10,501 | module MODULE1 (
VAR62,
VAR19,
VAR28,
VAR74,
VAR50,
VAR66,
VAR3,
VAR30,
VAR71,
VAR6,
VAR102,
VAR40,
VAR78,
VAR8,
VAR14,
VAR65,
VAR90,
VAR20,
VAR38,
VAR41,
VAR26,
VAR69,
VAR24,
VAR51,
VAR39,
VAR43,
VAR56,
VAR76,
VAR89,
VAR61,
VAR100,
VAR73,
VAR12,
VAR37,
VAR42,
VAR36,
VAR101,
VAR25,
VAR34,
VAR13
);
input wire VAR62;
inp... | gpl-3.0 |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CoreAPB3/4.0.100/rtl/vlog/amba_bfm/bfm_apb.v | 7,639 | module
MODULE1
(
VAR140
,
VAR25
,
VAR90
,
VAR171
,
VAR163
,
VAR117
,
VAR99
,
VAR137
,
VAR14
,
VAR100
,
VAR73
,
VAR101
,
VAR122
,
VAR86
,
VAR129
,
VAR111
,
VAR70
,
VAR48
,
VAR160
,
VAR138
,
VAR93
,
VAR27
)
;
parameter
VAR72
=
;
parameter
VAR1
=
16384
;
parameter
VAR130
=
1024
;
parameter
VAR30
=
65536
;
parameter
VAR21... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fa/sky130_fd_sc_ms__fa.behavioral.v | 1,977 | module MODULE1 (
VAR18,
VAR12 ,
VAR5 ,
VAR16 ,
VAR24
);
output VAR18;
output VAR12 ;
input VAR5 ;
input VAR16 ;
input VAR24 ;
supply1 VAR3;
supply0 VAR10;
supply1 VAR21 ;
supply0 VAR26 ;
wire VAR23 ;
wire VAR15 ;
wire VAR27 ;
wire VAR6 ;
wire VAR19 ;
wire VAR11 ;
wire VAR25;
wire VAR20 ;
or VAR9 (VAR23 , VAR24, VAR16 )... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invlp/sky130_fd_sc_lp__invlp_m.v | 2,022 | module MODULE2 (
VAR3 ,
VAR5 ,
VAR8,
VAR2,
VAR6 ,
VAR1
);
output VAR3 ;
input VAR5 ;
input VAR8;
input VAR2;
input VAR6 ;
input VAR1 ;
VAR7 VAR4 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
supply1 VAR8;
supply0 VAR2;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211ai/sky130_fd_sc_ls__o211ai.pp.blackbox.v | 1,397 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR5 ,
VAR7 ,
VAR3 ,
VAR2,
VAR8,
VAR4 ,
VAR6
);
output VAR1 ;
input VAR9 ;
input VAR5 ;
input VAR7 ;
input VAR3 ;
input VAR2;
input VAR8;
input VAR4 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31oi/sky130_fd_sc_lp__a31oi.behavioral.pp.v | 2,038 | module MODULE1 (
VAR13 ,
VAR15 ,
VAR7 ,
VAR11 ,
VAR8 ,
VAR17,
VAR5,
VAR14 ,
VAR6
);
output VAR13 ;
input VAR15 ;
input VAR7 ;
input VAR11 ;
input VAR8 ;
input VAR17;
input VAR5;
input VAR14 ;
input VAR6 ;
wire VAR16 ;
wire VAR4 ;
wire VAR3;
and VAR12 (VAR16 , VAR11, VAR15, VAR7 );
nor VAR9 (VAR4 , VAR8, VAR16 );
VAR2 V... | apache-2.0 |
ptracton/pmodacl2 | behavioral/wb_intercon/wb_arbiter.v | 4,824 | module MODULE1
parameter VAR17 = 32,
parameter VAR11 = 2)
(
input VAR30,
input VAR26,
input [VAR11*VAR17-1:0] VAR24,
input [VAR11*VAR20-1:0] VAR2,
input [VAR11*4-1:0] VAR25,
input [VAR11-1:0] VAR3,
input [VAR11-1:0] VAR21,
input [VAR11-1:0] VAR34,
input [VAR11*3-1:0] VAR8,
input [VAR11*2-1:0] VAR35,
output [VAR11*VAR20... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4/sky130_fd_sc_hdll__or4.symbol.v | 1,290 | module MODULE1 (
input VAR9,
input VAR6,
input VAR5,
input VAR1,
output VAR2
);
supply1 VAR4;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/probec_p/sky130_fd_sc_hdll__probec_p.blackbox.v | 1,256 | module MODULE1 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
supply1 VAR2;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/buf/sky130_fd_sc_hvl__buf_8.v | 2,001 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR8,
VAR5,
VAR6 ,
VAR2
);
output VAR1 ;
input VAR4 ;
input VAR8;
input VAR5;
input VAR6 ;
input VAR2 ;
VAR3 VAR7 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR8;
supply0 VAR5;... | apache-2.0 |
mithro/HDMI2USB | hdl/edid/edid_master_slave_hack.v | 4,748 | module MODULE1(
input VAR19,
input clk,
inout VAR21,
output VAR5,
inout VAR3,
input VAR18,
input VAR29,
output reg VAR13,
output [7:0] VAR9,
output VAR7,
output reg VAR6,
input VAR1
);
reg VAR28;
wire [7:0] VAR20;
reg [6:0] counter;
reg [6:0] VAR31, VAR25;
reg [7:0] VAR10;
reg VAR16,VAR4;
wire VAR2,VAR22;
assign VAR2 =... | bsd-2-clause |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/cmd_fsm.v | 11,842 | module MODULE1(
clk,
VAR7,
rst,
VAR6,
VAR40,
VAR2,
VAR8,
VAR10,
VAR39,
VAR22,
VAR18,
VAR36,
VAR34,
VAR26,
VAR3,
VAR15,
VAR12,
VAR29,
VAR45
);
input clk;
input VAR7;
input rst;
input VAR6;
input VAR40;
input VAR2;
input VAR8;
input VAR10;
input VAR39;
input VAR22;
input VAR18;
input VAR36;
input VAR34;
output VAR26;
out... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_buf_pt1.v | 2,255 | module MODULE1(
VAR6, VAR7, VAR10, VAR1,
VAR5, VAR13, VAR2, VAR11, VAR9, VAR3
);
output [4:0] VAR6;
output VAR7;
output [4:0] VAR10;
output VAR1;
input [4:0] VAR5;
input VAR13;
input [4:0] VAR2;
input VAR11;
input VAR9, VAR3;
VAR12 #(5) VAR4(
.din (VAR2[4:0]),
.VAR8 (VAR10[4:0]),
.clk (VAR11),
.VAR3 (1'b0),
.VAR9 (5'd0... | gpl-2.0 |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_SRAM_inputs.v | 2,318 | module MODULE1 (
address,
VAR7,
clk,
VAR3,
VAR8,
VAR4,
VAR9,
VAR1
)
;
output [ 14: 0] VAR9;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input VAR7;
input clk;
input VAR3;
input VAR8;
input [ 31: 0] VAR4;
wire VAR5;
reg [ 14: 0] VAR2;
wire [ 14: 0] VAR9;
wire [ 14: 0] VAR6;
wire [ 31: 0] VAR1;
assign VAR5 = 1;
assign V... | gpl-3.0 |
gilith/opentheory | data/verilog/counter.v | 2,154 | module MODULE3(VAR6,VAR3,VAR7,VAR15);
parameter VAR9 = 0;
input [VAR9-1:0] VAR6;
input [VAR9-1:0] VAR3;
output [VAR9-1:0] VAR7;
output [VAR9-1:0] VAR15;
assign VAR7 = VAR6 ^ VAR3;
assign VAR15 = VAR6 & VAR3;
endmodule
module MODULE1(clk,VAR18,VAR16,VAR5);
parameter VAR9 = 0;
input clk;
input VAR18;
input [VAR9-1:0] VAR... | mit |
kylemsguy/FPGA-Litecoin-Miner | experimental/LX150-EIGHT-C/ltcminer_icarus.v | 11,870 | module MODULE1 (VAR18, VAR82, VAR35, VAR40, VAR90, VAR97, VAR50, VAR109, VAR51, VAR16);
function integer VAR83; input integer VAR14;
begin
VAR14 = VAR14-1;
for (VAR83=0; VAR14>0; VAR83=VAR83+1)
VAR14 = VAR14>>1;
end
endfunction
parameter VAR91 = VAR91;
parameter VAR91 = 50; VAR61
parameter VAR46 = VAR46; else
parameter... | gpl-3.0 |
cwilkens/fpga-hero | PS2control.v | 6,042 | module MODULE1(clk, VAR6, VAR7, VAR11, VAR1, VAR2);
input clk;
input VAR6;
output VAR7;
output VAR11;
output VAR1;
output [7:0] VAR2;
reg VAR7;
reg VAR11;
reg VAR1;
reg [7:0] VAR2;
reg [3:0] VAR4;
reg [3:0] VAR3;
reg [3:0] VAR9;
reg [3:0] VAR8;
reg [10:0] VAR12;
reg [7:0] VAR10;
reg [7:0] VAR5; | mit |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_av_config_auto_init_ob_de2_115.v | 7,268 | module MODULE1 (
VAR13,
VAR10
);
parameter VAR4 = 9'h01A;
parameter VAR15 = 9'h01A;
parameter VAR12 = 9'h07B;
parameter VAR18 = 9'h07B;
parameter VAR7 = 9'h0F8;
parameter VAR9 = 9'h006;
parameter VAR2 = 9'h000;
parameter VAR6 = 9'h001;
parameter VAR17 = 9'h002;
parameter VAR3 = 9'h001;
input [ 5: 0] VAR13;
output [26: ... | mit |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/NIOS_SYSTEMV3/synthesis/submodules/NIOS_SYSTEMV3_CH0_TIME.v | 6,808 | module MODULE1 (
address,
VAR10,
clk,
VAR14,
VAR2,
VAR8,
VAR11,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input VAR10;
input clk;
input [ 13: 0] VAR14;
input VAR2;
input VAR8;
input [ 31: 0] VAR11;
wire VAR9;
reg [ 13: 0] VAR6;
reg [ 13: 0] VAR7;
wire [ 13: 0] VAR4;
reg [ 13: 0] VAR13;
wire VAR1;
wire [ 13:... | gpl-2.0 |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/nios_timer_0.v | 6,677 | module MODULE1 (
address,
VAR5,
clk,
VAR8,
VAR10,
VAR31,
irq,
VAR22
)
;
output irq;
output [ 15: 0] VAR22;
input [ 2: 0] address;
input VAR5;
input clk;
input VAR8;
input VAR10;
input [ 15: 0] VAR31;
wire VAR25;
wire VAR1;
wire VAR33;
reg [ 3: 0] VAR19;
wire VAR30;
reg VAR15;
wire VAR32;
wire [ 31: 0] VAR28;
reg [ 31: ... | gpl-3.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | receptor_teclado_ps2.v | 3,033 | module MODULE1
(
input wire clk, reset,
input wire VAR17, VAR3, VAR1,
output reg VAR4,
output wire [10:0] dout
);
localparam [1:0]
VAR16 = 2'b00,
VAR13 = 2'b01,
VAR11 = 2'b10;
reg [1:0] VAR10, VAR18;
reg [7:0] VAR12;
wire [7:0] VAR8;
reg VAR15;
wire VAR5;
reg [3:0] VAR7, VAR14;reg [10:0] VAR6, VAR2; wire VAR9;
always @... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31oi/sky130_fd_sc_lp__a31oi.functional.v | 1,448 | module MODULE1 (
VAR3 ,
VAR6,
VAR8,
VAR10,
VAR4
);
output VAR3 ;
input VAR6;
input VAR8;
input VAR10;
input VAR4;
wire VAR5 ;
wire VAR7;
and VAR9 (VAR5 , VAR10, VAR6, VAR8 );
nor VAR2 (VAR7, VAR4, VAR5 );
buf VAR1 (VAR3 , VAR7 );
endmodule | apache-2.0 |
bluespec/Flute | builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkCSR_MIP.v | 7,574 | module MODULE1(VAR34,
VAR59,
VAR7,
VAR5,
VAR19,
VAR44,
VAR13,
VAR3,
VAR56,
VAR53,
VAR24,
VAR28);
input VAR34;
input VAR59;
input VAR7;
output [63 : 0] VAR5;
input [27 : 0] VAR19;
input [63 : 0] VAR44;
input VAR13;
output [63 : 0] VAR3;
input VAR56;
input VAR53;
input VAR24;
input VAR28;
wire [63 : 0] VAR3, VAR5;
reg VA... | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/I2C/controller_tst.v | 3,857 | module MODULE1;
reg clk;
reg VAR10;
reg rst;
reg en;
wire VAR9;
wire [15:0] VAR3;
wire [15:0] VAR6;
wire [15:0] VAR8;
wire [15:0] VAR13;
wire [15:0] VAR4;
wire [15:0] VAR5;
wire VAR14;
wire VAR16;
wire VAR17;
reg VAR15, VAR2;
wire VAR11;
assign VAR17 = VAR2? 1'VAR12 : VAR15;
assign VAR11 = VAR17;
VAR7 VAR1 (
.clk(clk),... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1.functional.v | 1,556 | module MODULE1 (
VAR3,
VAR1,
VAR6
);
output VAR3;
input [7:0] VAR1;
input [7:0] VAR6;
bufif1 VAR9 (VAR3 , !VAR1[0], VAR6[0] );
bufif1 VAR11 (VAR3 , !VAR1[1], VAR6[1] );
bufif1 VAR2 (VAR3 , !VAR1[2], VAR6[2] );
bufif1 VAR5 (VAR3 , !VAR1[3], VAR6[3] );
bufif1 VAR10 (VAR3 , !VAR1[4], VAR6[4] );
bufif1 VAR4 (VAR3 , !VAR1[5... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31a/sky130_fd_sc_ms__o31a.symbol.v | 1,346 | module MODULE1 (
input VAR7,
input VAR6,
input VAR4,
input VAR8,
output VAR2
);
supply1 VAR9;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
marshmellow42/proxmark3 | fpga/hi_reader.v | 9,098 | module MODULE1(
VAR14,
VAR28, VAR5, VAR3, VAR16, VAR41, VAR19,
VAR27, VAR38,
VAR12, VAR22, VAR15, VAR36,
VAR18,
VAR29, VAR33
);
input VAR14;
output VAR28, VAR5, VAR3, VAR16, VAR41, VAR19;
input [7:0] VAR27;
output VAR38;
input VAR15;
output VAR12, VAR22, VAR36;
output VAR18;
input [1:0] VAR29;
input [2:0] VAR33;
assign... | gpl-2.0 |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_regfile_reg1.v | 1,988 | module MODULE1 (
address,
clk,
VAR1,
VAR3,
VAR2
)
;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input clk;
input [ 31: 0] VAR1;
input VAR3;
wire VAR5;
wire [ 31: 0] VAR4;
wire [ 31: 0] VAR6;
reg [ 31: 0] VAR2;
assign VAR5 = 1;
assign VAR6 = {32 {(address == 0)}} & VAR4;
always @(posedge clk or negedge VAR3)
begin
if (... | gpl-3.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_ddr_mc_phy.v | 91,290 | module MODULE1
parameter VAR414 = 4'b1111,
parameter VAR442 = 4'b0000,
parameter VAR160 = 4'b0000,
parameter VAR108 = 4'b0000,
parameter VAR257 = 4'b0000,
parameter VAR241 = 4'hc,
parameter VAR179 = 4'hf,
parameter VAR51 = 4'hf,
parameter VAR385 = 4'hf,
parameter VAR449 = 4'hf,
parameter VAR92 = 0,
parameter VAR461 = "... | mit |
benreynwar/fpga-sdrlib | verilog/uhd/qa_wrapper.v | 2,914 | module MODULE1
parameter VAR33 = 32
)
(
input wire clk,
input wire reset,
input wire [VAR33-1:0] VAR5,
input wire VAR3,
output wire [VAR33-1:0] VAR27,
output wire VAR23
);
wire [VAR33-1:0] VAR31;
wire VAR9;
wire [VAR4-1:0] VAR8;
wire VAR13;
wire VAR20;
wire VAR11;
assign VAR11 = ~reset;
VAR26 #(VAR33) VAR17
(.clk(clk),... | mit |
twlostow/dsi-shield | hdl/rtl/hpdmc/hpdmc.v | 7,164 | module MODULE1 #(
parameter VAR28 = 4'h0,
parameter VAR82 = 25,
parameter VAR10 = 10,
parameter VAR62 = 0,
parameter VAR92 = 0,
parameter VAR53 = 0,
parameter VAR19 = 0
) (
input VAR97,
input VAR12,
input VAR54,
input [13:0] VAR81,
input VAR45,
input [31:0] VAR27,
output [31:0] VAR18,
input [VAR82-1:0] VAR40,
input VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22ai/sky130_fd_sc_hdll__o22ai.functional.v | 1,527 | module MODULE1 (
VAR12 ,
VAR5,
VAR1,
VAR4,
VAR10
);
output VAR12 ;
input VAR5;
input VAR1;
input VAR4;
input VAR10;
wire VAR2 ;
wire VAR7 ;
wire VAR8;
nor VAR11 (VAR2 , VAR4, VAR10 );
nor VAR3 (VAR7 , VAR5, VAR1 );
or VAR9 (VAR8, VAR7, VAR2);
buf VAR6 (VAR12 , VAR8 );
endmodule | apache-2.0 |
dm-urievich/afc-smm | software/third-patry/pipelined_fft_256/trunk/SRC/rotator256_v.v | 5,283 | module MODULE1 (VAR6 ,VAR1,VAR9,VAR31, VAR4,VAR25, VAR11, VAR12,VAR19 );
input VAR1 ;
wire VAR1 ;
input VAR6 ;
wire VAR6 ;
input VAR9 ; input [VAR17-1:0] VAR25; wire [VAR17-1:0] VAR25 ;
input [VAR17-1:0] VAR4 ; input VAR31 ; wire VAR31 ;
output [VAR17-1:0] VAR12 ; wire [VAR17-1:0] VAR12 ;
output [VAR17-1:0] VAR11 ; wir... | apache-2.0 |
kyzhai/NUNY | src/hardware/coffee_bb.v | 4,986 | module MODULE1 (
address,
VAR2,
VAR1);
input [11:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
mindrobots/P8X32A_Emulation | P8X32A_DE0_Nano/cog.v | 17,859 | module MODULE1
(
input VAR101,
input VAR92, input VAR104,
input VAR102,
input VAR50, input [27:0] VAR18,
input VAR64,
input VAR12, output VAR42,
output VAR68,
output VAR93,
output [1:0] VAR3,
output [15:0] VAR53,
output [31:0] VAR66,
input [31:0] VAR86,
input VAR14,
input VAR108,
input [31:0] VAR33,
input [7:0] VAR34, ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2b/sky130_fd_sc_lp__nor2b_4.v | 2,173 | module MODULE2 (
VAR6 ,
VAR3 ,
VAR5 ,
VAR2,
VAR7,
VAR9 ,
VAR4
);
output VAR6 ;
input VAR3 ;
input VAR5 ;
input VAR2;
input VAR7;
input VAR9 ;
input VAR4 ;
VAR8 VAR1 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR6 ,
VAR3 ,
VAR5
);
output VAR6... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_pwrgood_pp_p/sky130_fd_sc_ls__udp_pwrgood_pp_p.symbol.v | 1,285 | module MODULE1 (
input VAR2 ,
output VAR1,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or3b/sky130_fd_sc_ms__or3b_4.v | 2,209 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR1 ,
VAR6 ,
VAR2,
VAR4,
VAR9 ,
VAR10
);
output VAR8 ;
input VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR2;
input VAR4;
input VAR9 ;
input VAR10 ;
VAR5 VAR7 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
mlarouche/sd2snes | verilog/sd2sneslite/address.v | 1,733 | module MODULE1(
input VAR2,
input [23:0] VAR9, input VAR8, output [23:0] VAR7, output VAR10, output VAR3, output VAR5, input [23:0] VAR6,
input [23:0] VAR4
);
wire [23:0] VAR1;
assign VAR5 = ((!VAR9[22] & VAR9[15])
|(VAR9[22]));
assign VAR3 = (!VAR9[22]
& &VAR9[21:20]
& &VAR9[14:13]
& !VAR9[15]
);
assign VAR1 = (VAR3
?... | gpl-2.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/lfsr32.v | 3,628 | module MODULE1 (
clk,
rst,
VAR4,
VAR3,
VAR6
);
input clk;
input rst;
input VAR4;
input VAR3;
output [143:0] VAR6;
reg [15:0] VAR5;
wire [7:0] VAR1;
wire [7:0] VAR2;
wire [15:0] counter;
assign VAR1 = ((rst == 1'b1) || (VAR4 == 1'b1)) ? 8'b00000000 :
(VAR3 == 1'b1) ? (VAR5[15:8] + 1'b1) :
VAR5[15:8];
assign VAR2 = ((rst... | lgpl-3.0 |
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