repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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|---|---|---|---|---|
secworks/ChaCha20-Poly1305 | src/rtl/chacha20_poly1305_core.v | 8,348 | module MODULE1(
input wire clk,
input wire VAR37,
input wire VAR7,
input wire VAR6,
input wire VAR15,
input wire VAR24,
input wire [255 : 0] VAR1,
input wire [095 : 0] VAR10,
input wire [511 : 0] VAR20,
output wire ready,
output wire valid,
output wire VAR39,
output wire [511 : 0] VAR8,
output wire [127 : 0] VAR36
);
l... | bsd-2-clause |
davidlee80/miaow | src/verilog/rtl/fetch/regblock.v | 9,493 | module MODULE1(
VAR82,
clk,
rst,
VAR51,
VAR95,
VAR120,
write
);
parameter VAR7 = 11;
input clk, rst;
input [5:0] VAR51;
input [5:0] VAR95;
input [(VAR7-1):0] VAR120;
input write;
output [(VAR7-1):0] VAR82;
wire VAR34;
wire [(VAR7-1):0] VAR27,VAR74;
wire [(VAR7-1):0] VAR107,VAR91;
wire [(VAR7-1):0] VAR58,VAR84;
wire [(V... | bsd-3-clause |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/ddr2_ctrl_module/ddr2_ctrl.v | 2,356 | module MODULE1(
VAR25,
VAR24,
VAR3,
VAR2,
VAR14,
VAR13,
VAR12,
VAR18,
VAR1,
VAR4,
VAR6,
VAR30,
VAR8,
VAR16,
VAR7,
VAR11,
VAR21,
VAR10,
VAR26,
VAR22,
VAR15,
VAR20,
VAR23,
VAR28,
VAR29
);
input VAR25;
input VAR24;
input VAR2;
input [31:0] VAR6;
input VAR30;
input VAR3;
output[25:0] VAR14;
output VAR12;
output VAR13;
outp... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_4.functional.pp.v | 1,190 | module MODULE1( VAR14, VAR2, VAR1, VAR13, VAR11, VAR15 );
input VAR14, VAR2;
inout VAR11, VAR15;
output VAR1, VAR13;
and VAR6( VAR1, VAR14, VAR2 );
wire VAR8;
not VAR10( VAR8, VAR2 );
wire VAR16;
and VAR3( VAR16, VAR8, VAR14 );
wire VAR12;
not VAR5( VAR12, VAR14 );
wire VAR7;
and VAR9( VAR7, VAR12, VAR2 );
or VAR4( VAR... | apache-2.0 |
alexforencich/xfcp | lib/eth/example/VCU108/fpga_10g/rtl/fpga.v | 22,190 | module MODULE1 (
input wire VAR90,
input wire VAR115,
input wire reset,
input wire VAR221,
input wire VAR82,
input wire VAR127,
input wire VAR260,
input wire VAR104,
input wire [3:0] VAR101,
output wire [7:0] VAR253,
inout wire VAR372,
inout wire VAR139,
input wire VAR295,
input wire VAR314,
input wire VAR247,
input wi... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_095.v | 1,468 | module MODULE2 (
VAR6,
VAR11
);
input [31:0] VAR6;
output [31:0]
VAR11;
wire [31:0]
VAR4,
VAR7,
VAR2,
VAR8,
VAR3,
VAR9,
VAR10,
VAR1;
assign VAR4 = VAR6;
assign VAR10 = VAR9 - VAR3;
assign VAR8 = VAR2 << 3;
assign VAR3 = VAR2 + VAR8;
assign VAR7 = VAR4 << 4;
assign VAR2 = VAR4 + VAR7;
assign VAR9 = VAR4 << 8;
assign VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfbbp/sky130_fd_sc_hdll__sdfbbp.functional.pp.v | 2,598 | module MODULE1 (
VAR21 ,
VAR7 ,
VAR24 ,
VAR18 ,
VAR1 ,
VAR15 ,
VAR20 ,
VAR12,
VAR2 ,
VAR25 ,
VAR17 ,
VAR10
);
output VAR21 ;
output VAR7 ;
input VAR24 ;
input VAR18 ;
input VAR1 ;
input VAR15 ;
input VAR20 ;
input VAR12;
input VAR2 ;
input VAR25 ;
input VAR17 ;
input VAR10 ;
wire VAR13 ;
wire VAR16 ;
wire VAR9 ;
wire V... | apache-2.0 |
civol/HDLRuby | lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_rg_23.v | 12,952 | module MODULE1(
module 00003aT0( );
reg rst;
reg VAR3;
reg VAR6;
reg VAR1;
reg [7:0] VAR7;
reg [7:0] VAR5;
wire [7:0] VAR4;
reg [3:0] counter;
reg [7:0] 00003a2;
wire [7:0] 00003a1;
wire [7:0] VAR2;
assign 00003a2 = VAR2;
assign 00003a1 = VAR2;
always @( posedge VAR6 ) begin
if (rst) begin
VAR7 <= 32'd0;
end
else begin... | mit |
mrehkopf/sd2snes | verilog/sd2snes_sa1/sa1.v | 132,965 | module MODULE1(
input VAR312,
input VAR147,
input [23:0] VAR214,
input [23:0] VAR69,
input VAR21,
input VAR402,
input VAR410,
input VAR112,
input VAR367,
input VAR152,
input VAR268,
input [23:0] VAR339,
input [7:0] VAR388,
output VAR114,
output [7:0] VAR3,
input VAR54,
output VAR346,
output VAR423,
output VAR183,
outpu... | gpl-2.0 |
toyoshim/tvcl | sample/UART.v | 3,801 | module MODULE1(
VAR34,
VAR28,
VAR24,
VAR29,
VAR38,
VAR33,
VAR4);
input VAR34;
input VAR28;
input VAR24;
output VAR29;
output [7:0] VAR38;
output VAR33;
output VAR4;
wire [7:0] VAR30;
wire VAR20;
wire VAR13;
wire VAR17;
wire VAR27;
wire VAR25;
reg [7:0] VAR3;
reg VAR7;
reg VAR23;
reg VAR22;
reg [7:0] VAR16;
reg [2:0] VA... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211o/sky130_fd_sc_ls__a211o.behavioral.v | 1,539 | module MODULE1 (
VAR3 ,
VAR11,
VAR2,
VAR5,
VAR9
);
output VAR3 ;
input VAR11;
input VAR2;
input VAR5;
input VAR9;
supply1 VAR13;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR14 ;
wire VAR6 ;
wire VAR10;
and VAR7 (VAR6 , VAR11, VAR2 );
or VAR1 (VAR10, VAR6, VAR9, VAR5);
buf VAR12 (VAR3 , VAR10 );
endmodule | apache-2.0 |
skarpenko/ultiparc | rtl/src/cpu/uparc_imuldivu.v | 7,744 | module MODULE1(
clk,
VAR9,
VAR58,
VAR38,
VAR8,
VAR42,
VAR45,
VAR27,
VAR5,
VAR11,
VAR49,
VAR12,
VAR14,
VAR20
);
input wire clk;
input wire VAR9;
output wire VAR58;
input wire VAR38;
input wire VAR8;
input wire VAR42;
input wire VAR45;
input wire VAR27;
input wire VAR5;
input wire [VAR34-1:0] VAR11;
input wire [VAR51-1:0... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufbuf/sky130_fd_sc_ms__bufbuf.pp.symbol.v | 1,258 | module MODULE1 (
input VAR3 ,
output VAR4 ,
input VAR5 ,
input VAR6,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/tx_multiplexer_128.v | 18,856 | module MODULE1
parameter VAR118 = 128,
parameter VAR8 = 12,
parameter VAR42 = 5, parameter VAR46 = "VAR68"
)
(
input VAR83,
input VAR95,
input [VAR8-1:0] VAR69, input [(VAR8*VAR38)-1:0] VAR89, input [(VAR8*VAR123)-1:0] VAR33, input [(VAR8*VAR118)-1:0] VAR109, output [VAR8-1:0] VAR4, output [VAR8-1:0] VAR79,
input [VAR8... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3b/sky130_fd_sc_ms__nor3b_1.v | 2,254 | module MODULE2 (
VAR5 ,
VAR8 ,
VAR9 ,
VAR2 ,
VAR3,
VAR10,
VAR7 ,
VAR6
);
output VAR5 ;
input VAR8 ;
input VAR9 ;
input VAR2 ;
input VAR3;
input VAR10;
input VAR7 ;
input VAR6 ;
VAR4 VAR1 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2.functional.pp.v | 1,733 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR7,
VAR9
);
output VAR1 ;
input VAR8 ;
input VAR7;
input VAR9;
wire VAR4 ;
wire VAR3;
buf VAR6 (VAR4 , VAR8 );
VAR2 VAR10 (VAR3, VAR4, VAR7, VAR9);
buf VAR5 (VAR1 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.v | 2,325 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR8 ,
VAR9 ,
VAR5 ,
VAR7,
VAR4,
VAR11 ,
VAR3
);
output VAR1 ;
input VAR10 ;
input VAR8 ;
input VAR9 ;
input VAR5 ;
input VAR7;
input VAR4;
input VAR11 ;
input VAR3 ;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR11(VAR11),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_hl_isowell_tap/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4.v | 2,501 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR5,
VAR3 ,
VAR4 ,
VAR6
);
output VAR8 ;
input VAR7 ;
input VAR5;
input VAR3 ;
input VAR4 ;
input VAR6 ;
VAR2 VAR1 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR8,
VAR7
);
output VAR8;
input VAR7;
wire VAR5;
supply1 VAR3 ;... | apache-2.0 |
Jawanga/ece385lab9 | lab9_soc/synthesis/submodules/lab9_soc_sdram_pll.v | 11,244 | module MODULE1
(
VAR1,
VAR3,
VAR6,
VAR9) ;
input VAR1;
input VAR3;
input [0:0] VAR6;
output [0:0] VAR9;
tri0 VAR1;
tri1 VAR3;
reg [0:0] VAR7;
reg [0:0] VAR8;
reg [0:0] VAR4;
wire VAR10;
wire VAR5;
wire VAR2; | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrbp/sky130_fd_sc_ms__dfrbp.behavioral.v | 2,313 | module MODULE1 (
VAR23 ,
VAR4 ,
VAR15 ,
VAR9 ,
VAR10
);
output VAR23 ;
output VAR4 ;
input VAR15 ;
input VAR9 ;
input VAR10;
supply1 VAR6;
supply0 VAR11;
supply1 VAR21 ;
supply0 VAR20 ;
wire VAR7 ;
wire VAR8 ;
reg VAR2 ;
wire VAR5 ;
wire VAR19;
wire VAR18 ;
wire VAR13 ;
wire VAR16 ;
wire VAR17 ;
not VAR22 (VAR8 , VAR19... | apache-2.0 |
takeshineshiro/fpga_linear_128 | DynamicDelay_Start.v | 6,620 | module MODULE1 (
address,
VAR29,
VAR26);
input [0:0] address;
input VAR29;
output [127:0] VAR26;
wire [127:0] VAR11;
wire [127:0] VAR26 = VAR11[127:0];
VAR1 VAR51 (
.VAR20 (VAR29),
.VAR36 (address),
.VAR23 (VAR11),
.VAR12 (1'b0),
.VAR25 (1'b0),
.VAR46 (1'b1),
.VAR24 (1'b0),
.VAR48 (1'b0),
.VAR17 (1'b1),
.VAR6 (1'b1),
.... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbn/sky130_fd_sc_ls__dfbbn.blackbox.v | 1,451 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR7 ,
VAR10 ,
VAR5 ,
VAR2
);
output VAR9 ;
output VAR1 ;
input VAR7 ;
input VAR10 ;
input VAR5 ;
input VAR2;
supply1 VAR3;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/macro_sparecell/sky130_fd_sc_hd__macro_sparecell.pp.symbol.v | 1,422 | module MODULE1 (
output VAR4 ,
input VAR1 ,
input VAR2,
input VAR3,
input VAR5
);
endmodule | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/ethmac/eth_spram_256x32.v | 9,749 | module MODULE1(
clk, rst, VAR9, VAR50, VAR44, addr, VAR51, VAR25
,
VAR45, VAR54, VAR7 VAR37
);
parameter VAR38 = 4;
input clk; input rst; input VAR9; input [VAR38-1:0] VAR50; input VAR44; input [7:0] addr; input [31:0] VAR51; output [31:0] VAR25;
input VAR45; output VAR54; input [VAR6 - 1:0] VAR7; VAR37
VAR12 VAR29
(
.... | mit |
htuNCSU/MmcCommunicationVerilog | DE2_115_SLAVE/source_code/phyInitial.v | 7,883 | module MODULE1 (
input clk,reset,
input VAR30,
input [3:0]VAR25,
input [31:0] VAR1,
input [15:0]VAR51,
inout VAR36,
inout VAR7,
output VAR45,
output reg [3: 0] VAR40,
output reg VAR63,
output reg [12:0]VAR26,
output [15:0]VAR70,
output VAR52,
output VAR42
);
wire VAR8;
wire VAR6, VAR50, VAR66, VAR14;
wire [15:0] VAR38;... | gpl-3.0 |
brysonli12/CS152A-Lab4-TicTacToe | VGA/vga640x480.v | 19,756 | module MODULE1(
input wire VAR20, input wire clk, input wire rst, input wire [8:0] VAR19,
input wire [8:0] VAR12,
input wire [2:0] VAR17,
output wire VAR23, output wire VAR18, output reg [2:0] VAR16, output reg [2:0] VAR3, output reg [1:0] VAR7 );
parameter [9:0] VAR24 = 800;parameter [9:0] VAR21 = 521; parameter [9:0]... | mit |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/vcr_ip_ctrl_mac.v | 23,693 | module MODULE1
(clk, reset, VAR22, VAR108, VAR31, VAR72,
VAR160, VAR124, VAR178, VAR119,
VAR163, VAR105, VAR102, VAR141, VAR60, VAR51,
VAR59, VAR80, VAR170, VAR167, VAR94);
parameter VAR188 = 32;
parameter VAR45 = 2;
parameter VAR32 = 2;
localparam VAR55 = VAR202(VAR32);
localparam VAR110 = VAR45 * VAR32;
parameter VAR... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/gpmc/gpmc.v | 7,085 | module MODULE1
parameter VAR55 = 11,
parameter VAR63 = 10,
parameter VAR58 = 1)
( input VAR15,
input VAR82, inout [15:0] VAR79, input [VAR63:1] VAR49, input [1:0] VAR76,
input VAR1, input VAR18, input VAR91, input VAR94, input VAR41,
output VAR78, output VAR13, output VAR29,
input VAR9, input VAR92,
output [35:0] VAR21... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinv/sky130_fd_sc_lp__clkinv_1.v | 2,036 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR2,
VAR4,
VAR5 ,
VAR7
);
output VAR3 ;
input VAR1 ;
input VAR2;
input VAR4;
input VAR5 ;
input VAR7 ;
VAR6 VAR8 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR3,
VAR1
);
output VAR3;
input VAR1;
supply1 VAR2;
supply0 VAR4;... | apache-2.0 |
esonghori/TinyGarble | circuit_synthesis/a23/a23_barrel_shift.v | 19,346 | module MODULE1 (
input [31:0] VAR10,
input VAR27,
input [7:0] VAR4, input [1:0] VAR12,
output [31:0] VAR3,
output VAR5
);
wire [32:0] VAR28;
wire [32:0] VAR13;
wire [32:0] VAR22;
wire [32:0] VAR19;
wire [32:0] VAR26;
MODULE3 #(.VAR6(5)) VAR14(VAR10, VAR4[4:0], VAR26);
assign VAR28[32] = VAR4 == 5'd0 ? VAR27: VAR26[32];... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/dsp_tx_glue.v | 3,585 | module MODULE1
parameter VAR15 = 0,
parameter VAR7 = 24
)
(
input VAR10, input reset, input VAR12, input enable,
input VAR1, input [7:0] VAR11, input [31:0] VAR16,
output [VAR7-1:0] VAR3,
output [VAR7-1:0] VAR2,
input [VAR7-1:0] VAR5,
input [VAR7-1:0] VAR17,
output [31:0] VAR14,
input VAR13, output VAR8,
input [31:0] V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221ai/sky130_fd_sc_lp__o221ai_lp.v | 2,465 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR9 ,
VAR2 ,
VAR11 ,
VAR6 ,
VAR12,
VAR1,
VAR3 ,
VAR8
);
output VAR5 ;
input VAR4 ;
input VAR9 ;
input VAR2 ;
input VAR11 ;
input VAR6 ;
input VAR12;
input VAR1;
input VAR3 ;
input VAR8 ;
VAR7 VAR10 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR12(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/and2/sky130_fd_sc_hvl__and2.behavioral.v | 1,354 | module MODULE1 (
VAR4,
VAR8,
VAR10
);
output VAR4;
input VAR8;
input VAR10;
supply1 VAR2;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR7 ;
wire VAR9;
and VAR5 (VAR9, VAR8, VAR10 );
buf VAR6 (VAR4 , VAR9 );
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/niosII_system/submodules/niosII_system_timer_0.v | 6,781 | module MODULE1 (
address,
VAR3,
clk,
VAR21,
VAR27,
VAR33,
irq,
VAR2
)
;
output irq;
output [ 15: 0] VAR2;
input [ 2: 0] address;
input VAR3;
input clk;
input VAR21;
input VAR27;
input [ 15: 0] VAR33;
wire VAR13;
wire VAR22;
wire VAR11;
reg [ 3: 0] VAR19;
wire VAR32;
reg VAR10;
wire VAR18;
wire [ 31: 0] VAR20;
reg [ 31:... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_p_pp_pkg_sn/sky130_fd_sc_hs__udp_dlatch_p_pp_pkg_sn.symbol.v | 1,492 | module MODULE1 (
input VAR6 ,
output VAR3 ,
input VAR7 ,
input VAR5 ,
input VAR1 ,
input VAR4,
input VAR2 ,
input VAR8
);
endmodule | apache-2.0 |
natsutan/NPU | fpga_implement/npu8/npu8.cache/ip/492adc01b6634d6a/mul8_8_stub.v | 1,303 | module MODULE1(VAR3, VAR2, VAR4, VAR1)
;
input VAR3;
input [7:0]VAR2;
input [7:0]VAR4;
output [15:0]VAR1;
endmodule | bsd-3-clause |
mgohde/MiniMicroII | RevisionB/registerfile.v | 1,298 | module MODULE1(
clk,
rst,
VAR13,
VAR3,
VAR7,
VAR5,
VAR8,
VAR17,
VAR9,
VAR10,
VAR11,
VAR19,
VAR1,
VAR16,
VAR2,
VAR4,
VAR18,
VAR14,
VAR6,
VAR12
);
input clk;
input rst;
input [2:0] VAR13;
input [2:0] VAR3;
input [2:0] VAR7;
input VAR5;
input [15:0] VAR8;
output [15:0] VAR1;
output [15:0] VAR16;
output [15:0] VAR2;
output... | bsd-2-clause |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_int_mult32s.v | 2,262 | module MODULE1 (
enable,
VAR4,
VAR10,
VAR6,
VAR12);
parameter VAR9 = 32;
parameter VAR7 = 32;
localparam VAR5 = VAR9 < 32 ? VAR9 + 1 : VAR9;
localparam VAR11 = VAR7 < 32 ? VAR7 + 1 : VAR7;
input enable;
input VAR4;
input [VAR5 - 1 : 0] VAR10;
input [VAR11 - 1 : 0] VAR6;
output reg [31:0] VAR12;
reg [VAR5 - 1 : 0] VAR8;... | mit |
xuefei1/ElectronicEngineControl | db/ip/niosII_system/submodules/niosII_system_button_shift_up.v | 3,525 | module MODULE1 (
address,
VAR11,
clk,
VAR3,
VAR14,
VAR8,
VAR1,
irq,
VAR5
)
;
output irq;
output [ 31: 0] VAR5;
input [ 1: 0] address;
input VAR11;
input clk;
input VAR3;
input VAR14;
input VAR8;
input [ 31: 0] VAR1;
wire VAR6;
reg VAR15;
reg VAR13;
wire VAR2;
reg VAR9;
wire VAR4;
wire VAR10;
wire irq;
reg VAR12;
wire V... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_2.behavioral.pp.v | 3,162 | module MODULE1( VAR6, VAR1, VAR8, VAR4, VAR3, VAR9, VAR2 );
input VAR1, VAR4, VAR8;
inout VAR9, VAR2;
output VAR3, VAR6;
VAR5 VAR10(.VAR6(VAR6),.VAR1(VAR1),.VAR8(VAR8),.VAR4(VAR4),.VAR3(VAR3),.VAR9(VAR9),.VAR2(VAR2));
VAR5 VAR7(.VAR6(VAR6),.VAR1(VAR1),.VAR8(VAR8),.VAR4(VAR4),.VAR3(VAR3),.VAR9(VAR9),.VAR2(VAR2)); | apache-2.0 |
aabdelfattah/alhaitham-hardware | v/CCD_Capture.v | 4,092 | module MODULE1( VAR21,
VAR9,
VAR1,
VAR4,
VAR25,
VAR15,
VAR5,
VAR20,
VAR14,
VAR24,
VAR22,
VAR8,
VAR2 );
input [11:0] VAR15;
input VAR5;
input VAR20;
input VAR14;
input VAR24;
input VAR22;
input VAR8;
output VAR2 ;
output [11:0] VAR21;
output [15:0] VAR1;
output [15:0] VAR4;
output [31:0] VAR25;
output VAR9;
reg VAR10;
r... | gpl-3.0 |
petrmikheev/miksys | verilog/COMMAND_PAGE_bb.v | 7,508 | module MODULE1 (
VAR6,
VAR4,
VAR1,
VAR2,
VAR5,
VAR3);
input VAR6;
input [15:0] VAR4;
input [7:0] VAR1;
input [8:0] VAR2;
input VAR5;
output [31:0] VAR3;
tri1 VAR6;
tri0 VAR5;
endmodule | gpl-3.0 |
kyflores/ice-mc | rtl/spi_multi_transfer.v | 2,353 | module MODULE1(
clk,
rst,
VAR4, VAR11,
VAR12,
VAR14, VAR15, VAR10,
VAR5,
VAR16
);
parameter VAR18 = 2;
input clk, rst, VAR4, VAR11, VAR12;
input[7:0] VAR15;
output[7:0] VAR14;
output reg VAR10, VAR5, VAR16;
reg[7:0] VAR6[VAR18-1:0];
reg[7:0] VAR7[VAR18-1:0];
localparam VAR1 = 3'd0, VAR8 = 3'd1, VAR9 = 3'd2,
VAR3 = 3'd3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31o/sky130_fd_sc_hdll__a31o.functional.pp.v | 2,046 | module MODULE1 (
VAR2 ,
VAR10 ,
VAR4 ,
VAR17 ,
VAR15 ,
VAR12,
VAR5,
VAR11 ,
VAR3
);
output VAR2 ;
input VAR10 ;
input VAR4 ;
input VAR17 ;
input VAR15 ;
input VAR12;
input VAR5;
input VAR11 ;
input VAR3 ;
wire VAR8 ;
wire VAR14 ;
wire VAR9;
and VAR7 (VAR8 , VAR17, VAR10, VAR4 );
or VAR13 (VAR14 , VAR8, VAR15 );
VAR16 V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111o/sky130_fd_sc_lp__a2111o.pp.symbol.v | 1,400 | module MODULE1 (
input VAR8 ,
input VAR1 ,
input VAR9 ,
input VAR6 ,
input VAR4 ,
output VAR5 ,
input VAR3 ,
input VAR2,
input VAR7,
input VAR10
);
endmodule | apache-2.0 |
esonghori/TinyGarble | circuit_synthesis/aes/aes_11cc.v | 1,683 | module MODULE1
(
clk,
rst,
VAR2,
VAR27,
VAR10
);
localparam VAR18 = 10;
localparam VAR1 = 10;
input clk;
input rst;
input [127:0] VAR2; input [127:0] VAR27; output [127:0] VAR10;
reg [127:0] VAR14;
reg [127:0] VAR25;
reg [3:0] counter;
wire [127:0] VAR3;
wire [127:0] VAR16;
wire [127:0] VAR24;
wire [127:0] VAR9;
wire [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111a/sky130_fd_sc_ms__o2111a_1.v | 2,448 | module MODULE2 (
VAR10 ,
VAR11 ,
VAR2 ,
VAR1 ,
VAR6 ,
VAR7 ,
VAR5,
VAR12,
VAR3 ,
VAR9
);
output VAR10 ;
input VAR11 ;
input VAR2 ;
input VAR1 ;
input VAR6 ;
input VAR7 ;
input VAR5;
input VAR12;
input VAR3 ;
input VAR9 ;
VAR8 VAR4 (
.VAR10(VAR10),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvpwrvgnd/sky130_fd_sc_lp__tapvpwrvgnd_1.v | 1,928 | module MODULE2 (
VAR5,
VAR1,
VAR3 ,
VAR6
);
input VAR5;
input VAR1;
input VAR3 ;
input VAR6 ;
VAR4 VAR2 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE2 ();
supply1 VAR5;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR6 ;
VAR4 VAR2 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22o/sky130_fd_sc_hd__a22o.blackbox.v | 1,356 | module MODULE1 (
VAR2 ,
VAR3,
VAR9,
VAR6,
VAR7
);
output VAR2 ;
input VAR3;
input VAR9;
input VAR6;
input VAR7;
supply1 VAR8;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/ss_rcvr.v | 2,672 | module MODULE1
(input VAR15,
input VAR2,
input rst,
input [VAR5-1:0] VAR14,
output [VAR5-1:0] VAR12,
output reg VAR6);
wire [3:0] VAR9, VAR7;
reg [VAR5-1:0] buffer [0:15];
always @(posedge VAR15)
buffer[VAR7] <= VAR14;
assign VAR12 = buffer[VAR9];
reg [3:0] VAR11;
always @(posedge VAR15 or posedge rst)
if (rst)
VAR11 <... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31a/sky130_fd_sc_ms__o31a.pp.symbol.v | 1,351 | module MODULE1 (
input VAR2 ,
input VAR6 ,
input VAR9 ,
input VAR7 ,
output VAR4 ,
input VAR3 ,
input VAR8,
input VAR1,
input VAR5
);
endmodule | apache-2.0 |
miamiasheep/nctu-dlab-99 | hw/t_binary_multiplier.v | 1,462 | module MODULE1;
wire VAR8;
wire [15:0] VAR7;
reg [7:0] VAR9, VAR11;
integer VAR6, VAR4;
reg VAR2, VAR5, reset, VAR3;
VAR10 VAR1(VAR5, reset, VAR2, VAR9, VAR11, VAR7, VAR8);
always VAR5 = ~VAR5;
begin
end else | gpl-3.0 |
eda-globetrotter/PicenoDecoders | final/src/tosynth Folder/alu_add.v | 31,407 | module MODULE1 (VAR9,VAR32,VAR12,VAR3,VAR18);
output [0:127] VAR18;
input [0:127] VAR9;
input [0:127] VAR32;
input [0:1] VAR12;
input [0:4] VAR3;
parameter VAR8 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR18;
reg [0:127] VAR4;
reg [0:15] VAR10;
reg [0:15] VAR2;
reg [0:15] VAR22;
reg [0:15] VAR27;
reg [0:15]... | mit |
gigglesninja/digital-system-design | lab9_uart_rx/uart_rx.v | 5,291 | module MODULE1(clk, reset, VAR10, VAR41, din, dout, VAR17, addr);
input clk, reset, VAR10, VAR41;
input [7:0] din;
output [2:0] dout;
input VAR17; input [2:0] addr;
reg [8:0] dout, VAR32;
reg [9:0] VAR45;
reg [7:0] VAR48;
reg VAR46, VAR19, VAR16, VAR44, VAR18;
reg VAR28, VAR33, VAR23, VAR22, VAR29, VAR31;
reg [3:0] VAR... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_1.behavioral.pp.v | 1,868 | module MODULE1( VAR4, VAR6, VAR9, VAR7, VAR8, VAR3, VAR2 );
input VAR9, VAR4, VAR7, VAR8;
inout VAR3, VAR2;
output VAR6;
VAR1 VAR10(.VAR4(VAR4),.VAR6(VAR6),.VAR9(VAR9),.VAR7(VAR7),.VAR8(VAR8),.VAR3(VAR3),.VAR2(VAR2));
VAR1 VAR5(.VAR4(VAR4),.VAR6(VAR6),.VAR9(VAR9),.VAR7(VAR7),.VAR8(VAR8),.VAR3(VAR3),.VAR2(VAR2)); | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/buf_ram_1p_64x192.v | 3,157 | module MODULE1 (
clk ,
VAR12 ,
VAR1 ,
addr ,
VAR9 ,
VAR11
);
input clk ;
input VAR12 ;
input VAR1 ;
input [7:0] addr ;
input [VAR19*8-1:0] VAR9 ;
output [VAR19*8-1:0] VAR11 ;
VAR8 #(.VAR17(8), .VAR4(VAR19*8))
VAR13 (
.clk ( clk ),
.VAR7 ( ~VAR12 ),
.VAR14 ( 1'b0 ),
.VAR15 ( ~VAR1 ),
.VAR5 ( addr ),
.VAR9 ( VAR9 ),
.VAR... | gpl-3.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/project_1.xpr/project_1/project_1.srcs/sources_1/imports/Proyecto_De_Graduacion/FPU_FLM/RTL/Add-Subt/Rotate_Mux_Array.v | 1,055 | module MODULE1
(
input wire [VAR6-1:0] VAR4,
input wire VAR9,
output wire [VAR6-1:0] VAR11
);
genvar VAR5;generate for (VAR5=0; VAR5 <= VAR6-1; VAR5=VAR5+1) begin
case (VAR5)
VAR6-1-VAR5:begin
assign VAR11[VAR5]=VAR4[VAR6-1-VAR5];
end
default:begin
VAR8 #(.VAR12(1)) VAR2(
.VAR10(VAR9),
.VAR3 (VAR4[VAR5]),
.VAR1 (VAR4[V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbn/sky130_fd_sc_hs__dfbbn_2.v | 2,462 | module MODULE2 (
VAR5 ,
VAR4 ,
VAR6 ,
VAR2 ,
VAR10 ,
VAR9,
VAR3 ,
VAR8
);
output VAR5 ;
output VAR4 ;
input VAR6 ;
input VAR2 ;
input VAR10 ;
input VAR9;
input VAR3 ;
input VAR8 ;
VAR1 VAR7 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MOD... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_2.behavioral.pp.v | 8,945 | module MODULE1( VAR55, VAR77, VAR48, VAR24, VAR85, VAR36, VAR32 );
input VAR55, VAR77, VAR24, VAR48;
inout VAR36, VAR32;
output VAR85;
reg VAR54;
VAR81 VAR82(.VAR55(VAR55),.VAR77(VAR77),.VAR48(VAR48),.VAR24(VAR24),.VAR85(VAR85),.VAR36(VAR36),.VAR32(VAR32),.VAR54(VAR54));
VAR81 VAR78(.VAR55(VAR55),.VAR77(VAR77),.VAR48(V... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/ppu.v | 25,494 | module MODULE1(
input clk,
input VAR12,
input reset,
output [239:0] VAR139,
output [239:0] VAR78,
input [63:0] VAR106,
input [23:0] VAR6,
input VAR132,
input VAR274,
output VAR63,
input VAR242,
input [63:0] VAR95,
input [23:0] VAR93,
input VAR221,
input VAR59,
output VAR163,
input VAR60,
input [63:0] VAR26,
input [23:0... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/acl_fp_sinpi_s5.v | 1,187 | module MODULE1 (
enable,
VAR6,
VAR5,
VAR3);
input enable;
input VAR6;
input [31:0] VAR5;
output [31:0] VAR3;
wire [31:0] VAR2;
wire [31:0] VAR3 = VAR2[31:0];
VAR8 VAR1(
.en (enable),
.clk (VAR6),
.VAR7 (VAR5),
.VAR9 (VAR2),
.VAR4(1'b0));
endmodule | mit |
hoang26/processor_verilog | 4_ALU.v | 1,369 | module MODULE1(clk, VAR5, VAR2, VAR3, VAR4, VAR1);
input clk;
input [3:0] VAR5;
input signed [31:0] VAR2, VAR3;
output reg signed [31:0] VAR4;
output reg VAR1;
always@(posedge clk)
begin
if (VAR5 == 4'b0010) begin
VAR4 = VAR2 + VAR3;
VAR1 = 0;
end
else if (VAR5 == 4'b0110)
begin
VAR4 = VAR2 - VAR3;
if (VAR4 == 0)
VAR1 ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2/sky130_fd_sc_ls__or2.pp.blackbox.v | 1,254 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR4 ,
VAR1,
VAR7,
VAR2 ,
VAR6
);
output VAR3 ;
input VAR5 ;
input VAR4 ;
input VAR1;
input VAR7;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvp/sky130_fd_sc_ms__einvp.behavioral.v | 1,302 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR4
);
output VAR8 ;
input VAR7 ;
input VAR4;
supply1 VAR5;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR6 ;
notif1 VAR2 (VAR8 , VAR7, VAR4 );
endmodule | apache-2.0 |
sarchar/uart_de0_nano | uart_fifo_dual_port_ram.v | 9,588 | module MODULE1 (
VAR59,
VAR35,
VAR45,
VAR13,
VAR47,
VAR43);
input VAR59;
input [7:0] VAR35;
input [9:0] VAR45;
input [9:0] VAR13;
input VAR47;
output [7:0] VAR43;
tri1 VAR59;
tri0 VAR47;
wire [7:0] VAR5;
wire [7:0] VAR43 = VAR5[7:0];
VAR29 VAR11 (
.VAR42 (VAR13),
.VAR34 (VAR45),
.VAR61 (VAR59),
.VAR37 (VAR35),
.VAR14 (... | mit |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/cpu/ex_reg.v | 6,584 | module MODULE1 (
input wire clk, input wire reset, input wire [VAR12] VAR19, input wire VAR24, input wire VAR35, input wire VAR28, input wire VAR21, input wire [VAR7] VAR10, input wire VAR3, input wire VAR43, input wire [VAR6] VAR34, input wire [VAR12] VAR40, input wire [VAR36] VAR16, input wire [VAR5] VAR32, input wir... | apache-2.0 |
tloinuy/opencpi-opencv | opencpi/hdl/prims/bsv/SyncHandshake.v | 4,729 | module MODULE1(
VAR16,
VAR19,
VAR15,
VAR3,
VAR5,
VAR10
);
parameter VAR6 = 1'b0;
input VAR16 ;
input VAR19 ;
input VAR3 ;
output VAR5 ;
input VAR15 ;
output VAR10 ;
reg VAR1 ;
reg VAR9, VAR17 ;
reg VAR13 ;
reg VAR11 ;
reg VAR7, VAR2 ;
reg VAR18 ;
reg VAR8 ;
wire VAR12 ;
assign VAR10 = VAR12 ;
assign VAR12 = VAR17 != VA... | gpl-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/bank_common.v | 17,378 | module MODULE1 #
(
parameter VAR97 = 100,
parameter VAR6 = 2,
parameter VAR63 = 1,
parameter VAR65 = 4,
parameter VAR80 = 2,
parameter VAR25 = 0,
parameter VAR38 = 44,
parameter VAR53 = 2,
parameter VAR51 = 4,
parameter VAR114 = 5, parameter VAR19 = 64
)
(
VAR17, VAR26, VAR44, VAR43,
VAR72, VAR103, VAR92, VAR84, VAR87,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2/sky130_fd_sc_lp__or2.behavioral.v | 1,340 | module MODULE1 (
VAR1,
VAR3,
VAR6
);
output VAR1;
input VAR3;
input VAR6;
supply1 VAR8;
supply0 VAR4;
supply1 VAR9 ;
supply0 VAR7 ;
wire VAR2;
or VAR10 (VAR2, VAR6, VAR3 );
buf VAR5 (VAR1 , VAR2 );
endmodule | apache-2.0 |
argonnexraydetector/RoachFirmPy | ANLYellowBlocks/mkid_dacadc_4x/ise/mkiddac/ipcore_dir/dacclk_mmcm/example_design/dacclk_mmcm_exdes.v | 6,112 | module MODULE1
parameter VAR15 = 100
)
( input VAR30,
input VAR40,
output [5:1] VAR16,
output [5:1] VAR26,
output VAR4
);
localparam VAR11 = 16;
localparam VAR18 = 5;
genvar VAR5;
wire VAR27 = !VAR4 || VAR40;
reg [VAR18:1] VAR7;
reg [VAR18:1] VAR22;
reg [VAR18:1] VAR35;
reg [VAR18:1] VAR3;
wire [VAR18:1] VAR43;
wire [V... | gpl-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_xcv_ram32x8d.v | 10,820 | module MODULE2
(
VAR7,
VAR28,
VAR42,
VAR38,
VAR26,
VAR33,
VAR43
);
output [7:0] VAR7;
output [7:0] VAR28;
input [4:0] VAR42;
input [4:0] VAR26;
input [7:0] VAR38;
input VAR33;
input VAR43;
wire [7:0] VAR3;
wire [7:0] VAR30;
wire [7:0] VAR5;
wire [7:0] VAR46;
wire VAR8 ;
wire VAR12 ;
assign VAR7 = VAR26[4] ? VAR5 : VAR3... | gpl-3.0 |
plindstroem/oh | elink/hdl/ecfg_elink.v | 4,706 | module MODULE1 (
VAR18, VAR8, VAR5, VAR29,
VAR32, VAR22, clk, reset
);
parameter VAR9 = 6; parameter VAR31 = 104; parameter VAR19 = 12'h000;
parameter VAR10 = 12'h808;
input VAR32;
input [VAR31-1:0] VAR22;
output VAR18;
input clk;
input reset;
output VAR8; output [15:0] VAR5; output [11:0] VAR29;
reg VAR21;
reg [15:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2/sky130_fd_sc_hdll__nand2_8.v | 2,113 | module MODULE2 (
VAR6 ,
VAR8 ,
VAR2 ,
VAR1,
VAR9,
VAR4 ,
VAR3
);
output VAR6 ;
input VAR8 ;
input VAR2 ;
input VAR1;
input VAR9;
input VAR4 ;
input VAR3 ;
VAR7 VAR5 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR6,
VAR8,
VAR2
);
output VAR6;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a21o/sky130_fd_sc_hvl__a21o.symbol.v | 1,345 | module MODULE1 (
input VAR1,
input VAR3,
input VAR6,
output VAR8
);
supply1 VAR4;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_1.functional.v | 1,046 | module MODULE1( VAR8, VAR7, VAR1 );
input VAR1, VAR8;
output VAR7;
wire VAR2;
not VAR5( VAR2, VAR1 );
wire VAR3;
not VAR6( VAR3, VAR8 );
or VAR4( VAR7, VAR2, VAR3 );
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_floor.v | 7,816 | module MODULE1(VAR12, VAR3, enable, VAR14, VAR9);
input VAR12, VAR3, enable;
input [31:0] VAR14;
output [31:0] VAR9;
reg VAR11;
reg [7:0] VAR4;
reg [22:0] VAR2;
always@(posedge VAR12 or negedge VAR3)
begin
if (~VAR3)
begin
VAR11 <= 1'b0;
VAR4 <= 8'd0;
VAR2 <= 23'd0;
end
else if (enable)
begin
VAR11 <= VAR14[31];
VAR4 <... | mit |
amrmorsey/Digital-Design-Project | Key_Processor.v | 3,505 | module MODULE1(
select,
VAR3,
VAR1,
VAR2
);
input select;
output [28:1] VAR3;
output [28:1] VAR1;
wire select;
reg [56:1] VAR5;
input [64:1] VAR2;
assign VAR1= VAR5[28:1];
assign VAR3 = VAR5[56:29];
always@(select or VAR2)
begin
if(select == 1)
begin
VAR5[1] <= VAR2[57];
VAR5[2] <= VAR2[49];
VAR5[3] <= VAR2[41];
VAR5[4... | gpl-2.0 |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_vinterp.v | 3,338 | module MODULE1(
input VAR7,
input VAR33,
output VAR5,
input VAR25,
output VAR10,
input signed [17:0] VAR50,
input signed [17:0] VAR20,
input signed [17:0] VAR4,
input signed [17:0] VAR26,
input VAR37,
input [16:0] VAR2,
input [16:0] VAR18,
input VAR3,
input [16:0] VAR42,
input [16:0] VAR6,
input VAR14,
input [16:0] VAR... | lgpl-3.0 |
trander1/Queues-and-Adders | Verilog Files/fifo_top.v | 4,619 | (VAR21<=4)?2:\
(VAR21<=8)?3:\
(VAR21<=16)?4:\
(VAR21<=32)?5:\
(VAR21<=64)?6:\
(VAR21<=128)?7:\
(VAR21<=256)?8:\
-1
module MODULE1(
VAR5, VAR15, VAR7,
VAR1, reset,
clk
);
parameter VAR17 = 4;
parameter VAR22 = 8;
parameter VAR11 = 2;
parameter VAR14 = VAR17+VAR11; parameter VAR23 = 'b0;
parameter VAR9 = VAR6(VAR22);
out... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_imul_iterative.v | 9,154 | module MODULE1 #( VAR18 = 32)
(input VAR22
,input VAR32
,input VAR13 ,output VAR36
,input [VAR18-1: 0] VAR7
,input VAR10
,input [VAR18-1: 0] VAR33
,input VAR34
,input VAR39
,output VAR21 ,output [VAR18-1: 0] VAR23
,input VAR40
);
localparam VAR2 = VAR9( VAR18 + 1);
logic[VAR2-1:0] VAR15;
logic VAR28;
wire VAR25 = VAR28... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbn/sky130_fd_sc_hs__dlxbn.functional.pp.v | 1,874 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR7 ,
VAR3 ,
VAR6 ,
VAR14
);
input VAR1 ;
input VAR10 ;
output VAR7 ;
output VAR3 ;
input VAR6 ;
input VAR14;
wire VAR13 ;
wire VAR4 ;
wire VAR12;
wire VAR16 ;
not VAR9 (VAR13 , VAR14 );
VAR2 VAR8 VAR5 (VAR4 , VAR6, VAR13, VAR1, VAR10);
buf VAR11 (VAR7 , VAR4 );
not VAR15 (VAR3 , VAR4 )... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4/sky130_fd_sc_hdll__nor4_2.v | 2,291 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR8 ,
VAR11 ,
VAR1 ,
VAR10,
VAR7,
VAR2 ,
VAR5
);
output VAR9 ;
input VAR3 ;
input VAR8 ;
input VAR11 ;
input VAR1 ;
input VAR10;
input VAR7;
input VAR2 ;
input VAR5 ;
VAR6 VAR4 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR2(VAR2),
.... | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3/ddr3_int_phy_alt_mem_phy_seq_wrapper.v | 19,961 | module MODULE1 (
VAR153,
VAR128,
VAR97,
VAR52,
VAR137,
VAR62,
VAR78,
VAR158,
VAR50,
VAR183,
VAR95,
VAR5,
VAR39,
VAR143,
VAR88,
VAR113,
VAR73,
VAR58,
VAR12,
VAR84,
VAR71,
VAR35,
VAR133,
VAR139,
VAR48,
VAR26,
VAR160,
VAR131,
VAR145,
VAR110,
VAR152,
VAR38,
VAR41,
VAR55,
VAR85,
VAR154,
VAR74,
VAR96,
VAR76,
VAR103,
VAR118,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_sio/sky130_fd_io__top_sio.symbol.v | 2,342 | module MODULE1 (
input VAR27 ,
output VAR23 ,
input VAR3 ,
output VAR15 ,
input VAR21 ,
inout VAR16 ,
inout VAR9,
inout VAR12,
inout VAR8,
input [2:0] VAR18 ,
input VAR7 ,
input VAR13 ,
input VAR24 ,
input VAR6 ,
input VAR19 ,
input VAR2 ,
input VAR11 ,
input VAR26 ,
input VAR20 ,
input VAR4 ,
output VAR25
);
supply0 V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4bb/sky130_fd_sc_hs__nor4bb.behavioral.pp.v | 1,900 | module MODULE1 (
VAR10,
VAR7,
VAR4 ,
VAR3 ,
VAR15 ,
VAR9 ,
VAR2
);
input VAR10;
input VAR7;
output VAR4 ;
input VAR3 ;
input VAR15 ;
input VAR9 ;
input VAR2 ;
wire VAR2 VAR11 ;
wire VAR5 ;
wire VAR1;
nor VAR6 (VAR11 , VAR3, VAR15 );
and VAR13 (VAR5 , VAR11, VAR9, VAR2 );
VAR12 VAR8 (VAR1, VAR5, VAR10, VAR7);
buf VAR14 ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_4.behavioral.pp.v | 1,686 | module MODULE1( VAR8, VAR3, VAR7, VAR2, VAR5, VAR6 );
input VAR2, VAR3, VAR7;
inout VAR5, VAR6;
output VAR8;
VAR9 VAR1(.VAR8(VAR8),.VAR3(VAR3),.VAR7(VAR7),.VAR2(VAR2),.VAR5(VAR5),.VAR6(VAR6));
VAR9 VAR4(.VAR8(VAR8),.VAR3(VAR3),.VAR7(VAR7),.VAR2(VAR2),.VAR5(VAR5),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fa/sky130_fd_sc_lp__fa.functional.pp.v | 3,007 | module MODULE1 (
VAR10,
VAR30 ,
VAR25 ,
VAR12 ,
VAR9 ,
VAR13,
VAR31,
VAR21 ,
VAR28
);
output VAR10;
output VAR30 ;
input VAR25 ;
input VAR12 ;
input VAR9 ;
input VAR13;
input VAR31;
input VAR21 ;
input VAR28 ;
wire VAR1 ;
wire VAR3 ;
wire VAR22 ;
wire VAR17 ;
wire VAR23 ;
wire VAR24 ;
wire VAR15 ;
wire VAR16;
wire VAR3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinv/sky130_fd_sc_hdll__clkinv_2.v | 2,052 | module MODULE2 (
VAR7 ,
VAR1 ,
VAR5,
VAR6,
VAR4 ,
VAR8
);
output VAR7 ;
input VAR1 ;
input VAR5;
input VAR6;
input VAR4 ;
input VAR8 ;
VAR3 VAR2 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR7,
VAR1
);
output VAR7;
input VAR1;
supply1 VAR5;
supply0 VAR6;... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_1/synth/design_1_auto_ds_1.v | 16,099 | module MODULE1 (
VAR60,
VAR83,
VAR5,
VAR40,
VAR50,
VAR73,
VAR26,
VAR81,
VAR8,
VAR47,
VAR21,
VAR10,
VAR17,
VAR66,
VAR96,
VAR97,
VAR16,
VAR58,
VAR84,
VAR82,
VAR6,
VAR37,
VAR72,
VAR78,
VAR38,
VAR7,
VAR2,
VAR87,
VAR54,
VAR79,
VAR45,
VAR11,
VAR49,
VAR80,
VAR51,
VAR62,
VAR42,
VAR92,
VAR9,
VAR14,
VAR64,
VAR35,
VAR63,
VAR94,
V... | mit |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/alt_vipitc131_common_generic_count.v | 1,814 | module MODULE1
parameter VAR5 = 1280,
parameter VAR15 = 0,
parameter VAR11 = 1,
parameter VAR4 = 1
)
(
input wire clk,
input wire VAR1,
input wire enable,
input wire VAR14,
input wire [VAR6-1:0] VAR10, output reg [VAR6-1:0] VAR9,
input wire VAR7,
input wire [VAR6-1:0] VAR2,
output wire VAR13,
output wire VAR3,
output w... | gpl-3.0 |
oblivioncth/DE0-Verilog-Processor | src/Instruction_Mem.v | 19,873 | module MODULE1(VAR2, VAR1);
output reg [15:0] VAR2;
input [15:0] VAR1;
always @(VAR1)
begin
case (VAR1)
8'h0: VAR2 = 16'hc000; 8'h1: VAR2 = 16'ha802; 8'h2: VAR2 = 16'hc66b; 8'h3: VAR2 = 16'hec00; 8'h4: VAR2 = 16'hd119; 8'h5: VAR2 = 16'h6895; 8'h6: VAR2 = 16'h6805; 8'h7: VAR2 = 16'h696d; 8'h8: VAR2 = 16'h68aa; 8'h9: VAR... | mit |
SergKolo/msudenver_eet_4020_verilog | LAB_2/two_by_one_mux.v | 1,327 | module MODULE2(VAR6,VAR15,VAR10,sel);
output VAR6;
input VAR15,VAR10,sel;
wire VAR14,VAR9,VAR8;
not VAR12(VAR14,sel);
and VAR7(VAR9,VAR14,VAR15);
and VAR11(VAR8,sel,VAR10);
or VAR2(VAR6,VAR9,VAR8);
endmodule
module MODULE1;
reg VAR5,VAR13,VAR1;
wire VAR4;
MODULE2 MODULE1(VAR4,VAR5,VAR1,VAR13);
begin | mit |
sergev/vak-opensource | hardware/s3esk-openrisc/dbg_interface/dbg_crc8_d1.v | 6,136 | module MODULE1 (VAR4, VAR9, VAR11, VAR3, VAR10, VAR5);
parameter VAR6 = 1;
input VAR4;
input VAR9;
input VAR11;
input VAR3;
input VAR5;
output [7:0] VAR10;
reg [7:0] VAR10;
function [7:0] VAR7;
input VAR4;
input [7:0] VAR8;
reg [0:0] VAR1;
reg [7:0] VAR2;
reg [7:0] VAR12;
begin
VAR1[0] = VAR4;
VAR2 = VAR8;
VAR12[0] = V... | apache-2.0 |
drom/robot | src/robo.v | 3,233 | module MODULE1 (
clk,
VAR1, VAR6, VAR9, VAR12, VAR15, VAR10, VAR3, VAR13,
VAR7, VAR2, VAR14, VAR4
);
input clk ;
output reg VAR1 ;
output reg VAR6 ;
output reg VAR9 ;
output reg VAR12 ;
output reg VAR15 ;
output reg VAR10 ;
output reg VAR3 ;
output reg VAR13 ;
output reg VAR7 ; output reg VAR2 ; output reg VAR14 ; outp... | mit |
MarcoVogt/basil | firmware/modules/cmd_seq/cmd_seq_core.v | 10,743 | module MODULE1
parameter VAR70 = 16,
parameter VAR55 = 1,
parameter VAR5 = 2048
) (
input wire VAR77,
input wire VAR14,
input wire [VAR70-1:0] VAR3,
input wire [7:0] VAR91,
input wire VAR52,
input wire VAR9,
output reg [7:0] VAR15,
output wire [VAR55-1:0] VAR63,
input wire VAR27,
input wire VAR36,
output wire VAR20,
ou... | bsd-3-clause |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/hostSlaveMux/hostSlaveMux.v | 6,962 | module MODULE1 (
VAR22,
VAR18,
VAR3,
VAR19,
VAR2,
VAR17,
VAR20,
VAR26,
VAR9,
VAR16,
VAR21,
VAR24,
VAR15,
VAR27,
VAR28,
VAR4,
VAR25,
VAR1,
VAR10,
VAR30,
address,
VAR31,
VAR23,
VAR29,
VAR13,
VAR6,
VAR11,
VAR14,
VAR12
);
output [7:0] VAR22;
input [7:0] VAR18;
input [7:0] VAR3;
output [7:0] VAR19;
input [7:0] VAR2;
input [... | gpl-3.0 |
eda-globetrotter/PicenoDecoders | andy/design/spd.v | 5,477 | module MODULE1 (VAR42, VAR72, VAR15, VAR86, VAR28, VAR64, VAR19, VAR88, out, clk, reset);
output out;
input VAR42, VAR72, VAR15, VAR86;
input [3:0] VAR28, VAR64, VAR19, VAR88;
input clk, reset;
wire out;
wire VAR43, VAR25;
wire VAR49, VAR23, VAR51, VAR89;
wire VAR45, VAR6, VAR1, VAR11;
wire VAR59, VAR40, VAR30, VAR61;
... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_idle_inserter.v | 2,761 | module MODULE1 (
input clk,
input VAR3,
output reg VAR10,
input VAR1,
input [7: 0] VAR6,
input VAR4,
output reg VAR9,
output reg [7: 0] VAR8
);
reg VAR2;
wire VAR7, VAR5;
assign VAR5 = (VAR6 == 8'h4a);
assign VAR7 = (VAR6 == 8'h4d);
always @(posedge clk or negedge VAR3) begin
if (!VAR3) begin
VAR2 <= 0;
end else begin
... | mit |
jhol/butterflylogic | rtl/delay_fifo.v | 1,659 | module MODULE1 #(
parameter VAR4 = 3, parameter VAR6 = 32
)(
input wire clk,
input wire rst,
input wire VAR5,
input wire [VAR6-1:0] VAR3,
output wire VAR7,
output wire [VAR6-1:0] VAR1
);
reg [VAR4*(VAR6+1)-1:0] VAR2;
always @(posedge clk)
VAR2 <= {VAR2, {VAR5, VAR3}};
assign {VAR7, VAR1} = VAR2[(VAR4-1)*(VAR6+1)+:(VAR6... | gpl-2.0 |
lvd2/zxevo | fpga/sdload/trunk/z80/zdos.v | 1,375 | module MODULE1(
input wire VAR1,
input wire VAR6,
input wire VAR4,
input wire VAR3,
input wire VAR2,
output reg VAR5
);
always @(posedge VAR1, negedge VAR6)
if( !VAR6 )
begin
VAR5 = 1'b1;
end
else begin
if( !VAR2 )
VAR5 <= 1'b1;
end
else if( VAR3 )
VAR5 <= 1'b0;
else if( VAR4 )
VAR5 <= 1'b1;
end
endmodule | gpl-3.0 |
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