repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
monotone-RK/FACE | MCSoC-15/8-way_4-parallel/src/main.v | 9,145 | module MODULE1(input wire VAR9,
input wire VAR43,
input wire VAR82,
output wire [7:0] VAR7,
output wire VAR78,
inout wire [VAR88] VAR18,
inout wire [7:0] VAR67,
inout wire [7:0] VAR50,
output wire [VAR69] VAR69,
output wire [2:0] VAR8,
output wire VAR13,
output wire VAR20,
output wire VAR53,
output wire VAR70,
output w... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrtn/sky130_fd_sc_hd__sdfrtn.blackbox.v | 1,440 | module MODULE1 (
VAR10 ,
VAR9 ,
VAR6 ,
VAR7 ,
VAR8 ,
VAR1
);
output VAR10 ;
input VAR9 ;
input VAR6 ;
input VAR7 ;
input VAR8 ;
input VAR1;
supply1 VAR4;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | network_interface/arbiter_4_deq.v | 21,043 | module MODULE1 (
clk,
rst,
VAR1,
VAR63,
VAR39,
VAR34,
VAR23,
VAR32,
VAR4,
VAR61,
VAR6,
VAR7,
VAR56,
VAR14,
VAR16,
VAR19,
VAR5,
select
);
input clk;
input rst;
input VAR1; input VAR63; input VAR39; input VAR34; input VAR32; input VAR4; input VAR61; input VAR6; input [3:0] VAR7; input [3:0] VAR56;
input VAR14; input VAR1... | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/01BLUETOOTH/Version_01/02 verilog/Transmisión/Transmision.v | 1,728 | module MODULE1 (input VAR7, input clk,
input reset, input wire [7:0] din,
output VAR1,
output reg VAR3,
output VAR4,
output reg VAR2
);
wire VAR6;
VAR8 VAR5(.clk(clk), .VAR6(VAR6), .reset(reset));
parameter VAR9 = 8;
assign VAR4 = VAR6; | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/phy/phy_rdlvl.v | 71,947 | module MODULE1 #
(
parameter VAR228 = 100, parameter VAR192 = 2, parameter VAR199 = 3333, parameter VAR22 = 64, parameter VAR42 = 3, parameter VAR131 = 8, parameter VAR27 = 8, parameter VAR68 = 1, parameter VAR165 = "VAR184", parameter VAR45 = "VAR156", parameter VAR41 = "VAR189" )
(
input clk,
input rst,
input VAR96,
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2b/sky130_fd_sc_lp__nand2b.symbol.v | 1,297 | module MODULE1 (
input VAR5,
input VAR1 ,
output VAR7
);
supply1 VAR4;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
jotego/jt51 | hdl/jt51_csr_ch.v | 2,056 | module MODULE1(
input rst,
input clk,
input VAR22,
input [ 7:0] din,
input VAR16,
input VAR3,
input VAR17,
input VAR11,
input VAR9,
input VAR23,
input VAR25,
output [1:0] VAR14,
output [2:0] VAR2,
output [2:0] VAR27,
output [6:0] VAR6,
output [5:0] VAR28,
output [1:0] VAR19,
output [2:0] VAR7
);
wire [1:0] VAR13 = din[... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_sao_add_offset.v | 17,406 | module MODULE1(
VAR18 ,
VAR9 ,
VAR8
);
parameter VAR20 = 128 ;
input [VAR20-1:0] VAR18 ; input [ 16:0] VAR9 ;
output [VAR20-1:0] VAR8 ;
wire [VAR20-1:0] VAR31 ; wire [4:0] VAR6 ;
wire [4:0] VAR44 ;
wire [4:0] VAR45 ;
wire [4:0] VAR30 ;
wire signed [2:0] VAR43 ;
wire signed [2:0] VAR7 ;
wire signed [2:0] VAR13 ;
wire si... | gpl-3.0 |
archlabo/Frix | fpga/nexys4/rtl/clock/clock.v | 2,120 | module MODULE1( input wire VAR15,
input wire VAR8,
output wire VAR2,
output wire VAR14,
output wire VAR10
);
wire VAR4, VAR7, VAR1;
wire VAR5;
VAR6 VAR3(VAR15, VAR2, VAR14, VAR4);
MODULE2 MODULE1(VAR2, (VAR8 & VAR4), VAR10);
endmodule
module MODULE2(VAR13, VAR12, VAR11);
input VAR13, VAR12;
output VAR11;
reg [23:0] VAR... | bsd-2-clause |
alexforencich/verilog-i2c | rtl/axis_fifo.v | 10,453 | module MODULE1 #
(
parameter VAR21 = 4096,
parameter VAR6 = 8,
parameter VAR38 = (VAR6>8),
parameter VAR32 = (VAR6/8),
parameter VAR25 = 1,
parameter VAR10 = 0,
parameter VAR19 = 8,
parameter VAR20 = 0,
parameter VAR39 = 8,
parameter VAR18 = 1,
parameter VAR36 = 1,
parameter VAR24 = 2,
parameter VAR23 = 0,
parameter VA... | mit |
gralco/FPGA-Elevator-Project | Mojo V3 - Xilinx Spartan 6 Project/Elevator/work/planAhead/Elevator/Elevator.srcs/sources_1/imports/verilog/mojo_top.v | 1,388 | module MODULE1(
input clk,
input VAR22,
input VAR25,
output[7:0]VAR8,
output VAR10,
input VAR3,
input VAR9,
input VAR18,
output [3:0] VAR20,
input VAR23, output VAR13, input VAR17, input en,
input [3:0] VAR12,
output [3:0] VAR1,
output [3:0] VAR2,
output VAR15,
output VAR4,
output VAR6,
output VAR19
);
wire rst = ~VAR2... | gpl-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_ddr_byte_lane.v | 28,504 | module MODULE1 #(
parameter VAR130 = "VAR83", parameter VAR182 = "VAR215",
parameter VAR327 = 12'b111111111111,
parameter VAR2 = 12'b111111111111,
parameter VAR230 = 24'b001000100010001000100010,
parameter VAR185 = "VAR31",
parameter VAR338 = 4,
parameter VAR194 = "VAR215",
parameter VAR21 = 1,
parameter VAR132 = 1,
pa... | mit |
anderson1008/NOCulator | hring/hw/buffered/src/vcr_crossbar_mac.v | 2,940 | module MODULE1
(clk, reset, VAR14, VAR17, VAR1);
parameter VAR8 = 5;
parameter VAR5 = 5;
parameter VAR10 = 32;
parameter VAR13 = VAR12;
parameter VAR11 = VAR2;
input clk;
input reset;
input [0:VAR8*VAR5-1] VAR14;
input [0:VAR8*VAR10-1] VAR17;
output [0:VAR5*VAR10-1] VAR1;
wire [0:VAR5*VAR10-1] VAR1;
wire [0:VAR8*VAR5-1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2b/sky130_fd_sc_hdll__or2b.behavioral.pp.v | 1,944 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR13 ,
VAR5,
VAR14,
VAR10 ,
VAR4
);
output VAR8 ;
input VAR6 ;
input VAR13 ;
input VAR5;
input VAR14;
input VAR10 ;
input VAR4 ;
wire VAR9 ;
wire VAR15 ;
wire VAR7;
not VAR12 (VAR9 , VAR13 );
or VAR1 (VAR15 , VAR9, VAR6 );
VAR3 VAR11 (VAR7, VAR15, VAR5, VAR14);
buf VAR2 (VAR8 , VAR7 );
e... | apache-2.0 |
google/yaricv32 | cpu.v | 17,923 | module MODULE1(
input clk,
output VAR10);
localparam VAR3 = 32;
localparam VAR69 = VAR3;
localparam VAR107 = 32;
localparam VAR127 = 14;
localparam VAR111 = 2; localparam VAR2 = 2;
localparam VAR122 = VAR46(VAR69) - 1;
localparam VAR25 = VAR46(VAR3 / 8);
localparam VAR118 = ((1 << (VAR127 - VAR111 - 1)) << VAR25) - VAR... | apache-2.0 |
sirchuckalot/zet-ng | rtl/zet_front_fifo16to8.v | 1,936 | module MODULE1(
input VAR7,
input VAR2,
input VAR3,
input VAR14,
input [15:0] VAR9,
output VAR6,
output VAR4,
output reg [7:0] VAR11,
input VAR1
);
reg [15:0] VAR12[0:7];
reg [2:0] VAR10;
reg [3:0] VAR5;
reg [3:0] VAR13;
wire [15:0] VAR8;
assign VAR8 = VAR12[VAR5[3:1]];
always @(*) begin
case(VAR5[0])
1'd0: VAR11 <= VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufinv/sky130_fd_sc_lp__bufinv.symbol.v | 1,272 | module MODULE1 (
input VAR1,
output VAR2
);
supply1 VAR6;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2bb2ai/sky130_fd_sc_hd__o2bb2ai_4.v | 2,411 | module MODULE2 (
VAR10 ,
VAR1,
VAR2,
VAR6 ,
VAR11 ,
VAR5,
VAR8,
VAR3 ,
VAR4
);
output VAR10 ;
input VAR1;
input VAR2;
input VAR6 ;
input VAR11 ;
input VAR5;
input VAR8;
input VAR3 ;
input VAR4 ;
VAR7 VAR9 (
.VAR10(VAR10),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111ai/sky130_fd_sc_hs__o2111ai.functional.v | 1,978 | module MODULE1 (
VAR10,
VAR4,
VAR14 ,
VAR2 ,
VAR1 ,
VAR12 ,
VAR3 ,
VAR5
);
input VAR10;
input VAR4;
output VAR14 ;
input VAR2 ;
input VAR1 ;
input VAR12 ;
input VAR3 ;
input VAR5 ;
wire VAR3 VAR13 ;
wire VAR11 ;
wire VAR6;
or VAR9 (VAR13 , VAR1, VAR2 );
nand VAR16 (VAR11 , VAR3, VAR12, VAR5, VAR13 );
VAR8 VAR15 (VAR6, ... | apache-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_timer_0.v | 6,701 | module MODULE1 (
address,
VAR30,
clk,
VAR10,
VAR1,
VAR14,
irq,
VAR22
)
;
output irq;
output [ 15: 0] VAR22;
input [ 2: 0] address;
input VAR30;
input clk;
input VAR10;
input VAR1;
input [ 15: 0] VAR14;
wire VAR20;
wire VAR23;
wire VAR19;
reg [ 3: 0] VAR15;
wire VAR31;
reg VAR33;
wire VAR28;
wire [ 31: 0] VAR11;
reg [ 3... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkinvlp/sky130_fd_sc_hd__clkinvlp.behavioral.v | 1,369 | module MODULE1 (
VAR7,
VAR6
);
output VAR7;
input VAR6;
supply1 VAR2;
supply0 VAR3;
supply1 VAR8 ;
supply0 VAR4 ;
wire VAR5;
not VAR1 (VAR5, VAR6 );
buf VAR9 (VAR7 , VAR5 );
endmodule | apache-2.0 |
freecores/zet86 | rtl-model/jmp_cond.v | 2,047 | module MODULE1 (
input [4:0] VAR11,
input [3:0] VAR8,
input VAR3,
input [15:0] VAR1,
output reg VAR10
);
wire VAR4, VAR2, VAR9, VAR7, VAR6;
wire VAR5;
assign VAR4 = VAR11[4];
assign VAR2 = VAR11[3];
assign VAR9 = VAR11[2];
assign VAR7 = VAR11[1];
assign VAR6 = VAR11[0];
assign VAR5 = ~(|VAR1);
always @(VAR8 or VAR3 or ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkinv/sky130_fd_sc_ms__clkinv.symbol.v | 1,264 | module MODULE1 (
input VAR4,
output VAR1
);
supply1 VAR2;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/enet_if/enet_ddr_ctrl.v | 10,124 | module MODULE1(
input VAR54, input VAR14, input VAR18, input [31:0] VAR7, input [31:0] VAR47, input [31:0] VAR40, input [31:0] VAR51, output [31:0] VAR32,
output [31:0] VAR23,
output VAR34,
output VAR55,
output reg VAR45,
input VAR3,
output reg VAR31,
input [63:0] VAR15,
output [63:0] VAR10,
output reg VAR29,
input VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfxbp/sky130_fd_sc_hs__dfxbp_2.v | 2,101 | module MODULE2 (
VAR1 ,
VAR5 ,
VAR4 ,
VAR7 ,
VAR3,
VAR8
);
input VAR1 ;
input VAR5 ;
output VAR4 ;
output VAR7 ;
input VAR3;
input VAR8;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR1,
VAR5 ,
VAR4 ,
VAR7
);
input VAR1;
input VAR5 ;
output VAR4... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3.behavioral.v | 1,440 | module MODULE1 (
VAR8,
VAR9
);
output VAR8;
input VAR9;
supply1 VAR1;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR4 ;
wire VAR6;
not VAR3 (VAR6, VAR9 );
buf VAR7 (VAR8 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfbbp/sky130_fd_sc_ms__dfbbp.pp.blackbox.v | 1,465 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR9 ,
VAR4 ,
VAR8 ,
VAR1,
VAR7 ,
VAR3 ,
VAR6 ,
VAR10
);
output VAR2 ;
output VAR5 ;
input VAR9 ;
input VAR4 ;
input VAR8 ;
input VAR1;
input VAR7 ;
input VAR3 ;
input VAR6 ;
input VAR10 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_4.behavioral.pp.v | 1,495 | module MODULE1( VAR5, VAR8, VAR2, VAR1, VAR6 );
input VAR8, VAR5;
inout VAR1, VAR6;
output VAR2;
VAR4 VAR7(.VAR5(VAR5),.VAR8(VAR8),.VAR2(VAR2),.VAR1(VAR1),.VAR6(VAR6));
VAR4 VAR3(.VAR5(VAR5),.VAR8(VAR8),.VAR2(VAR2),.VAR1(VAR1),.VAR6(VAR6)); | apache-2.0 |
google/CFU-Playground | proj/skip_tflm/cfu.v | 1,446 | module MODULE1 (
input VAR4,
output VAR8,
input [9:0] VAR5,
input [31:0] VAR6,
input [31:0] VAR3,
output VAR1,
input VAR2,
output [31:0] VAR7,
input reset,
input clk
);
assign VAR1 = VAR4;
assign VAR8 = VAR2;
assign VAR7 = VAR5[0] ?
VAR6 + VAR3:
VAR6 - VAR3;
endmodule | apache-2.0 |
GustavoOS/ARMAria | src/MemoryUnit/MemoryUnit.v | 1,782 | module MODULE1
parameter VAR8 = 32,
parameter VAR11 = 13,
parameter VAR23 = 8,
parameter VAR12 = 15,
parameter VAR9 = 16
)(
input VAR24, VAR14, VAR7,
input [(VAR8 -1):0] VAR27,
VAR22,
VAR6,
input VAR10,
output [(VAR9 -1):0] VAR26,
output [(VAR8-1):0] VAR20
);
wire [(VAR12 - 1) : 0] VAR18;
wire [(VAR8 -1): 0] VAR28, VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.v | 2,034 | module MODULE2 (
VAR3 ,
VAR8 ,
VAR4,
VAR1,
VAR6 ,
VAR7
);
output VAR3 ;
input VAR8 ;
input VAR4;
input VAR1;
input VAR6 ;
input VAR7 ;
VAR2 VAR5 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR3,
VAR8
);
output VAR3;
input VAR8;
supply1 VAR4;
supply0 VAR1;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o221a/sky130_fd_sc_hd__o221a.pp.blackbox.v | 1,428 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR7 ,
VAR4 ,
VAR1 ,
VAR8 ,
VAR10,
VAR6,
VAR5 ,
VAR3
);
output VAR9 ;
input VAR2 ;
input VAR7 ;
input VAR4 ;
input VAR1 ;
input VAR8 ;
input VAR10;
input VAR6;
input VAR5 ;
input VAR3 ;
endmodule | apache-2.0 |
wgml/sysrek | skin_color_segm/ipcore_dir/multiply.v | 25,133 | module MODULE2 (
clk, VAR33, VAR8, VAR15
);
input clk;
input [17 : 0] VAR33;
input [17 : 0] VAR8;
output [35 : 0] VAR15;
wire \VAR89/VAR6 ;
wire \VAR89/VAR81 ;
wire \VAR13/VAR41 ;
wire \VAR13/VAR19 ;
wire \VAR13/VAR40<17>VAR9 ;
wire \VAR13/VAR40<16>VAR9 ;
wire \VAR13/VAR40<15>VAR9 ;
wire \VAR13/VAR40<14>VAR9 ;
wire \VA... | gpl-2.0 |
jas0n1ee/THU-DSD | FB/hardmodle.v | 1,803 | module MODULE1 (
address,
clk,
VAR2,
VAR6,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input [ 3: 0] VAR2;
input VAR6;
wire VAR4;
wire [ 3: 0] VAR1;
wire [ 3: 0] VAR5;
reg [ 31: 0] VAR3;
assign VAR4 = 1;
assign VAR5 = {4 {(address == 0)}} & VAR1;
always @(posedge clk or negedge VAR6)
begin
if (VAR6... | mit |
hhuang25/uwaterloo_ece224 | ANT/sdram_0.v | 23,303 | module MODULE1 (
clk,
rd,
VAR34,
wr,
VAR4,
VAR24,
VAR35,
VAR10,
VAR57,
VAR14
)
;
output VAR24;
output VAR35;
output VAR10;
output VAR57;
output [ 40: 0] VAR14;
input clk;
input rd;
input VAR34;
input wr;
input [ 40: 0] VAR4;
wire VAR24;
wire VAR35;
wire VAR10;
reg [ 1: 0] VAR60;
reg [ 40: 0] VAR78;
reg [ 40: 0] VAR45;
... | mit |
Elphel/x393_sata | host/gtx_elastic.v | 15,636 | module MODULE1 #(
parameter VAR86 = 4, parameter VAR81 = 8 )
(
input wire rst,
input wire VAR96,
input wire VAR11,
input wire VAR36,
input wire [1:0] VAR56,
input wire [1:0] VAR85,
input wire [1:0] VAR83,
input wire [15:0] VAR29,
output wire VAR21,
output wire [1:0] VAR60,
output wire [1:0] VAR99,
output wire [1:0] VAR... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_2.behavioral.v | 1,250 | module MODULE1( VAR2, VAR7, VAR6, VAR4 );
input VAR2, VAR7, VAR6;
output VAR4;
VAR3 VAR1(.VAR2(VAR2),.VAR7(VAR7),.VAR6(VAR6),.VAR4(VAR4));
VAR3 VAR5(.VAR2(VAR2),.VAR7(VAR7),.VAR6(VAR6),.VAR4(VAR4)); | apache-2.0 |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v | 1,179 | module MODULE1(VAR1, VAR2)
;
output VAR1;
input VAR2;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22o/sky130_fd_sc_ms__a22o.behavioral.pp.v | 2,151 | module MODULE1 (
VAR19 ,
VAR4 ,
VAR10 ,
VAR15 ,
VAR18 ,
VAR5,
VAR17,
VAR14 ,
VAR16
);
output VAR19 ;
input VAR4 ;
input VAR10 ;
input VAR15 ;
input VAR18 ;
input VAR5;
input VAR17;
input VAR14 ;
input VAR16 ;
wire VAR11 ;
wire VAR9 ;
wire VAR13 ;
wire VAR12;
and VAR3 (VAR11 , VAR15, VAR18 );
and VAR2 (VAR9 , VAR4, VAR1... | apache-2.0 |
DigitalLogicSummerTerm2015/mips-cpu-single-cycle | Peripheral.v | 1,806 | module MODULE1 (reset,clk,rd,wr,addr,VAR5,VAR15,VAR1,VAR9,VAR8,VAR7,din,dout);
input reset,clk;
input rd,wr;
input [31:0] addr;
input [31:0] VAR5;
input din;
output dout;
output [31:0] VAR15;
reg [31:0] VAR15;
output [7:0] VAR1;
reg [7:0] VAR1;
input [7:0] VAR9;
output [11:0] VAR8;
reg [11:0] VAR8;
output VAR7;
reg [31... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_avlmm_pr_freeze_bridge_0/ghrd_10as066n2_avlmm_pr_freeze_bridge_0_bb.v | 2,895 | module MODULE1 (
input wire VAR20, input wire VAR29, output wire VAR7, input wire VAR11, output wire VAR3, input wire VAR2, output wire VAR21, output wire [9:0] VAR25, output wire [3:0] VAR30, output wire [31:0] VAR8, input wire [31:0] VAR5, output wire [2:0] VAR16, input wire VAR12, output wire VAR31, output wire VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111ai/sky130_fd_sc_hs__o2111ai.pp.symbol.v | 1,375 | module MODULE1 (
input VAR6 ,
input VAR4 ,
input VAR7 ,
input VAR1 ,
input VAR3 ,
output VAR5 ,
input VAR2,
input VAR8
);
endmodule | apache-2.0 |
SymbiFlow/fpga-tool-perf | src/bram-n2/bram_n2.v | 1,389 | module MODULE1
(
input wire clk,
output wire VAR4,
input wire VAR2,
input wire [15:0] VAR14,
output wire [15:0] VAR3
);
reg rst = 1;
reg VAR13 = 1;
reg VAR11 = 1;
reg VAR8 = 1;
assign VAR3[0] = rst;
assign VAR3[13:1] = VAR14[13:1];
assign VAR3[14] = ^VAR14;
assign VAR3[15] = VAR2;
always @(posedge clk) begin
VAR8 <= 0;... | isc |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_miim.v | 15,742 | module MODULE1
(
VAR8,
VAR56,
VAR42,
VAR49,
VAR29,
VAR43,
VAR60,
VAR13,
VAR24,
VAR37,
VAR55,
VAR19,
VAR18,
VAR3,
VAR17,
VAR48,
VAR54,
VAR30,
VAR51,
VAR52,
VAR11
);
input VAR8; input VAR56; input [7:0] VAR42; input [15:0] VAR29; input [4:0] VAR43; input [4:0] VAR60; input VAR49; input VAR13; input VAR24; input VAR37; in... | gpl-2.0 |
asm2750/Neopixel_TX_Core | hdl/neopixel_tx.v | 3,128 | module MODULE1(
input wire VAR35, input wire VAR5, input wire VAR15, input wire VAR4, input wire VAR8, input wire [23:0] VAR22, input wire VAR23,
output wire VAR34, output wire VAR25, output wire VAR11 );
wire VAR3;
wire VAR17;
wire [23:0] VAR16;
wire VAR14;
wire VAR19;
wire VAR7;
wire VAR31;
wire VAR1;
VAR21 #(
24,
10... | apache-2.0 |
aap/pdp6 | verilog/core161c.v | 10,328 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR54,
input wire VAR12,
input wire VAR90,
input wire VAR157,
input wire VAR39,
input wire VAR81,
input wire VAR34,
input wire [21:35] VAR131,
input wire [18:21] VAR83,
input wire VAR76,
input wire [0:35] VAR150,
output wire VAR101,
output wire VAR74,
output ... | mit |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/v/sasc_top.v | 10,306 | module MODULE1( clk, VAR29,
VAR9, VAR39, VAR23, VAR13,
VAR51, VAR11,
VAR36, VAR26, VAR46, VAR17, VAR40, VAR32);
input clk;
input VAR29;
input VAR9;
output VAR39;
input VAR23;
output VAR13;
input VAR51;
input VAR11;
input [7:0] VAR36;
output [7:0] VAR26;
input VAR46, VAR17;
output VAR40, VAR32;
parameter VAR35 = 1'b0,
V... | gpl-2.0 |
Triple-Z/COExperiment_Repo | Project_2_OC/ALUOnBoard/alu.v | 8,553 | module MODULE1(
input [11:0] VAR23, input [31:0] VAR46, input [31:0] VAR31, output [31:0] VAR26 );
wire VAR33; wire VAR8; wire VAR17; wire VAR2; wire VAR18; wire VAR22; wire VAR28; wire VAR19; wire VAR1; wire VAR7; wire VAR10; wire VAR24;
assign VAR33 = VAR23[11];
assign VAR8 = VAR23[10];
assign VAR17 = VAR23[ 9];
assi... | mit |
SymbiFlow/yosys | techlibs/intel/cycloneiv/cells_arith.v | 3,848 | module MODULE1(
module 80cycloneivalu (VAR21, VAR26, VAR16, VAR1, VAR2, VAR18, VAR14);
parameter VAR10 = 0;
parameter VAR23 = 0;
parameter VAR25 = 1;
parameter VAR5 = 1;
parameter VAR12 = 1;
input [VAR25-1:0] VAR21;
input [VAR5-1:0] VAR26;
output [VAR12-1:0] VAR2, VAR18;
input VAR16, VAR1;
output [VAR12:0] VAR14;
wire ... | isc |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2a/sky130_fd_sc_lp__o2bb2a.behavioral.pp.v | 2,171 | module MODULE1 (
VAR15 ,
VAR8,
VAR3,
VAR1 ,
VAR19 ,
VAR16,
VAR17,
VAR12 ,
VAR7
);
output VAR15 ;
input VAR8;
input VAR3;
input VAR1 ;
input VAR19 ;
input VAR16;
input VAR17;
input VAR12 ;
input VAR7 ;
wire VAR11 ;
wire VAR5 ;
wire VAR2 ;
wire VAR9;
nand VAR10 (VAR11 , VAR3, VAR8 );
or VAR4 (VAR5 , VAR19, VAR1 );
and VA... | apache-2.0 |
bigeagle/riffa | fpga/riffa_hdl/translation_altera.v | 9,299 | module MODULE1
parameter VAR7 = 128
)
(
input VAR20,
input VAR90,
input [VAR7-1:0] VAR53,
input [0:0] VAR23,
input [0:0] VAR69,
input [0:0] VAR89,
output VAR93,
input [0:0] VAR83,
output [VAR7-1:0] VAR79,
output [0:0] VAR32,
input VAR15,
output [0:0] VAR39,
output [0:0] VAR10,
output [0:0] VAR28,
input [VAR66-1:0] VAR7... | bsd-3-clause |
linuxbest/lzs | pcores/comp_unit_v1_00_a/hdl/verilog/ch_fifo.v | 5,421 | module MODULE1(
rst,
VAR68,
VAR66,
din,
VAR80,
VAR96,
dout,
VAR73,
VAR69,
VAR90,
VAR86,
VAR28,
VAR64);
input rst;
input VAR68;
input VAR66;
input [64 : 0] din;
input VAR80;
input VAR96;
output [64 : 0] dout;
output VAR73;
output VAR69;
output VAR90;
output VAR86;
output VAR28;
output VAR64;
VAR34 #(
.VAR83(0),
.VAR25(0... | gpl-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/axi/mig_7series_v4_0_axi_mc_ar_channel.v | 10,259 | module MODULE1 #
(
parameter integer VAR44 = 4,
parameter integer VAR29 = 32,
parameter integer VAR39 = 30,
parameter integer VAR18 = 32,
parameter integer VAR27 = 1,
parameter integer VAR56 = 2,
parameter integer VAR50 = 2
)
(
input wire clk ,
input wire reset ,
input wire [VAR44-1:0] VAR20 ,
input wire [VAR29-1:0] VA... | mit |
bbrown1867/ObjectTracking | hw/common/video_input/DIV.v | 4,458 | module MODULE1 (
VAR13,
VAR2,
VAR22,
VAR20,
VAR16,
VAR9);
input VAR13;
input VAR2;
input [3:0] VAR22;
input [9:0] VAR20;
output [9:0] VAR16;
output [3:0] VAR9;
wire [9:0] VAR18;
wire [3:0] VAR10;
wire [9:0] VAR16 = VAR18[9:0];
wire [3:0] VAR9 = VAR10[3:0];
VAR5 VAR4 (
.VAR22 (VAR22),
.VAR13 (VAR13),
.VAR2 (VAR2),
.VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvn/sky130_fd_sc_hs__einvn_8.v | 2,020 | module MODULE2 (
VAR4 ,
VAR1,
VAR3 ,
VAR5,
VAR6
);
input VAR4 ;
input VAR1;
output VAR3 ;
input VAR5;
input VAR6;
VAR2 VAR7 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR4 ,
VAR1,
VAR3
);
input VAR4 ;
input VAR1;
output VAR3 ;
supply1 VAR5;
supply0 VAR6;
VAR2 VAR7 (
... | apache-2.0 |
antmicro/yosys | manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v | 1,574 | module MODULE1 (VAR5, VAR7, VAR10);
parameter VAR2 = 0;
parameter VAR3 = 0;
parameter VAR14 = 1;
parameter VAR1 = 1;
parameter VAR4 = 1;
input [VAR14-1:0] VAR5;
input [VAR1-1:0] VAR7;
output [VAR4-1:0] VAR10;
wire [17:0] VAR6 = VAR5;
wire [24:0] VAR9 = VAR7;
wire [47:0] VAR12;
assign VAR10 = VAR12;
wire [1023:0] VAR11 ... | isc |
DoctorWkt/CSCv2 | Verilog/cscv2.v | 2,566 | module MODULE1 (
input VAR22, output VAR26, output [3:0] VAR11, output [3:0] VAR23, output [7:0] VAR8,
output VAR14,
output [7:0] address,
output [3:0] VAR1,
output [2:0] VAR25,
output [3:0] VAR19,
output [3:0] VAR2,
output [3:0] VAR4,
output VAR7,
output VAR27,
output VAR18
);
reg clk= 0;
wire VAR5;
wire VAR16;
assign... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_2.functional.pp.v | 1,072 | module MODULE1( VAR3, VAR9, VAR7, VAR4, VAR2 );
input VAR7, VAR3;
inout VAR4, VAR2;
output VAR9;
wire VAR10;
not VAR8( VAR10, VAR7 );
wire VAR6;
not VAR1( VAR6, VAR3 );
or VAR5( VAR9, VAR10, VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvp/sky130_fd_sc_hs__einvp.blackbox.v | 1,231 | module MODULE1 (
VAR5 ,
VAR1,
VAR3
);
input VAR5 ;
input VAR1;
output VAR3 ;
supply1 VAR4;
supply0 VAR2;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_1.functional.v | 1,787 | module MODULE1( VAR15, VAR9, VAR18, VAR25, VAR20, VAR14, VAR1, VAR27 );
input VAR25, VAR18, VAR14, VAR15, VAR20, VAR9, VAR27;
output VAR1;
not VAR16( VAR12, VAR14 );
not VAR7( VAR8, VAR20 );
wire VAR10;
not VAR5( VAR10, VAR18 );
wire VAR19;
not VAR22( VAR19, VAR15 );
wire VAR23;
and VAR24( VAR23, VAR10, VAR19 );
wire V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32oi/sky130_fd_sc_ms__a32oi.symbol.v | 1,433 | module MODULE1 (
input VAR4,
input VAR9,
input VAR6,
input VAR8,
input VAR10,
output VAR7
);
supply1 VAR1;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_1.behavioral.v | 1,718 | module MODULE1( VAR8, VAR11, VAR6 );
input VAR11, VAR8;
output VAR6;
reg VAR5;
VAR4 VAR1(.VAR8(VAR8),.VAR11(VAR11),.VAR6(VAR6),.VAR5(VAR5));
VAR4 VAR10(.VAR8(VAR8),.VAR11(VAR11),.VAR6(VAR6),.VAR5(VAR5));
not VAR3(VAR7,VAR11);
buf VAR9(VAR2,VAR11); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdlclkp/sky130_fd_sc_hd__sdlclkp.functional.pp.v | 2,018 | module MODULE1 (
VAR16,
VAR3 ,
VAR1,
VAR7 ,
VAR5,
VAR9,
VAR15 ,
VAR6
);
output VAR16;
input VAR3 ;
input VAR1;
input VAR7 ;
input VAR5;
input VAR9;
input VAR15 ;
input VAR6 ;
wire VAR4 ;
wire VAR2 ;
wire VAR12 ;
wire VAR17;
not VAR13 (VAR2 , VAR4 );
not VAR11 (VAR12 , VAR7 );
nor VAR8 (VAR17, VAR1, VAR3 );
VAR10 VAR18 ... | apache-2.0 |
walkthetalk/fsref | ip/axis_reshaper_v2/src/axis_reshaper_v2.v | 4,920 | module MODULE1 #
(
parameter integer VAR2 = 8,
parameter integer VAR17 = 2,
parameter integer VAR31 = 12,
parameter integer VAR32 = 12
) (
input wire clk,
input wire VAR34,
input wire VAR33,
input wire [VAR2-1:0] VAR23,
input wire VAR36,
input wire VAR15,
output reg VAR27,
output wire VAR28,
output reg [VAR2-1:0] VAR3,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2b/sky130_fd_sc_hs__nand2b_2.v | 2,020 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR7 ,
VAR1,
VAR2
);
output VAR5 ;
input VAR4 ;
input VAR7 ;
input VAR1;
input VAR2;
VAR6 VAR3 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR5 ,
VAR4,
VAR7
);
output VAR5 ;
input VAR4;
input VAR7 ;
supply1 VAR1;
supply0 VAR2;
VAR6 VAR3 ... | apache-2.0 |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_dsp.v | 16,867 | module MODULE1 #(
parameter VAR99 = 8
)
(
input VAR76 , input VAR106 , input [ 14-1: 0] VAR53 , input [ 14-1: 0] VAR20 , output [ 14-1: 0] VAR3 , output [ 14-1: 0] VAR17 ,
output [ 14-1: 0] VAR19,
output [ 14-1: 0] VAR62,
input [ 14-1: 0] VAR98,
input [ 14-1: 0] VAR56,
input [ 14-1: 0] VAR71,
output [ 14-1: 0] VAR77,
o... | mit |
SI-RISCV/e200_opensource | rtl/e203/subsys/e203_subsys_pllclkdiv.v | 2,447 | module MODULE1(
input VAR15,
input VAR18,
input VAR2,
input [5:0] VAR19,
input clk, output VAR14 );
wire [5:0] VAR1;
wire VAR10 = (VAR1 == VAR19);
wire [5:0] VAR5 = VAR10 ? 6'b0 : (VAR1 + 1'b1);
wire VAR20 = (~VAR2);
VAR11 #(6) VAR7 (VAR20, VAR5, VAR1, clk, VAR15);
wire VAR9;
wire VAR6 = ~VAR9;
wire VAR4 = VAR20 & VAR1... | apache-2.0 |
rohit91/HDMI2USB | hdl/jpeg_encoder/design/HeaderRAM.v | 2,240 | module MODULE1(VAR1, VAR9, VAR7, VAR4, clk, VAR2);
output [7:0] VAR2;
input [7:0] VAR1;
input[9:0] VAR7;
input[9:0] VAR9;
input clk, VAR4;
reg [9:0] VAR8;
reg[7:0] VAR5 [1023:0] ;
VAR3 VAR6("..
assign VAR2 = VAR5[VAR8];
always @(posedge clk) begin
if (VAR4)
VAR5[VAR9] <= VAR1;
VAR8 <= VAR7;
end
endmodule | bsd-2-clause |
olajep/oh | src/common/hdl/oh_crc32_64b.v | 22,911 | module MODULE1(
VAR2,
VAR3, VAR1
);
input [63:0] VAR3;
input [31:0] VAR1;
output [31:0] VAR2;
assign VAR2[0] = VAR1[1] ^ VAR1[3] ^ VAR1[4] ^ VAR1[6] ^ VAR1[9] ^ VAR1[10] ^ VAR1[11] ^ VAR1[14] ^ VAR1[16] ^ VAR1[17] ^ VAR1[19] ^ VAR1[20] ^ VAR1[27] ^ VAR1[30] ^ VAR3[1] ^ VAR3[3] ^ VAR3[4] ^ VAR3[6] ^ VAR3[9] ^ VAR3[10] ^... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w.v | 1,790 | module MODULE1 #(parameter VAR21(VAR16)
, parameter VAR21(VAR5)
, parameter VAR18=0
, parameter VAR14=VAR12(VAR5)
)
(input VAR2
, input VAR13
, input VAR15
, input [VAR14-1:0] VAR4
, input [VAR26(VAR16, 1):0] VAR11
, input VAR22
, input [VAR14-1:0] VAR9
, output logic [VAR26(VAR16, 1):0] VAR25
, input VAR24
, input [VA... | bsd-3-clause |
peteg944/music-fpga | Experimental/RainbowMatrix and Partial Spectrum/ipcore_dir/Clock48MHZ/example_design/Clock48MHZ_exdes.v | 6,003 | module MODULE1
parameter VAR15 = 100
)
( input VAR1,
input VAR14,
output [3:1] VAR22,
output [3:1] VAR21,
output VAR20
);
localparam VAR19 = 16;
localparam VAR6 = 3;
genvar VAR29;
wire VAR23 = !VAR20 || VAR14;
reg [VAR6:1] VAR7;
reg [VAR6:1] VAR30;
reg [VAR6:1] VAR3;
reg [VAR6:1] VAR5;
wire [VAR6:1] VAR12;
wire [VAR6:1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxbp/sky130_fd_sc_ms__sdfxbp.behavioral.v | 2,477 | module MODULE1 (
VAR15 ,
VAR20,
VAR14,
VAR17 ,
VAR12,
VAR24
);
output VAR15 ;
output VAR20;
input VAR14;
input VAR17 ;
input VAR12;
input VAR24;
supply1 VAR9;
supply0 VAR7;
supply1 VAR21 ;
supply0 VAR19 ;
wire VAR13 ;
wire VAR10 ;
reg VAR25 ;
wire VAR18 ;
wire VAR26;
wire VAR22;
wire VAR2;
wire VAR23 ;
wire VAR5 ;
wire... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/probe_p/sky130_fd_sc_hvl__probe_p.behavioral.v | 1,364 | module MODULE1 (
VAR7,
VAR2
);
output VAR7;
input VAR2;
supply1 VAR5;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR1 ;
wire VAR8;
buf VAR9 (VAR8, VAR2 );
buf VAR4 (VAR7 , VAR8 );
endmodule | apache-2.0 |
AndreaCorallo/KPU | rtl/kpu/alu.v | 3,108 | module MODULE1(input wire [3:0] VAR3,
input wire [VAR6-1:0] VAR8,
input wire [VAR6-1:0] VAR2,
output reg [VAR6-1:0] VAR7,
output reg [3:0] VAR10);
wire [VAR6-1:0] addr;
wire [VAR6-1:0] VAR1;
wire VAR11;
wire VAR5;
wire signed [VAR6-1:0] VAR9;
wire signed [VAR6-1:0] VAR4;
assign VAR9 = VAR8;
assign VAR4 = VAR2;
assign a... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_1.behavioral.pp.v | 1,686 | module MODULE1( VAR4, VAR8, VAR7, VAR9, VAR5, VAR3 );
input VAR9, VAR8, VAR7;
inout VAR5, VAR3;
output VAR4;
VAR2 VAR6(.VAR4(VAR4),.VAR8(VAR8),.VAR7(VAR7),.VAR9(VAR9),.VAR5(VAR5),.VAR3(VAR3));
VAR2 VAR1(.VAR4(VAR4),.VAR8(VAR8),.VAR7(VAR7),.VAR9(VAR9),.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111o/sky130_fd_sc_ms__a2111o.pp.blackbox.v | 1,427 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR1 ,
VAR8 ,
VAR3 ,
VAR2 ,
VAR9,
VAR7,
VAR5 ,
VAR4
);
output VAR10 ;
input VAR6 ;
input VAR1 ;
input VAR8 ;
input VAR3 ;
input VAR2 ;
input VAR9;
input VAR7;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
secworks/rosc_entropy | src/rtl/rosc_entropy.v | 10,147 | module MODULE1(
input wire clk,
input wire VAR11,
input wire VAR39,
input wire VAR8,
input wire [7 : 0] address,
input wire [31 : 0] VAR56,
output wire [31 : 0] VAR52,
output wire VAR54,
input wire VAR33,
input wire VAR6,
output wire VAR55,
output wire VAR48,
output wire [31 : 0] VAR44,
output wire VAR36,
input wire VA... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvgnd/sky130_fd_sc_ms__tapvgnd.blackbox.v | 1,249 | module MODULE1 ();
supply1 VAR1;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
Murailab-arch/magukara | boards/ecp3versa/rtl/ipexpress/ecp3/pciex1/pcie_eval/models/ecp3/pipe_top.v | 21,437 | module MODULE1 (
input wire VAR37,
input wire VAR54,
input wire VAR88,
input wire VAR90,
input wire VAR16,
input wire [1:0] VAR56,
input wire VAR28,
input wire VAR67,
input wire VAR73,
input wire [7:0] VAR2,
input wire VAR102,
input wire [2:0] VAR7,
input wire VAR68,
input wire VAR59,
input wire VAR94,
input wire VAR48... | gpl-3.0 |
sergev/vak-opensource | hardware/verilog/d-flop-rtl/dflop3.v | 1,439 | module MODULE1;
reg VAR6; reg VAR2;
wire VAR4; wire VAR8; wire VAR5, VAR7, VAR1, VAR3; | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_01/02 verilog/Otros/Prueba5/fifo.v | 3,258 | module MODULE1 # (parameter VAR1 =6, VAR13 = 321)(
input reset, VAR22,
input rd, wr,
input [VAR13-1:0] din,
output [VAR13-1:0] dout,
output VAR2,
output VAR15
);
wire VAR4, VAR16;
reg VAR10, VAR11, VAR8, VAR3;
reg [VAR13-1:0] out;
always @ (posedge VAR22) VAR10 <= wr;
always @ (posedge VAR22) VAR11 <= VAR10;
assign VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlclkp/sky130_fd_sc_hvl__dlclkp.blackbox.v | 1,263 | module MODULE1 (
VAR1,
VAR4,
VAR5
);
output VAR1;
input VAR4;
input VAR5 ;
supply1 VAR3;
supply0 VAR2;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_46.v | 32,180 | module MODULE4 (
clk,
reset,
VAR138,
VAR238,
VAR113,
VAR70,
VAR218
);
parameter VAR244 = 18;
parameter VAR170 = 46;
parameter VAR255 = 23;
localparam VAR23 = 53;
input clk;
input reset;
input VAR138;
input VAR238;
input [VAR244-1:0] VAR113; output VAR70;
output [VAR244-1:0] VAR218;
localparam VAR124 = 18; localparam VA... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_hip_s4gx_gen2_x8_128/pci_express_compiler-library/altpcie_pll_phy0.v | 13,113 | module MODULE1 (
VAR67,
VAR51,
VAR38,
VAR56,
VAR40,
VAR13);
input VAR67;
input VAR51;
output VAR38;
output VAR56;
output VAR40;
output VAR13;
wire [5:0] VAR15;
wire VAR45;
wire [0:0] VAR37 = 1'h1;
wire [0:0] VAR39 = 1'h0;
wire [2:2] VAR36 = VAR15[2:2];
wire [1:1] VAR19 = VAR15[1:1];
wire [0:0] VAR65 = VAR15[0:0];
wire ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvp/sky130_fd_sc_ms__einvp.pp.symbol.v | 1,329 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR6 ,
input VAR3 ,
input VAR7,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
Jawanga/ece385lab8 | lab8_usb/db/altera_mult_add_q1u2.v | 18,123 | module MODULE1
(
VAR185,
VAR327,
VAR172,
VAR247,
VAR310) ;
input VAR185;
input VAR327;
input [15:0] VAR172;
input [15:0] VAR247;
output [31:0] VAR310;
tri0 VAR185;
tri1 VAR327;
tri0 [15:0] VAR172;
tri0 [15:0] VAR247;
wire [31:0] VAR290;
VAR161 VAR168
(
.VAR185(VAR185),
.VAR80(),
.VAR327(VAR327),
.VAR172(VAR172),
.VAR24... | apache-2.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/freedm_bus/fb_slave_mac.v | 7,248 | module MODULE1 (VAR1, VAR40, VAR12, VAR38, VAR10,
VAR36, VAR26, VAR6, VAR49,
VAR61, VAR5, VAR23, VAR45, VAR31, VAR64
VAR18,
VAR4, VAR24, VAR2, VAR11, VAR8, VAR33, VAR30
);
input VAR1;
input VAR40; input [3:0] VAR12; input VAR38;
input [7:0] VAR10; input VAR36; input VAR26; input VAR6; input VAR49;
output [3:0] VAR61; o... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/phy/phy_write.v | 86,909 | module MODULE1 #
(
parameter VAR113 = 100,
parameter VAR109 = "VAR68",
parameter VAR65 = "VAR97",
parameter VAR22 = 64,
parameter VAR42 = 8,
parameter VAR98 = 5,
parameter VAR81 = "VAR69",
parameter VAR117 = 1,
parameter VAR7 = "VAR69"
)
(
input clk,
input rst,
input VAR14,
input VAR35,
input VAR70,
input [VAR42-1:0] V... | lgpl-3.0 |
ElegantLin/My-CPU | project_4/project_4.srcs/sources_1/imports/Chapter11/cp0_reg.v | 6,653 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR3,
input wire[4:0] VAR7,
input wire[4:0] VAR21,
input wire[VAR16] VAR2,
input wire[31:0] VAR5,
input wire[5:0] VAR12,
input wire[VAR16] VAR22,
input wire VAR6,
output reg[VAR16] VAR1,
output reg[VAR16] VAR13,
output reg[VAR16] VAR11,
output reg[VAR16] VAR15,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o211ai/sky130_fd_sc_hdll__o211ai_2.v | 2,377 | module MODULE2 (
VAR9 ,
VAR3 ,
VAR7 ,
VAR6 ,
VAR5 ,
VAR11,
VAR8,
VAR4 ,
VAR10
);
output VAR9 ;
input VAR3 ;
input VAR7 ;
input VAR6 ;
input VAR5 ;
input VAR11;
input VAR8;
input VAR4 ;
input VAR10 ;
VAR1 VAR2 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR4(VAR4),
.VA... | apache-2.0 |
DigitalLogicSummerTerm2015/mips-cpu-pipeline | ppcpu/Peripheral.v | 1,829 | module MODULE1 (reset,VAR17,clk,rd,wr,addr,VAR3,VAR6,VAR2,VAR14,VAR11,VAR7,din,dout);
input reset,VAR17,clk;
input rd,wr;
input [31:0] addr;
input [31:0] VAR3;
input din;
output dout;
output [31:0] VAR6;
reg [31:0] VAR6;
output [7:0] VAR2;
reg [7:0] VAR2;
input [7:0] VAR14;
output [11:0] VAR11;
reg [11:0] VAR11;
output... | mit |
AbhishekShah212/School_Projects | ELEN232/pset6/FullAdder.v | 1,528 | module MODULE1(
input [3:0] VAR11,
input [3:0] VAR6,
input VAR1,
output [3:0] VAR8,
output VAR7
);
wire VAR3, VAR13, VAR4;
VAR10 VAR12 (
.VAR11(VAR11[0]),
.VAR6(VAR6[0]), .VAR8(VAR8[0]),
.VAR7(VAR3),
.VAR9(VAR1)
);
VAR10 VAR2 (
.VAR11(VAR11[1]),
.VAR6(VAR6[1] ),
.VAR8(VAR8[1]),
.VAR7(VAR13), .VAR9(VAR3)
);
VAR10 VAR5 (... | mit |
ptracton/wb_soc_template | rtl/ZIP/rtl/pipefetch.v | 10,648 | module MODULE1(VAR3, VAR20, VAR38, VAR16, VAR25, VAR26,
VAR35, VAR8, VAR43,
VAR27, VAR19, VAR34, VAR13, VAR31,
VAR39, VAR24, VAR11, VAR44, VAR9,
VAR2);
parameter VAR7=32'h00100000,
VAR5 = 6, VAR15=24,
VAR36=(1<<VAR5), VAR28=32, VAR33=VAR15;
input wire VAR3, VAR20, VAR38,
VAR16, VAR25;
input wire [(VAR33-1):0] VAR26;
ou... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/hrfp_1.0/hrfp_swap.v | 2,835 | module MODULE1
(input wire clk,
input wire [VAR6:0] VAR17, VAR9,
input wire VAR7,
output reg [VAR6:0] VAR1, VAR22,
output reg [2:0] VAR3,
output reg VAR19
);
reg [VAR4 + 1:0] VAR23;
reg [VAR4 + 1:0] VAR21;
reg [VAR4 + 1:0] VAR10;
always @* begin
VAR21 = VAR7 ? ~{2'b00, VAR13} : {2'b00, VAR13};
VAR10 = VAR7 ? {2'b00, VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221oi/sky130_fd_sc_ms__a221oi.pp.symbol.v | 1,409 | module MODULE1 (
input VAR6 ,
input VAR3 ,
input VAR8 ,
input VAR10 ,
input VAR5 ,
output VAR7 ,
input VAR1 ,
input VAR4,
input VAR9,
input VAR2
);
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | fpga/src/elink/hdl/emaxi.v | 15,312 | module MODULE1(
VAR28, VAR53, VAR36, VAR43, VAR76,
VAR17, VAR86, VAR29, VAR19, VAR49,
VAR65, VAR2, VAR22, VAR90,
VAR44, VAR3, VAR21, VAR14,
VAR42, VAR58, VAR51, VAR74, VAR81,
VAR73, VAR79, VAR46, VAR82, VAR55,
VAR83, VAR41, VAR45, VAR7,
VAR70, VAR30, VAR57, VAR26,
VAR37, VAR35, VAR56, VAR20,
VAR38, VAR50, VAR5, VAR85, ... | gpl-3.0 |
donnaware/AGC | rtl/de0/modules/virt_jtag.v | 7,002 | module MODULE1 (
VAR9,
VAR34,
VAR5,
VAR4,
VAR39,
VAR12,
VAR45,
VAR8,
VAR42,
VAR46,
VAR26,
VAR29,
VAR44);
input [7:0] VAR9;
input VAR34;
output [7:0] VAR5;
output VAR4;
output VAR39;
output VAR12;
output VAR45;
output VAR8;
output VAR42;
output VAR46;
output VAR26;
output VAR29;
output VAR44;
wire VAR17;
wire VAR11;
wir... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_io | cells/bi_t/gf180mcu_fd_io__bi_t.v | 4,053 | module MODULE1 (VAR7, VAR15, VAR13, VAR11, VAR9, VAR17, VAR6, VAR2, VAR4, VAR12, VAR8, VAR1, VAR14, VAR3, VAR5);
input VAR7;
input VAR15;
input VAR13;
input VAR11;
input VAR9;
input VAR17;
input VAR6;
input VAR2;
input VAR4;
inout VAR12;
output VAR8;
inout VAR1;
inout VAR14;
inout VAR3;
inout VAR5;
supply0 VAR10;
suppl... | apache-2.0 |
tau-tao/FPGAIPFilter | FPGA_CODE/JTAG_RW_PKT_PROC_MOORE/clckctrl/greybox/clckctrl.v | 2,926 | module MODULE2 (
VAR1,
VAR12,
VAR15);
input VAR1;
input VAR12;
output VAR15;
wire VAR4;
wire VAR5;
wire VAR13;
assign VAR4 = 1'b0;
assign VAR5 = 1'b1;
assign VAR13 = 1'b0;
wire \MODULE1|MODULE2|VAR10 ;
wire \VAR12~VAR14 ;
wire \VAR1~VAR14 ;
MODULE3 MODULE1(
.VAR15(\MODULE1|MODULE2|VAR10 ),
.VAR12(\VAR12~VAR14 ),
.VAR1(... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd/sky130_fd_sc_hs__tapvgnd.behavioral.v | 1,170 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
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