repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a311oi/sky130_fd_sc_lp__a311oi.pp.blackbox.v | 1,429 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR5 ,
VAR4 ,
VAR3 ,
VAR8 ,
VAR1,
VAR9,
VAR10 ,
VAR7
);
output VAR2 ;
input VAR6 ;
input VAR5 ;
input VAR4 ;
input VAR3 ;
input VAR8 ;
input VAR1;
input VAR9;
input VAR10 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sedfxbp/sky130_fd_sc_hdll__sedfxbp.functional.pp.v | 2,281 | module MODULE1 (
VAR20 ,
VAR6 ,
VAR5 ,
VAR2 ,
VAR17 ,
VAR13 ,
VAR1 ,
VAR22,
VAR21,
VAR4 ,
VAR18
);
output VAR20 ;
output VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR17 ;
input VAR13 ;
input VAR1 ;
input VAR22;
input VAR21;
input VAR4 ;
input VAR18 ;
wire VAR15 ;
wire VAR14;
wire VAR12 ;
VAR16 VAR7 (VAR14, VAR12, VAR13, V... | apache-2.0 |
cafe-alpha/wascafe | v13/wasca_10m08sc_20191205_abus_divide/wasca/synthesis/submodules/altera_avalon_st_clock_crosser.v | 4,885 | module MODULE1(
VAR19,
VAR4,
VAR16,
VAR6,
VAR23,
VAR12,
VAR8,
VAR14,
VAR25,
VAR13
);
parameter VAR11 = 1;
parameter VAR1 = 8;
parameter VAR18 = 2;
parameter VAR5 = 2;
parameter VAR30 = 1;
localparam VAR9 = VAR11 * VAR1;
input VAR19;
input VAR4;
output VAR16;
input VAR6;
input [VAR9-1:0] VAR23;
input VAR12;
input VAR8;
... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_4.behavioral.v | 1,429 | module MODULE1( VAR3, VAR2, VAR6 );
input VAR2, VAR3;
output VAR6;
VAR5 VAR4(.VAR3(VAR3),.VAR2(VAR2),.VAR6(VAR6));
VAR5 VAR1(.VAR3(VAR3),.VAR2(VAR2),.VAR6(VAR6)); | apache-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/SD_CMD.v | 2,631 | module MODULE1 (
address,
VAR8,
clk,
VAR10,
VAR6,
VAR7,
VAR11,
VAR5
)
;
inout VAR11;
output [ 31: 0] VAR5;
input [ 1: 0] address;
input VAR8;
input clk;
input VAR10;
input VAR6;
input [ 31: 0] VAR7;
wire VAR11;
wire VAR1;
reg VAR4;
wire VAR12;
reg VAR2;
wire VAR3;
reg [ 31: 0] VAR5;
assign VAR1 = 1;
assign VAR3 = ({1 {... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/buf/sky130_fd_sc_ms__buf_4.v | 1,993 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR1,
VAR4,
VAR3 ,
VAR6
);
output VAR8 ;
input VAR5 ;
input VAR1;
input VAR4;
input VAR3 ;
input VAR6 ;
VAR2 VAR7 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR8,
VAR5
);
output VAR8;
input VAR5;
supply1 VAR1;
supply0 VAR4;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22oi/sky130_fd_sc_hvl__a22oi.blackbox.v | 1,368 | module MODULE1 (
VAR8 ,
VAR5,
VAR4,
VAR7,
VAR3
);
output VAR8 ;
input VAR5;
input VAR4;
input VAR7;
input VAR3;
supply1 VAR6;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_4.v | 2,411 | module MODULE1 (
VAR8 ,
VAR5,
VAR1,
VAR10 ,
VAR9 ,
VAR4,
VAR3,
VAR7 ,
VAR2
);
output VAR8 ;
input VAR5;
input VAR1;
input VAR10 ;
input VAR9 ;
input VAR4;
input VAR3;
input VAR7 ;
input VAR2 ;
VAR11 VAR6 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR2(VA... | apache-2.0 |
pradeep9676/pradeep_9676 | sincos.v | 2,033 | module MODULE1(VAR8, VAR4,VAR12
);
input [15:0] VAR8;
output reg signed [15:0] VAR4;
output reg signed [15:0] VAR12;
reg [1:0] VAR9;
reg [13:0] VAR1;
reg [13:0] VAR2;
reg [6:0] address;
reg [15:0] VAR11;
reg [15:0] VAR7;
reg [33:0] VAR3;
reg [33:0] VAR5;
reg [18:0] VAR10[127:0];
reg [18:0] VAR6[127:0];
begin
begin
begi... | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd/gcd.cache/ip/2018.2/ddc26209722952ee/gcd_block_design_processing_system7_0_2_stub.v | 5,430 | module MODULE1(VAR47, VAR68, VAR16,
VAR49, VAR43, VAR63, VAR22,
VAR64, VAR27, VAR4, VAR28,
VAR45, VAR36, VAR15, VAR19, VAR56,
VAR51, VAR50, VAR31, VAR24,
VAR41, VAR14, VAR48, VAR3, VAR40,
VAR5, VAR33, VAR62, VAR18, VAR42,
VAR6, VAR32, VAR8, VAR13, VAR23,
VAR53, VAR66, VAR44, VAR55,
VAR20, VAR61, VAR25, VAR12, VAR34,
VA... | mit |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/soc_system_hps_0.v | 34,748 | module MODULE1 #(
parameter VAR109 = 3,
parameter VAR154 = 2
) (
output wire VAR6, input wire VAR63, input wire VAR79, input wire VAR119, input wire [7:0] VAR30, input wire [31:0] VAR10, input wire [3:0] VAR157, input wire [2:0] VAR73, input wire [1:0] VAR128, input wire [1:0] VAR125, input wire [3:0] VAR34, input wire... | epl-1.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/user_design/rtl/phy/phy_pd.v | 23,431 | module MODULE1 #
(
parameter VAR67 = 100,
parameter VAR87 = "VAR50", parameter VAR16 = 16 )
(
output [99:0] VAR7, input [4:0] VAR49,
output [4:0] VAR48,
output reg VAR45, output reg VAR39, output VAR79, input VAR28, input VAR84,
input VAR35, input [1:0] VAR43, input VAR31,
input VAR65,
input VAR33, input VAR59, input V... | lgpl-3.0 |
ShepardSiegel/ocpi | scripts/auguste/bram/mkBRAM100.v | 8,704 | module MODULE1(VAR34,
VAR26,
VAR23,
VAR28,
VAR53,
VAR31,
VAR33,
VAR46,
VAR6);
input VAR34;
input VAR26;
input [43 : 0] VAR23;
input VAR28;
output VAR53;
input VAR31;
output [31 : 0] VAR33;
output VAR46;
input VAR6;
wire [31 : 0] VAR33;
wire VAR53, VAR46;
wire [1 : 0] VAR52;
wire VAR24,
VAR4,
VAR40,
VAR16;
reg [2 : 0] V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4/sky130_fd_sc_lp__nand4_4.v | 2,253 | module MODULE1 (
VAR6 ,
VAR11 ,
VAR5 ,
VAR7 ,
VAR8 ,
VAR2,
VAR9,
VAR1 ,
VAR3
);
output VAR6 ;
input VAR11 ;
input VAR5 ;
input VAR7 ;
input VAR8 ;
input VAR2;
input VAR9;
input VAR1 ;
input VAR3 ;
VAR4 VAR10 (
.VAR6(VAR6),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR... | apache-2.0 |
freecores/verilog_fixed_point_math_library | qadd.v | 2,506 | module MODULE1 #(
parameter VAR4 = 15,
parameter VAR1 = 32
)
(
input [VAR1-1:0] VAR6,
input [VAR1-1:0] VAR5,
output [VAR1-1:0] VAR2
);
reg [VAR1-1:0] VAR3;
assign VAR2 = VAR3;
always @(VAR6,VAR5) begin
if(VAR6[VAR1-1] == VAR5[VAR1-1]) begin VAR3[VAR1-2:0] = VAR6[VAR1-2:0] + VAR5[VAR1-2:0]; VAR3[VAR1-1] = VAR6[VAR1-1]; ... | lgpl-2.1 |
r2t2sdr/r2t2 | fpga/modules/cores/axi_bram_writer_v1_0/src/axi_bram_writer.v | 3,184 | module MODULE1 #
(
parameter integer VAR9 = 32,
parameter integer VAR11 = 32,
parameter integer VAR30 = 32,
parameter integer VAR20 = 10
)
(
input wire VAR8,
input wire VAR17,
input wire [VAR11-1:0] VAR13, input wire VAR10, output wire VAR21, input wire [VAR9-1:0] VAR16, input wire [VAR9/8-1:0] VAR28, input wire VAR12,... | gpl-3.0 |
davidlee80/miaow | src/verilog/rtl/fetch/mask_gen.v | 2,852 | module MODULE1(in,out);
input [5:0]in;
output [63:0]out;
assign out = (in == 6'd0) ? 64'h0000000000000001:
(in == 6'd1) ? 64'h0000000000000003:
(in == 6'd2) ? 64'h0000000000000007:
(in == 6'd3) ? 64'h000000000000000f:
(in == 6'd4) ? 64'h000000000000001f:
(in == 6'd5) ? 64'h000000000000003f:
(in == 6'd6) ? 64'h000000000... | bsd-3-clause |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/bee3Top/src/c3dTop.v | 8,105 | module MODULE1 (
input VAR27,
input VAR61,
input VAR16,
output VAR83,
input [31:00] VAR17,
input [31:00] VAR37,
output [31:00] VAR72,
output [31:00] VAR104,
input VAR67,
output VAR44,
input VAR93,
output VAR26,
input VAR6,
output VAR2,
input VAR53,
output VAR68,
input [7:0] VAR59,
input [7:0] VAR63,
output [7:0] VAR101... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbus_common/rtl/bw_io_dtl_padx11.v | 16,619 | module MODULE1(VAR64 ,VAR66 ,VAR36 ,
VAR77 ,VAR9 ,VAR35 ,clk ,VAR51 ,VAR44 ,VAR26 ,VAR3 ,
VAR53 ,VAR76 ,VAR27 ,VAR71 ,VAR22 ,VAR55 ,VAR69 ,VAR10 ,VAR4 ,
VAR50 ,VAR31 ,VAR14 ,VAR18 ,VAR5 ,
VAR45 ,VAR12 ,VAR6 ,VAR37 ,
VAR43 ,VAR23 ,VAR63 ,VAR49 ,ref );
output [10:0] VAR66 ;
output [10:0] VAR55 ;
input [10:0] VAR64 ;
inpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtn/sky130_fd_sc_hdll__dlrtn.pp.blackbox.v | 1,393 | module MODULE1 (
VAR4 ,
VAR1,
VAR6 ,
VAR8 ,
VAR5 ,
VAR2 ,
VAR3 ,
VAR7
);
output VAR4 ;
input VAR1;
input VAR6 ;
input VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR3 ;
input VAR7 ;
endmodule | apache-2.0 |
cafe-alpha/wascafe | v11/fpga_firmware/wasca/wasca_bb.v | 2,783 | module MODULE1 (
VAR9,
VAR6,
VAR26,
VAR24,
VAR19,
VAR31,
VAR10,
VAR33,
VAR36,
VAR28,
VAR8,
VAR35,
VAR27,
VAR34,
VAR21,
VAR14,
VAR13,
VAR18,
VAR17,
VAR2,
VAR5,
VAR4,
VAR32,
VAR15,
VAR11,
VAR29,
VAR12,
VAR20,
VAR1,
VAR7,
VAR30,
VAR23,
VAR37,
VAR38,
VAR3,
VAR16,
VAR25,
VAR22);
input VAR9;
output VAR6;
output VAR26;
input ... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/ucore/timer.v | 4,340 | module MODULE1 (VAR2,VAR1,VAR5);
parameter VAR3 = VAR6;
parameter VAR4 = VAR4;
input VAR2;
input VAR1;
output reg VAR5;
reg [VAR4-1:0] counter;
always @(posedge VAR2 or posedge VAR1)
begin
if(VAR1) {VAR5,counter} <= 0;
end
else {VAR5,counter} <= counter+1;
end
endmodule | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9122_v6_00_a/hdl/verilog/axi_ad9122.v | 10,994 | module MODULE1 (
VAR82,
VAR79,
VAR54,
VAR24,
VAR128,
VAR60,
VAR66,
VAR118,
VAR120,
VAR88,
VAR131,
VAR92,
VAR26,
VAR35,
VAR4,
VAR5,
VAR85,
VAR39,
VAR99,
VAR84,
VAR28,
VAR43,
VAR129,
VAR71,
VAR41,
VAR38,
VAR69,
VAR56,
VAR105,
VAR130,
VAR45,
VAR124,
VAR97,
VAR67,
VAR127,
VAR37);
parameter VAR62 = 0;
parameter VAR13 = 0;
p... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32a/sky130_fd_sc_lp__o32a.blackbox.v | 1,384 | module MODULE1 (
VAR9 ,
VAR7,
VAR3,
VAR1,
VAR5,
VAR2
);
output VAR9 ;
input VAR7;
input VAR3;
input VAR1;
input VAR5;
input VAR2;
supply1 VAR4;
supply0 VAR6;
supply1 VAR8 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_mem.v | 3,313 | module MODULE1 (
VAR4,
VAR6,
VAR8,
VAR5,
VAR2,
VAR1,
VAR12);
parameter VAR10 = 16;
parameter VAR9 = 5;
localparam VAR3 = VAR10 - 1;
localparam VAR7 = VAR9 - 1;
input VAR4;
input VAR6;
input [VAR7:0] VAR8;
input [VAR3:0] VAR5;
input VAR2;
input [VAR7:0] VAR1;
output [VAR3:0] VAR12;
reg [VAR3:0] VAR11[0:((2**VAR9)-1)];
r... | mit |
cpulabs/mist1032sa | src/core/execute/divider/radix2_linediv.v | 1,365 | module MODULE1(
input wire [1:0] VAR13,
input wire [31:0] VAR11,
input wire [30:0] VAR5,
output wire [1:0] VAR2,
output wire [30:0] VAR1
);
wire VAR9, VAR7;
wire [30:0] VAR6, VAR3;
assign {VAR9, VAR6} = VAR4({VAR5, VAR13[1]}, VAR11);
assign {VAR7, VAR3} = VAR4({VAR6, VAR13[0]}, VAR11);
function [31:0] VAR4;
input [31:0... | bsd-2-clause |
eda-globetrotter/PicenoDecoders | final/src/hazard_detect.v | 37,696 | module MODULE1(VAR2, VAR3, VAR6,
VAR4, VAR9, VAR8, VAR7);
input [0:31] VAR2, VAR3, VAR6;
output VAR4, VAR9, VAR8, VAR7;
reg VAR4, VAR9, VAR8, VAR7;
parameter VAR5 = 1'b0;
parameter VAR1 = 1'b1;
always @ (VAR2 or VAR6)
begin
if (VAR2[2] == 1'b1) begin
if (VAR6[2] == 1'b1) begin
VAR4 <= (VAR2[11:15]==VAR6[6:10])? VAR1 : ... | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/snickerdoodle_try/snickerdoodle_try.cache/ip/2017.4.1/3096c1ea67ba29c5/design_1_processing_system7_0_1_stub.v | 5,081 | module MODULE1(VAR3, VAR63, VAR10, VAR40,
VAR20, VAR23, VAR31, VAR38, VAR49,
VAR56, VAR14, VAR16, VAR22, VAR33,
VAR17, VAR15, VAR53, VAR35,
VAR25, VAR51, VAR42, VAR59, VAR24,
VAR9, VAR18, VAR37, VAR29, VAR12,
VAR46, VAR2, VAR57, VAR27, VAR13,
VAR32, VAR60, VAR26, VAR36, VAR62,
VAR50, VAR64, VAR43, VAR8, VAR5, VAR30,
VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22ai/sky130_fd_sc_hd__o22ai.blackbox.v | 1,364 | module MODULE1 (
VAR6 ,
VAR1,
VAR5,
VAR7,
VAR3
);
output VAR6 ;
input VAR1;
input VAR5;
input VAR7;
input VAR3;
supply1 VAR8;
supply0 VAR9;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
aquaxis/synverll | lib/llvm_memcpy/aq_fifo.v | 8,171 | module MODULE2
parameter VAR25 = 10,
parameter VAR1 = 64
)
(
input VAR24,
input VAR55,
input VAR8,
input [VAR1 -1:0] VAR51,
input VAR60,
output VAR26,
output VAR50,
input [VAR25 -1:0] VAR56,
input VAR64,
input VAR41,
output [VAR1 -1:0] VAR15,
output VAR57,
output VAR9,
input [VAR25 -1:0] VAR38
);
wire VAR23, VAR48;
reg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_isobufsrc/sky130_fd_sc_hd__lpflow_isobufsrc_4.v | 2,319 | module MODULE1 (
VAR1 ,
VAR7,
VAR4 ,
VAR9 ,
VAR5 ,
VAR2 ,
VAR8
);
output VAR1 ;
input VAR7;
input VAR4 ;
input VAR9 ;
input VAR5 ;
input VAR2 ;
input VAR8 ;
VAR6 VAR3 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR1 ,
VAR7,
VAR4
);
output VAR... | apache-2.0 |
ptracton/pmodacl2 | behavioral/verilog-arbiter/arbiter.v | 2,797 | module MODULE1
VAR3 = 6)
(input clk,
input rst,
input [VAR3-1:0] request,
output reg [VAR3-1:0] VAR4,
output reg [VAR5(VAR3)-1:0] select,
output reg VAR1
);
localparam VAR7 = 2*VAR3;
function [VAR5(VAR3)-1:0] VAR2;
input [VAR3-1:0] in;
integer VAR6;
begin
VAR2 = 0;
for (VAR6 = VAR3-1; VAR6 >= 0; VAR6=VAR6-1) begin
if (... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.v | 2,042 | module MODULE2 (
VAR8 ,
VAR1 ,
VAR4,
VAR5,
VAR7 ,
VAR6
);
output VAR8 ;
input VAR1 ;
input VAR4;
input VAR5;
input VAR7 ;
input VAR6 ;
VAR3 VAR2 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR8,
VAR1
);
output VAR8;
input VAR1;
supply1 VAR4;
supply0 VAR5;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfrtp/sky130_fd_sc_hdll__dfrtp.behavioral.pp.v | 2,261 | module MODULE1 (
VAR20 ,
VAR3 ,
VAR19 ,
VAR17,
VAR7 ,
VAR15 ,
VAR2 ,
VAR13
);
output VAR20 ;
input VAR3 ;
input VAR19 ;
input VAR17;
input VAR7 ;
input VAR15 ;
input VAR2 ;
input VAR13 ;
wire VAR8 ;
wire VAR4 ;
reg VAR14 ;
wire VAR11 ;
wire VAR18;
wire VAR9 ;
wire VAR21 ;
wire VAR16 ;
wire VAR1 ;
not VAR10 (VAR4 , VAR1... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_1.functional.v | 1,728 | module MODULE1( VAR16, VAR25, VAR10, VAR9, VAR2, VAR18, VAR26 );
input VAR9, VAR10, VAR2, VAR16, VAR25, VAR26;
output VAR18;
not VAR14( VAR3, VAR2 );
wire VAR6;
not VAR1( VAR6, VAR10 );
wire VAR23;
not VAR21( VAR23, VAR16 );
wire VAR19;
and VAR4( VAR19, VAR6, VAR23 );
wire VAR15;
not VAR20( VAR15, VAR25 );
wire VAR22;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2o/sky130_fd_sc_hs__a2bb2o.symbol.v | 1,415 | module MODULE1 (
input VAR3,
input VAR6,
input VAR4 ,
input VAR5 ,
output VAR2
);
supply1 VAR1;
supply0 VAR7;
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/thirtysix_six_comp.v | 2,500 | module MODULE1 (VAR12,sum);
input [31:0] VAR12;
output [31:0] sum;
wire [31:0] sum;
wire [5:0] VAR25;
wire [5:0] VAR24;
wire [5:0] VAR19;
wire [2:0] VAR15,VAR4,VAR20,VAR18,VAR22,VAR16;
wire [2:0] VAR9,VAR2,VAR8;
VAR14 VAR26 (.VAR12(VAR12[5:0]),.sum(VAR15));
VAR14 VAR3 (.VAR12(VAR12[11:6]),.sum(VAR4));
VAR14 VAR23 (.VAR... | mit |
petrmikheev/miksys | verilog/RAM512x16_1R1W.v | 9,147 | module MODULE1 (
VAR58,
VAR11,
VAR57,
VAR26,
VAR52,
VAR10);
input VAR58;
input [15:0] VAR11;
input [8:0] VAR57;
input [8:0] VAR26;
input VAR52;
output [15:0] VAR10;
tri1 VAR58;
tri0 VAR52;
wire [15:0] VAR15;
wire [15:0] VAR10 = VAR15[15:0];
VAR24 VAR18 (
.VAR45 (VAR26),
.VAR7 (VAR58),
.VAR23 (VAR11),
.VAR17 (VAR52),
.V... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/example_design/rtl/traffic_gen/tg_prbs_gen.v | 6,447 | module MODULE1 #
(
parameter VAR18 = 64, parameter VAR3 = 32'h00000000,
parameter VAR2 = "VAR1",
parameter VAR14 = 0,
parameter [VAR18-1:0] VAR25= 32'h80200003
)
(
input VAR21,
input VAR24,
input rst,
input [VAR18-1:0] VAR6,
output VAR15,
output [VAR18-1:0] VAR7, output reg [3:0] VAR5,
output [31:0] VAR12
);
wire VAR9;... | lgpl-3.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | Driver_bus_bidireccional.v | 1,753 | module MODULE1(
input clk,
input VAR4, input VAR2,
input VAR5,
input [7:0]VAR10, output reg [7:0]VAR8, input [7:0]VAR9, inout tri [7:0]VAR6 );
reg [7:0]VAR7;
reg [7:0]VAR3;
assign VAR6 = (VAR4)? VAR7 : 8'VAR1;
always@(posedge clk) begin
VAR8 <= VAR3;
end
always @(*)
begin
case({VAR4,VAR2,VAR5})
3'b000: begin VAR7 = 8'd... | mit |
tommythorn/yari | DE2-70/rtl/dummy_master.v | 1,895 | module MODULE1(
input wire VAR11 ,input wire reset
,input VAR16
,output reg [1:0] VAR7 = 1
,output reg [29:0] VAR10 = 0
,output reg VAR3 = 0
,output reg VAR18 = 0
,output reg [31:0] VAR9 = 0
,output reg [3:0] VAR8 = 0
,input [31:0] VAR2
,input [1:0] VAR1
,output reg [31:0] VAR6 = 0
);
reg [18:0] VAR5 = 0, VAR17 = 0, VA... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0_0/bd_0/ip/ip_3/synth/bd_c3fe_slot_0_w_0.v | 4,558 | module MODULE1 (
VAR45,
VAR8,
dout
);
input wire [0 : 0] VAR45;
input wire [0 : 0] VAR8;
output wire [1 : 0] dout;
VAR6 #(
.VAR61(1),
.VAR32(1),
.VAR40(1),
.VAR51(1),
.VAR19(1),
.VAR29(1),
.VAR33(1),
.VAR37(1),
.VAR38(1),
.VAR27(1),
.VAR25(1),
.VAR44(1),
.VAR1(1),
.VAR66(1),
.VAR4(1),
.VAR52(1),
.VAR14(1),
.VAR64(1),
.... | mit |
lsnow/mips32 | MIPS32.v | 9,222 | module MODULE1(
VAR10, VAR9, VAR110,
rst, clk, VAR24
);
input rst;
input clk;
input [4:0] VAR24;
output reg [31:0] VAR10, VAR9, VAR110;
reg [31:0] VAR112;
reg [31:0] VAR114;
wire [31:0] VAR134, VAR43;
wire [31:0] VAR14;
wire [31:0] VAR89;
wire [31:0] VAR99;
wire [31:0] VAR107;
wire [4:0] VAR52, VAR74, rd;
wire VAR44, V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ha/sky130_fd_sc_ls__ha.functional.pp.v | 2,194 | module MODULE1 (
VAR12,
VAR19 ,
VAR6 ,
VAR17 ,
VAR7,
VAR11,
VAR13 ,
VAR18
);
output VAR12;
output VAR19 ;
input VAR6 ;
input VAR17 ;
input VAR7;
input VAR11;
input VAR13 ;
input VAR18 ;
wire VAR15 ;
wire VAR10;
wire VAR2 ;
wire VAR9 ;
and VAR1 (VAR15 , VAR6, VAR17 );
VAR3 VAR5 (VAR10, VAR15, VAR7, VAR11);
buf VAR8 (VAR... | apache-2.0 |
YoelRP/PROYECTO | bin/example/example_code2.v | 2,024 | module MODULE1 (
VAR8 , reset , VAR15 , VAR12 , VAR5 , VAR10
);
input VAR8,reset,VAR15,VAR12;
output VAR5,VAR10;
wire VAR8,reset,VAR15,VAR12;
reg VAR5,VAR10;
parameter VAR4 = 3 ;
parameter VAR7 = 3'b001,VAR6 = 3'b010,VAR3 = 3'b100 ;
reg [VAR4-1:0] state ;reg [VAR4-1:0] VAR9 ;always @ (posedge VAR8)
begin : VAR2
if (res... | gpl-3.0 |
emeb/iceRadio | FPGA/rxadc_2/verilog/src/ddc_2.v | 6,903 | module MODULE1 #(
parameter VAR26 = 10,
VAR33 = 26,
VAR13 = 16
)
(
input clk, reset,
input [VAR26-1:0] in,
input [VAR33-1:0] VAR16,
input VAR20,
output reg valid,
output reg signed [VAR13-1:0] VAR21, VAR42
);
reg [7:0] VAR41;
reg VAR38;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
VAR41 <= 8'b0;
VAR38 <= 1'b0;
e... | mit |
rurume/openrisc_vision_hardware | ISE/or1200_dc_tag.v | 5,246 | module MODULE1(
clk, rst,
VAR12, VAR9, VAR6,
addr, en, VAR4, VAR13, VAR8, VAR1
);
parameter VAR15 = VAR10;
parameter VAR11 = VAR19;
input clk;
input rst;
input [VAR11-1:0] addr;
input en;
input VAR4;
input [VAR15-1:0] VAR13;
output VAR8;
output [VAR15-2:0] VAR1;
input VAR12;
input [VAR16 - 1:0] VAR6;
output VAR9;
assig... | gpl-2.0 |
freecores/tiny_tate_bilinear_pairing | group_size_is_911_bits/rtl/pairing.v | 1,522 | module MODULE1(clk, reset, sel, addr, VAR4, VAR10, ready, VAR6, VAR9, VAR7);
input clk;
input reset; input sel;
input [5:0] addr;
input VAR4;
input VAR10; input ready; input VAR6;
output VAR9;
output VAR7;
reg [VAR5:0] VAR1, VAR3;
wire [VAR5:0] out;
assign VAR9 = VAR3[0];
VAR8
VAR2 (clk, reset, sel, addr, VAR4, VAR1, o... | apache-2.0 |
olgirard/openmsp430 | core/synthesis/altera/src/megawizard/stratix2_dmem.v | 7,464 | module MODULE1 (
address,
VAR38,
VAR47,
VAR28,
VAR31,
VAR11,
VAR25);
input [9:0] address;
input [1:0] VAR38;
input VAR47;
input VAR28;
input [15:0] VAR31;
input VAR11;
output [15:0] VAR25;
tri1 [1:0] VAR38;
tri1 VAR47;
tri1 VAR28;
wire [15:0] VAR26;
wire [15:0] VAR25 = VAR26[15:0];
VAR32 VAR6 (
.VAR33 (VAR47),
.VAR12 (... | bsd-3-clause |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_addr_decoder.v | 11,631 | module MODULE1 #
(
parameter VAR4 = "none",
parameter integer VAR43 = 2, parameter integer VAR38 = 1, parameter integer VAR17 = 1, parameter integer VAR35 = 32, parameter integer VAR10 = 0, parameter integer VAR18 = 1, parameter integer VAR49 = 0, parameter [VAR43*VAR17*64-1:0] VAR3 = {VAR43*VAR17*64{1'b1}},
parameter ... | gpl-3.0 |
qiuzou/nysa_saya | rtl/command/sata_command_layer.v | 20,807 | module MODULE1 (
input rst, input clk,
input VAR84,
input VAR146,
output VAR55,
output VAR109,
output reg VAR92,
input VAR15,
input [15:0] VAR74,
input VAR96,
input VAR136,
input VAR64,
output VAR123,
input VAR10,
input VAR130,
output reg VAR79,
input [7:0] VAR3,
input [15:0] VAR122,
input [47:0] VAR95,
input VAR29,
in... | mit |
drichmond/riffa | fpga/altera/de2i/riffa_wrapper_de2i.v | 37,115 | module MODULE1
parameter VAR331 = 64,
parameter VAR245 = 256,
parameter VAR67 = 5,
parameter VAR194 = "VAR314")
( input [VAR331-1:0] VAR5,
input [0:0] VAR323,
input [0:0] VAR297,
input [0:0] VAR188,
output VAR195,
input [0:0] VAR139,
output [VAR331-1:0] VAR296,
output [0:0] VAR78,
input VAR54,
output [0:0] VAR291,
outp... | bsd-3-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/address_generator.v | 5,317 | module MODULE1 (
input clk,
input VAR29,
input VAR28,
output reg VAR23,
input [31:VAR9] VAR19,
input [VAR24-1:0] VAR22,
output reg [VAR10-1:0] VAR12,
input [VAR10-1:0] VAR20,
input VAR26,
input VAR1,
input enable,
input VAR21,
output reg VAR8,
input VAR15,
output reg VAR13,
output [31:0] addr,
output [ 7:0] VAR25,
outp... | gpl-3.0 |
fbalakirev/red-pitaya-notes | cores/axis_bram_writer_v1_0/axis_bram_writer.v | 1,735 | module MODULE1 #
(
parameter integer VAR7 = 32,
parameter integer VAR2 = 32,
parameter integer VAR9 = 10
)
(
input wire VAR5,
input wire VAR10,
output wire [VAR9-1:0] VAR6,
output wire VAR3,
input wire [VAR7-1:0] VAR18,
input wire VAR14,
output wire VAR13,
output wire VAR8,
output wire [VAR9-1:0] VAR15,
output wire [VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2/sky130_fd_sc_ms__nor2.behavioral.v | 1,350 | module MODULE1 (
VAR6,
VAR7,
VAR2
);
output VAR6;
input VAR7;
input VAR2;
supply1 VAR10;
supply0 VAR9;
supply1 VAR8 ;
supply0 VAR5 ;
wire VAR3;
nor VAR4 (VAR3, VAR7, VAR2 );
buf VAR1 (VAR6 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2/sky130_fd_sc_hs__or2.symbol.v | 1,218 | module MODULE1 (
input VAR2,
input VAR3,
output VAR1
);
supply1 VAR4;
supply0 VAR5;
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/8-way/src/ip_pcie/source/PCIeGen2x8If128_pipe_drp.v | 38,891 | module MODULE1 #
(
parameter VAR89 = "VAR81", parameter VAR137 = "3.0", parameter VAR52 = "VAR11", parameter VAR164 = "VAR126", parameter VAR25 = "VAR114", parameter VAR172 = "VAR11", parameter VAR80 = "VAR114", parameter VAR93 = 0, parameter VAR135 = 0, parameter VAR101 = 2'd1, parameter VAR115 = 5'd21
)
(
input VAR85... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/Tiger4NSC/src/d_parallel_m_lfs_XOR.v | 3,029 | module MODULE1
(
input wire [VAR9-1:0] VAR5,
input wire [VAR1-1:0] VAR3,
output wire [VAR1-1:0] VAR10
);
wire [VAR1*(VAR9+1)-1:0] VAR7;
genvar VAR4;
generate
for (VAR4=0; VAR4<VAR9; VAR4=VAR4+1)
begin: VAR6
VAR8 VAR2(
.VAR5 (VAR5[VAR4]),
.VAR3(VAR7[VAR1*(VAR4+2)-1:VAR1*(VAR4+1)]),
.VAR10(VAR7[VAR1*(VAR4+1)-1:VAR1*(VAR4... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxtn/sky130_fd_sc_hs__dlxtn_2.v | 2,069 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR6,
VAR4 ,
VAR7
);
output VAR5 ;
input VAR2 ;
input VAR6;
input VAR4 ;
input VAR7 ;
VAR1 VAR3 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR5 ,
VAR2 ,
VAR6
);
output VAR5 ;
input VAR2 ;
input VAR6;
supply1 VAR4;
supply0 VAR7;
VAR1 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111oi/sky130_fd_sc_ls__a2111oi_1.v | 2,461 | module MODULE2 (
VAR3 ,
VAR1 ,
VAR9 ,
VAR7 ,
VAR4 ,
VAR12 ,
VAR8,
VAR11,
VAR5 ,
VAR10
);
output VAR3 ;
input VAR1 ;
input VAR9 ;
input VAR7 ;
input VAR4 ;
input VAR12 ;
input VAR8;
input VAR11;
input VAR5 ;
input VAR10 ;
VAR6 VAR2 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR8(V... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/verilog/convolve_kernel_fbkb.v | 1,881 | module MODULE1
VAR26 = 1,
VAR7 = 14,
VAR22 = 32,
VAR19 = 32,
VAR17 = 32
)(
input wire clk,
input wire reset,
input wire VAR20,
input wire [VAR22-1:0] VAR21,
input wire [VAR19-1:0] VAR25,
output wire [VAR17-1:0] dout
);
wire VAR4;
wire VAR10;
wire VAR15;
wire [31:0] VAR5;
wire VAR2;
wire [31:0] VAR13;
wire VAR16;
wire [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22oi/sky130_fd_sc_hdll__a22oi_4.v | 2,368 | module MODULE2 (
VAR6 ,
VAR8 ,
VAR2 ,
VAR4 ,
VAR7 ,
VAR1,
VAR9,
VAR3 ,
VAR11
);
output VAR6 ;
input VAR8 ;
input VAR2 ;
input VAR4 ;
input VAR7 ;
input VAR1;
input VAR9;
input VAR3 ;
input VAR11 ;
VAR5 VAR10 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR11... | apache-2.0 |
HSID/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/old/RCB_FRL_fifo_MSG.v | 3,204 | module MODULE1(VAR21, VAR1, VAR22, VAR17, VAR2, VAR31, VAR16, VAR30, VAR7, VAR26, VAR3);
output VAR21, VAR1, VAR17, VAR2;
output [39:0] VAR22;
input [39:0] VAR31;
input VAR16, VAR30, VAR7, VAR26, VAR3;
wire [63:40] VAR28;
VAR9 #(
.VAR19(9'h080), .VAR27(9'h080), .VAR8(1), .VAR23("VAR29"), .VAR5("VAR29"), .VAR12("VAR29")... | bsd-2-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_compare_and_swap.v | 1,206 | module MODULE1 #(parameter VAR10(VAR3)
, parameter VAR7 = VAR3-1
, parameter VAR9 = 0
, parameter VAR11=0)
(input [1:0] [VAR3-1:0] VAR6
, input VAR5
, output logic [1:0] [VAR3-1:0] VAR8
, output VAR2
);
wire VAR4 = VAR6[0][VAR7:VAR9] > VAR6[1][VAR7:VAR9];
if (VAR11)
begin
wire VAR1 = (VAR6[0][VAR7:VAR9] == VAR6[1][VAR7... | bsd-3-clause |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad7091r_v1_00_a/hdl/verilog/axi_ad7091r_dev_if.v | 12,752 | module MODULE1
(
input VAR37, input VAR29, input VAR30,
output [15:0] VAR17, output reg VAR8, output reg VAR32,
input VAR40,
output VAR19,
output VAR38,
output VAR21
);
reg [ 7:0] VAR27; reg [ 7:0] VAR24; reg [ 7:0] VAR9; reg [ 7:0] VAR7;
reg [ 6:0] VAR3;
reg [ 6:0] VAR15;
reg [ 6:0] VAR2;
reg [ 4:0] VAR26;
reg VAR36;
... | mit |
SiLab-Bonn/basil | basil/firmware/modules/fei4_rx/decode_8b10b.v | 6,087 | module MODULE1 (VAR31, VAR10, VAR59, VAR32, VAR67, VAR47);
input wire [9:0] VAR31;
input wire VAR10;
output wire [8:0] VAR59;
output wire VAR32;
output wire VAR67;
output wire VAR47;
wire VAR18 = VAR31[0];
wire VAR46 = VAR31[1];
wire VAR2 = VAR31[2];
wire VAR28 = VAR31[3];
wire VAR36 = VAR31[4];
wire VAR41 = VAR31[5];
... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.blackbox.v | 1,441 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR6 ,
VAR7 ,
VAR2,
VAR5 ,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR6 ;
input VAR7 ;
input VAR2;
input VAR5 ;
input VAR3 ;
endmodule | apache-2.0 |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_texmem.v | 10,718 | module MODULE1 #(
parameter VAR81 = 13,
parameter VAR137 = 5,
parameter VAR20 = 4,
parameter VAR4 = 4,
parameter VAR88 = 26
) (
input VAR140,
input VAR3,
output [VAR88-1:0] VAR151,
output VAR149,
input VAR133,
input [63:0] VAR157,
input VAR72,
output VAR24,
input VAR66,
output VAR161,
input [VAR88-1-1:0] VAR113,
input ... | lgpl-3.0 |
linuxbest/lzs | encode/rtl/verilog/encode_ctl.v | 9,798 | module MODULE1(
VAR8, VAR38, VAR30, VAR21,
VAR1,
clk, rst, VAR39, VAR41, VAR18, VAR32,
VAR19, VAR4, VAR28, VAR16, VAR23, VAR7, VAR26,
VAR27
);
parameter VAR31 = 20;
input clk, rst;
input VAR39;
input VAR41;
input [7:0] VAR18, VAR32, VAR19, VAR4;
input [VAR31-1:0] VAR28, VAR16;
input [7:0] VAR23, VAR7, VAR26;
output [10... | gpl-2.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi_one_db_load/solution1/impl/ip/hdl/verilog/contact_discovery.v | 44,066 | module MODULE1 (
VAR164,
VAR81,
VAR133,
VAR54,
VAR143,
VAR188,
VAR6,
VAR115,
VAR42,
VAR22,
VAR8,
VAR34,
VAR10,
VAR2,
VAR163,
VAR170,
VAR117,
VAR154,
VAR63,
interrupt
);
parameter VAR64 = 17'd1;
parameter VAR35 = 17'd2;
parameter VAR87 = 17'd4;
parameter VAR152 = 17'd8;
parameter VAR16 = 17'd16;
parameter VAR40 = 17'd32... | gpl-3.0 |
jordens/redpid | verilog/red_pitaya_dfilt1.v | 4,043 | module MODULE1
(
input VAR22 , input VAR18 , input [ 14-1: 0] VAR1 , output [ 14-1: 0] VAR7 ,
input [ 18-1: 0] VAR11 , input [ 25-1: 0] VAR21 , input [ 25-1: 0] VAR8 , input [ 25-1: 0] VAR24 );
reg [ 18-1: 0] VAR16 ;
reg [ 25-1: 0] VAR19 ;
reg [ 25-1: 0] VAR6 ;
reg [ 25-1: 0] VAR17 ;
always @(posedge VAR22) begin
VAR16... | gpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab02/lab02/Code/GPIO.v | 1,701 | module MODULE1(input clk,
input rst,
input VAR4,
input VAR16,
input [31:0] VAR14,
output reg[1:0] VAR5,
output [15:0] VAR11,
output wire VAR1,
output wire VAR18,
output wire VAR15,
output wire VAR7,
output reg[13:0] VAR3
);
reg [15:0]VAR6;
assign VAR11 = VAR6;
always @(negedge clk or posedge rst) begin
if(rst)begin VAR... | gpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_cx4/cx4_datrom.v | 6,464 | module MODULE1 (
address,
VAR9,
VAR21);
input [9:0] address;
input VAR9;
output [23:0] VAR21;
tri1 VAR9;
wire [23:0] VAR23;
wire [23:0] VAR21 = VAR23[23:0];
VAR25 VAR28 (
.VAR19 (address),
.VAR3 (VAR9),
.VAR44 (VAR23),
.VAR51 (1'b0),
.VAR43 (1'b0),
.VAR14 (1'b1),
.VAR48 (1'b0),
.VAR31 (1'b0),
.VAR16 (1'b1),
.VAR1 (1'b1... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/decoder_3_8.v | 1,211 | module MODULE1
(input [2:0] sel,
output reg [7:0] VAR1);
always @(sel or VAR1)
begin
case (sel)
3'b000 : VAR1 = 8'b00000001;
3'b001 : VAR1 = 8'b00000010;
3'b010 : VAR1 = 8'b00000100;
3'b011 : VAR1 = 8'b00001000;
3'b100 : VAR1 = 8'b00010000;
3'b101 : VAR1 = 8'b00100000;
3'b110 : VAR1 = 8'b01000000;
default : VAR1 = 8'b1... | gpl-2.0 |
azonenberg/antikernel-ipcores | noc/rpcv3/RPCv3RouterArbiter.v | 9,176 | module MODULE1 #(
parameter VAR15 = 4,
parameter VAR5 = 1'b0,
parameter VAR2 = 0,
parameter VAR20 = 4'h0,
parameter VAR3 = 4'h0
) (
input wire clk,
input wire[VAR15-1 : 0] VAR1,
input wire[16*VAR15 - 1 : 0] VAR11,
output reg VAR10 = 0,
output reg[8:0] VAR21 = 0,
input wire VAR7
);
reg[8:0] VAR17 = 0;
wire[8:0] VAR8 = V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3.behavioral.pp.v | 1,832 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR5,
VAR1,
VAR7 ,
VAR11
);
output VAR6 ;
input VAR9 ;
input VAR5;
input VAR1;
input VAR7 ;
input VAR11 ;
wire VAR4 ;
wire VAR8;
buf VAR2 (VAR4 , VAR9 );
VAR10 VAR12 (VAR8, VAR4, VAR5, VAR1);
buf VAR3 (VAR6 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.symbol.v | 1,340 | module MODULE1 (
input VAR1 ,
output VAR2,
input VAR4 ,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21a/sky130_fd_sc_lp__o21a.symbol.v | 1,341 | module MODULE1 (
input VAR3,
input VAR8,
input VAR6,
output VAR1
);
supply1 VAR5;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_pipe_clock.v | 21,205 | module MODULE1 #
(
parameter VAR113 = "VAR118", parameter VAR10 = "VAR118", parameter VAR13 = 1, parameter VAR102 = 3, parameter VAR6 = 0, parameter VAR50 = 2, parameter VAR1 = 2, parameter VAR27 = 1, parameter VAR142 = 0
)
(
input VAR61,
input VAR43,
input [VAR13-1:0] VAR35,
input VAR19,
input [VAR13-1:0] VAR143,
inpu... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_adder_one_hot.v | 1,400 | module MODULE1 #(parameter VAR8(VAR14), parameter VAR7=VAR14)
(input [VAR14-1:0] VAR4
, input [VAR14-1:0] VAR9
, output [VAR7-1:0] VAR3
);
genvar VAR1,VAR2;
VAR5 assert (VAR7 >= VAR14)
else begin ("%VAR11: VAR12 VAR7 < VAR14");
end
for (VAR1=0; VAR1 < VAR7; VAR1++) begin: VAR13
wire [VAR14-1:0] VAR15;
for (VAR2=0; VAR2... | bsd-3-clause |
zeldin/logic16_bitstream | src/clock_generators.v | 3,099 | module MODULE1(
input VAR20,
input VAR7,
input VAR27,
input VAR66,
output VAR8,
output VAR60,
output VAR58
);
localparam VAR59 = 1000.0/48.0;
wire VAR37, VAR24;
wire VAR64, VAR39;
wire VAR49, VAR2, VAR29;
wire VAR13, VAR6, VAR11, VAR42;
wire VAR35;
VAR32 #( .VAR52(4), .VAR68(1),
.VAR62(VAR59), .VAR48("VAR65"),
.VAR15("... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mm_interconnect_0_avalon_st_adapter_002.v | 6,149 | module MODULE1 #(
parameter VAR15 = 10,
parameter VAR4 = 0,
parameter VAR14 = 10,
parameter VAR21 = 0,
parameter VAR9 = 0,
parameter VAR1 = 0,
parameter VAR20 = 1,
parameter VAR6 = 1,
parameter VAR2 = 0,
parameter VAR16 = 10,
parameter VAR23 = 0,
parameter VAR22 = 1,
parameter VAR8 = 0,
parameter VAR7 = 1,
parameter VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfstp/sky130_fd_sc_hvl__dfstp.behavioral.v | 2,014 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR6 ,
VAR15
);
output VAR7 ;
input VAR9 ;
input VAR6 ;
input VAR15;
supply1 VAR12;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR16 ;
wire VAR18 ;
wire VAR14 ;
reg VAR13 ;
wire VAR2 ;
wire VAR5 ;
wire VAR19;
wire VAR11 ;
not VAR17 (VAR14 , VAR19 );
VAR3 VAR10 (VAR18 , VAR5, VAR11, VAR14, VAR13... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp.functional.v | 1,783 | module MODULE1 (
VAR1,
VAR2 ,
VAR4,
VAR7
);
output VAR1;
input VAR2 ;
input VAR4;
input VAR7 ;
wire VAR6 ;
wire VAR11 ;
wire VAR8 ;
wire VAR13;
not VAR3 (VAR11 , VAR6 );
not VAR5 (VAR8 , VAR7 );
nor VAR14 (VAR13, VAR4, VAR2 );
VAR12 VAR10 (VAR6 , VAR13, VAR8 );
and VAR9 (VAR1 , VAR11, VAR7 );
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/Multipliers/26bit/FrancisKOA/Sgf_Multiplication.v | 6,457 | module MODULE1
(
input wire clk,
input wire [VAR13-1:0] VAR26,
input wire [VAR13-1:0] VAR29,
output wire [2*VAR13-1:0] VAR20
);
wire [VAR13/2+1:0] VAR15;
wire [VAR13/2+1:0] VAR19;
wire [2*(VAR13/2)-1:0] VAR16;
wire [2*(VAR13/2+1)-1:0] VAR7;
wire [2*(VAR13/2+2)-1:0] VAR8;
wire [2*(VAR13/2+2)-1:0] VAR21;
wire [2*(VAR13/2... | gpl-3.0 |
archlabo/Frix | common/pc_bus_to_vga.v | 5,079 | module MODULE1
(
input wire VAR21,
input wire rst,
input wire [31:0] VAR5,
input wire [3:0] VAR26,
input wire VAR22,
output wire [31:0] VAR32,
input wire VAR23,
input wire [31:0] VAR45,
output wire VAR33,
output wire VAR40,
input wire [2:0] VAR35,
output wire [16:0] VAR15,
output wire VAR13,
input wire [7:0] VAR18,
out... | bsd-2-clause |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_040.v | 1,553 | module MODULE1 (
VAR5,
VAR1
);
input [31:0] VAR5;
output [31:0]
VAR1;
wire [31:0]
VAR15,
VAR2,
VAR9,
VAR12,
VAR13,
VAR14,
VAR6,
VAR3,
VAR11,
VAR7;
assign VAR15 = VAR5;
assign VAR11 = VAR3 - VAR13;
assign VAR3 = VAR6 << 4;
assign VAR14 = VAR9 << 8;
assign VAR7 = VAR11 << 1;
assign VAR2 = VAR15 << 2;
assign VAR9 = VAR15 ... | mit |
skarpenko/ultiparc | rtl/src/cpu/uparc_coproc0.v | 11,385 | module MODULE1(
clk,
VAR76,
VAR30,
VAR25,
VAR57,
VAR66,
VAR38,
VAR6,
VAR21,
VAR47,
VAR4,
VAR58,
VAR41,
VAR3,
VAR24,
VAR50,
VAR35,
VAR28,
VAR65,
VAR13,
VAR33,
VAR54,
VAR56,
VAR23,
VAR63
);
localparam [VAR49-1:0] VAR48 = 32'h00000000;
localparam [VAR42-1:0] VAR55 = 5'h08;
localparam [VAR42-1:0] VAR34 = 5'h09;
localparam ... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fahcin/sky130_fd_sc_ms__fahcin.symbol.v | 1,330 | module MODULE1 (
input VAR5 ,
input VAR8 ,
input VAR6 ,
output VAR9,
output VAR7
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_1.behavioral.v | 3,096 | module MODULE1( VAR5, VAR1, VAR2, VAR7, VAR3 );
input VAR1, VAR7, VAR2;
output VAR3, VAR5;
VAR8 VAR4(.VAR5(VAR5),.VAR1(VAR1),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3));
VAR8 VAR6(.VAR5(VAR5),.VAR1(VAR1),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3)); | apache-2.0 |
hpcn-uam/hardware_packet_train | NetFPGA10G/Verilog/osnt_10g_interface.v | 14,461 | module MODULE1
parameter VAR76 = 0,
parameter VAR139=64,
parameter VAR33=64,
parameter VAR94=0,
parameter VAR26 = {5'b01000, 64'h0583000000000000},
parameter VAR104 = 7'b0,
parameter VAR116=128,
parameter VAR140=128,
parameter VAR50 = 0,
parameter VAR120 = 0,
parameter VAR67 = 0,
parameter VAR9 = 64,
parameter VAR90 = ... | gpl-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/verilog/axi_vdma_v6_2_axis_dwidth_converter_v1_0_axis_dwidth_converter.v | 16,791 | module MODULE1 #
(
parameter VAR20 = "VAR21",
parameter integer VAR46 = 32,
parameter integer VAR34 = 32,
parameter integer VAR24 = 1,
parameter integer VAR47 = 1,
parameter integer VAR35 = 1,
parameter integer VAR26 = 1,
parameter [31:0] VAR15 = 32'hFF
)
(
input wire VAR32,
input wire VAR29,
input wire VAR22,
input wi... | gpl-3.0 |
fallen/milkymist-mmu | cores/sysctl/rtl/sysctl.v | 5,182 | module MODULE1 #(
parameter VAR28 = 4'h0,
parameter VAR6 = 16,
parameter VAR2 = 16,
parameter VAR9 = 32'h00000000,
parameter VAR22 = 32'habadface
) (
input VAR43,
input VAR41,
output reg VAR33,
output reg VAR16,
output reg VAR24,
input [13:0] VAR23,
input VAR30,
input [31:0] VAR34,
output reg [31:0] VAR4,
input [VAR6-1... | lgpl-3.0 |
hhuang25/uwaterloo_ece224 | Lab1Good/pio_egmreset.v | 2,101 | module MODULE1 (
address,
VAR2,
clk,
VAR4,
VAR5,
VAR3,
VAR9,
VAR7
)
;
output VAR9;
output VAR7;
input [ 1: 0] address;
input VAR2;
input clk;
input VAR4;
input VAR5;
input VAR3;
wire VAR1;
reg VAR8;
wire VAR9;
wire VAR6;
wire VAR7;
assign VAR1 = 1;
assign VAR6 = {1 {(address == 0)}} & VAR8;
always @(posedge clk or nege... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/controller/rank_cntrl.v | 19,281 | module MODULE1 #
(
parameter VAR40 = 100, parameter VAR22 = "8", parameter VAR20 = 5, parameter VAR60 = 0, parameter VAR9 = 4, parameter VAR72 = 2, parameter VAR69 = 30, parameter VAR33 = 8, parameter VAR29 = 4, parameter VAR17 = 4, parameter VAR68 = 20, parameter VAR80 = 16, parameter VAR77 = 2, parameter VAR49 = 4, p... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a21oi/sky130_fd_sc_hvl__a21oi.pp.blackbox.v | 1,363 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR5 ,
VAR7 ,
VAR1,
VAR4,
VAR3 ,
VAR6
);
output VAR2 ;
input VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR1;
input VAR4;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32a/sky130_fd_sc_ls__o32a.behavioral.pp.v | 2,188 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR14 ,
VAR11 ,
VAR16 ,
VAR15 ,
VAR12,
VAR7,
VAR18 ,
VAR13
);
output VAR1 ;
input VAR8 ;
input VAR14 ;
input VAR11 ;
input VAR16 ;
input VAR15 ;
input VAR12;
input VAR7;
input VAR18 ;
input VAR13 ;
wire VAR10 ;
wire VAR3 ;
wire VAR2 ;
wire VAR9;
or VAR17 (VAR10 , VAR14, VAR8, VAR11 );
or ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_1.functional.pp.v | 1,935 | module MODULE1( VAR13, VAR1, VAR25, VAR12, VAR18, VAR22, VAR26, VAR9, VAR27 );
input VAR26, VAR22, VAR25, VAR18, VAR1, VAR13;
inout VAR9, VAR27;
output VAR12;
wire VAR10;
not VAR15( VAR10, VAR26 );
wire VAR5;
not VAR3( VAR5, VAR22 );
wire VAR14;
and VAR20( VAR14, VAR10, VAR5 );
wire VAR16;
not VAR24( VAR16, VAR25 );
wi... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_bs.v | 66,159 | module MODULE1(
clk ,
VAR227 ,
VAR60 ,
VAR125 ,
VAR290 ,
VAR133 ,
VAR253 ,
VAR248 ,
VAR62,
VAR130,
VAR136 ,
VAR92 ,
VAR272 ,
VAR310 ,
VAR104 ,
VAR146 ,
VAR267 ,
VAR220 ,
VAR71 ,
VAR304 ,
VAR273
);
input clk ;input VAR227 ;
input [VAR284-1:0] VAR290 ;input [VAR143-1:0] VAR133 ;input [VAR284-1:0] VAR253 ;input [VAR143-1:... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_1c_2p_v1_00_a/hdl/verilog/cf_mem.v | 3,216 | module MODULE1 (
VAR4,
VAR5,
VAR7,
VAR1,
VAR3,
VAR6,
VAR10);
parameter VAR2 = 16;
parameter VAR8 = 5;
input VAR4;
input VAR5;
input [VAR8-1:0] VAR7;
input [VAR2-1:0] VAR1;
input VAR3;
input [VAR8-1:0] VAR6;
output [VAR2-1:0] VAR10;
reg [VAR2-1:0] VAR9[0:((2**VAR8)-1)];
reg [VAR2-1:0] VAR10;
always @(posedge VAR4) begin... | mit |
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