repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
Arlet/vga16 | vga.v | 3,360 | module MODULE1(
input clk, output reg VAR23, input [15:0] VAR15, input VAR3, output VAR17,
input VAR1, output reg VAR14, output reg VAR22, output [15:0] VAR11 );
parameter
VAR7 = 2'd0, VAR4 = 2'd1, VAR19 = 2'd2, VAR20 = 2'd3;
reg [11:0] VAR21 = 0; reg [1:0] VAR10 = VAR19; wire VAR6 = VAR21 <= 1; reg [11:0] VAR8[3:0]; r... | lgpl-2.1 |
h-j-13/MyNote | Programming language/Verilog/sync_FIFO/Source_Code/FIFO_0.v | 2,701 | module MODULE1(VAR16, rd, wr, rst, clk, VAR21, VAR1,VAR19,VAR5);
input [3:0] VAR16;
input rd, wr, rst, clk;
output [6:0] VAR19;
output VAR21, VAR1, VAR5;
reg [3:0] VAR14;
reg VAR26, VAR20,VAR11,VAR13;
reg [3:0] VAR8 [15:0];
reg [23:0]VAR22;
reg [3:0] VAR28, VAR12;
reg [6:0] VAR19;
assign VAR21 = VAR26;
assign VAR1 = VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/maj3/sky130_fd_sc_ls__maj3.blackbox.v | 1,264 | module MODULE1 (
VAR7,
VAR3,
VAR8,
VAR4
);
output VAR7;
input VAR3;
input VAR8;
input VAR4;
supply1 VAR5;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/data_read_controller.v | 37,677 | module MODULE1 (
VAR316,
VAR22,
VAR179,
VAR38,
VAR324,
VAR201,
VAR132,
VAR212,
VAR303,
VAR177,
VAR262,
VAR215,
VAR62,
VAR82,
VAR254,
VAR97,
VAR182,
VAR139,
VAR122,
VAR222,
VAR78,
VAR244,
VAR2,
VAR280,
VAR195,
VAR226,
VAR332,
VAR93,
VAR302,
VAR172,
VAR272,
VAR293,
VAR327,
VAR125,
VAR81,
VAR198,
VAR312,
VAR178,
VAR308,
V... | lgpl-3.0 |
drichmond/riffa | fpga/xilinx/vc709/VC709_Gen3x4If128/hdl/VC709_Gen3x4If128.v | 26,211 | module MODULE1
parameter VAR208 = 4,
parameter VAR154 = 128,
parameter VAR155 = 256,
parameter VAR169 = 5
)
(output [(VAR208 - 1) : 0] VAR70,
output [(VAR208 - 1) : 0] VAR122,
input [(VAR208 - 1) : 0] VAR38,
input [(VAR208 - 1) : 0] VAR52,
output [7:0] VAR157,
input VAR71,
input VAR29,
input VAR181
);
wire VAR43;
wire ... | bsd-3-clause |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_108.v | 1,441 | module MODULE2 (
VAR5,
VAR7
);
input [31:0] VAR5;
output [31:0]
VAR7;
wire [31:0]
VAR6,
VAR8,
VAR3,
VAR1,
VAR9,
VAR12,
VAR10;
assign VAR6 = VAR5;
assign VAR12 = VAR6 << 10;
assign VAR3 = VAR8 - VAR6;
assign VAR8 = VAR6 << 5;
assign VAR1 = VAR3 << 8;
assign VAR9 = VAR3 + VAR1;
assign VAR10 = VAR9 + VAR12;
assign VAR7 = ... | mit |
chaohu/Daily-Learning | Digital-Logic/lab/design/Decoder/Decoder.srcs/sources_1/new/Chip_Decoder.v | 1,196 | module MODULE1(
input VAR5,VAR10,VAR13,VAR9,VAR15,VAR14,VAR2,VAR16,
output reg [3:0] VAR12,
output reg VAR11,VAR4
);
reg [1:0] VAR6;
parameter VAR1 = 0,VAR3 = 1,VAR8 = 2,VAR7 = 3;
always @(VAR5 or VAR10 or VAR14 or VAR13 or VAR2 or VAR16)
begin
if((VAR5 == 1) & (VAR10 == 1) & (VAR14 == 0) & VAR13 & (VAR2 != VAR16))
VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux4/sky130_fd_sc_ls__mux4.symbol.v | 1,368 | module MODULE1 (
input VAR8,
input VAR5,
input VAR9,
input VAR6,
output VAR4 ,
input VAR7,
input VAR3
);
supply1 VAR10;
supply0 VAR2;
supply1 VAR11 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_fp_ldexp.v | 2,688 | module MODULE1(VAR9, VAR1, VAR3, VAR11, enable, VAR8);
input VAR9, VAR1;
input [31:0] VAR3;
input [31:0] VAR11;
input enable;
output [31:0] VAR8;
wire [7:0] VAR4 = VAR3[30:23];
wire [22:0] VAR10 = VAR3[22:0];
wire VAR14 = VAR3[31];
wire [31:0] VAR13 = VAR11;
wire [31:0] VAR5 = VAR13 + VAR4;
reg [7:0] VAR15;
reg [22:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21o/sky130_fd_sc_lp__a21o_m.v | 2,245 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR5 ,
VAR7 ,
VAR4,
VAR10,
VAR2 ,
VAR8
);
output VAR3 ;
input VAR1 ;
input VAR5 ;
input VAR7 ;
input VAR4;
input VAR10;
input VAR2 ;
input VAR8 ;
VAR9 VAR6 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfsbp/sky130_fd_sc_lp__sdfsbp.pp.symbol.v | 1,523 | module MODULE1 (
input VAR7 ,
output VAR3 ,
output VAR9 ,
input VAR8,
input VAR4 ,
input VAR2 ,
input VAR10 ,
input VAR1 ,
input VAR5 ,
input VAR11 ,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211ai/sky130_fd_sc_ls__o211ai.behavioral.pp.v | 2,048 | module MODULE1 (
VAR8 ,
VAR17 ,
VAR7 ,
VAR1 ,
VAR9 ,
VAR5,
VAR10,
VAR4 ,
VAR11
);
output VAR8 ;
input VAR17 ;
input VAR7 ;
input VAR1 ;
input VAR9 ;
input VAR5;
input VAR10;
input VAR4 ;
input VAR11 ;
wire VAR2 ;
wire VAR13 ;
wire VAR6;
or VAR3 (VAR2 , VAR7, VAR17 );
nand VAR14 (VAR13 , VAR9, VAR2, VAR1 );
VAR12 VAR15 ... | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/axi_dwidth_converter_v2_1/0a9a1aa5/hdl/verilog/axi_dwidth_converter_v2_1_axi4lite_upsizer.v | 11,267 | module MODULE1 #
(
parameter VAR40 = "none",
parameter integer VAR55 = 32,
parameter integer VAR54 = 1,
parameter integer VAR43 = 1
)
(
input wire VAR56,
input wire VAR34,
input wire [VAR55-1:0] VAR27,
input wire [3-1:0] VAR47,
input wire VAR39,
output wire VAR17,
input wire [32-1:0] VAR1,
input wire [32/8-1:0] VAR33,
... | mit |
donnaware/AGC | rtl/de0/agc/JTAG_Source1.v | 3,899 | module MODULE1 (
VAR16,
VAR5);
input [0:0] VAR16;
output [0:0] VAR5;
wire [0:0] VAR29;
wire [0:0] VAR5 = VAR29[0:0];
VAR26 VAR28 (
.VAR16 (VAR16),
.VAR5 (VAR29)
,
.VAR9 (),
.VAR21 (),
.VAR20 (),
.VAR10 (),
.VAR1 (),
.VAR32 (),
.VAR3 (),
.VAR4 (),
.VAR22 (),
.VAR15 (),
.VAR24 (),
.VAR8 (),
.VAR19 (),
.VAR11 (),
.VAR30 (... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41o/sky130_fd_sc_lp__a41o_4.v | 2,426 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR7 ,
VAR1 ,
VAR5 ,
VAR9 ,
VAR12,
VAR4,
VAR10 ,
VAR3
);
output VAR6 ;
input VAR2 ;
input VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR9 ;
input VAR12;
input VAR4;
input VAR10 ;
input VAR3 ;
VAR11 VAR8 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR12(VAR... | apache-2.0 |
marmolejo/zet | cores/hpdmc_sdr16/rtl/hpdmc_ctlif.v | 3,416 | module MODULE1 #(
parameter VAR11 = 1'b0,
parameter VAR1 = 12
) (
input VAR22,
input VAR2,
input [ 2:0] VAR14,
input VAR23,
input [15:0] VAR7,
output reg [15:0] VAR3,
output reg VAR18,
output reg VAR6,
output reg VAR9,
output reg VAR20,
output reg VAR16,
output reg VAR13,
output reg VAR26,
output reg [VAR1-1:0] VAR5,
o... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxtp/sky130_fd_sc_ms__sedfxtp_4.v | 2,466 | module MODULE1 (
VAR12 ,
VAR7 ,
VAR10 ,
VAR5 ,
VAR6 ,
VAR2 ,
VAR4,
VAR1,
VAR11 ,
VAR9
);
output VAR12 ;
input VAR7 ;
input VAR10 ;
input VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR4;
input VAR1;
input VAR11 ;
input VAR9 ;
VAR8 VAR3 (
.VAR12(VAR12),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfxtp/sky130_fd_sc_hvl__dfxtp.behavioral.v | 1,708 | module MODULE1 (
VAR8 ,
VAR10,
VAR9
);
output VAR8 ;
input VAR10;
input VAR9 ;
supply1 VAR2;
supply0 VAR7;
supply1 VAR12 ;
supply0 VAR1 ;
wire VAR3 ;
reg VAR11 ;
wire VAR6 ;
wire VAR4;
VAR13 VAR5 (VAR3 , VAR6, VAR4, VAR11, VAR2, VAR7);
buf VAR14 (VAR8 , VAR3 );
endmodule | apache-2.0 |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_0_0/affine_block_ieee754_fp_multiplier_0_0_stub.v | 1,367 | module MODULE1(VAR1, VAR3, VAR2)
;
input [31:0]VAR1;
input [31:0]VAR3;
output [31:0]VAR2;
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/antenna/gf180mcu_fd_sc_mcu9t5v0__antenna.behavioral.v | 1,032 | module MODULE1( VAR3 );
input VAR3;
VAR1 VAR2(.VAR3(VAR3));
VAR1 VAR4(.VAR3(VAR3)); | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/scsdpram.v | 2,946 | module MODULE1
parameter VAR4 = 32,
parameter VAR1 = 1024
)
(
input VAR10,
input VAR2,
input [VAR8(VAR1)-1:0] VAR11,
output [VAR4-1:0] VAR6,
input VAR7,
input [VAR8(VAR1)-1:0] VAR12,
input [VAR4-1:0] VAR9
);
reg [VAR4-1:0] VAR5 [VAR1-1:0];
reg [VAR4-1:0] VAR3;
assign VAR6 = VAR3;
always @(posedge VAR10) begin
if (VAR7)... | gpl-3.0 |
rkrajnc/minimig-de1 | rtl/ctrl/qmem_sram.v | 8,515 | module MODULE1 #(
parameter VAR27 = 32,
parameter VAR4 = 32,
parameter VAR21 = VAR4/8
)(
input wire VAR37,
input wire VAR22,
input wire rst,
input wire [VAR27-1:0] VAR18,
input wire VAR35,
input wire VAR15,
input wire [VAR21-1:0] sel,
input wire [VAR4-1:0] VAR9,
output reg [VAR4-1:0] VAR16,
output wire ack,
output wire... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_8.behavioral.pp.v | 1,084 | module MODULE1( VAR4, VAR1 );
inout VAR4, VAR1;
VAR3 VAR2(.VAR4(VAR4),.VAR1(VAR1));
VAR3 VAR5(.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_or.v | 4,393 | module MODULE1 #
(
parameter VAR13 = "VAR9"
)
(
input wire VAR10,
input wire VAR12,
output wire VAR14
);
generate
if ( VAR13 == "VAR11" ) begin : VAR8
assign VAR14 = VAR10 | VAR12;
end else begin : VAR1
wire VAR4;
assign VAR4 = ~VAR12;
VAR7 VAR3
(
.VAR6 (VAR14),
.VAR5 (VAR10),
.VAR2 (1'b1),
.VAR12 (VAR4)
);
end
endgene... | gpl-3.0 |
amrmorsey/Digital-Design-Project | inverse_perm.v | 3,175 | module MODULE1(
VAR1,
VAR2,
VAR4
);
input [32:1] VAR1;
input [32:1] VAR2;
output reg [64:1] VAR4;
wire [64:1] VAR3 ;
assign VAR3 = {VAR2,VAR1}; always @(VAR3)
begin
VAR4[1] <= VAR3[40];
VAR4[2] <= VAR3[8];
VAR4[3] <= VAR3[48];
VAR4[4] <= VAR3[16];
VAR4[5] <= VAR3[56];
VAR4[6] <= VAR3[24];
VAR4[7] <= VAR3[64];
VAR4[8] <... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or2/sky130_fd_sc_hvl__or2_1.v | 2,083 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR2 ,
VAR9,
VAR8,
VAR7 ,
VAR6
);
output VAR1 ;
input VAR5 ;
input VAR2 ;
input VAR9;
input VAR8;
input VAR7 ;
input VAR6 ;
VAR3 VAR4 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR1,
VAR5,
VAR2
);
output VAR1;
... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_4.functional.pp.v | 1,692 | module MODULE1( VAR19, VAR3, VAR11, VAR15, VAR16, VAR8, VAR21, VAR20 );
input VAR11, VAR19, VAR3, VAR8, VAR16;
inout VAR21, VAR20;
output VAR15;
wire VAR6;
not VAR14( VAR6, VAR11 );
wire VAR22;
not VAR5( VAR22, VAR19 );
wire VAR1;
not VAR4( VAR1, VAR3 );
wire VAR17;
and VAR13( VAR17, VAR6, VAR22, VAR1 );
wire VAR7;
not... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/phy/if_post_fifo.v | 7,935 | module MODULE1 #
(
parameter VAR19 = 100, parameter VAR3 = 4, parameter VAR28 = 32 )
(
input clk, input rst, input VAR24,
input VAR8,
input [VAR28-1:0] din, output VAR6,
output [VAR28-1:0] dout );
localparam VAR18
= (VAR3 == 2) ? 1 :
(((VAR3 == 3) || (VAR3 == 4)) ? 2 : 'VAR5);
integer VAR2;
reg [VAR28-1:0] VAR4[0:VAR3-... | lgpl-3.0 |
alexforencich/verilog-ethernet | example/S10DX_DK/fpga_10g/rtl/xcvr_ctrl.v | 9,499 | module MODULE1 (
input wire VAR10,
input wire VAR22,
input wire VAR8,
output wire [18:0] VAR12,
output wire VAR25,
output wire VAR3,
input wire [7:0] VAR32,
output wire [7:0] VAR23,
input wire VAR27
);
localparam [3:0]
VAR34 = 4'd0,
VAR28 = 4'd1,
VAR38 = 4'd2,
VAR9 = 4'd3,
VAR7 = 4'd4,
VAR13 = 4'd5,
VAR30 = 4'd6,
VAR11... | mit |
antmicro/yosys | techlibs/intel/max10/cells_arith.v | 2,706 | module MODULE1(
module 80alteramax10alu (VAR1, VAR12, VAR10, VAR21, VAR36, VAR30, VAR35);
parameter VAR23 = 0;
parameter VAR11 = 0;
parameter VAR13 = 1;
parameter VAR17 = 1;
parameter VAR31 = 1;
input [VAR13-1:0] VAR1;
input [VAR17-1:0] VAR12;
output [VAR31-1:0] VAR36, VAR30;
input VAR10, VAR21;
output VAR35;
wire VAR2... | isc |
Jam-G/MIPS | FORWARD.v | 1,899 | module MODULE1(
input [4:0] VAR10,
input [4:0] VAR9,
input [4:0] VAR8,
input [4:0] VAR11,
input [4:0] VAR7,
input [4:0] VAR12,
input VAR2,
input VAR4,
input [3:0] VAR5,
input VAR3,
output reg [3:0] VAR1,
output reg [3:0] VAR6,
output reg [7:0] VAR14,
output reg [7:0] VAR13
);
always@(*)begin
if(!VAR3 && VAR4 && VAR12 =... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a222oi/sky130_fd_sc_hdll__a222oi.functional.v | 1,743 | module MODULE1 (
VAR14 ,
VAR2,
VAR4,
VAR7,
VAR1,
VAR6,
VAR12
);
output VAR14 ;
input VAR2;
input VAR4;
input VAR7;
input VAR1;
input VAR6;
input VAR12;
wire VAR5 ;
wire VAR13 ;
wire VAR16 ;
wire VAR8;
nand VAR11 (VAR5 , VAR4, VAR2 );
nand VAR10 (VAR13 , VAR1, VAR7 );
nand VAR15 (VAR16 , VAR12, VAR6 );
and VAR3 (VAR8, V... | apache-2.0 |
bluespec/Flute | builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkMem_Model.v | 5,585 | module MODULE1(VAR20,
VAR17,
VAR33,
VAR16,
VAR8,
VAR54,
VAR26,
VAR15);
input VAR20;
input VAR17;
input [352 : 0] VAR33;
input VAR16;
output VAR8;
input VAR54;
output [255 : 0] VAR26;
output VAR15;
wire [255 : 0] VAR26;
wire VAR8, VAR15;
wire [255 : 0] VAR11, VAR13;
wire VAR49,
VAR6,
VAR24,
VAR61,
VAR59;
wire [255 : 0] ... | apache-2.0 |
bbrown1867/ObjectTracking | hw/new_pipeline/new_pipeline.v | 6,841 | module MODULE1(
input VAR69,
input VAR119,
input VAR57,
output [8:0] VAR102,
output [17:0] VAR30,
input [3:0] VAR68,
output [7:0] VAR113,
output VAR80,
output VAR122,
output [7:0] VAR112,
output VAR53,
output [7:0] VAR22,
output VAR63,
output VAR81,
output VAR90,
inout VAR18,
input VAR78,
input [7:0] VAR117,
input VAR8... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfsbp/sky130_fd_sc_hvl__dfsbp.symbol.v | 1,417 | module MODULE1 (
input VAR5 ,
output VAR4 ,
output VAR6 ,
input VAR2,
input VAR9
);
supply1 VAR7;
supply0 VAR3;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
kazuyamashi/cReComp | example/verilog/sonic_sensor.v | 3,731 | module MODULE1(
input clk,
input rst,
input req,
output [0:0] VAR9,
inout VAR16,
output VAR23,
output [31:0] VAR17
);
parameter VAR3 = 0,
VAR4 = 1,
VAR5 = 2,
VAR20 = 3,
VAR2 = 4,
VAR11 = 5,
VAR8 = 6,
VAR15 = 7,
VAR18 = 8,
VAR22 = 9;
reg [3:0] state;
reg [31:0] VAR19;
reg [32:0] counter;
reg [31:0] VAR14;
wire VAR1;
wir... | bsd-3-clause |
mammenx/synesthesia_moksha | wxp/dgn/rtl/top/syn_moksha.v | 14,262 | module MODULE1(
VAR70,
VAR2,
VAR177,
VAR13,
VAR174,
VAR29,
VAR16,
VAR173,
VAR149,
VAR74,
VAR106,
VAR79,
VAR14,
VAR152,
VAR10,
VAR62,
VAR33,
VAR119,
VAR52,
VAR176,
VAR133,
VAR30,
VAR175,
VAR108,
VAR112,
VAR142,
VAR67,
VAR92,
VAR162,
VAR109,
VAR171,
VAR15,
VAR91,
VAR5,
VAR172,
VAR6,
VAR116,
VAR151,
VAR120,
VAR12,
VAR137,... | gpl-3.0 |
alankarkotwal/lca-processor | USE THESE FILES PRAVEEN/decode.v | 7,691 | module MODULE2(VAR18, VAR5, VAR28, VAR12, VAR9, VAR1, VAR21, VAR19, VAR6, VAR35, VAR15, VAR30, VAR34, VAR11, VAR7, VAR24, VAR2,VAR22,VAR25);
output [15:0] VAR12, VAR19, VAR6;
output reg [2:0] VAR9, VAR1, VAR21;
output reg [1:0] VAR11;
output wire [2:0]VAR22;
output reg VAR25;
assign VAR22=VAR21;
output reg VAR18;
integ... | gpl-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/verilog/FIFO_image_filter_gray_rows_V.v | 2,983 | module MODULE2 (
clk,
VAR14,
VAR10,
VAR6,
VAR27);
parameter VAR5 = 32'd12;
parameter VAR7 = 32'd2;
parameter VAR15 = 32'd3;
input clk;
input [VAR5-1:0] VAR14;
input VAR10;
input [VAR7-1:0] VAR6;
output [VAR5-1:0] VAR27;
reg[VAR5-1:0] VAR8 [0:VAR15-1];
integer VAR17;
always @ (posedge clk)
begin
if (VAR10)
begin
for (VA... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/pcim_top.v | 9,800 | module MODULE1 (
inout [31:0] VAR106, inout [3:0] VAR30,
inout VAR78,
inout VAR37,
inout VAR5,
inout VAR84,
inout VAR68,
inout VAR111,
input VAR36,
output VAR34,
inout VAR28,
inout VAR95,
output VAR52,
input VAR101,
input VAR112,
input VAR4,
output VAR65, output VAR76,
output VAR53, output VAR64,
output [31:0] VAR9, ou... | mit |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/phyIniCommand0.v | 1,127 | module MODULE1
(
input [(VAR4-1):0] VAR6,
input [(VAR3-1):0] addr,
input VAR1, clk,
output [(VAR4-1):0] VAR7
);
reg [VAR4-1:0] VAR2[2**VAR3-1:0];
reg [VAR3-1:0] VAR5;
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfstp/sky130_fd_sc_hs__dfstp.functional.v | 1,720 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR4 ,
VAR13 ,
VAR8 ,
VAR11
);
input VAR2 ;
input VAR1 ;
output VAR4 ;
input VAR13 ;
input VAR8 ;
input VAR11;
wire VAR6;
wire VAR3 ;
not VAR7 (VAR3 , VAR11 );
VAR9 VAR5 VAR12 (VAR6 , VAR8, VAR13, VAR3, VAR2, VAR1);
buf VAR10 (VAR4 , VAR6 );
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/mig_7series_v1_8_ddr_mc_phy_wrapper.v | 65,933 | module MODULE1 #
(
parameter VAR384 = 100, parameter VAR194 = 2500, parameter VAR143 = "VAR332", parameter VAR62 = "VAR281", parameter VAR7 = "VAR57", parameter VAR132 = "VAR327",
parameter VAR48 = 4, parameter VAR330 = 1, parameter VAR151 = 3, parameter VAR363 = 1, parameter VAR326 = 1, parameter VAR407 = 1, parameter... | mit |
kyzhai/NUNY | src/hardware/stage3_bb.v | 4,980 | module MODULE1 (
address,
VAR1,
VAR2);
input [11:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdlclkp/sky130_fd_sc_hd__sdlclkp_1.v | 2,262 | module MODULE2 (
VAR8,
VAR10 ,
VAR2,
VAR7 ,
VAR9,
VAR5,
VAR3 ,
VAR6
);
output VAR8;
input VAR10 ;
input VAR2;
input VAR7 ;
input VAR9;
input VAR5;
input VAR3 ;
input VAR6 ;
VAR4 VAR1 (
.VAR8(VAR8),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
... | apache-2.0 |
KorotkiyEugene/Netmaker_vc_router_syn_quartus | NW_vc_fc_out.v | 5,881 | module MODULE1 (VAR26, VAR20,
VAR19,
VAR31, VAR35, VAR12,
clk, VAR1);
parameter VAR36 = 4;
parameter VAR10 = 4;
parameter VAR5 = 1;
parameter VAR16 = VAR21(VAR10+1);
input VAR24 VAR26;
input VAR20;
input VAR2 VAR19;
output VAR14 VAR31;
output [VAR36-1:0] VAR35;
output [VAR36-1:0][VAR16-1:0] VAR12;
input clk, VAR1;
logi... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffrnq/gf180mcu_fd_sc_mcu9t5v0__dffrnq_2.behavioral.v | 3,634 | module MODULE1( VAR7, VAR15, VAR5, VAR8 );
input VAR7, VAR15, VAR5;
output VAR8;
reg VAR24;
VAR10 VAR32(.VAR7(VAR7),.VAR15(VAR15),.VAR5(VAR5),.VAR8(VAR8),.VAR24(VAR24));
VAR10 VAR16(.VAR7(VAR7),.VAR15(VAR15),.VAR5(VAR5),.VAR8(VAR8),.VAR24(VAR24));
not VAR25(VAR11,VAR15);
and VAR12(VAR20,VAR5,VAR11);
and VAR18(VAR2,VAR5... | apache-2.0 |
jotego/jt12 | hdl/jt12_mmr.v | 18,910 | module MODULE1(
input rst,
input clk,
input VAR48 ,
output VAR18,
output VAR32,
output VAR71,
output VAR115,
output VAR49,
output VAR22,
input [7:0] din,
input write,
input [1:0] addr,
output reg VAR35,
output VAR38,
output [2:0] VAR98,
output [1:0] VAR11,
output reg [2:0] VAR69,
output reg VAR80,
output reg [9:0] VAR4... | gpl-3.0 |
Dokany/STA | Verilog_modules/CSA16_CLA.v | 1,490 | module MODULE2 (
input [3:0] VAR2,
input [3:0] VAR12,
input VAR3,
output [3:0] VAR9,
output VAR13
);
wire [3:0] VAR7, VAR4, VAR16;
assign VAR7 = VAR2 & VAR12;
assign VAR4 = VAR2 | VAR12;
assign VAR16[0] = VAR3;
assign VAR16[1] = VAR7[0] | (VAR3 & VAR4[0]);
assign VAR16[2] = VAR7[1] | (VAR7[0] & VAR4[1]) | (VAR3 & VAR4[... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9652/axi_ad9652.v | 11,744 | module MODULE1 (
VAR77,
VAR21,
VAR57,
VAR69,
VAR117,
VAR4,
VAR151,
VAR147,
VAR42,
VAR64,
VAR18,
VAR62,
VAR61,
VAR8,
VAR33,
VAR131,
VAR86,
VAR153,
VAR94,
VAR127,
VAR89,
VAR103,
VAR126,
VAR99,
VAR132,
VAR93,
VAR112,
VAR91,
VAR145,
VAR115,
VAR36,
VAR19,
VAR26,
VAR37,
VAR133,
VAR136,
VAR140);
parameter VAR39 = 0;
parameter... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/Video_System/submodules/altera_up_video_clipper_drop.v | 10,517 | module MODULE1 (
clk,
reset,
VAR18,
VAR13,
VAR15,
VAR39,
VAR25,
VAR7,
VAR40,
VAR31,
VAR5,
VAR27,
VAR44,
VAR29
);
parameter VAR11 = 15; parameter VAR41 = 0;
parameter VAR24 = 640; parameter VAR32 = 480; parameter VAR37 = 9; parameter VAR4 = 8;
parameter VAR26 = 0;
parameter VAR30 = 0;
parameter VAR22 = 0;
parameter VAR3... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and2b/sky130_fd_sc_hs__and2b_2.v | 2,009 | module MODULE2 (
VAR6 ,
VAR7 ,
VAR5 ,
VAR2,
VAR3
);
output VAR6 ;
input VAR7 ;
input VAR5 ;
input VAR2;
input VAR3;
VAR4 VAR1 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR6 ,
VAR7,
VAR5
);
output VAR6 ;
input VAR7;
input VAR5 ;
supply1 VAR2;
supply0 VAR3;
VAR4 VAR1 ... | apache-2.0 |
alexforencich/hdg2000 | fpga/lib/dsp/rtl/dsp_iq_mult.v | 4,007 | module MODULE1 #
(
parameter VAR4 = 16
)
(
input wire clk,
input wire rst,
input wire [VAR4-1:0] VAR3,
input wire [VAR4-1:0] VAR21,
input wire VAR11,
output wire VAR6,
input wire [VAR4-1:0] VAR18,
input wire [VAR4-1:0] VAR10,
input wire VAR25,
output wire VAR22,
output wire [(VAR4*2)-1:0] VAR15,
output wire [(VAR4*2)-1... | mit |
fabianz66/cursos-tec | taller-digital/Proyecto Final/Referencias/soc/asram16_if.v | 15,029 | module MODULE1
(
VAR25,
VAR13,
VAR32,
VAR15,
VAR10,
VAR34,
VAR33,
VAR29,
VAR14,
VAR37,
VAR5,
VAR35,
VAR6,
VAR17,
VAR31,
VAR36,
VAR24,
VAR11
);
parameter [31:0] VAR21 = 17;
input VAR25 ;
input VAR13 ;
input [(32 - 1):0] VAR32 ;
output [(VAR21 - 1):0] VAR15 ;
output [(16 - 1):0] VAR10 ;
input [(16 - 1):0] VAR34 ;
output ... | mit |
mlarouche/sd2snes | verilog/sd2snes/address.v | 9,451 | module MODULE1(
input VAR2,
input [7:0] VAR34, input [2:0] VAR10, input [23:0] VAR15, input [7:0] VAR19, output [23:0] VAR1, output VAR36, output VAR25, output VAR37, output VAR8, input [23:0] VAR7,
input [23:0] VAR17,
output VAR9,
output VAR38,
output VAR13,
output VAR5,
input [14:0] VAR24,
output VAR22,
output VAR14,... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_bleeder/sky130_fd_sc_hd__lpflow_bleeder.behavioral.pp.v | 1,176 | module MODULE1 (
VAR3,
VAR1 ,
VAR5 ,
VAR6 ,
VAR4
);
input VAR3;
inout VAR1 ;
input VAR5 ;
input VAR6 ;
input VAR4 ;
wire VAR2;
pulldown(VAR2);
bufif1 (VAR1, VAR2, VAR3);
endmodule | apache-2.0 |
omicronns/studies-sys-rek | de1-soc/v/VGAController.v | 3,987 | module MODULE1(
input VAR9,
input VAR15,
input [7:0] VAR18,
input [7:0] VAR22,
input [7:0] VAR26,
output [7:0] VAR12,
output [7:0] VAR10,
output [7:0] VAR6,
output VAR32,
output VAR25,
output VAR31,
output VAR13
);
parameter VAR24 = 96;
parameter VAR5 = 48;
parameter VAR28 = 640;
parameter VAR4 = 16;
parameter VAR30 = ... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/np_core_back.v | 25,703 | module MODULE1
parameter VAR288=VAR107/8,
parameter VAR98 = 2,
parameter VAR78 = 2,
parameter VAR197 = 8'hff,
parameter VAR199 = 8,
parameter VAR103 = 3,
parameter VAR291 = 4,
parameter VAR284 = 0)
( output [VAR107-1:0] VAR9,
output [VAR288-1:0] VAR130,
output VAR202,
input VAR245,
input [VAR107-1:0] VAR181,
input [VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.v | 2,389 | module MODULE1 (
VAR4 ,
VAR3,
VAR9 ,
VAR2 ,
VAR5 ,
VAR7 ,
VAR10 ,
VAR1
);
output VAR4 ;
input VAR3;
input VAR9 ;
input VAR2 ;
input VAR5 ;
input VAR7 ;
input VAR10 ;
input VAR1 ;
VAR8 VAR6 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR1(VAR1)
);
endmodule
module MODU... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/SHD.v | 26,438 | module MODULE1 #(parameter VAR31 = 200) (
VAR14,
VAR8,
VAR19
);
input [VAR31-1:0] VAR14, VAR8;
reg [(VAR31/2)-1:0] VAR18, VAR1, VAR28, VAR12, VAR7, VAR26, VAR30, VAR22, VAR20, VAR5, VAR23, VAR11;
output reg VAR19;
reg [VAR31-1:0] VAR9, VAR29, VAR10, VAR13, VAR6, VAR25, VAR27, VAR16, VAR21, VAR15, VAR24;
integer VAR3, V... | gpl-3.0 |
twlostow/dsi-shield | hdl/rtl/dsi_core/dphy_lane.v | 8,686 | module MODULE1
(
input VAR10,
input VAR34,
input VAR27,
input VAR12,
input [3:0] VAR11,
input [31:0] VAR7,
output reg VAR6,
input VAR19,
input [7:0] VAR26,
input VAR15,
output reg VAR42,
output reg VAR37,
output reg [7:0] VAR5,
output reg VAR36,
input [1:0] VAR13,
input VAR33,
output VAR32,
output VAR41,
output reg VAR... | lgpl-3.0 |
SymbiFlow/fpga-tool-perf | src/bram/processing_unit.v | 1,327 | module MODULE1
(
input wire VAR9,
input wire VAR7,
input wire VAR1,
input wire [31:0] VAR3,
output wire VAR4,
output wire [31:0] VAR5
);
wire [15:0] VAR8 = VAR3[15: 0];
wire [15:0] VAR2 = VAR3[31:16];
reg VAR6;
reg [31:0] VAR10;
always @(posedge VAR9)
VAR10 <= VAR8 * VAR2;
always @(posedge VAR9 or posedge VAR7)
if (VAR... | isc |
mrehkopf/sd2snes | verilog/sd2snes_sgb/oam.v | 10,585 | module MODULE1 (
VAR26,
VAR61,
VAR24,
VAR20,
VAR56,
VAR41,
VAR6,
VAR44,
VAR54);
input [7:0] VAR26;
input [7:0] VAR61;
input VAR24;
input [7:0] VAR20;
input [7:0] VAR56;
input VAR41;
input VAR6;
output [7:0] VAR44;
output [7:0] VAR54;
tri1 VAR24;
tri0 VAR41;
tri0 VAR6;
wire [7:0] VAR58;
wire [7:0] VAR4;
wire [7:0] VAR44... | gpl-2.0 |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/new/segDisplayDriver.v | 2,683 | module MODULE1(clk,VAR2,VAR3,VAR7);
input clk;
input [15:0] VAR2;
output [3:0] VAR3;
output [7:0] VAR7;
reg [31:0] VAR4;
reg VAR5;
always @ (posedge clk)
if(VAR4 == 32'd200000) begin
VAR4 <= 1'b0;
VAR5 <= ~VAR5;
end
else
VAR4 <= VAR4 + 1'b1;
reg [3:0] VAR6 = 4'b1110;
always @(posedge VAR5)
VAR6 <= { VAR6[2:0], VAR6[3] ... | gpl-3.0 |
DougFirErickson/parallella-hw | fpga/src/common/hdl/clock_divider.v | 4,031 | module MODULE1(
VAR14, VAR15,
VAR3, VAR6, reset
);
input VAR3; input [3:0] VAR6; input reset;
output VAR14; output VAR15;
reg VAR2;
reg [7:0] counter;
reg [7:0] VAR10;
reg [3:0] VAR13;
reg [3:0] VAR16;
wire VAR7;
wire VAR12;
wire VAR1;
wire VAR8;
wire VAR5;
wire VAR4;
reg VAR11;
reg VAR9;
always @ (VAR6[3:0])
casez (VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_pr_pp_pkg_s/sky130_fd_sc_lp__udp_dlatch_pr_pp_pkg_s.symbol.v | 1,525 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR5 ,
input VAR1 ,
input VAR7,
input VAR6 ,
input VAR4 ,
input VAR8
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4.behavioral.pp.v | 3,755 | module MODULE1( VAR23, VAR16, VAR20, VAR8, VAR12, VAR15 );
input VAR23, VAR16, VAR20;
inout VAR12, VAR15;
output VAR8;
reg VAR7;
VAR22 VAR19(.VAR23(VAR23),.VAR16(VAR16),.VAR20(VAR20),.VAR8(VAR8),.VAR12(VAR12),.VAR15(VAR15),.VAR7(VAR7));
VAR22 VAR18(.VAR23(VAR23),.VAR16(VAR16),.VAR20(VAR20),.VAR8(VAR8),.VAR12(VAR12),.VA... | apache-2.0 |
jayrandez/Processor | digits.v | 1,639 | module MODULE1(
VAR5,
enable,
VAR8,
VAR9,
VAR3
);
input wire VAR5;
input wire[3:0] enable;
input wire[15:0] VAR8;
output reg[6:0] VAR9 = 8'b1111111;
output reg[3:0] VAR3 = 4'b1111;
reg[14:0] counter = 0;
reg VAR1 = 0;
reg[1:0] VAR12;
wire VAR7;
wire[3:0] VAR13;
VAR10 VAR2(
.VAR6(VAR1),
.VAR14(VAR7)
);
assign VAR13 =
(V... | apache-2.0 |
emeb/iceRadio | FPGA/rxadc_2/verilog/src/cic_dec_2.v | 2,241 | module MODULE1 #(
parameter VAR5 = 4, VAR14 = 8, VAR1 = 10, VAR12 = (VAR1 + (VAR5 * VAR14)) )
(
input clk, input reset, input VAR10, input signed [VAR1-1:0] VAR3, output signed [VAR12-1:0] VAR7, output valid );
wire signed [VAR12-1:0] VAR13 = {{VAR12-VAR1{VAR3[VAR1-1]}},VAR3};
reg signed [VAR12-1:0] VAR11[0:VAR5-1];
al... | mit |
shahid313/MSCourseWork | Adv ASIC Design and FPGA/8bitRISCProcessor/8bitRISCProcessor/RISC/alu.v | 1,338 | module MODULE1(VAR8,VAR2,VAR9,VAR10,VAR3
);
parameter VAR11 = 8,
VAR6= 3;
input [VAR11-1:0] VAR8,VAR2;
input [VAR6-1:0] VAR9;
output reg [VAR11-1:0] VAR3;
output VAR10;
localparam VAR15 = 3'b000,
VAR4 = 3'b001,
VAR5 = 3'b010,
VAR1 = 3'b011,
VAR14 = 3'b100,
VAR12 = 3'b101,
VAR13 = 3'b110,
VAR7 = 3'b111;
assign VAR10 = ~... | gpl-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/ICESTICK/T25-uart-rx/uart_rx.v | 3,721 | module MODULE1
parameter VAR18 = VAR16
)
(input wire clk, input wire VAR1, input wire VAR2, output reg VAR4, output reg [7:0] VAR5);
wire VAR14;
reg VAR3;
reg VAR10; reg VAR6; reg VAR12;
always @(posedge clk)
VAR3 <= VAR2;
VAR20 #(.VAR18(VAR18))
VAR15 (
.clk(clk),
.VAR7(VAR10),
.VAR17(VAR14)
);
reg [3:0] VAR11;
always ... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/rxc_engine_ultrascale.v | 19,287 | module MODULE1
parameter VAR44 = 128,
parameter VAR15=10,
parameter VAR30 = 0,
parameter VAR69 = 1
)
(
input VAR101,
input VAR99,
input VAR52,
input VAR109,
input [VAR44-1:0] VAR48,
input [(VAR44/32)-1:0] VAR40,
input [VAR89-1:0] VAR119,
output VAR123,
output [VAR44-1:0] VAR86,
output VAR47,
output [(VAR44/32)-1:0] VAR... | gpl-3.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_csc_1_mul.v | 4,030 | module MODULE1 (
clk,
VAR2,
VAR3,
VAR5,
VAR12,
VAR14);
parameter VAR15 = 16;
localparam VAR19 = VAR15 - 1;
input clk;
input [16:0] VAR2;
input [ 7:0] VAR3;
output [24:0] VAR5;
input [VAR19:0] VAR12;
output [VAR19:0] VAR14;
reg [VAR19:0] VAR11 = 'd0;
reg [VAR19:0] VAR21 = 'd0;
reg [VAR19:0] VAR14 = 'd0;
reg VAR8 = 'd0;
... | lgpl-3.0 |
ptracton/wb_soc_template | rtl/cpu/cpu_wrapper.v | 16,792 | module MODULE1 (
VAR30, VAR13, VAR42, VAR31, VAR10,
VAR20, VAR9, VAR7, VAR26, VAR36,
VAR2, VAR25, VAR16, VAR12, VAR17,
VAR44, VAR22, VAR32, VAR5, VAR4, VAR34,
VAR38,
VAR39, VAR33, VAR46, VAR43, VAR8, VAR37,
VAR11, VAR23, VAR6, VAR45, VAR19,
VAR40, VAR28, VAR24, VAR14, VAR29, VAR18,
VAR15, VAR21, VAR35, VAR3, VAR1
) ;
p... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2bb2a/sky130_fd_sc_hd__o2bb2a.pp.symbol.v | 1,383 | module MODULE1 (
input VAR3,
input VAR6,
input VAR8 ,
input VAR9 ,
output VAR2 ,
input VAR7 ,
input VAR1,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
silent-observer/RCPU | CPU/source/Debouncer.v | 1,409 | module MODULE1(
input clk,
input VAR7,
output reg VAR4, output VAR1, output VAR3 );
reg VAR9; always @(posedge clk) VAR9 <= ~VAR7; reg VAR2; always @(posedge clk) VAR2 <= VAR9;
reg [15:0] VAR8;
wire VAR5 = (VAR4==VAR2);
wire VAR6 = &VAR8;
always @(posedge clk)
if(VAR5)
VAR8 <= 0; else
begin
VAR8 <= VAR8 + 16'd1; if(VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtn/sky130_fd_sc_ms__dlxtn_1.v | 2,204 | module MODULE2 (
VAR4 ,
VAR1 ,
VAR2,
VAR6 ,
VAR8 ,
VAR5 ,
VAR3
);
output VAR4 ;
input VAR1 ;
input VAR2;
input VAR6 ;
input VAR8 ;
input VAR5 ;
input VAR3 ;
VAR9 VAR7 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR4 ,
VAR1 ,
VAR2
);
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3/sky130_fd_sc_ms__nor3_1.v | 2,198 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR6 ,
VAR7 ,
VAR10,
VAR8,
VAR9 ,
VAR4
);
output VAR3 ;
input VAR2 ;
input VAR6 ;
input VAR7 ;
input VAR10;
input VAR8;
input VAR9 ;
input VAR4 ;
VAR5 VAR1 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sedfxbp/sky130_fd_sc_hdll__sedfxbp.pp.symbol.v | 1,526 | module MODULE1 (
input VAR5 ,
output VAR1 ,
output VAR10 ,
input VAR4 ,
input VAR3 ,
input VAR9 ,
input VAR8 ,
input VAR7 ,
input VAR6,
input VAR11,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4/sky130_fd_sc_hdll__nor4.blackbox.v | 1,316 | module MODULE1 (
VAR2,
VAR6,
VAR9,
VAR1,
VAR7
);
output VAR2;
input VAR6;
input VAR9;
input VAR1;
input VAR7;
supply1 VAR5;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
JakeMercer/mac | MAC/rtl/mac/mac.v | 3,152 | module MODULE1(
input wire reset,
input wire [31:0] VAR49,
input wire VAR38,
input wire VAR13,
input wire VAR47,
input wire VAR11,
output wire [31:0] VAR25,
input wire VAR6,
input wire VAR22,
output wire VAR24,
output wire VAR39,
output wire [6:0] VAR48,
input wire VAR9,
input wire VAR53,
input wire VAR26,
input wire V... | mit |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/v/model_uart.v | 1,793 | module MODULE1 (
VAR7,
VAR4
);
output VAR7;
input VAR4;
parameter VAR1 = 17361; parameter VAR6 = 1'b0;
parameter VAR2 = 1'b1;
integer period;
reg VAR7;
reg VAR5;
reg VAR3;
begin
begin
begin
begin
begin | gpl-2.0 |
bigeagle/riffa | fpga/riffa_hdl/rxr_engine_ultrascale.v | 21,042 | module MODULE1
parameter VAR124=10
)
(
input VAR52,
input VAR45,
input VAR19,
input VAR86,
input [VAR43-1:0] VAR120,
input [(VAR43/32)-1:0] VAR83,
input [VAR72-1:0] VAR102,
output VAR67,
output [VAR43-1:0] VAR78,
output VAR107,
output [(VAR43/32)-1:0] VAR17,
output VAR68,
output [VAR75(VAR43/32)-1:0] VAR14,
output VAR5... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.behavioral.v | 18,312 | module MODULE1( VAR17, VAR116, VAR262, VAR10, VAR277, VAR55 );
input VAR10, VAR262, VAR277, VAR17, VAR116;
output VAR55;
reg VAR212;
VAR115 VAR282(.VAR17(VAR17),.VAR116(VAR116),.VAR262(VAR262),.VAR10(VAR10),.VAR277(VAR277),.VAR55(VAR55),.VAR212(VAR212));
VAR115 VAR64(.VAR17(VAR17),.VAR116(VAR116),.VAR262(VAR262),.VAR10... | apache-2.0 |
takeshineshiro/fpga_linear_128 | ABS_bb.v | 2,693 | module MODULE1 (
VAR1,
VAR2);
input [29:0] VAR1;
output [29:0] VAR2;
endmodule | mit |
ptracton/UART_ECHO | rtl/uart_fifo.v | 6,429 | module MODULE1 (
VAR6, VAR2, irq, VAR27, VAR28, VAR26,
VAR8, clk, rst, VAR3, VAR19, VAR33
) ;
input [7:0] VAR8; input clk; input rst; input VAR3; input VAR19; input VAR33;
output [7:0] VAR6; output VAR2; output irq; output VAR27; output VAR28; output VAR26;
reg VAR18;
wire VAR29; wire VAR30; wire VAR34; wire VAR23;
wir... | mit |
jrward/qdbreakout | rtl/qdbreakout.v | 3,929 | module MODULE1( input wire clk,
input wire VAR18,
input wire VAR32,
input wire VAR30,
output wire VAR25,
output wire [2:0] VAR17,
output wire VAR8,
output wire VAR10
);
wire [9:0] VAR26;
wire [9:0] VAR24;
wire [5:0] VAR3;
wire VAR4; wire VAR2;
wire VAR7;
wire [9:0] VAR19;
wire [9:0] VAR22;
wire [3:0] VAR13;
wire VAR5;
... | gpl-2.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/pcie_core/source/pcie_core_axi_basic_tx_pipeline.v | 22,378 | module MODULE1 #(
parameter VAR12 = 128, parameter VAR58 = "VAR60", parameter VAR35 = 1,
parameter VAR1 = (VAR12 == 128) ? 2 : 1, parameter VAR11 = VAR12 / 8 ) (
input [VAR12-1:0] VAR38, input VAR3, output VAR2, input [VAR11-1:0] VAR49, input VAR50, input [3:0] VAR14,
output [VAR12-1:0] VAR6, output VAR48, output VAR55... | lgpl-3.0 |
tmatsuya/milkymist-ml401 | cores/hpdmc_ddr32/rtl/virtex4/hpdmc_oddr32.v | 6,127 | module MODULE1 #(
parameter VAR11 = "VAR25",
parameter VAR18 = 1'b0,
parameter VAR34 = "VAR10"
) (
output [31:0] VAR31,
input VAR8,
input VAR26,
input [31:0] VAR4,
input [31:0] VAR16,
input VAR33,
input VAR7
);
VAR27 #(
.VAR11(VAR11),
.VAR18(VAR18),
.VAR34(VAR34)
) VAR28 (
.VAR31(VAR31[0]),
.VAR8(VAR8),
.VAR26(VAR26),
... | lgpl-3.0 |
monotone-RK/FACE | IEICE-Trans/8-way_2-tree/src/riffa/rxr_engine_ultrascale.v | 21,844 | module MODULE1
parameter VAR110=10)
( input VAR143,
input VAR124, input VAR60, output VAR106,
input VAR102,
input VAR76,
input [VAR51-1:0] VAR109,
input [(VAR51/32)-1:0] VAR56,
input [VAR26-1:0] VAR90,
output VAR32,
output [VAR51-1:0] VAR71,
output VAR138,
output [(VAR51/32)-1:0] VAR103,
output VAR94,
output [VAR4(VAR5... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3/sky130_fd_sc_hdll__and3.symbol.v | 1,282 | module MODULE1 (
input VAR7,
input VAR6,
input VAR3,
output VAR1
);
supply1 VAR2;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0p/sky130_fd_sc_lp__inputiso0p.functional.pp.v | 1,849 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR8,
VAR4 ,
VAR5 ,
VAR2 ,
VAR11
);
output VAR3 ;
input VAR1 ;
input VAR8;
input VAR4 ;
input VAR5 ;
input VAR2 ;
input VAR11 ;
wire VAR6 ;
wire VAR7;
not VAR10 (VAR6 , VAR8 );
and VAR13 (VAR7, VAR1, VAR6 );
VAR12 VAR9 (VAR3 , VAR7, VAR4, VAR5);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd3/sky130_fd_sc_hdll__dlygate4sd3.functional.v | 1,317 | module MODULE1 (
VAR2,
VAR3
);
output VAR2;
input VAR3;
wire VAR1;
buf VAR4 (VAR1, VAR3 );
buf VAR5 (VAR2 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_mux_2to1_n/sky130_fd_sc_ms__udp_mux_2to1_n.blackbox.v | 1,236 | module MODULE1 (
VAR1 ,
VAR2,
VAR4,
VAR3
);
output VAR1 ;
input VAR2;
input VAR4;
input VAR3 ;
endmodule | apache-2.0 |
freecores/sha3 | low_throughput_core/rtl/f_permutation.v | 2,046 | module MODULE1(clk, reset, in, VAR4, ack, out, VAR11);
input clk, reset;
input [575:0] in;
input VAR4;
output ack;
output reg [1599:0] out;
output reg VAR11;
reg [22:0] VAR2;
wire [1599:0] VAR9, VAR1;
wire [63:0] VAR3;
wire VAR7;
wire VAR5;
reg VAR6;
assign VAR5 = VAR4 & (~ VAR6);
always @ (posedge clk)
if (reset) VAR2... | apache-2.0 |
amrmorsey/Digital-Design-Project | clk50.v | 1,184 | module MODULE1(
input clk,
input rst,
input select,
output reg [31:0] VAR2,
output reg [31:0] VAR1,
output VAR3,
output VAR4,
output VAR5
);
always @ (posedge clk or posedge rst)
begin
if (rst)
VAR2<=32'd0;
end
else
if (VAR2 == 32'd4)
VAR2<=32'd0;
else
VAR2 <= VAR2 + 1;
end
always @ (posedge clk or posedge rst)
begin
i... | gpl-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/pcie_data_send_fifo.v | 13,701 | module MODULE1(
rst,
VAR65,
VAR337,
din,
VAR353,
VAR43,
dout,
VAR2,
VAR16,
VAR282,
VAR111,
VAR394,
VAR126,
VAR218
);
input rst;
input VAR65;
input VAR337;
input [255 : 0] din;
input VAR353;
input VAR43;
output [127 : 0] dout;
output VAR2;
output VAR16;
output VAR282;
output VAR111;
output [10 : 0] VAR394;
output [10 : ... | gpl-2.0 |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_VCU118/mkDM_GPR_Tap.v | 7,692 | module MODULE1(VAR58,
VAR64,
VAR21,
VAR17,
VAR25,
VAR6,
VAR5,
VAR15,
VAR70,
VAR54,
VAR40,
VAR18,
VAR24,
VAR71,
VAR20,
VAR61,
VAR8);
input VAR58;
input VAR64;
input VAR21;
output [69 : 0] VAR17;
output VAR25;
input [64 : 0] VAR6;
input VAR5;
output VAR15;
input [69 : 0] VAR70;
input VAR54;
output VAR40;
input VAR18;
out... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpmult_arch2/KOA_2c.v | 5,879 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR36,
input wire [VAR34-1:0] VAR15,
input wire [VAR34-1:0] VAR39,
output wire [2*VAR34-1:0] VAR21
);
wire [1:0] VAR24;
wire [3:0] VAR37;
assign VAR24 = 2'b00;
assign VAR37 = 4'b0000;
wire [VAR34/2-1:0] VAR17;
wire [VAR34/2:0] VAR6;
wire [VAR34/2-3:0] VAR35;
w... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/bw_clk_cclk_inv_48x.v | 1,293 | module MODULE1 (
VAR2,
VAR1 );
output VAR2;
input VAR1;
assign VAR2 = ~( VAR1 );
endmodule | gpl-2.0 |
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