repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
chaohu/Daily-Learning | Verilog/lab2/lab2_2/lab2_3_2/lab2_3_2.srcs/sources_1/new/bcdto7segment_dataflow.v | 1,043 | module MODULE1(
input [3:0] VAR2,
output [6:0] VAR1
);
assign VAR1[6] = (VAR2[2]&(~VAR2[1])&(~VAR2[0]))|((~VAR2[3])&(~VAR2[2])&(~VAR2[1])&VAR2[0]);
assign VAR1[5] = (VAR2[2]&(~VAR2[1])&VAR2[0])|(VAR2[2]&VAR2[1]&(~VAR2[0]));
assign VAR1[4] = (~VAR2[3])&(~VAR2[2])&VAR2[1]&(~VAR2[0]);
assign VAR1[3] = (VAR2[2]&(~VAR2[1])&... | mit |
gtaylormb/opl3_fpga | fpga/modules/clks/ip/clk_gen/clk_gen.v | 3,922 | module MODULE1
(
input VAR3,
output clk,
output VAR4
);
VAR1 VAR2
(
.VAR3(VAR3),
.clk(clk),
.VAR4(VAR4)
);
endmodule | lgpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/RAMB16_S4_altera.v | 7,888 | module MODULE1 (
VAR31,
address,
VAR27,
VAR48,
VAR50,
VAR53,
VAR38);
input VAR31;
input [11:0] address;
input VAR27;
input VAR48;
input [3:0] VAR50;
input VAR53;
output [3:0] VAR38;
parameter VAR54 = "";
tri0 VAR31;
tri1 VAR27;
tri1 VAR48;
wire [3:0] VAR6;
wire [3:0] VAR38 = VAR6[3:0];
VAR35 VAR45 (
.VAR22 (VAR31),
.VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4/sky130_fd_sc_hd__and4.functional.pp.v | 1,837 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR11 ,
VAR14 ,
VAR6 ,
VAR4,
VAR10,
VAR13 ,
VAR9
);
output VAR7 ;
input VAR2 ;
input VAR11 ;
input VAR14 ;
input VAR6 ;
input VAR4;
input VAR10;
input VAR13 ;
input VAR9 ;
wire VAR8 ;
wire VAR12;
and VAR1 (VAR8 , VAR2, VAR11, VAR14, VAR6 );
VAR5 VAR3 (VAR12, VAR8, VAR4, VAR10);
buf VAR15 ... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/Tiger4NSC/src/PageDecoderTop.v | 17,922 | module MODULE1
parameter VAR5 = 2,
parameter VAR6 = 12,
parameter VAR58 = 9,
parameter VAR120 = 32,
parameter VAR76 = 27,
parameter VAR99 = 15
)
(
VAR135 ,
VAR102 ,
VAR104 ,
VAR122 ,
VAR62 ,
VAR119 ,
VAR54 ,
VAR66 ,
VAR4 ,
VAR39 ,
VAR132 ,
VAR48 ,
VAR45 ,
VAR35 ,
VAR27 ,
VAR78 ,
VAR77 ,
VAR91 ,
VAR9 ,
VAR46 ,
VAR65 ,
V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp.symbol.v | 1,514 | module MODULE1 (
input VAR4 ,
output VAR1 ,
input VAR10,
input VAR3 ,
input VAR2 ,
input VAR7
);
supply1 VAR5;
supply0 VAR9;
supply1 VAR8 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21bo/sky130_fd_sc_lp__a21bo.functional.v | 1,483 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR7 ,
VAR8
);
output VAR4 ;
input VAR6 ;
input VAR7 ;
input VAR8;
wire VAR5 ;
wire VAR2;
nand VAR9 (VAR5 , VAR7, VAR6 );
nand VAR1 (VAR2, VAR8, VAR5);
buf VAR3 (VAR4 , VAR2 );
endmodule | apache-2.0 |
eSedano/vrudy | rtl/dpth_addr.v | 3,723 | module MODULE1 (
input wire clk,
input wire VAR4,
input wire [7:0] VAR8,
input wire [7:0] VAR3,
input wire VAR10,
input wire VAR9,
input wire VAR2,
output wire [7:0] VAR13
);
wire [7:0] VAR5;
wire [7:0] VAR12;
reg [7:0] VAR6;
reg [7:0] VAR7;
always @(negedge VAR4, posedge clk)
begin: VAR1
if (VAR4 == 1'b0)
VAR6 <= {8{1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/fill/sky130_fd_sc_hvl__fill.functional.pp.v | 1,151 | module MODULE1 (
VAR4,
VAR2,
VAR3 ,
VAR1
);
input VAR4;
input VAR2;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
azonenberg/yosys | techlibs/intel/max10/cells_map.v | 3,553 | module \VAR6 (input VAR43, VAR26, output VAR36);
parameter VAR28="VAR25";
VAR21 #(.VAR40(VAR28)) VAR3 (.VAR14(VAR43), .VAR37(VAR36), .clk(VAR26), .VAR42(1'b1), .VAR8(1'b1), .VAR13(1'b1), .VAR27(1'b0), .VAR12(1'b0), .VAR23(1'b0), .VAR30(1'b0));
endmodule
module \VAR9 (input VAR43, VAR26, output VAR36);
parameter VAR28="... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/diode/sky130_fd_sc_ls__diode.pp.symbol.v | 1,213 | module MODULE1 (
input VAR2,
input VAR3 ,
input VAR5 ,
input VAR1 ,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311oi/sky130_fd_sc_hd__a311oi_2.v | 2,450 | module MODULE1 (
VAR10 ,
VAR11 ,
VAR3 ,
VAR7 ,
VAR9 ,
VAR5 ,
VAR4,
VAR2,
VAR12 ,
VAR8
);
output VAR10 ;
input VAR11 ;
input VAR3 ;
input VAR7 ;
input VAR9 ;
input VAR5 ;
input VAR4;
input VAR2;
input VAR12 ;
input VAR8 ;
VAR6 VAR1 (
.VAR10(VAR10),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4... | apache-2.0 |
kylemsguy/FPGA-Litecoin-Miner | experimental/LX150-EIGHT-C/salsa_piped.v | 8,357 | module MODULE2 (clk, VAR14, VAR49, VAR27, VAR20, VAR54, VAR84, VAR119);
input clk;
input VAR14;
input [511:0]VAR49;
input [511:0]VAR27;
output [511:0]VAR20;
output [511:0]VAR54; output [511:0]VAR84; output [9:0]VAR119;
wire [511:0]VAR154; wire [511:0]VAR151;
wire [511:0]VAR38; reg [511:0]VAR62; reg [511:0]VAR106;
wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.v | 2,406 | module MODULE2 (
VAR2 ,
VAR9,
VAR10,
VAR5 ,
VAR3 ,
VAR4,
VAR11,
VAR6 ,
VAR1
);
output VAR2 ;
input VAR9;
input VAR10;
input VAR5 ;
input VAR3 ;
input VAR4;
input VAR11;
input VAR6 ;
input VAR1 ;
VAR8 VAR7 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR1... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/general/sirv_1cyc_sram_ctrl.v | 3,694 | module MODULE1 #(
parameter VAR5 = 32,
parameter VAR34 = 4,
parameter VAR22 = 32,
parameter VAR29 = 3,
parameter VAR30 = 3
)(
output VAR2,
input VAR40,
input VAR18, output VAR21, input VAR1, input [VAR22-1:0] VAR17,
input [VAR5-1:0] VAR4,
input [VAR34-1:0] VAR23,
input [VAR30-1:0] VAR16,
output VAR19, input VAR41, outp... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211o/sky130_fd_sc_ms__a211o.behavioral.pp.v | 2,032 | module MODULE1 (
VAR13 ,
VAR10 ,
VAR15 ,
VAR6 ,
VAR12 ,
VAR4,
VAR8,
VAR9 ,
VAR1
);
output VAR13 ;
input VAR10 ;
input VAR15 ;
input VAR6 ;
input VAR12 ;
input VAR4;
input VAR8;
input VAR9 ;
input VAR1 ;
wire VAR16 ;
wire VAR3 ;
wire VAR5;
and VAR2 (VAR16 , VAR10, VAR15 );
or VAR11 (VAR3 , VAR16, VAR12, VAR6 );
VAR17 VA... | apache-2.0 |
bluespec/Flute | builds/RV64ACIMU_Flute_verilator/Verilog_RTL/mkGPR_RegFile.v | 6,954 | module MODULE1(VAR28,
VAR43,
VAR54,
VAR58,
VAR6,
VAR59,
VAR47,
VAR62,
VAR71,
VAR17,
VAR1,
VAR23,
VAR48,
VAR56,
VAR29);
input VAR28;
input VAR43;
input VAR54;
output VAR58;
input VAR6;
output VAR59;
input [4 : 0] VAR47;
output [63 : 0] VAR62;
input [4 : 0] VAR71;
output [63 : 0] VAR17;
input [4 : 0] VAR1;
output [63 : 0... | apache-2.0 |
cwilkens/fpga-hero-ii | fpga-hero-ii.srcs/sources_1/new/sram_interface.v | 2,057 | module MODULE1(rst, clk, addr, dout, VAR3, VAR4, VAR1, VAR10, VAR11, VAR9, VAR12, VAR8, VAR7, VAR6, VAR5);
input clk, rst;
input [23:0] addr;
output reg [15:0] dout;
output VAR3;
output VAR4, VAR1, VAR10, VAR11, VAR9, VAR8, VAR7;
output [22:0] VAR5;
output VAR12;
inout [15:0] VAR6;
assign VAR4 = 0;
assign VAR1 = 0;
ass... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai.behavioral.pp.v | 2,085 | module MODULE1 (
VAR5,
VAR10,
VAR8 ,
VAR6,
VAR7,
VAR3 ,
VAR16
);
input VAR5;
input VAR10;
output VAR8 ;
input VAR6;
input VAR7;
input VAR3 ;
input VAR16 ;
wire VAR16 VAR15 ;
wire VAR16 VAR17 ;
wire VAR4 ;
wire VAR14;
nand VAR13 (VAR15 , VAR7, VAR6 );
or VAR9 (VAR17 , VAR16, VAR3 );
nand VAR1 (VAR4 , VAR15, VAR17 );
VAR... | apache-2.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/sgpr/sgpr.v | 12,268 | module MODULE1(
VAR70,
VAR186,
VAR142,
VAR41,
VAR93,
VAR103,
VAR26,
VAR39,
VAR166,
VAR207,
VAR37,
VAR104,
VAR134,
VAR159,
VAR197,
VAR9,
VAR106,
VAR75,
VAR201,
VAR143,
VAR111,
VAR124,
VAR146,
VAR114,
VAR107,
VAR165,
VAR192,
VAR12,
VAR148,
VAR58,
VAR18,
VAR68,
VAR177,
VAR175,
VAR169,
VAR154,
VAR29,
VAR74,
VAR188,
VAR32,
... | bsd-3-clause |
luke-jr/ZtexBTCMiner | fpga/ztex_ufm1_15d1.v | 3,697 | module MODULE1 (VAR70, reset, VAR52, VAR9, VAR11, VAR1, VAR27, VAR34, VAR40, read, write);
input VAR70, reset, VAR52, VAR9, VAR11, VAR1, VAR27, VAR34, VAR40;
input [7:0] read;
output [7:0] write;
reg [3:0] VAR68, VAR20;
reg VAR58, VAR56, VAR44;
reg VAR42, VAR22, VAR65;
reg [4:0] VAR46;
reg [351:0] VAR28, VAR41;
reg [95... | gpl-3.0 |
cafe-alpha/wascafe | v10/fpga_firmware/wasca/synthesis/submodules/wasca_nios2_gen2_0_cpu_debug_slave_tck.v | 8,183 | module MODULE1 (
VAR26,
VAR40,
VAR27,
VAR12,
VAR3,
VAR7,
VAR5,
VAR14,
VAR8,
VAR24,
VAR6,
VAR30,
VAR2,
VAR28,
VAR19,
VAR35,
VAR13,
VAR4,
VAR16,
VAR31,
VAR15,
VAR9,
VAR20,
VAR33,
VAR23,
VAR39,
VAR34,
VAR37,
VAR22,
VAR38,
VAR25
)
;
output [ 1: 0] VAR34;
output VAR37;
output [ 37: 0] VAR22;
output VAR38;
output VAR25;
inpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp_4.v | 2,361 | module MODULE2 (
VAR11 ,
VAR4 ,
VAR2 ,
VAR9 ,
VAR8 ,
VAR6,
VAR3,
VAR7 ,
VAR5
);
output VAR11 ;
input VAR4 ;
input VAR2 ;
input VAR9 ;
input VAR8 ;
input VAR6;
input VAR3;
input VAR7 ;
input VAR5 ;
VAR1 VAR10 (
.VAR11(VAR11),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/altera/ad_mul_u16_alt.v | 4,043 | module MODULE1 (
clk,
VAR8,
VAR19,
VAR2,
VAR10,
VAR25);
parameter VAR1 = 16;
localparam VAR15 = VAR1 - 1;
input clk;
input [15:0] VAR8;
input [15:0] VAR19;
output [31:0] VAR2;
input [VAR15:0] VAR10;
output [VAR15:0] VAR25;
reg [VAR15:0] VAR17 = 'd0;
reg [VAR15:0] VAR7 = 'd0;
reg [VAR15:0] VAR25 = 'd0;
always @(posedge ... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/fifo/fifo16s.v | 3,774 | module MODULE1 (
VAR18,
VAR21,
VAR10, VAR2, VAR14,
VAR7,
VAR12,
VAR17
);
parameter VAR9 = 16;
parameter VAR19 = VAR9 - 1;
input VAR18;
input VAR21;
input VAR10;
input VAR2;
input [VAR19:0] VAR14;
output [VAR19:0] VAR7;
output VAR12;
output VAR17;
reg [4:0] VAR8 = 5'h0;
reg [4:0] VAR16 = 5'h0;
wire VAR3;
reg [VAR19:0] V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/decap/sky130_fd_sc_hdll__decap.pp.symbol.v | 1,208 | module MODULE1 (
input VAR4 ,
input VAR3,
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41o/sky130_fd_sc_ls__a41o.pp.symbol.v | 1,388 | module MODULE1 (
input VAR6 ,
input VAR2 ,
input VAR8 ,
input VAR10 ,
input VAR3 ,
output VAR4 ,
input VAR7 ,
input VAR5,
input VAR9,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4bb/sky130_fd_sc_hdll__and4bb_2.v | 2,339 | module MODULE2 (
VAR7 ,
VAR9 ,
VAR5 ,
VAR6 ,
VAR4 ,
VAR3,
VAR11,
VAR10 ,
VAR2
);
output VAR7 ;
input VAR9 ;
input VAR5 ;
input VAR6 ;
input VAR4 ;
input VAR3;
input VAR11;
input VAR10 ;
input VAR2 ;
VAR8 VAR1 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR10(VAR10),
.... | apache-2.0 |
eda-globetrotter/PicenoDecoders | viterbi/syn/src/pipe2.v | 6,993 | module MODULE1 (in,out,VAR4,reset);
output [1:0] out;
input [1:0] in; input VAR4; input reset;
reg [1:0] out;
reg [1:0] o1; reg [1:0] o2; reg [1:0] o3; reg [1:0] o4; reg [1:0] o5; reg [1:0] o6; reg [1:0] o7; reg [1:0] VAR7; reg [1:0] VAR6; reg [1:0] o10; reg [1:0] o11; reg [1:0] o12; reg [1:0] o13; reg [1:0] o14;
reg [... | mit |
Gifts/descrypt-ztex-bruteforcer | user_cores/des/src/crypt_step.v | 1,358 | module MODULE1(
input [31:0] VAR13,
input [31:0] VAR6,
input [59:0] VAR15,
input VAR16,
output [31:0] VAR4,
output [31:0] VAR12
);
wire [31:0]VAR3;
wire [31:0]VAR11;
wire [31:0]VAR10;
VAR5 VAR8(VAR6, VAR15, VAR10, VAR16);
VAR17 VAR7(VAR13, VAR11, VAR16);
VAR14 VAR2(VAR6, VAR4, VAR16);
VAR1 VAR9(VAR11, VAR10, VAR12, VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311a/sky130_fd_sc_lp__o311a.pp.symbol.v | 1,379 | module MODULE1 (
input VAR3 ,
input VAR5 ,
input VAR2 ,
input VAR10 ,
input VAR8 ,
output VAR9 ,
input VAR6 ,
input VAR4,
input VAR7,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2b/sky130_fd_sc_hdll__nor2b_2.v | 2,189 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR8 ,
VAR2,
VAR9,
VAR4 ,
VAR3
);
output VAR1 ;
input VAR5 ;
input VAR8 ;
input VAR2;
input VAR9;
input VAR4 ;
input VAR3 ;
VAR6 VAR7 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR1 ,
VAR5 ,
VAR8
);
output VAR1... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_tlfragmenter_qspi_1.v | 16,660 | module MODULE1(
input VAR11,
input reset,
output VAR238,
input VAR35,
input [2:0] VAR175,
input [2:0] VAR63,
input [2:0] VAR132,
input [1:0] VAR231,
input [29:0] VAR85,
input VAR141,
input [7:0] VAR52,
input VAR45,
output VAR89,
output [2:0] VAR144,
output [1:0] VAR202,
output [2:0] VAR37,
output [1:0] VAR65,
output [2... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_rxeq_scan.v | 14,858 | module MODULE1 #
(
parameter VAR14 = "VAR13", parameter VAR2 = "VAR17", parameter VAR6 = 1, parameter VAR46 = 22'd3125000, parameter VAR40 = 23'd4687500 )
(
input VAR48,
input VAR44,
input [ 1:0] VAR36,
input [ 2:0] VAR21,
input VAR45,
input [ 3:0] VAR35,
input [17:0] VAR50,
input VAR20,
input [ 5:0] VAR5,
input [ 5:0]... | gpl-3.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/BRAM1Load.v | 3,044 | module MODULE1(VAR2,
VAR8,
VAR12,
VAR5,
VAR3,
VAR15
);
parameter VAR11 = "";
parameter VAR9 = 0;
parameter VAR4 = 1;
parameter VAR10 = 1;
parameter VAR1 = 1;
parameter VAR14 = 0;
input VAR2;
input VAR8;
input VAR12;
input [VAR4-1:0] VAR5;
input [VAR10-1:0] VAR3;
output [VAR10-1:0] VAR15;
reg [VAR10-1:0] VAR13[0:VAR1-1]... | lgpl-3.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/vfabric_fsub.v | 2,585 | module MODULE1(VAR10, VAR27,
VAR30, VAR31, VAR16,
VAR5, VAR32, VAR9,
VAR21, VAR34, VAR25);
parameter VAR26 = 32;
parameter VAR15 = 8;
parameter VAR24 = 64;
input VAR10, VAR27;
input [VAR26-1:0] VAR30;
input [VAR26-1:0] VAR5;
input VAR31, VAR32;
output VAR16, VAR9;
output [VAR26-1:0] VAR21;
output VAR34;
input VAR25;
wi... | mit |
UA3MQJ/fpga-synth | modules/voice_ssaw.v | 15,224 | module MODULE1(clk, VAR21, VAR44, VAR5, VAR56, VAR63, VAR49, VAR4, VAR26, VAR3, VAR17, VAR8, VAR41, VAR64, VAR18);
input wire clk;
input wire VAR21;
input wire [6:0] VAR44;
input wire [6:0] VAR56;
input wire [6:0] VAR63;
input wire [13:0] VAR5;
output wire [7:0] VAR4;
input wire [2:0] VAR49;
output wire [7:0] VAR26, VA... | gpl-3.0 |
archlabo/Frix | fpga/de2-115/rtl/clock/clock.v | 2,118 | module MODULE1( input wire VAR15,
input wire VAR12,
output wire VAR2,
output wire VAR9,
output wire VAR6
);
wire VAR5, VAR11, VAR13;
wire VAR8;
VAR7 VAR4(VAR15, VAR2, VAR9, VAR5);
MODULE2 MODULE1(VAR2, (VAR12 & VAR5), VAR6);
endmodule
module MODULE2(VAR10, VAR1, VAR3);
input VAR10, VAR1;
output VAR3;
reg [7:0] VAR16;
a... | bsd-2-clause |
ncos/Xilinx-Verilog | GYRACC/src/GYRO/display_controller.v | 4,695 | module MODULE1(
clk,
rst,
sel,
VAR19,
VAR39,
VAR31,
VAR30,
VAR42,
VAR10,
VAR24,
VAR43,
VAR15
);
input clk;
input rst;
input [1:0] sel;
input [7:0] VAR19;
input [15:0] VAR39;
input [15:0] VAR31;
input [15:0] VAR30;
input VAR43;
output VAR42;
output [3:0] VAR10;
output [6:0] VAR24;
output [15:0] VAR15;
wire [1:0] VAR3;
w... | mit |
EmbeddedANT/XILINX_Spartan3AN-StarterKit | Spartan3AN_PicoBlaze_Leds/picoblze/bbfifo_16x8.v | 12,628 | module MODULE1
(VAR11,
VAR26,
reset,
write,
read,
VAR10,
VAR14,
VAR50,
clk);
input [7:0] VAR11;
output [7:0] VAR26;
input reset;
input write;
input read;
output VAR10;
output VAR14;
output VAR50;
input clk;
wire [3:0] VAR20;
wire [3:0] VAR24;
wire [3:0] VAR54;
wire [2:0] VAR35;
wire VAR55;
wire VAR57;
wire VAR16;
wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.v | 2,154 | module MODULE2 (
VAR7 ,
VAR4 ,
VAR9 ,
VAR5 ,
VAR3,
VAR8 ,
VAR1
);
output VAR7 ;
input VAR4 ;
input VAR9 ;
input VAR5 ;
input VAR3;
input VAR8 ;
input VAR1 ;
VAR6 VAR2 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR7,
VAR4
);
output VAR7;
inpu... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/user_data_path.v | 17,883 | module MODULE1
parameter VAR17=VAR28/8,
parameter VAR13 = 2,
parameter VAR77 = 32,
parameter VAR93 = 32,
parameter VAR40 = 2,
parameter VAR157 = 8,
parameter VAR29 = 8,
parameter VAR139 = VAR28+VAR17,
parameter VAR109 = 19)
(
input [VAR28-1:0] VAR54,
input [VAR17-1:0] VAR24,
input VAR67,
output VAR146,
input [VAR28-1:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probe_p/sky130_fd_sc_hd__probe_p.blackbox.v | 1,243 | module MODULE1 (
VAR5,
VAR6
);
output VAR5;
input VAR6;
supply0 VAR3;
supply0 VAR4 ;
supply1 VAR1 ;
supply1 VAR2;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/ad9434_fmc/common/ad9434_spi.v | 3,593 | module MODULE1 (
VAR7,
VAR14,
VAR10,
VAR12,
VAR4);
input [ 1:0] VAR7;
input VAR14;
input VAR10;
output VAR12;
inout VAR4;
reg [ 5:0] VAR6 = 'd0;
reg VAR16 = 'd0;
reg VAR1 = 'd0;
wire VAR2;
wire VAR5;
assign VAR2 = & VAR7;
assign VAR5 = VAR1 & ~VAR2;
always @(posedge VAR14 or posedge VAR2) begin
if (VAR2 == 1'b1) begin
... | gpl-3.0 |
KestrelComputer/polaris | bottleneck/rtl/verilog/bottleneckSequencer.v | 7,297 | module MODULE1(
input VAR23,
input VAR113,
input VAR87,
input VAR13,
input VAR24,
input VAR133,
input VAR49,
input VAR107,
input VAR89,
input VAR15,
input VAR69,
input VAR3,
output VAR44,
output VAR32,
output VAR96,
output VAR67,
output VAR123,
output VAR83,
output VAR58,
output VAR120,
output VAR119,
output VAR130,
ou... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtp/sky130_fd_sc_ms__dlrtp_4.v | 2,362 | module MODULE1 (
VAR10 ,
VAR9,
VAR2 ,
VAR4 ,
VAR3 ,
VAR1 ,
VAR7 ,
VAR6
);
output VAR10 ;
input VAR9;
input VAR2 ;
input VAR4 ;
input VAR3 ;
input VAR1 ;
input VAR7 ;
input VAR6 ;
VAR8 VAR5 (
.VAR10(VAR10),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODU... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xbar_1/synth/zqynq_lab_1_design_xbar_1.v | 23,470 | module MODULE1 (
VAR2,
VAR118,
VAR64,
VAR12,
VAR116,
VAR51,
VAR75,
VAR19,
VAR74,
VAR54,
VAR92,
VAR16,
VAR38,
VAR105,
VAR115,
VAR61,
VAR25,
VAR70,
VAR124,
VAR107,
VAR14,
VAR32,
VAR84,
VAR73,
VAR121,
VAR78,
VAR122,
VAR30,
VAR33,
VAR27,
VAR45,
VAR131,
VAR96,
VAR50,
VAR95,
VAR37,
VAR102,
VAR48,
VAR127,
VAR22,
VAR36,
VAR29,... | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/hostController/hostcontroller.v | 12,744 | module MODULE1 (VAR31, VAR24, clk, VAR35, VAR40, VAR4, rst, VAR1, VAR69, VAR75, VAR14, VAR9, VAR44, VAR57, VAR36);
input [7:0] VAR31;
input clk;
input VAR40;
input VAR4;
input rst;
input VAR1;
input VAR14;
input VAR57;
input [1:0] VAR36;
output VAR24;
output VAR35;
output VAR69;
output [3:0] VAR75;
output VAR9;
output ... | gpl-3.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/synth/ghrd_10as066n2_f2sdram0_m.v | 2,076 | module MODULE1 (
input wire VAR15, input wire VAR2, output wire [31:0] VAR13, input wire [31:0] VAR10, output wire VAR11, output wire VAR14, output wire [31:0] VAR16, input wire VAR3, input wire VAR1, output wire [3:0] VAR12, output wire VAR6 );
VAR9 #(
.VAR5 (0),
.VAR8 (50000),
.VAR7 (2)
) VAR4 (
.VAR15 (VAR15), .VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fahcon/sky130_fd_sc_hs__fahcon.pp.blackbox.v | 1,335 | module MODULE1 (
VAR4,
VAR6 ,
VAR3 ,
VAR5 ,
VAR7 ,
VAR1 ,
VAR2
);
output VAR4;
output VAR6 ;
input VAR3 ;
input VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/a79f7727e74fe6ae/zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_stub.v | 1,748 | module MODULE1(VAR10, VAR4, VAR6, VAR13, VAR1, VAR5, VAR7, VAR9, VAR3, VAR2,
VAR14, VAR11, VAR12, VAR8)
;
input VAR10;
input VAR4;
input VAR6;
input [3:0]VAR13;
input [31:0]VAR1;
input [31:0]VAR5;
output [31:0]VAR7;
input VAR9;
input VAR3;
input VAR2;
input [3:0]VAR14;
input [31:0]VAR11;
input [31:0]VAR12;
output [31:0... | mit |
dm-urievich/afc-smm | software/third-patry/pipelined_fft_256/trunk/SRC/fft256.v | 8,660 | module MODULE1 ( VAR45 ,VAR12 ,VAR11 ,VAR56 ,VAR7 ,VAR27 ,VAR34 ,VAR15 ,VAR44 ,VAR38 ,VAR18 ,VAR21 ,VAR9 );
output VAR15 ; wire VAR15 ;
output VAR44 ; wire VAR44 ;
output VAR38 ; wire VAR38 ;
output [7:0] VAR18 ; wire [7:0] VAR18 ;
output [VAR26+3:0] VAR21 ; wire [VAR26+3:0] VAR21 ; output [VAR26+3:0] VAR9 ; wire [VAR2... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_1.behavioral.pp.v | 7,224 | module MODULE1( VAR11, VAR4, VAR5, VAR10, VAR3, VAR8, VAR9, VAR7, VAR2 );
input VAR9, VAR8, VAR10, VAR3, VAR4, VAR11;
inout VAR7, VAR2;
output VAR5;
VAR1 VAR12(.VAR11(VAR11),.VAR4(VAR4),.VAR5(VAR5),.VAR10(VAR10),.VAR3(VAR3),.VAR8(VAR8),.VAR9(VAR9),.VAR7(VAR7),.VAR2(VAR2));
VAR1 VAR6(.VAR11(VAR11),.VAR4(VAR4),.VAR5(VAR5... | apache-2.0 |
sh-chris110/chris | FPGA/chris/db/ip/soc_design/submodules/soc_design_SystemID.v | 2,203 | module MODULE1 (
address,
VAR1,
VAR2,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR1;
input VAR2;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1504770449 : 255;
endmodule | gpl-2.0 |
perillamint/verilogmaze | maprom1.v | 1,045 | module MODULE1(clk, en, addr, VAR1);
input clk;
input en;
input [3:0] addr;
output reg [7:0] VAR1;
always @(posedge clk)
begin
if(en)
begin
case(addr)
4'b0000: VAR1 <= 8'b11111111;
4'b0001: VAR1 <= 8'b10000001;
4'b0010: VAR1 <= 8'b11101111;
4'b0011: VAR1 <= 8'b01100100;
4'b0100: VAR1 <= 8'b11110111;
4'b0101: VAR1 <= 8'... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/conb/sky130_fd_sc_ms__conb.behavioral.v | 1,279 | module MODULE1 (
VAR3,
VAR6
);
output VAR3;
output VAR6;
supply1 VAR7;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR5 ;
pullup VAR2 (VAR3 );
pulldown VAR1 (VAR6 );
endmodule | apache-2.0 |
juan199/Lab_Digitales | Proyecto/controlador.v | 5,646 | module MODULE1 (
input wire clk,
input wire reset,
output wire VAR24,
output wire VAR30,
output wire VAR42,
output wire VAR20,
output wire VAR21,
output wire VAR31,
output wire VAR43,
output wire VAR17,
output wire VAR15,
output wire VAR36,
output wire VAR23,
output wire VAR2,
output wire VAR9,
output wire VAR37,
outpu... | lgpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/example_design/rtl/traffic_gen/read_posted_fifo.v | 8,046 | module MODULE1 #
(
parameter VAR6 = 100,
parameter VAR1 = "VAR43",
parameter VAR40 = 4,
parameter VAR22 = 32,
parameter VAR39 = 6
)
(
input VAR28,
input VAR2,
output reg VAR32,
input VAR19,
input VAR33,
input VAR45,
input VAR47,
input [VAR22-1:0] VAR11,
input [VAR39-1:0] VAR10,
input [2:0] VAR49,
input [5:0] VAR36 ,
in... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkmux2/sky130_fd_sc_hdll__clkmux2_4.v | 2,223 | module MODULE2 (
VAR2 ,
VAR3 ,
VAR10 ,
VAR6 ,
VAR5,
VAR4,
VAR9 ,
VAR7
);
output VAR2 ;
input VAR3 ;
input VAR10 ;
input VAR6 ;
input VAR5;
input VAR4;
input VAR9 ;
input VAR7 ;
VAR1 VAR8 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/hostController/directcontrol.v | 7,137 | module MODULE1 (VAR18, VAR22, VAR3, VAR6, VAR26, VAR2, clk, VAR5, VAR14, rst);
input VAR3;
input VAR6;
input clk;
input VAR5;
input [1:0] VAR14;
input rst;
output [7:0] VAR18;
output [7:0] VAR22;
output VAR26;
output VAR2;
reg [7:0] VAR18, VAR10;
reg [7:0] VAR22, VAR1;
wire VAR3;
wire VAR6;
reg VAR26, VAR24;
reg VAR2, ... | gpl-3.0 |
linuxbest/lzs | common/fifo_control.v | 12,829 | module MODULE1
(
VAR46,
VAR21,
VAR13,
VAR18,
VAR23,
VAR14,
VAR29,
VAR34,
VAR45,
VAR39,
VAR38,
VAR4,
VAR17,
VAR44,
VAR3,
VAR10,
VAR27
);
parameter VAR37 = 7 ;
input VAR46, VAR21;
input VAR13, VAR18;
input VAR23, VAR14;
output VAR29, VAR45;
output VAR34, VAR39;
output [(VAR37 - 1):0] VAR38, VAR4;
output VAR17, VAR44 ;
ou... | gpl-2.0 |
jairov4/accel-oil | solution_kintex7/impl/verilog/nfa_accept_sample.v | 48,630 | module MODULE1 (
VAR198,
VAR148,
VAR136,
VAR94,
VAR13,
VAR73,
VAR9,
VAR18,
VAR133,
VAR195,
VAR184,
VAR146,
VAR302,
VAR86,
VAR206,
VAR152,
VAR48,
VAR202,
VAR176,
VAR179,
VAR208,
VAR306,
VAR256,
VAR174,
VAR248,
VAR41,
VAR161,
VAR109,
VAR101,
VAR188,
VAR193,
VAR164,
VAR226,
VAR264,
VAR236,
VAR269,
VAR56,
VAR143,
VAR142,
V... | lgpl-3.0 |
samyk/proxmark3 | fpga/fpga_felica.v | 9,093 | module MODULE1(
input VAR81, output VAR38, input VAR16, input VAR49,
input VAR52, input VAR5, input VAR24,
output VAR27, output VAR76,
output VAR48, output VAR26, output VAR36, output VAR25,
input [7:0] VAR56, output VAR64, output VAR83,
output VAR50, output VAR62, input VAR23, output VAR66,
input VAR73, input VAR19,
o... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3b/sky130_fd_sc_ls__or3b_2.v | 2,209 | module MODULE2 (
VAR3 ,
VAR8 ,
VAR2 ,
VAR10 ,
VAR4,
VAR5,
VAR7 ,
VAR9
);
output VAR3 ;
input VAR8 ;
input VAR2 ;
input VAR10 ;
input VAR4;
input VAR5;
input VAR7 ;
input VAR9 ;
VAR6 VAR1 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
dmlloyd/PBIBox | pbibox/cpld/PBIBox.v | 1,484 | module MODULE1(
input [15:0] VAR6,
input VAR12,
output VAR5,
input VAR3,
output VAR8,
input VAR1,
input VAR2,
output VAR11,
output VAR10,
output VAR9,
output VAR7
);
assign VAR11 = (VAR6 == 'hD1FF) ? 'b0 : 'VAR4;
assign VAR10 = (VAR6[15:8] == 'hD1) && (VAR6[7:0] != 'hFF) ? 'b0 : 'VAR4;
assign VAR9 = (VAR6[15:9] == ('hD... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor2/sky130_fd_sc_hdll__xnor2.symbol.v | 1,309 | module MODULE1 (
input VAR3,
input VAR4,
output VAR2
);
supply1 VAR1;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/submodules/wasca_onchip_memory2_0.v | 2,887 | module MODULE1 (
address,
VAR4,
VAR31,
clk,
VAR6,
reset,
VAR22,
write,
VAR25,
VAR24
)
;
output [ 31: 0] VAR24;
input [ 11: 0] address;
input [ 3: 0] VAR4;
input VAR31;
input clk;
input VAR6;
input reset;
input VAR22;
input write;
input [ 31: 0] VAR25;
wire VAR9;
wire [ 31: 0] VAR24;
wire VAR5;
assign VAR5 = VAR31 & wri... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Complex_Multiply.v | 1,979 | module MODULE1
(
VAR8,
VAR5,
VAR11,
VAR2,
VAR12,
VAR4
);
input signed [17:0] VAR8; input signed [17:0] VAR5; input signed [17:0] VAR11; input signed [17:0] VAR2; output signed [35:0] VAR12; output signed [35:0] VAR4;
wire signed [35:0] VAR10; wire signed [35:0] VAR7; wire signed [35:0] VAR9; wire signed [35:0] VAR1; wi... | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_AsyncResetRegVec_67.v | 15,182 | module MODULE1(
input VAR177,
input reset,
input [31:0] VAR246,
output [31:0] VAR106,
input VAR28
);
wire VAR261;
wire VAR221;
wire VAR129;
wire VAR62;
wire VAR11;
wire VAR143;
wire VAR211;
wire VAR49;
wire VAR75;
wire VAR257;
wire VAR68;
wire VAR118;
wire VAR138;
wire VAR213;
wire VAR54;
wire VAR37;
wire VAR253;
wire ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_p_pp_pkg_s/sky130_fd_sc_lp__udp_dlatch_p_pp_pkg_s.blackbox.v | 1,448 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR3 ,
VAR5,
VAR1 ,
VAR6 ,
VAR7
);
output VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR5;
input VAR1 ;
input VAR6 ;
input VAR7 ;
endmodule | apache-2.0 |
kigawas/MipsCPU | CPU/alu.v | 5,920 | module MODULE1(
input [31:0] VAR20,
input [31:0] VAR21,
input [3:0] VAR2,
output [31:0] VAR18,
output VAR7,
output VAR23,
output VAR24,
output VAR1
);
reg VAR28;
reg VAR14;
reg VAR22;
reg VAR8;
reg [31:0] VAR5;
assign VAR18=VAR5;
assign VAR7=VAR28;
assign VAR23=VAR14;
assign VAR24=VAR22;
assign VAR1=VAR8;
wire [31:0] V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfstp/sky130_fd_sc_hs__dfstp_4.v | 2,142 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR6 ,
VAR7,
VAR8 ,
VAR4
);
input VAR5 ;
input VAR2 ;
output VAR6 ;
input VAR7;
input VAR8 ;
input VAR4 ;
VAR3 VAR1 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR5 ,
VAR2 ,
VAR6 ,
VAR7
);
input VAR5 ;
input VAR2 ;
output VA... | apache-2.0 |
bluespec/Flute | src_SSITH_P2/xilinx_ip/hdl/mkDM_Mem_Tap.v | 35,195 | module MODULE1(VAR161,
VAR8,
VAR203,
VAR80,
VAR51,
VAR48,
VAR56,
VAR139,
VAR145,
VAR175,
VAR22,
VAR197,
VAR30,
VAR214,
VAR190,
VAR132,
VAR109,
VAR208,
VAR148,
VAR5,
VAR4,
VAR71,
VAR142,
VAR38,
VAR7,
VAR167,
VAR207,
VAR92,
VAR124,
VAR14,
VAR107,
VAR113,
VAR213,
VAR183,
VAR10,
VAR44,
VAR101,
VAR182,
VAR138,
VAR29,
VAR86,... | apache-2.0 |
olgirard/openmsp430 | core/synthesis/xilinx/src/openMSP430_fpga.v | 9,529 | module MODULE1 (
VAR1, VAR39, VAR54, VAR50, VAR12, VAR26, VAR28, VAR37, VAR59,
VAR34, VAR35, irq, VAR6, VAR43, VAR38, VAR23 );
output VAR1; output VAR39; output VAR54; output [13:0] VAR50; output [7:0] VAR12; output [15:0] VAR26; output [1:0] VAR28; output VAR37; output VAR59;
input VAR34; input VAR35; input [13:0] irq... | bsd-3-clause |
arthurafarias/UFCG-EE-LASD-2014.1-Experiments | experimento-2.stable/Datapath_RegisterFile.v | 1,091 | module MODULE1(
output reg [VAR6-1:0] VAR9, VAR8,
input [VAR6-1:0] VAR2,
input [2:0] VAR5, VAR11, VAR1,
input VAR4, VAR3
);
parameter VAR6 = 16;
reg [VAR6-1:0] VAR7[7:0];
always@(posedge VAR3)
if(VAR4)
case(VAR1)
3'VAR10 000 : VAR7[0] = VAR2;
3'VAR10 001 : VAR7[1] = VAR2;
3'VAR10 010 : VAR7[2] = VAR2;
3'VAR10 011 : VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi.symbol.v | 1,424 | module MODULE1 (
input VAR5,
input VAR2,
input VAR3 ,
input VAR4 ,
output VAR7
);
supply1 VAR1;
supply0 VAR6;
endmodule | apache-2.0 |
briburrell/amica | device/natura_salsa8/natura_salsa8.srcs/sources_1/imports/natura_salsa8/salsa_eight.v | 9,002 | module MODULE2 (clk, VAR121, VAR76, VAR135, VAR68, VAR116);
input clk;
input [511:0]VAR121;
input [511:0]VAR76;
output [511:0]VAR135; output [511:0]VAR68; output [9:0] VAR116;
wire [9:0] VAR17, VAR107, VAR112, VAR16, VAR29, VAR7, VAR125, VAR9;
reg [511:0]VAR144, VAR72;
reg [511:0]VAR75, VAR3;
reg [511:0]VAR13, VAR108;
... | gpl-3.0 |
sh-chris110/chris | FPGA/uCos/system/synthesis/system.v | 28,905 | module MODULE1 (
output wire [12:0] VAR95, output wire [1:0] VAR137, output wire VAR229, output wire VAR58, output wire VAR45, inout wire [15:0] VAR216, output wire [1:0] VAR99, output wire VAR97, output wire VAR119, output wire VAR83, input wire VAR64, input wire VAR133 );
wire VAR206; wire [31:0] VAR185; wire VAR30; ... | gpl-2.0 |
sirchuckalot/zet | cores/timer/rtl/timer.v | 6,543 | module MODULE1
(
input VAR15,
input VAR32,
input VAR30,
input [1:0] VAR38,
input [15:0] VAR24,
output reg [15:0] VAR3,
input VAR43,
input VAR9,
input VAR40,
output VAR1,
output reg VAR6,
input VAR12, input VAR27,
output VAR42
);
wire [15:0] VAR18;
wire VAR21;
wire VAR46;
wire [1:0] VAR36;
reg [15:0] VAR18;
reg VAR21;
r... | gpl-3.0 |
rbarzic/arty-cm0-designstart | ips/clock_manager/arty_mmcm/arty_mmcm.v | 3,975 | module MODULE1
(
input VAR1,
output VAR5,
input VAR4,
output VAR3
);
VAR6 VAR2
(
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule | gpl-2.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_audio_in_deserializer.v | 9,330 | module MODULE1 (
clk,
reset,
VAR8,
VAR19,
VAR3,
VAR36,
VAR26,
VAR6,
VAR17,
VAR7,
VAR16,
VAR4,
VAR13,
VAR35
);
parameter VAR11 = 15;
parameter VAR29 = 5'h0F;
input clk;
input reset;
input VAR8;
input VAR19;
input VAR3;
input VAR36;
input VAR26;
input VAR6;
input VAR17;
input VAR7;
output reg [ 7: 0] VAR16;
output reg [ ... | mit |
monotone-RK/FACE | IEICE-Trans/data_compression/4-way_2-tree/src/ip_pcie/source/PCIeGen2x8If128_axi_basic_rx_pipeline.v | 26,724 | module MODULE1 #(
parameter VAR47 = 128, parameter VAR33 = "VAR55", parameter VAR43 = 1,
parameter VAR22 = (VAR47 == 128) ? 2 : 1, parameter VAR31 = VAR47 / 8 ) (
output reg [VAR47-1:0] VAR64, output reg VAR74, input VAR57, output [VAR31-1:0] VAR71, output VAR72, output reg [21:0] VAR86,
input [VAR47-1:0] VAR34, input ... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_39.v | 26,131 | module MODULE3 (
clk,
reset,
VAR205,
VAR230,
VAR188,
VAR19,
VAR113
);
parameter VAR91 = 18;
parameter VAR174 = 39;
parameter VAR39 = 20;
localparam VAR125 = 40;
input clk;
input reset;
input VAR205;
input VAR230;
input [VAR91-1:0] VAR188; output VAR19;
output [VAR91-1:0] VAR113;
localparam VAR99 = 18; localparam VAR118... | mit |
MarcoVogt/basil | firmware/modules/gpac_adc_rx/gpac_adc_rx.v | 1,956 | module MODULE1
parameter VAR19 = 16'h0000,
parameter VAR5 = 16'h0000,
parameter VAR24 = 16,
parameter [1:0] VAR30 = 0,
parameter [0:0] VAR29 = 0
)
(
input wire VAR3,
input wire [13:0] VAR17,
input wire VAR25,
input wire VAR2,
input wire VAR14,
output wire VAR12,
output wire [31:0] VAR8,
input wire VAR1,
input wire VAR2... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32a/sky130_fd_sc_ls__o32a.behavioral.v | 1,635 | module MODULE1 (
VAR14 ,
VAR12,
VAR3,
VAR5,
VAR17,
VAR6
);
output VAR14 ;
input VAR12;
input VAR3;
input VAR5;
input VAR17;
input VAR6;
supply1 VAR9;
supply0 VAR16;
supply1 VAR11 ;
supply0 VAR2 ;
wire VAR1 ;
wire VAR4 ;
wire VAR15;
or VAR10 (VAR1 , VAR3, VAR12, VAR5 );
or VAR8 (VAR4 , VAR6, VAR17 );
and VAR13 (VAR15, V... | apache-2.0 |
secworks/siphash | src/rtl/siphash.v | 9,623 | module MODULE1(
input wire clk,
input wire VAR62,
input wire VAR38,
input wire VAR3,
input wire [7 : 0] addr,
input wire [31 : 0] VAR68,
output wire [31 : 0] VAR45
);
localparam VAR69 = 8'h00;
localparam VAR33 = 8'h01;
localparam VAR14 = 8'h02;
localparam VAR73 = 8'h08;
localparam VAR2 = 0;
localparam VAR8 = 1;
localpa... | bsd-2-clause |
sh-chris110/chris | FPGA/chris/Qsys/soc_design/synthesis/submodules/soc_design_SystemID.v | 2,203 | module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1504770410 : 255;
endmodule | gpl-2.0 |
makestuff/swled | fifo/verilog/fifo-gen/fifo_wrapper_altera.v | 1,672 | module
MODULE1(
input wire VAR3,
output wire[7:0] VAR8,
input wire[7:0] VAR11,
input wire VAR1,
output wire VAR16,
output wire[7:0] VAR5,
output wire VAR12,
input wire VAR10
);
wire VAR6;
wire VAR7;
assign VAR16 = !VAR6;
assign VAR12 = !VAR7;
VAR19 VAR9(
.VAR2(VAR3),
.VAR14(VAR8),
.VAR18(VAR11),
.VAR17(VAR1),
.VAR4(VAR... | gpl-3.0 |
efabless/openlane | designs/usb/src/usb2p0_core.v | 32,667 | module MODULE1(
input VAR57,
input VAR38,
input VAR27,
input VAR30,
output VAR54,
output VAR64,
output VAR22,
input[6:0] VAR18,
output VAR93,
output reg VAR62,
output reg[3:0] VAR16,
output reg VAR67,
output reg VAR73,
input VAR21,
input[1:0] VAR113,
output reg[7:0] VAR100,
input[7:0] VAR83,
input VAR59,
output reg VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4/sky130_fd_sc_ms__nor4.pp.blackbox.v | 1,347 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR2 ,
VAR4 ,
VAR5 ,
VAR6,
VAR1,
VAR9 ,
VAR3
);
output VAR7 ;
input VAR8 ;
input VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR6;
input VAR1;
input VAR9 ;
input VAR3 ;
endmodule | apache-2.0 |
TonyBrewer/OpenHT | ht_lib/platform/convey/verilog/HtResetFlop2x.v | 1,254 | module MODULE1 (
input VAR11,
input VAR7,
input VAR5,
output VAR14
);
reg VAR3;
always @(posedge VAR11) begin
if (VAR5)
VAR3 <= 1'b1;
end
else
VAR3 <= 1'b0;
end
VAR8 rst (.VAR10(VAR11), .VAR12(VAR5), .VAR6(VAR3), .VAR4(!VAR3), .VAR13(VAR3));
reg VAR1;
always @(posedge VAR7) begin
VAR1 <= VAR3;
end
assign VAR14 = VAR1;
... | bsd-3-clause |
SymbiFlow/symbiflow-arch-defs | library/uart/uart.v | 1,504 | module MODULE1 (
input rst,
input clk,
input VAR1,
output VAR19,
input VAR10,
input [7:0] VAR9,
output VAR13,
output [7:0] VAR3,
output VAR2,
output VAR4
);
parameter VAR21 = 25;
parameter VAR5 = 8;
wire VAR14;
wire VAR6;
VAR22 #(.VAR21(VAR21*VAR5)) VAR17 (
.clk(clk),
.rst(rst),
.VAR8(VAR14)
);
VAR15 VAR18(
.rst(rst),
... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211a/sky130_fd_sc_hd__o211a_2.v | 2,348 | module MODULE2 (
VAR7 ,
VAR11 ,
VAR8 ,
VAR1 ,
VAR2 ,
VAR5,
VAR9,
VAR10 ,
VAR3
);
output VAR7 ;
input VAR11 ;
input VAR8 ;
input VAR1 ;
input VAR2 ;
input VAR5;
input VAR9;
input VAR10 ;
input VAR3 ;
VAR4 VAR6 (
.VAR7(VAR7),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR10(VAR10),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3b/sky130_fd_sc_lp__nor3b.symbol.v | 1,341 | module MODULE1 (
input VAR8 ,
input VAR4 ,
input VAR5,
output VAR2
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or3b/sky130_fd_sc_ms__or3b.behavioral.v | 1,467 | module MODULE1 (
VAR12 ,
VAR13 ,
VAR7 ,
VAR1
);
output VAR12 ;
input VAR13 ;
input VAR7 ;
input VAR1;
supply1 VAR3;
supply0 VAR9;
supply1 VAR6 ;
supply0 VAR5 ;
wire VAR4 ;
wire VAR8;
not VAR2 (VAR4 , VAR1 );
or VAR11 (VAR8, VAR7, VAR13, VAR4 );
buf VAR10 (VAR12 , VAR8 );
endmodule | apache-2.0 |
parallella/oh | common/hdl/oh_rsync.v | 1,059 | module MODULE1 #(parameter VAR2 = 2 )
(
input clk,
input VAR1,
output VAR3
);
VAR4 VAR4 (.clk(clk),
.VAR1(VAR1),
.VAR3(VAR3));
reg [VAR2-1:0] VAR5;
always @ (posedge clk or negedge VAR1)
if(!VAR1)
VAR5[VAR2-1:0] <= 1'b0;
else
VAR5[VAR2-1:0] <= {VAR5[VAR2-2:0],1'b1};
assign VAR3 = VAR5[VAR2-1];
endmodule | mit |
aap/pdp6 | verilog/core164.v | 9,548 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR129,
input wire VAR167,
input wire VAR79,
input wire VAR85,
input wire VAR114,
input wire VAR156,
input wire VAR54,
input wire [21:35] VAR30,
input wire [18:21] VAR87,
input wire VAR140,
input wire [0:35] VAR37,
output wire VAR88,
output wire VAR62,
output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21bo/sky130_fd_sc_lp__a21bo_m.v | 2,315 | module MODULE2 (
VAR1 ,
VAR9 ,
VAR2 ,
VAR7,
VAR5,
VAR3,
VAR10 ,
VAR8
);
output VAR1 ;
input VAR9 ;
input VAR2 ;
input VAR7;
input VAR5;
input VAR3;
input VAR10 ;
input VAR8 ;
VAR6 VAR4 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR8(VAR8)
);
endmodule
module MODULE2 ... | apache-2.0 |
cpulabs/mist1032sa | src/core/losd_store_pipe_arbiter.v | 2,551 | module MODULE1(
output wire VAR28,
input wire VAR4,
output wire [1:0] VAR37, output wire [3:0] VAR35,
output wire VAR18, output wire [13:0] VAR36,
output wire [1:0] VAR20,
output wire [31:0] VAR40,
output wire [31:0] VAR17,
output wire [31:0] VAR27,
input wire VAR8,
input wire VAR1,
input wire [13:0] VAR38,
input wire ... | bsd-2-clause |
monotone-RK/FACE | IEICE-Trans/16-way_2-tree/src/riffa/tx_data_shift.v | 13,708 | module MODULE1
parameter VAR34 = 1,
parameter VAR15 = 1,
parameter VAR2 = 128,
parameter VAR3 = "VAR80"
)
(
input VAR12,
input VAR29,
input VAR37,
input [VAR2-1:0] VAR4,
input VAR7,
input [VAR83(VAR2/32)-1:0] VAR56,
input VAR42,
input [VAR83(VAR2/32)-1:0] VAR43,
output VAR40,
input VAR25,
output [VAR2-1:0] VAR28,
outpu... | mit |
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