repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_1.v | 2,345 | module MODULE2 (
VAR9 ,
VAR3 ,
VAR10 ,
VAR11 ,
VAR8 ,
VAR7,
VAR4,
VAR2 ,
VAR5
);
output VAR9 ;
input VAR3 ;
input VAR10 ;
input VAR11 ;
input VAR8 ;
input VAR7;
input VAR4;
input VAR2 ;
input VAR5 ;
VAR6 VAR1 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2),
.... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_fpu/bsg_fpu_add_sub.v | 12,085 | module MODULE1
(
input VAR49
, input VAR150
, input VAR45
, input VAR53
, input [VAR60+VAR57:0] VAR80
, input [VAR60+VAR57:0] VAR140
, input VAR65
, output logic VAR115
, output logic VAR146
, output logic [VAR60+VAR57:0] VAR55
, output logic VAR101
, output logic VAR67
, output logic VAR153
, output logic VAR151
, inp... | bsd-3-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_fsb/bsg_fsb_node_level_shift_node_domain.v | 3,331 | module MODULE1 #(parameter VAR17(VAR7 ))
(
input VAR20,
input VAR9,
input VAR23,
output VAR4,
output VAR18,
output VAR15,
output [VAR7-1:0] VAR10,
input VAR24,
input VAR26,
input [VAR7-1:0] VAR33,
output VAR13,
output VAR19,
output [VAR7-1:0] VAR22,
input VAR14,
input VAR25,
input [VAR7-1:0] VAR6,
output VAR30
);
VAR28... | bsd-3-clause |
chriz2600/DreamcastHDMI | Core/source/data.v | 14,772 | module MODULE1(
input VAR47,
input reset,
input [11:0] VAR14,
input VAR26,
input VAR51,
input VAR13,
input VAR18,
input VAR9,
input [23:0] VAR5,
input VAR31,
output [7:0] VAR58,
output [7:0] VAR34,
output [7:0] VAR40,
output [11:0] VAR37,
output [11:0] VAR49,
output VAR42,
output VAR15,
output VAR44,
output [23:0] VAR1... | mit |
aanunez/KeypadScanner | Source/LFSR25000.v | 1,026 | module MODULE1(
input VAR3,
input VAR4,
output reg VAR2
);
reg [14:0] VAR1;
always @(posedge VAR3, negedge VAR4) begin
if(VAR4==0) begin
VAR2 <= 0;
VAR1 <= 15'b111111111111111;
end
else begin
VAR1[0] <= VAR1[13] ^ VAR1[14];
VAR1[14:1] <= VAR1[13:0];
if(VAR1==15'b001000010001100) VAR2 <= 1;
end
end
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21ba/sky130_fd_sc_hdll__o21ba_4.v | 2,332 | module MODULE2 (
VAR9 ,
VAR8 ,
VAR2 ,
VAR10,
VAR4,
VAR3,
VAR6 ,
VAR1
);
output VAR9 ;
input VAR8 ;
input VAR2 ;
input VAR10;
input VAR4;
input VAR3;
input VAR6 ;
input VAR1 ;
VAR7 VAR5 (
.VAR9(VAR9),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE2 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlxtp/sky130_fd_sc_hvl__dlxtp.symbol.v | 1,343 | module MODULE1 (
input VAR2 ,
output VAR6 ,
input VAR5
);
supply1 VAR7;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/synth/system_auto_pc_5.v | 10,197 | module MODULE1 (
VAR102,
VAR59,
VAR73,
VAR45,
VAR56,
VAR61,
VAR23,
VAR34,
VAR43,
VAR9,
VAR31,
VAR74,
VAR1,
VAR111,
VAR19,
VAR54,
VAR101,
VAR88,
VAR6,
VAR68,
VAR89,
VAR85,
VAR28,
VAR50,
VAR79,
VAR46,
VAR66,
VAR5,
VAR3,
VAR7,
VAR95,
VAR57,
VAR17
);
input wire VAR102;
input wire VAR59;
input wire [31 : 0] VAR73;
input wir... | bsd-2-clause |
FAST-Switch/fast | projects/SDTS/hw-src/localbus_manage.v | 6,909 | module MODULE1(
clk,
reset,
VAR24,
VAR8,
VAR15,
VAR2,
VAR30,
VAR11,
VAR21,
VAR1,
VAR22,
VAR23,
VAR4,
VAR17,
VAR25,
VAR27,
VAR10,
VAR9,
VAR33
);
input clk;
input reset;
input VAR24;
input VAR8;
input [31:0] VAR15;
input VAR2;
output reg VAR30;
output reg [31:0] VAR11;
output wire VAR21;
output wire VAR1;
output wire [31... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_spram_64x14.v | 10,798 | module MODULE1(
VAR43, VAR11, VAR48,
clk, rst, VAR46, VAR35, VAR51, addr, VAR17, VAR41
);
parameter VAR5 = 6;
parameter VAR39 = 14;
input VAR43;
input [VAR53 - 1:0] VAR48;
output VAR11;
input clk; input rst; input VAR46; input VAR35; input VAR51; input [VAR5-1:0] addr; input [VAR39-1:0] VAR17; output [VAR39-1:0] VAR41;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2/sky130_fd_sc_lp__nand2.behavioral.v | 1,366 | module MODULE1 (
VAR10,
VAR7,
VAR1
);
output VAR10;
input VAR7;
input VAR1;
supply1 VAR3;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR8 ;
wire VAR5;
nand VAR2 (VAR5, VAR1, VAR7 );
buf VAR9 (VAR10 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41a/sky130_fd_sc_lp__o41a.behavioral.pp.v | 2,047 | module MODULE1 (
VAR10 ,
VAR3 ,
VAR15 ,
VAR6 ,
VAR5 ,
VAR7 ,
VAR9,
VAR11,
VAR2 ,
VAR16
);
output VAR10 ;
input VAR3 ;
input VAR15 ;
input VAR6 ;
input VAR5 ;
input VAR7 ;
input VAR9;
input VAR11;
input VAR2 ;
input VAR16 ;
wire VAR18 ;
wire VAR12 ;
wire VAR4;
or VAR8 (VAR18 , VAR5, VAR6, VAR15, VAR3 );
and VAR17 (VAR12... | apache-2.0 |
secworks/sha512 | src/rtl/sha512_k_constants.v | 6,106 | module MODULE1(
input wire [6 : 0] addr,
output wire [63 : 0] VAR3
);
reg [63 : 0] VAR2;
assign VAR3 = VAR2;
always @*
begin : VAR1
case(addr)
0: VAR2 = 64'h428a2f98d728ae22;
1: VAR2 = 64'h7137449123ef65cd;
2: VAR2 = 64'hb5c0fbcfec4d3b2f;
3: VAR2 = 64'he9b5dba58189dbbc;
4: VAR2 = 64'h3956c25bf348b538;
5: VAR2 = 64'h59f... | bsd-2-clause |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/MUL_FPU_FUNCIONAL_v1/MUL_FPU_FUNCIONAL_v1.srcs/sources_1/imports/rtl/RecursiveKOA.v | 2,469 | module MODULE1
parameter VAR8=0) (
input wire clk,
input wire rst,
input wire VAR3,
input wire [VAR6-1:0] VAR7,
input wire [VAR6-1:0] VAR10,
output wire [2*VAR6-1:0] VAR5
);
wire [2*VAR6-1:0] VAR17;
generate
if (VAR8) begin
VAR13 #(.VAR6(VAR6)) VAR15(
.VAR7(VAR7[VAR6-1:0]),
.VAR10(VAR10[VAR6-1:0]),
.VAR5(VAR17[2*VAR6-1... | gpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_errorStatus.v | 1,850 | module MODULE1 (
address,
clk,
VAR4,
VAR6,
VAR5
)
;
output [ 31: 0] VAR5;
input [ 1: 0] address;
input clk;
input [ 7: 0] VAR4;
input VAR6;
wire VAR3;
wire [ 7: 0] VAR2;
wire [ 7: 0] VAR1;
reg [ 31: 0] VAR5;
assign VAR3 = 1;
assign VAR1 = {8 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR6)
begin
if (VAR6... | gpl-3.0 |
Jbag/Uart_zhixin | design/Uart_top.v | 1,368 | module MODULE1(
input clk,
input VAR11,
input VAR15,
output VAR7
);
wire VAR14;
wire VAR6,VAR16,VAR17;
wire VAR8;
wire [3:0] VAR1,VAR3,VAR13;
wire [7:0] VAR18;
VAR9 VAR19(
.clk (clk), .VAR11 (VAR11), .en (VAR14), .VAR6 (VAR16), .VAR1 (VAR3) );
VAR2 VAR5( .clk (clk),
.VAR11 (VAR11),
.VAR15 (VAR15),
.VAR1 (VAR3),
.VAR6 (... | gpl-3.0 |
Dokany/STA | Verilog_modules/ALU32.v | 1,974 | module MODULE1 (
input [3:0] sel,
input [31:0] VAR16,
input [31:0] VAR4,
output reg [31:0] VAR6,
output reg VAR1,
output reg VAR10,
output reg VAR15,
output reg VAR11
);
parameter VAR3 = 4'b0000;
parameter VAR5 = 4'b0001;
parameter VAR7 = 4'b0010;
parameter VAR18 = 4'b0011;
parameter VAR9 = 4'b0100;
parameter VAR8 = 4'... | mit |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_async_fifo.v | 5,889 | module MODULE1 #
(
parameter VAR16 = 12,
parameter VAR31 = 8
)
(
input wire VAR36,
input wire VAR18,
input wire [VAR31-1:0] VAR15,
input wire VAR30,
output wire VAR9,
input wire VAR2,
input wire VAR28,
input wire VAR17,
input wire VAR29,
output wire [VAR31-1:0] VAR14,
output wire VAR8,
input wire VAR24,
output wire VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311a/sky130_fd_sc_hd__o311a.symbol.v | 1,372 | module MODULE1 (
input VAR2,
input VAR3,
input VAR6,
input VAR1,
input VAR10,
output VAR5
);
supply1 VAR4;
supply0 VAR8;
supply1 VAR9 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/vfabric_exp.v | 2,315 | module MODULE1(VAR26, VAR2,
VAR4, VAR10, VAR28,
VAR25, VAR24, VAR19);
parameter VAR21 = 32;
parameter VAR9 = 16;
parameter VAR27 = 64;
input VAR26, VAR2;
input [VAR21-1:0] VAR4;
input VAR10;
output VAR28;
output [VAR21-1:0] VAR25;
output VAR24;
input VAR19;
reg [VAR9-1:0] VAR11;
wire [VAR21-1:0] VAR6;
wire VAR14;
wire ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2/sky130_fd_sc_hs__nand2_8.v | 1,970 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR2 ,
VAR7,
VAR4
);
output VAR3 ;
input VAR6 ;
input VAR2 ;
input VAR7;
input VAR4;
VAR1 VAR5 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR3,
VAR6,
VAR2
);
output VAR3;
input VAR6;
input VAR2;
supply1 VAR7;
supply0 VAR4;
VAR1 VAR5 (
.... | apache-2.0 |
audiocircuit/NCSU-Low-Power-RFID | rfid-verilog/tag/txclkdivide.v | 1,518 | module MODULE1(reset, VAR9, VAR10, VAR8, VAR1);
input reset, VAR9, VAR8;
input [9:0] VAR10; output VAR1;
reg VAR1;
reg [6:0] counter;
wire [10:0] VAR7;
assign VAR7[10:1] = VAR10;
assign VAR7[0] = 1'b0;
wire [11:0] VAR3;
assign VAR3 = VAR7 + VAR10;
wire [11:0] VAR6;
assign VAR6 = (11'd75+VAR3); wire [11:0] VAR4;
assign ... | gpl-3.0 |
efabless/openlane | designs/usb_cdc_core/src/usbf_sie_rx.v | 13,480 | module MODULE1
(
input VAR25
,input VAR44
,input VAR56
,input [ 7:0] VAR31
,input VAR38
,input VAR9
,input [ 6:0] VAR33
,output [ 7:0] VAR23
,output VAR67
,output [ 10:0] VAR19
,output VAR42
,output [ 6:0] VAR57
,output [ 3:0] VAR18
,output VAR49
,output VAR66
,output VAR39
,output VAR47
,output [ 7:0] VAR35
,output VA... | apache-2.0 |
ptracton/Picoblaze | library/display/pb_display.v | 2,688 | module MODULE1 (
VAR15, VAR10, VAR14,
clk, reset, VAR5, VAR4, VAR6, VAR8
) ;
parameter VAR1 = 8'h00;
input clk;
input reset;
input [7:0] VAR5;
input [7:0] VAR4;
output [7:0] VAR15;
input VAR6;
input VAR8;
output [3:0] VAR10;
output [7:0] VAR14;
wire [7:0] VAR7; wire [7:0] VAR11; wire [7:0] VAR13; wire [7:0] VAR9;
VAR16... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221oi/sky130_fd_sc_hd__a221oi_4.v | 2,457 | module MODULE1 (
VAR10 ,
VAR12 ,
VAR7 ,
VAR1 ,
VAR11 ,
VAR3 ,
VAR4,
VAR2,
VAR6 ,
VAR8
);
output VAR10 ;
input VAR12 ;
input VAR7 ;
input VAR1 ;
input VAR11 ;
input VAR3 ;
input VAR4;
input VAR2;
input VAR6 ;
input VAR8 ;
VAR5 VAR9 (
.VAR10(VAR10),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR3(VAR3),
.VA... | apache-2.0 |
combinatorylogic/soc | backends/c2/hw/rtl/regfile.v | 1,968 | module MODULE1
(input clk,
input rst,
input [31:0] VAR1,
input [4:0] VAR10,
input [4:0] VAR6,
input [4:0] VAR4,
output reg [31:0] VAR9,
output reg [31:0] VAR13,
output [31:0] VAR9,
output [31:0] VAR13,
input [4:0] VAR7,
input VAR12,
input [31:0] VAR17,
input VAR8,
input [31:0] VAR3);
reg [31:0] VAR18 [0:31];
wire [31:0... | mit |
oblivioncth/DE0-Verilog-Processor | src/Memory_16x256_bb.v | 5,983 | module MODULE1 (
VAR2,
address,
VAR1,
VAR4,
VAR5,
VAR3);
input VAR2;
input [7:0] address;
input VAR1;
input [15:0] VAR4;
input VAR5;
output [15:0] VAR3;
tri0 VAR2;
tri1 VAR1;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbp/sky130_fd_sc_hs__dlxbp.symbol.v | 1,328 | module MODULE1 (
input VAR5 ,
output VAR2 ,
output VAR4 ,
input VAR6
);
supply1 VAR1;
supply0 VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41o/sky130_fd_sc_hd__a41o.functional.pp.v | 2,058 | module MODULE1 (
VAR10 ,
VAR1 ,
VAR18 ,
VAR5 ,
VAR6 ,
VAR4 ,
VAR15,
VAR13,
VAR11 ,
VAR12
);
output VAR10 ;
input VAR1 ;
input VAR18 ;
input VAR5 ;
input VAR6 ;
input VAR4 ;
input VAR15;
input VAR13;
input VAR11 ;
input VAR12 ;
wire VAR7 ;
wire VAR14 ;
wire VAR17;
and VAR3 (VAR7 , VAR1, VAR18, VAR5, VAR6 );
or VAR8 (VAR... | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/or1200_cfgr.v | 10,374 | module MODULE1(
VAR18, VAR63
);
input [31:0] VAR18; output [31:0] VAR63;
reg [31:0] VAR63;
always @(VAR18)
if (~|VAR18[31:4])
case(VAR18[3:0]) VAR120: begin
VAR63[VAR40] = VAR26;
VAR63[VAR113] = VAR98;
VAR63[VAR97] = VAR4;
VAR63[VAR53] = VAR76;
end
VAR63[VAR104] = VAR56;
VAR63[VAR39] = VAR126;
VAR63[VAR81] = VAR114;
VA... | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/DOUBLE/Add_Subt_syn.v | 20,377 | module MODULE2 ( VAR91, VAR123, VAR277, VAR243, VAR305 );
input [26:0] VAR91;
input [26:0] VAR123;
output [26:0] VAR243;
input VAR277;
output VAR305;
wire VAR311, VAR303, VAR360, VAR259, VAR12, VAR374, VAR239, VAR34, VAR309, VAR358, VAR184, VAR151, VAR312, VAR76, VAR386, VAR142,
VAR158, VAR356, VAR345, VAR319, VAR170, ... | gpl-3.0 |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/synth/design_1_xbar_0.v | 14,571 | module MODULE1 (
VAR13,
VAR43,
VAR86,
VAR121,
VAR31,
VAR80,
VAR81,
VAR11,
VAR71,
VAR104,
VAR7,
VAR76,
VAR128,
VAR51,
VAR45,
VAR77,
VAR4,
VAR28,
VAR130,
VAR132,
VAR118,
VAR30,
VAR60,
VAR37,
VAR111,
VAR95,
VAR99,
VAR26,
VAR126,
VAR5,
VAR49,
VAR92,
VAR131,
VAR89,
VAR46,
VAR36,
VAR64,
VAR124,
VAR84,
VAR33
);
input wire VAR... | gpl-3.0 |
c4puter/bridge-hdl | modules/wb_conmax/wb_conmax_master_if.v | 20,112 | module MODULE1(
VAR163, VAR95,
VAR123, VAR130, VAR14, VAR6, VAR1, VAR12,
VAR156, VAR91, VAR114, VAR62,
VAR47, VAR61, VAR10, VAR154, VAR45, VAR133,
VAR76, VAR16, VAR69, VAR188,
VAR173, VAR55, VAR142, VAR149, VAR23, VAR26,
VAR135, VAR48, VAR97, VAR40,
VAR58, VAR187, VAR132, VAR90, VAR79, VAR42,
VAR4, VAR105, VAR34, VAR11... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221ai/sky130_fd_sc_lp__o221ai_0.v | 2,457 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR11 ,
VAR4 ,
VAR8 ,
VAR2 ,
VAR10,
VAR1,
VAR9 ,
VAR7
);
output VAR6 ;
input VAR5 ;
input VAR11 ;
input VAR4 ;
input VAR8 ;
input VAR2 ;
input VAR10;
input VAR1;
input VAR9 ;
input VAR7 ;
VAR12 VAR3 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR10(V... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_addr_decoder.v | 11,886 | module MODULE1
(
VAR74,
reset,
VAR25,
VAR15,
VAR70,
VAR23,
VAR3,
VAR18,
VAR43,
VAR56,
VAR35,
VAR77,
VAR40,
VAR32,
VAR76,
VAR24,
VAR39,
VAR45
);
input VAR74;
input reset;
input [31:0] VAR25; input [13:0] VAR15; input VAR70; input VAR23; input signed [18:0] VAR3; output [31:0] VAR18; output VAR43; output [1:0] VAR56; out... | gpl-3.0 |
freecores/verilog_fixed_point_math_library | qmults.v | 3,570 | module MODULE1#(
parameter VAR12 = 15,
parameter VAR13 = 32
)
(
input [VAR13-1:0] VAR16,
input [VAR13-1:0] VAR14,
input VAR1,
input VAR2,
output [VAR13-1:0] VAR3,
output VAR8,
output VAR9
);
reg [2*VAR13-2:0] VAR4; reg [2*VAR13-2:0] VAR11; reg [VAR13-1:0] VAR10;
reg [VAR13-1:0] VAR7;
reg VAR15; reg VAR17; reg VAR6;
VAR... | lgpl-2.1 |
8l/kestrel | cores/VRAM16K/rtl/verilog/VRAM16K.v | 6,053 | module MODULE1(
input VAR4,
output VAR17,
input [13:1] VAR95,
input VAR52,
output [15:0] VAR7,
input [15:0] VAR73,
input [1:0] VAR53,
input VAR68,
input VAR41,
output VAR76,
input [13:1] VAR32,
input VAR72,
output [15:0] VAR59,
input [15:0] VAR44,
input [1:0] VAR29,
input VAR19,
input VAR85
);
reg VAR92;
reg VAR23;
ass... | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v | 66,043 | module MODULE1 #
(
parameter VAR376 = 100, parameter VAR16 = 2500, parameter VAR455 = "VAR201", parameter VAR77 = "VAR375", parameter VAR81 = "VAR60", parameter VAR130 = "VAR122",
parameter VAR341 = 4, parameter VAR121 = 1, parameter VAR284 = 3, parameter VAR208 = 1, parameter VAR443 = 1, parameter VAR449 = 1, paramete... | lgpl-3.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_prc.v | 10,099 | module MODULE1
( VAR13,
reset,
VAR46,
VAR100,
VAR31,
VAR85,
VAR7,
VAR104,
VAR26,
VAR109,
VAR40,
VAR16,
VAR71,
VAR50,
VAR35,
VAR49,
VAR45,
VAR118,
VAR33,
VAR17,
VAR66);
parameter VAR98 = 8;
parameter VAR61 = 3;
parameter VAR97 = 1;
parameter VAR52 = 1920; parameter VAR63 = 1080; parameter VAR54 = 256;
parameter VAR48 = ... | mit |
sirchuckalot/zet | cores/vga/rtl/vga_config_iface.v | 10,244 | module MODULE1 (
input VAR64,
input VAR46,
input [15:0] VAR1,
output reg [15:0] VAR16,
input [ 4:1] VAR45,
input VAR15,
input [ 1:0] VAR56,
input VAR61,
output VAR38,
output [3:0] VAR2, output VAR55, output VAR81,
output VAR40, output VAR21, output VAR69, output [1:0] VAR67, output [1:0] VAR37, output VAR79, output [7:... | gpl-3.0 |
housq/lc3 | LC3_MIO.v | 2,836 | module MODULE1(
input clk,
input reset,
input [15:0] VAR38,
input VAR13,
input VAR31,
input VAR15,
input VAR18,
input VAR1,
output [15:0] VAR33,
output VAR4,
output VAR39,
input VAR2,
input [7:0] VAR26,
output [15:0] VAR25,
output VAR17
);
wire [1:0] VAR24;
wire VAR21;
wire VAR10;
wire VAR22;
wire VAR34;
wire VAR36;
wi... | gpl-2.0 |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/verilog/Loop_loop_height_cud.v | 2,034 | module MODULE1 (
VAR12, VAR4, VAR2, VAR8, VAR14, VAR13, VAR10, VAR9, VAR1, clk);
parameter VAR6 = 8;
parameter VAR5 = 8;
parameter VAR3 = 256;
input[VAR5-1:0] VAR12;
input VAR4;
output reg[VAR6-1:0] VAR2;
input[VAR5-1:0] VAR8;
input VAR14;
output reg[VAR6-1:0] VAR13;
input[VAR5-1:0] VAR10;
input VAR9;
output reg[VAR6-1... | mit |
peteasa/oh | src/elink/hdl/erx_io.v | 10,344 | module MODULE1 (
VAR55, VAR54, VAR11, VAR77,
VAR90, VAR42, VAR109, VAR60,
VAR50, VAR99, VAR58, VAR106, VAR89,
VAR101, VAR12, VAR79, VAR7, VAR13,
VAR98, VAR47, VAR23
);
parameter VAR94 = "VAR84";
parameter VAR69 = 104;
parameter VAR39 = 1;
input VAR50; input VAR99; input VAR58; output VAR55;
input [44:0] VAR106;
input V... | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_1_0/synth/OpenSSD2_Tiger4NSC_1_0.v | 14,564 | module MODULE1 (
VAR37,
VAR42,
VAR39,
VAR19,
VAR5,
VAR10,
VAR17,
VAR51,
VAR62,
VAR61,
VAR48,
VAR11,
VAR20,
VAR15,
VAR13,
VAR50,
VAR67,
VAR91,
VAR47,
VAR31,
VAR52,
VAR38,
VAR41,
VAR70,
VAR92,
VAR28,
VAR75,
VAR33,
VAR60,
VAR76,
VAR56,
VAR6,
VAR69,
VAR90,
VAR3,
VAR74,
VAR2,
VAR64,
VAR35,
VAR1,
VAR12,
VAR14,
VAR58,
VAR55,
... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_8.behavioral.v | 1,108 | module MODULE1( VAR2, VAR5 );
input VAR2;
output VAR5;
VAR4 VAR1(.VAR2(VAR2),.VAR5(VAR5));
VAR4 VAR3(.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
vipinkmenon/scas | hw/fpga/ipcore_dir/dp_ram_blank.v | 3,049 | module MODULE1(
VAR6,
VAR4,
VAR5,
VAR9,
VAR8,
VAR1,
VAR2,
VAR3,
VAR7
);
input VAR6;
input VAR4;
input VAR5;
output VAR9;
input [7 : 0] VAR8;
output VAR1;
input VAR2;
output [7 : 0] VAR3;
output [11 : 0] VAR7;
endmodule | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/387128e4034068b3/zynq_design_1_processing_system7_0_2_stub.v | 5,336 | module MODULE1(VAR22, VAR62,
VAR40, VAR66, VAR45, VAR32,
VAR43, VAR19, VAR53, VAR59,
VAR17, VAR48, VAR33, VAR14, VAR3,
VAR41, VAR35, VAR25, VAR12,
VAR57, VAR61, VAR56, VAR51, VAR55,
VAR49, VAR64, VAR38, VAR36, VAR2,
VAR31, VAR37, VAR8, VAR9, VAR34,
VAR67, VAR30, VAR58, VAR5,
VAR11, VAR27, VAR26, VAR7, VAR6,
VAR39, VAR4... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4b/sky130_fd_sc_hdll__and4b.pp.symbol.v | 1,332 | module MODULE1 (
input VAR8 ,
input VAR9 ,
input VAR4 ,
input VAR2 ,
output VAR1 ,
input VAR6 ,
input VAR7,
input VAR3,
input VAR5
);
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/rw_manager_di_buffer_wrap.v | 2,631 | module MODULE1(
VAR5,
VAR22,
VAR15,
VAR13,
VAR6,
VAR3,
VAR11);
parameter VAR8 = 18;
parameter VAR23 = 9;
parameter VAR25 = 2;
parameter VAR14 = 1;
parameter VAR9 = 2;
parameter VAR10 = 16;
input VAR5;
input [VAR8-1:0] VAR22;
input [VAR9 - 1 : 0] VAR15;
input [VAR9-1:0] VAR13;
input VAR6;
output [VAR23 - 1 : 0] VAR3;
in... | gpl-3.0 |
hcabrera-/lancetfish | RTL/shared/rtl/fifo_control.v | 5,338 | module MODULE1
(
input wire clk,
input wire reset,
input wire VAR14,
input wire VAR17,
output wire VAR1,
output wire VAR15,
output wire [VAR2-1:0] VAR10,
output wire [VAR2-1:0] VAR19
);
localparam VAR2 = VAR11(VAR6);
reg [VAR2-1:0] VAR4;
reg [VAR2-1:0] VAR8;
reg [VAR2-1:0] VAR9;
reg [VAR2-1:0] VAR16;
reg VAR5;
reg VAR1... | gpl-3.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_mdm_1_0/system_mdm_1_0_stub.v | 1,614 | module MODULE1(VAR3, VAR9, VAR10, VAR5,
VAR1, VAR7, VAR4, VAR6, VAR2, VAR8)
;
output VAR3;
output VAR9;
output VAR10;
input VAR5;
output [0:7]VAR1;
output VAR7;
output VAR4;
output VAR6;
output VAR2;
output VAR8;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrtp/sky130_fd_sc_hd__sdfrtp.blackbox.v | 1,444 | module MODULE1 (
VAR10 ,
VAR3 ,
VAR1 ,
VAR2 ,
VAR7 ,
VAR4
);
output VAR10 ;
input VAR3 ;
input VAR1 ;
input VAR2 ;
input VAR7 ;
input VAR4;
supply1 VAR9;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/dram_ctl_edgelogic.v | 2,061 | module MODULE1(
VAR1, VAR2,
clk, VAR7, VAR9, VAR11, VAR6, VAR12
);
input clk;
input VAR7;
input VAR12;
input VAR9;
input VAR11;
input VAR6;
output VAR1;
output VAR2;
wire VAR4 = VAR12 ? ~clk : clk;
VAR10 #(1) VAR13(
.din(VAR6),
.VAR8(VAR2),
.VAR7(VAR7),
.clk(VAR4), .VAR3(VAR11), .VAR14(VAR1), .VAR5(VAR9));
endmodule | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_pcie_pipe_misc.v | 8,537 | module MODULE1 #
(
parameter VAR28 = 0, parameter VAR25 = 1 )
(
input wire VAR19 , input wire VAR29 , input wire VAR9 , input wire VAR18 , input wire [2:0] VAR17 , input wire VAR8 ,
output wire VAR11 , output wire VAR23 , output wire VAR10 , output wire VAR1 , output wire [2:0] VAR14 , output wire VAR7 ,
input wire VAR... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_023.v | 1,397 | module MODULE2 (
VAR10,
VAR6
);
input [31:0] VAR10;
output [31:0]
VAR6;
wire [31:0]
VAR11,
VAR1,
VAR5,
VAR8,
VAR4,
VAR3;
assign VAR11 = VAR10;
assign VAR5 = VAR1 - VAR11;
assign VAR3 = VAR4 << 6;
assign VAR1 = VAR11 << 5;
assign VAR8 = VAR5 << 4;
assign VAR4 = VAR11 + VAR8;
assign VAR6 = VAR3;
endmodule
module MODULE1(... | mit |
rkrajnc/minimig-de1 | lib/models/ps2mouse.v | 3,985 | module MODULE1 (
input wire clk,
input wire rst,
inout wire VAR22,
inout wire VAR24
);
localparam [8-1:0]
VAR29 = 8'haa,
VAR25 = 8'h00,
VAR3 = 8'h03,
VAR28 = 8'hfa;
reg VAR14=1'b0, VAR10=1'b0;
reg VAR31 = 1'b1, VAR4 = 1'b1;
wire VAR5, VAR26;
assign VAR22 = VAR14 ? VAR31 : 1'VAR13;
assign VAR24 = VAR10 ? VAR4 : 1'VAR13;... | gpl-3.0 |
miamiasheep/nctu-dlab-99 | hw/t_multiply.v | 1,414 | module MODULE1;
wire VAR3;
wire [15:0] VAR8;
reg [7:0] VAR1, VAR4;
integer VAR6, VAR5;
reg VAR7, VAR9, reset, VAR2;
VAR11 VAR10(VAR9, reset, VAR7, VAR1, VAR4, VAR8, VAR3);
always VAR9 = ~VAR9;
begin
end else | gpl-3.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_async_fifo.v | 17,994 | module MODULE1 #
(
parameter VAR4 = 4096,
parameter VAR17 = 8,
parameter VAR34 = (VAR17>8),
parameter VAR33 = (VAR17/8),
parameter VAR18 = 1,
parameter VAR32 = 0,
parameter VAR23 = 8,
parameter VAR5 = 0,
parameter VAR31 = 8,
parameter VAR8 = 1,
parameter VAR21 = 1,
parameter VAR42 = 2,
parameter VAR7 = 0,
parameter VAR... | mit |
csail-csg/recycle-bsv-lib | src/v/EHRU_4.v | 2,517 | module MODULE1 (
VAR14,
VAR15,
VAR18,
VAR2,
VAR3,
VAR5,
VAR20,
VAR7,
VAR17,
VAR4,
VAR1,
VAR10,
VAR16
);
parameter VAR9 = 1;
parameter VAR19 = 0;
input VAR14;
output [VAR9-1:0] VAR15;
input [VAR9-1:0] VAR18;
input VAR2;
output [VAR9-1:0] VAR3;
input [VAR9-1:0] VAR5;
input VAR20;
output [VAR9-1:0] VAR7;
input [VAR9-1:0] ... | mit |
kkalavantavanich/SD2017 | spiRead.v | 2,189 | /* VAR31 VAR9 VAR3 VAR19 VAR22 VAR13 VAR17.
* VAR11 VAR1 VAR4 use/VAR16/VAR5 in VAR15 VAR28 VAR34 this VAR10 VAR32 VAR23 VAR29 VAR21.
* VAR18: VAR7:
module MODULE1(
VAR12,
VAR25,
VAR30,
VAR24,
VAR20,
VAR14
);
parameter VAR27 = 1;
input VAR12;
input VAR25;
input VAR30;
output [(VAR27 * 8) - 1:0] VAR20;
output reg VAR24;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dlatch_p/sky130_fd_sc_hdll__udp_dlatch_p.symbol.v | 1,302 | module MODULE1 (
input VAR1 ,
output VAR2 ,
input VAR3
);
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/offset_to_mask.v | 3,740 | module MODULE1
parameter VAR1 = 4)
(
input VAR9,
input [VAR7(VAR1)-1:0] VAR4,
output [VAR1-1:0] VAR2
);
reg [7:0] VAR8,VAR6;
wire [3:0] VAR5;
assign VAR5 = {VAR9,{{(3-VAR7(VAR1)){1'b0}},VAR4}};
assign VAR2 = (VAR3)? VAR6[7 -: VAR1]: VAR8[VAR1-1:0];
always @(*) begin
VAR8 = 0;
VAR6 = 0;
casex(VAR5)
default: begin
VAR8 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211a/sky130_fd_sc_ls__o211a.blackbox.v | 1,360 | module MODULE1 (
VAR9 ,
VAR3,
VAR7,
VAR6,
VAR2
);
output VAR9 ;
input VAR3;
input VAR7;
input VAR6;
input VAR2;
supply1 VAR5;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill_diode/sky130_fd_sc_ms__fill_diode.blackbox.v | 1,197 | module MODULE1 ();
supply1 VAR4;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Mod_2pi_Scale_And_Bit_Slice.v | 1,779 | module MODULE1
(
VAR1,
VAR3
);
input signed [17:0] VAR1; output signed [17:0] VAR3;
wire signed [35:0] VAR5; wire [35:0] VAR4; wire [17:0] VAR9; wire [35:0] VAR7; wire signed [17:0] VAR6;
assign VAR5 = 83443 * VAR1;
assign VAR4 = {{13{VAR5[35]}}, VAR5[35:13]};
VAR11 VAR10 (.VAR2(VAR4), .VAR8(VAR9) );
assign VAR7 = 2058... | gpl-3.0 |
archlabo/Frix | common/byteen_converter.v | 6,784 | module MODULE1
parameter VAR2 = 32,
parameter VAR6 = 32
)
(
input wire VAR8,
input wire rst,
input wire [VAR2-1:0] VAR10,
input wire VAR5,
input wire [31:0] VAR12,
input wire VAR16,
output reg [31:0] VAR14,
output reg VAR29,
input wire [3:0] VAR3,
output wire VAR9,
output wire [VAR6-1:0] VAR22,
output wire VAR27,
outpu... | bsd-2-clause |
Tao-J/nexys3MIPSSoC | cellram_ctrl.v | 10,739 | module MODULE1
(
VAR48, VAR3,
VAR13, VAR23,
VAR15, VAR8,
VAR41, VAR6,
VAR35, VAR40,
VAR25, VAR27,
VAR14,
VAR18,
VAR34,
VAR31,
VAR24,
VAR9,
VAR10,
VAR7,
VAR43,
VAR46,
VAR32,
VAR26,
VAR12
);
parameter VAR36 = 16;
parameter VAR29 = 23;
parameter VAR42 = 4; parameter VAR28 = 7;
inout [VAR36-1:0] VAR14;
output [VAR29-1:0] V... | gpl-3.0 |
praveendath92/DDR2_Interface_Xilinx_XUPV5 | source/ddr2_phy_dqs_iob.v | 8,885 | module MODULE1 #
(
parameter VAR54 = 1,
parameter VAR4 = "VAR27",
parameter VAR77 = "VAR20"
)
(
input VAR63,
input VAR64,
input VAR38,
input VAR56,
input VAR55,
input VAR19,
input VAR45,
input VAR58,
input VAR35,
input VAR61,
input VAR42,
input VAR49,
inout VAR43,
inout VAR2,
output VAR69,
output VAR9
);
wire VAR7;
wir... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfstp/sky130_fd_sc_hs__sdfstp_4.v | 2,380 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR8 ,
VAR10 ,
VAR9 ,
VAR5,
VAR6 ,
VAR3
);
input VAR1 ;
input VAR2 ;
output VAR8 ;
input VAR10 ;
input VAR9 ;
input VAR5;
input VAR6 ;
input VAR3 ;
VAR4 VAR7 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODU... | apache-2.0 |
leekeith/DEVBOX | Dev_Box_HW/ip/TERASIC_SEG7/SEG7_IF.v | 3,628 | module MODULE1(
VAR14,
VAR5,
VAR18,
VAR17,
VAR1,
VAR2,
VAR7,
VAR10
);
parameter VAR6 = 8;
parameter VAR3 = 3;
parameter VAR12 = 1;
parameter VAR19 = 1;
reg [7:0] VAR11;
reg [7:0] VAR9;
reg [7:0] VAR13;
reg [(VAR6*8-1):0] VAR8;
input VAR14;
input [(VAR3-1):0] VAR5;
input VAR18;
output [7:0] VAR17;
input VAR1;
input [7:0... | gpl-2.0 |
jakubfi/mera400f | src/drv_bus_req.v | 1,219 | module MODULE1(
input VAR23,
input ready,
input VAR14,
input VAR5,
input in,
input [0:7] VAR1,
input [0:15] VAR16,
input [0:15] VAR9,
input VAR2,
output reg VAR19,
input VAR21,
output VAR20,
output VAR18,
output din,
output VAR11,
output [0:3] VAR7,
output [0:15] VAR10,
output [0:15] VAR3
);
reg VAR8, VAR4, VAR22;
reg ... | gpl-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_phy_alt_mem_phy_dq_dqs.v | 31,154 | module MODULE1
(
VAR23,
VAR15,
VAR44,
VAR41,
VAR68,
VAR65,
VAR67,
VAR18,
VAR1,
VAR33,
VAR9,
VAR45,
VAR34,
VAR66,
VAR20,
VAR55,
VAR51,
VAR5,
VAR29,
VAR21,
VAR47,
VAR60,
VAR61,
VAR37,
VAR11,
VAR58,
VAR4,
VAR49) ;
input [7:0] VAR23;
input [7:0] VAR15;
output [7:0] VAR44;
output [7:0] VAR41;
input [7:0] VAR68;
output [7:0]... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/v6_mig39_2_patch20131030.v | 20,692 | module MODULE1 #
(
parameter VAR177 = 200,
parameter VAR88 = "VAR128",
parameter VAR171 = "VAR64", parameter VAR55 = 6, parameter VAR80 = 2, parameter VAR174 = 3, parameter VAR144 = 2,
parameter VAR111 = 2500,
parameter VAR132 = "VAR77",
parameter VAR21 = "VAR112",
parameter VAR153 = 1,
parameter VAR165 = 3, parameter ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a311o/sky130_fd_sc_lp__a311o_0.v | 2,437 | module MODULE2 (
VAR6 ,
VAR12 ,
VAR4 ,
VAR11 ,
VAR9 ,
VAR3 ,
VAR10,
VAR5,
VAR2 ,
VAR7
);
output VAR6 ;
input VAR12 ;
input VAR4 ;
input VAR11 ;
input VAR9 ;
input VAR3 ;
input VAR10;
input VAR5;
input VAR2 ;
input VAR7 ;
VAR1 VAR8 (
.VAR6(VAR6),
.VAR12(VAR12),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_003.v | 1,524 | module MODULE2 (
VAR3,
VAR5
);
input [31:0] VAR3;
output [31:0]
VAR5;
wire [31:0]
VAR2,
VAR11,
VAR14,
VAR10,
VAR6,
VAR9,
VAR7,
VAR12,
VAR1;
assign VAR2 = VAR3;
assign VAR9 = VAR2 << 7;
assign VAR11 = VAR2 << 4;
assign VAR14 = VAR2 + VAR11;
assign VAR1 = VAR7 - VAR12;
assign VAR7 = VAR6 - VAR9;
assign VAR10 = VAR14 << 1... | mit |
walkthetalk/fsref | ip/mm2s_adv/src/include/line_reader.v | 5,886 | module MODULE1 #
(
parameter integer VAR14 = 12,
parameter integer VAR15 = 10,
parameter integer VAR44 = 16,
parameter integer VAR16 = 32,
parameter integer VAR42 = 32
)
(
input wire [VAR14-1:0] VAR13,
input wire VAR39,
input wire [VAR16-1 : 0] VAR19,
output wire VAR38,
output wire [VAR42-1 : 0] VAR12,
output wire [VAR... | gpl-3.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/mega/io_buf.v | 5,581 | module MODULE1
(
VAR2,
VAR14,
VAR21,
VAR22) ;
input [0:0] VAR2;
inout [0:0] VAR14;
output [0:0] VAR21;
input [0:0] VAR22;
wire [0:0] VAR17;
wire [0:0] VAR7;
VAR10 VAR16
(
.VAR19(VAR14),
.VAR8(VAR17[0:0])
,
.VAR11(1'b0),
.VAR18(1'b0)
);
VAR16.VAR24 = "false",
VAR16.VAR4 = "false",
VAR16.VAR15 = "VAR10";
VAR23 VAR12
(
.... | bsd-3-clause |
Murailab-arch/magukara | boards/ecp3versa/rtl/ipexpress/ecp3/rcx1/pcie_eval/models/ecp3/tx_gear.v | 5,759 | module MODULE1 #(
parameter VAR4 = 20
)
(
input wire VAR17 , input wire VAR5 , input wire VAR18 ,
input wire VAR14, input wire [VAR4-1:0] VAR6 ,
output reg [VAR4/2-1:0] VAR8 );
reg [1:0] VAR15; reg [1:0] VAR12; reg VAR9;
wire [VAR4/2-1:0] VAR16; wire [VAR4/2-1:0] VAR19;
integer VAR3;
integer VAR1;
reg [VAR4/2-1:0] VAR1... | gpl-3.0 |
elegabriel/myzju | junior1/CA/pipeline3/code/cpu_ctl.v | 2,962 | module MODULE1(VAR15,VAR31,VAR10,VAR8,VAR43,VAR22,VAR30,VAR11,VAR6,VAR14,VAR19,VAR35,VAR13,VAR3,VAR27
);
input wire [5:0] VAR15, VAR31;
input wire VAR10;
output wire VAR8,VAR43,VAR22,VAR30,VAR11,VAR6,VAR14,VAR19,VAR35,VAR13,VAR3;
output wire [4:0] VAR27;
wire VAR34, VAR36, VAR42, VAR12, VAR23; wire VAR21, VAR17, VAR38,... | gpl-2.0 |
cpulabs/mist1032isa | src/dps/utim64/dps_main_counter.v | 1,069 | module MODULE1(
input wire VAR4,
input wire VAR1,
input wire VAR8,
input wire VAR7,
input wire VAR9,
input wire [1:0] VAR5,
input wire [63:0] VAR11,
output wire VAR2,
output wire [63:0] VAR3
);
reg VAR6;
reg [63:0] VAR10;
always@(posedge VAR4 or negedge VAR1)begin
if(!VAR1)begin
VAR6 <= 1'b0;
VAR10 <= {64{1'b0}};
end
e... | bsd-2-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad6676/axi_ad6676_if.v | 4,159 | module MODULE1 (
VAR11,
VAR6,
VAR4,
VAR3,
VAR5,
VAR9,
VAR13,
VAR8,
VAR12);
input VAR11;
input [63:0] VAR6;
output VAR4;
input VAR3;
output [31:0] VAR5;
output [31:0] VAR9;
output VAR13;
output VAR8;
output VAR12;
reg VAR12 = 'd0;
wire [15:0] VAR1;
wire [15:0] VAR2;
wire [15:0] VAR7;
wire [15:0] VAR10;
assign VAR4 = VAR... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_1.behavioral.v | 6,154 | module MODULE1( VAR6, VAR45, VAR19, VAR17, VAR48 );
input VAR45, VAR6, VAR19, VAR17;
output VAR48;
reg VAR58;
VAR56 VAR33(.VAR6(VAR6),.VAR45(VAR45),.VAR19(VAR19),.VAR17(VAR17),.VAR48(VAR48),.VAR58(VAR58));
VAR56 VAR28(.VAR6(VAR6),.VAR45(VAR45),.VAR19(VAR19),.VAR17(VAR17),.VAR48(VAR48),.VAR58(VAR58));
and VAR61(VAR30,VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31ai/sky130_fd_sc_ls__o31ai_2.v | 2,335 | module MODULE1 (
VAR2 ,
VAR10 ,
VAR9 ,
VAR11 ,
VAR6 ,
VAR4,
VAR8,
VAR1 ,
VAR5
);
output VAR2 ;
input VAR10 ;
input VAR9 ;
input VAR11 ;
input VAR6 ;
input VAR4;
input VAR8;
input VAR1 ;
input VAR5 ;
VAR7 VAR3 (
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.... | apache-2.0 |
alpenwasser/pitaya | firmware/fpga/cores/axis_red_pitaya_adc_v1_0/axis_red_pitaya_adc.v | 1,269 | module MODULE1 #
(
parameter integer VAR16 = 14,
parameter integer VAR12 = 32
)
(
output wire VAR2,
output wire VAR8,
input wire VAR11,
input wire VAR13,
input wire [VAR16-1:0] VAR18,
input wire [VAR16-1:0] VAR14,
output wire VAR7,
output wire [VAR12-1:0] VAR5
);
localparam VAR1 = VAR12/2 - VAR16;
reg [VAR16-1:0] VAR3;... | mit |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/altera_spram_256x32.v | 8,371 | module MODULE1 (
address,
VAR35,
VAR46,
VAR28,
VAR29,
VAR25);
input [7:0] address;
input [3:0] VAR35;
input VAR46;
input [31:0] VAR28;
input VAR29;
output [31:0] VAR25;
wire [31:0] VAR19;
wire [31:0] VAR25 = VAR19[31:0];
VAR38 VAR47 (
.VAR43 (VAR29),
.VAR39 (VAR46),
.VAR35 (VAR35),
.VAR17 (address),
.VAR3 (VAR28),
.VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxtp/sky130_fd_sc_hd__dlxtp_1.v | 2,162 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR4,
VAR5,
VAR2,
VAR1 ,
VAR9
);
output VAR8 ;
input VAR3 ;
input VAR4;
input VAR5;
input VAR2;
input VAR1 ;
input VAR9 ;
VAR6 VAR7 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR8 ,
VAR3 ,
VAR4
);
output VAR8 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21boi/sky130_fd_sc_lp__a21boi_4.v | 2,332 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR6 ,
VAR5,
VAR7,
VAR10,
VAR3 ,
VAR8
);
output VAR9 ;
input VAR4 ;
input VAR6 ;
input VAR5;
input VAR7;
input VAR10;
input VAR3 ;
input VAR8 ;
VAR1 VAR2 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE1 ... | apache-2.0 |
Digilent/vivado-library | ip/Pmods/PmodAD1_v1_0/hdl/PmodAD1_v1_0_S00_AXI.v | 14,948 | module MODULE1 #
(
parameter VAR44 = 0,
parameter VAR48 = 20, parameter VAR12 = 60, parameter VAR36 = 500, parameter VAR8 = 400,
parameter integer VAR9 = 32,
parameter integer VAR53 = 4
)
(
output wire VAR38,
input wire VAR26,
input wire VAR46,
output wire VAR11,
output wire [1:0] VAR35,
input wire VAR28,
input wire VA... | mit |
merckhung/zet | cores/vga/rtl/vga_write_iface.v | 9,159 | module MODULE1 (
input VAR74,
input VAR30,
input [16:1] VAR7,
input [ 1:0] VAR27,
input [15:0] VAR72,
input VAR10,
output VAR43,
output [17:1] VAR84,
output [ 1:0] VAR54,
output [15:0] VAR6,
output VAR49,
input VAR34,
input VAR18,
input [ 1:0] VAR47,
input [ 1:0] VAR59,
input [ 7:0] VAR31,
input [ 3:0] VAR73,
input [ 3... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1.functional.v | 1,759 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR10,
VAR3
);
output VAR6 ;
input VAR2 ;
input VAR10;
input VAR3;
wire VAR7 ;
wire VAR4;
not VAR5 (VAR7 , VAR2 );
VAR1 VAR8 (VAR4, VAR7, VAR10, VAR3);
buf VAR9 (VAR6 , VAR4 );
endmodule | apache-2.0 |
darrylring/SDRdrum | fpga/rtl/ad5545.v | 5,585 | module MODULE1
(
input wire clk,
input wire VAR9,
input wire [31:0] VAR24,
input wire valid,
output wire ready,
output wire VAR19,
output wire din,
output wire VAR10,
output wire VAR23
);
localparam [2:0]
VAR16 = 3'd0,
VAR3 = 3'd1,
VAR21 = 3'd2,
VAR7 = 3'd3,
VAR13 = 3'd4;
reg [2:0] VAR15, VAR18;
reg [6:0] VAR6, VAR27;
... | gpl-3.0 |
tugrulyatagan/RISC-processor | xilinx_processor/IR_fetch.v | 1,729 | module MODULE1(
input VAR11,
input VAR12,
input [11:0] VAR3,
input [11:0] VAR6,
input VAR5,
input VAR10,
input VAR2,
input VAR7,
output reg [15:0] VAR8,
output reg [11:0] VAR1
);
wire [15:0] VAR4;
wire VAR9;
assign VAR9 = VAR7 || VAR5; | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ai/sky130_fd_sc_ls__o21ai_1.v | 2,261 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR8 ,
VAR9 ,
VAR2,
VAR3,
VAR5 ,
VAR6
);
output VAR4 ;
input VAR7 ;
input VAR8 ;
input VAR9 ;
input VAR2;
input VAR3;
input VAR5 ;
input VAR6 ;
VAR10 VAR1 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE1 (... | apache-2.0 |
sh-chris110/chris | FPGA/chris.sdram.ok/Qsys/soc_design/synthesis/submodules/soc_design_timer_0.v | 4,976 | module MODULE1 (
address,
VAR6,
clk,
VAR13,
VAR11,
VAR18,
irq,
VAR8
)
;
output irq;
output [ 15: 0] VAR8;
input [ 2: 0] address;
input VAR6;
input clk;
input VAR13;
input VAR11;
input [ 15: 0] VAR18;
wire VAR23;
wire VAR7;
reg VAR15;
wire VAR12;
reg VAR22;
wire VAR10;
wire [ 16: 0] VAR4;
reg VAR17;
wire VAR19;
wire VAR... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/iobdg_dbg/rtl/iobdg_dbg_l2.v | 15,842 | module MODULE1 (
VAR52, VAR14, VAR114, VAR74,
VAR25, VAR113, VAR45,
VAR85, VAR24, VAR23,
VAR51, VAR118,
VAR62, VAR58, VAR97, clk, VAR92, VAR77, VAR116,
VAR16, VAR84, VAR61, VAR94,
VAR108, VAR28,
VAR37, VAR41,
VAR30, VAR103,
VAR15
);
input VAR62;
input VAR58;
input VAR97;
input clk;
input VAR92;
input VAR77;
input [39:0... | gpl-2.0 |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/Pulse_Width_Modulation.v | 4,261 | module MODULE1 #(
parameter
VAR13 = 50, VAR5 = 20000, VAR8 = 8
)
(
input wire VAR3,
input wire VAR4,
input wire [VAR8-1:0] VAR10,
output wire VAR2
);
parameter integer VAR11 = VAR13*1000000/VAR5/2/2**VAR8;
reg [VAR8-1:0] VAR14;
reg VAR9;
reg VAR6;
reg [VAR1(VAR11):0] VAR12;
reg VAR7;
begin
begin
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep.functional.v | 1,367 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR3 ,
VAR2
);
output VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR2;
wire VAR4;
endmodule | apache-2.0 |
masc-ucsc/cmpe220fall16 | rtl/l2cache_pipe_backup.v | 57,726 | module MODULE1(
input clk
,input reset
,input VAR145
,output VAR330
,input VAR112 VAR54
,output VAR315
,input VAR290
,output VAR227 VAR221
,input VAR47
,output VAR23
,input VAR296 VAR305
,input VAR18
,output VAR279
,input VAR253 VAR137
,output VAR322
,input VAR250
,output VAR73 VAR345
,input VAR349
,output VAR308
,inpu... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_1.behavioral.pp.v | 1,784 | module MODULE1( VAR7, VAR12, VAR9, VAR10, VAR5 );
input VAR12, VAR7;
inout VAR10, VAR5;
output VAR9;
reg VAR8;
VAR3 VAR4(.VAR7(VAR7),.VAR12(VAR12),.VAR9(VAR9),.VAR10(VAR10),.VAR5(VAR5),.VAR8(VAR8));
VAR3 VAR11(.VAR7(VAR7),.VAR12(VAR12),.VAR9(VAR9),.VAR10(VAR10),.VAR5(VAR5),.VAR8(VAR8));
not VAR1(VAR13,VAR12);
buf VAR2(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2b/sky130_fd_sc_ls__or2b.symbol.v | 1,285 | module MODULE1 (
input VAR7 ,
input VAR6,
output VAR4
);
supply1 VAR1;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
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