repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/rw_manager_data_decoder.v | 2,809 | module MODULE1(
VAR2,
VAR7,
VAR1,
VAR8
);
parameter VAR5 = "";
parameter VAR4 = "";
input VAR2;
input VAR7;
input [3:0] VAR1;
output [2 * VAR5 * VAR4 - 1 : 0] VAR8;
reg [3:0] VAR6;
always @(posedge VAR2 or negedge VAR7) begin
if(~VAR7) begin
VAR6 <= 4'b0000;
end
else begin
VAR6 <= VAR1;
end
end
genvar VAR3;
generate
fo... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/mux2/sky130_fd_sc_hvl__mux2.functional.v | 1,516 | module MODULE1 (
VAR5 ,
VAR1,
VAR4,
VAR3
);
output VAR5 ;
input VAR1;
input VAR4;
input VAR3 ;
wire VAR7;
VAR8 VAR6 (VAR7, VAR1, VAR4, VAR3 );
buf VAR2 (VAR5 , VAR7);
endmodule | apache-2.0 |
jhol/butterflylogic | rtl/spi_transmitter.v | 6,366 | module MODULE1 (
input wire clk,
input wire rst,
input wire VAR32,
input wire VAR38,
output reg VAR36,
input wire VAR8,
input wire [31:0] VAR7,
input wire [3:0] VAR2,
input wire VAR18,
input wire [7:0] VAR28,
input wire VAR10,
input wire VAR30,
input wire [31:0] VAR14,
output reg VAR5,
output reg VAR17
);
reg [31:0] VA... | gpl-2.0 |
ultraembedded/altor32 | rtl/cpu/altor32_lsu.v | 5,447 | module MODULE1
(
input VAR10 ,
input [7:0] VAR1 ,
input VAR15 ,
input VAR3 ,
input [4:0] VAR7 ,
input VAR12 ,
input VAR14 ,
input VAR9 ,
output reg VAR6 ,
output reg VAR8 ,
output reg VAR13 ,
output reg VAR5
);
reg VAR4;
reg VAR16;
always @ *
begin
VAR6 = VAR15;
VAR8 = VAR3;
VAR5 = 1'b0;
VAR13 = 1'b0;
VAR4 = VAR2(VAR1)... | lgpl-3.0 |
borti4938/sd2snes | verilog/sd2snes_sa1/address.v | 4,321 | module MODULE1(
input VAR26,
input [15:0] VAR10, input [2:0] VAR29, input [23:0] VAR12, input [7:0] VAR11, input VAR8, output [23:0] VAR21, output VAR6, output VAR31, output VAR7, output VAR22, input [23:0] VAR5,
input [23:0] VAR18,
output VAR34,
input [4:0] VAR20,
input VAR28,
input [11:0] VAR23,
input [3:0] VAR27,
ou... | gpl-2.0 |
wkoszek/hardware | rotary/rotary.v | 2,113 | module MODULE1(VAR5, VAR11, VAR4, VAR12, VAR1);
input wire VAR5;
input wire [2:0] VAR11;
output wire VAR4;
output wire VAR12;
output wire [1:0] VAR1;
wire [2:0] VAR2;
wire [1:0] VAR6;
VAR8 #(
.VAR3(VAR7/6)
) VAR14 (
.VAR5(VAR5),
.VAR9(VAR11[0]),
.do(VAR2[0])
);
VAR8 #(
.VAR3(VAR7/6)
) VAR10 (
.VAR5(VAR5),
.VAR9(VAR11[1... | bsd-2-clause |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/bus/rtl/bus_slave_mux.v | 3,322 | module MODULE1 (
input wire VAR6, input wire VAR23, input wire VAR15, input wire VAR7, input wire VAR9, input wire VAR26, input wire VAR1, input wire VAR24,
input wire [VAR17] VAR18, input wire VAR10, input wire [VAR17] VAR27, input wire VAR3, input wire [VAR17] VAR28, input wire VAR13, input wire [VAR17] VAR8, input w... | apache-2.0 |
justinzhf/MIPS-CPU | CPU.v | 7,084 | module MODULE1(clk,rst);
input clk;
input rst;
wire[31:0] VAR7; reg[31:0] VAR14;
wire[31:0] VAR30;
wire[31:0] VAR11;
wire[9:0] VAR45;
wire[31:0] VAR21;
wire[31:0] VAR44;
wire[4:0] VAR16;
wire[31:0] VAR38; wire[31:0] VAR47;
wire[3:0] VAR20; wire[31:0] VAR27; wire[31:0] VAR43;
wire[31:0] VAR8;
wire[31:0] VAR15;
wire VAR2... | gpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/pcie_core/source/pcie_core_rxeq_scan.v | 14,812 | module MODULE1 #
(
parameter VAR42 = "VAR46", parameter VAR34 = "VAR48", parameter VAR25 = 1, parameter VAR37 = 22'd3125000, parameter VAR17 = 22'd2083333 )
(
input VAR6,
input VAR3,
input [ 1:0] VAR41,
input [ 2:0] VAR23,
input VAR21,
input [ 3:0] VAR20,
input [17:0] VAR9,
input VAR10,
input [ 5:0] VAR38,
input [ 5:0]... | lgpl-3.0 |
kevintownsend/R3 | verilog/packet_decoder.v | 1,595 | module MODULE1(
input reset,
input clk,
input [63:0] VAR2,
input VAR12,
output [63:0] VAR3,
output [31:0] VAR9,
output [31:0] VAR8,
output VAR10);
reg [127:0] buffer;
reg [4:0] VAR11, VAR13;
reg [63:0] VAR7;
reg [31:0] VAR1, VAR14;
reg VAR4;
integer VAR5;
always @(posedge clk) begin
if(reset)begin
buffer <= 0;
VAR11 <=... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_1.behavioral.pp.v | 1,159 | module MODULE1( VAR1, VAR7, VAR6, VAR5 );
input VAR1;
inout VAR6, VAR5;
output VAR7;
VAR2 VAR3(.VAR1(VAR1),.VAR7(VAR7),.VAR6(VAR6),.VAR5(VAR5));
VAR2 VAR4(.VAR1(VAR1),.VAR7(VAR7),.VAR6(VAR6),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4/sky130_fd_sc_ms__and4.blackbox.v | 1,275 | module MODULE1 (
VAR6,
VAR7,
VAR9,
VAR8,
VAR3
);
output VAR6;
input VAR7;
input VAR9;
input VAR8;
input VAR3;
supply1 VAR1;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/system_mm_interconnect_0.v | 18,924 | module MODULE1 (
input wire VAR63, input wire VAR65, input wire [29:0] VAR61, output wire VAR34, input wire [4:0] VAR78, input wire [31:0] VAR104, input wire VAR58, output wire [255:0] VAR64, output wire VAR98, input wire VAR79, input wire [255:0] VAR39, output wire [29:0] VAR92, output wire VAR82, output wire VAR27, i... | mit |
javierbrito29/papiGB | rtl/pGB.v | 8,026 | module MODULE1
(
input wire VAR130,
output wire [3:0] VAR65,
output wire [3:0] VAR83,
output wire [3:0] VAR96,
output wire VAR71,
output wire VAR17,
input wire [5:0] VAR2,
output wire VAR123,
output wire [15:0] VAR119,
output wire [15:0] VAR50,
input wire VAR151
);
wire [15:0] VAR171, VAR54;
wire [7:0] VAR42, VAR91;
wi... | gpl-2.0 |
siavooshpayandehazad/property_evaluation | DUTs/arbiter/arbiter.v | 6,612 | module MODULE1(clk, rst,
VAR19, VAR43, VAR10, VAR22, VAR36,
VAR15, VAR7, VAR4, VAR24, VAR29,
VAR8, VAR32, VAR16, VAR20, VAR25,
VAR14
);
input clk, rst;
input [2:0] VAR19, VAR43, VAR10, VAR22, VAR36;
input [11:0] VAR15, VAR7, VAR4, VAR24, VAR29;
input VAR8, VAR32, VAR16, VAR20, VAR25;
output reg [5:0] VAR14;
reg [5:0] V... | gpl-3.0 |
ensdac/hydra | src/register.v | 2,266 | module MODULE1 # (
parameter VAR21 = 16,
parameter VAR12 = 2,
parameter VAR11 = 4,
parameter VAR17 = VAR3(VAR21),
parameter VAR9 = 32
) (
input VAR13,
input [VAR12-1:0] VAR7,
input [VAR11-1:0] VAR15,
input [VAR12*VAR17-1:0] VAR14,
input [VAR11*VAR17-1:0] VAR22,
input [VAR12*VAR9-1:0] VAR10,
output [VAR11*VAR9-1:0] VAR5... | mit |
titorgalaxy/Titor | rtl/verilog/core/Sign_Ext_Return.v | 1,782 | module MODULE1 (
VAR8,
VAR5,
VAR6,
VAR3
);
output reg [VAR9-1:0] VAR8; input [VAR9-1:0] VAR5; input [VAR1-1:0] VAR6; input VAR3;
reg [VAR9-1:0] VAR2 [VAR7-1:0];
genvar VAR4;
generate
for(VAR4=0; VAR4<VAR7; VAR4=VAR4+1) begin
always @ begin
VAR8 <= VAR2[VAR6];
end
endmodule | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_riscv/bsg_nasti/bsg_fsb_to_nasti_master_connector.v | 5,778 | module MODULE1
import VAR47::VAR4;
import VAR47::VAR36;
import VAR47::VAR27;
import VAR47::VAR44;
, VAR6="not VAR17")
(
input VAR15
, input VAR34
, input VAR4 VAR49
, output logic VAR8
, input VAR4 VAR29
, output logic VAR46
, input VAR36 VAR40
, output logic VAR9
, output VAR27 VAR22
, input VAR31
, output VAR44 VAR24... | bsd-3-clause |
efabless/openlane | designs/151/src/Riscv141.v | 3,656 | module MODULE1(
input clk,
input reset,
output [31:0] VAR50,
output [31:0] VAR33,
output [3:0] VAR6,
output VAR4,
output VAR17,
output [31:0] VAR31,
input VAR9,
input [31:0] VAR13,
input [31:0] VAR36,
input VAR25,
output [31:0] VAR27
);
wire [1:0] VAR21;
wire VAR10;
wire [4:0] VAR46;
wire [4:0] VAR48;
wire [4:0] VAR51;... | apache-2.0 |
svofski/mahponk | src/button2.v | 1,037 | module MODULE1(clk, pulse, VAR2);
parameter VAR1 = 32767;
input clk;
output pulse;
input VAR2;
reg [15:0] delay;
assign pulse = (delay != 0) | (!VAR2);
always @(posedge clk) begin
if (delay != 0)
delay <= delay - 1;
end
else
if (!VAR2) delay <= VAR1;
end
endmodule | bsd-2-clause |
franmolinaca/papiGB | rtl/dzcpu.v | 31,594 | module MODULE1
(
input wire VAR113,
input wire VAR1,
input wire [7:0] VAR176,
output wire [7:0] VAR66,
output wire [15:0] VAR111,
output wire VAR112,
input wire [3:0] VAR53,
output reg VAR117
);
wire[15:0] VAR69, VAR259, VAR120, VAR254, VAR127, VAR55, VAR203, VAR90, VAR93 ;
wire [7:0] VAR250, VAR51, VAR229;
wire [8:0] ... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/rx_engine_ultrascale.v | 10,129 | module MODULE1
)
(
input VAR31,
input VAR15,
input VAR12,
input VAR7,
input [VAR56-1:0] VAR19,
input [(VAR56/32)-1:0] VAR36,
input [VAR8-1:0] VAR67,
output VAR70,
input VAR3,
input VAR28,
input [VAR56-1:0] VAR39,
input [(VAR56/32)-1:0] VAR24,
input [VAR17-1:0] VAR69,
output VAR48,
output [VAR56-1:0] VAR64,
output VAR54... | gpl-3.0 |
borti4938/sd2snes | verilog/sd2snes_gsu/address.v | 3,371 | module MODULE1(
input VAR1,
input [15:0] VAR20, input [2:0] VAR7, input [23:0] VAR9, input [7:0] VAR25, input VAR6, output [23:0] VAR18, output VAR13, output VAR8, output VAR12, output VAR22, input [23:0] VAR3,
input [23:0] VAR23,
output VAR17,
output VAR26,
output VAR21,
output VAR19,
output VAR14,
output VAR4,
output... | gpl-2.0 |
Mailaender/linguist | samples/Verilog/t_div_pipelined.v | 1,988 | module MODULE1();
reg clk, VAR10, VAR7;
reg [7:0] VAR2, VAR3;
wire VAR1, VAR8;
wire [7:0] VAR9, VAR5;
parameter
VAR6 = 8;
VAR4
.VAR6(VAR6)
)
VAR4
(
.clk(clk),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR1(VAR1)
); | mit |
monotone-RK/FACE | IEICE-Trans/8-way_2-tree/src/ip_pcie/PCIeGen2x8If128_stub.v | 7,236 | module MODULE1(VAR43, VAR15, VAR83, VAR17, VAR16, VAR32, VAR11, VAR81, VAR53, VAR42, VAR54, VAR8, VAR76, VAR86, VAR67, VAR46, VAR2, VAR35, VAR70, VAR71, VAR28, VAR65, VAR52, VAR50, VAR49, VAR39, VAR12, VAR23, VAR14, VAR84, VAR72, VAR6, VAR3, VAR68, VAR44, VAR5, VAR38, VAR37, VAR41, VAR9, VAR61, VAR27, VAR85, VAR51, VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3b/sky130_fd_sc_hdll__or3b.functional.pp.v | 1,971 | module MODULE1 (
VAR6 ,
VAR16 ,
VAR12 ,
VAR7 ,
VAR4,
VAR14,
VAR3 ,
VAR5
);
output VAR6 ;
input VAR16 ;
input VAR12 ;
input VAR7 ;
input VAR4;
input VAR14;
input VAR3 ;
input VAR5 ;
wire VAR1 ;
wire VAR15 ;
wire VAR9;
not VAR13 (VAR1 , VAR7 );
or VAR2 (VAR15 , VAR12, VAR16, VAR1 );
VAR8 VAR11 (VAR9, VAR15, VAR4, VAR14);... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/mem_if/sram_top.v | 13,325 | module MODULE1 (
VAR8, VAR32,
VAR24, VAR5, VAR20, VAR14, VAR17, VAR3,
VAR11, VAR29, VAR18,
VAR13, VAR33, VAR25, VAR27, VAR10, VAR12, VAR26, VAR30,
VAR9, VAR7, VAR23, VAR21, VAR4, VAR16, VAR19
);
parameter VAR1 = 19;
input VAR8;
input VAR32;
input [31:0] VAR24;
output [31:0] VAR5;
input [31:0] VAR20;
input [3:0] VAR14;
... | apache-2.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/new/7seg.v | 1,776 | module MODULE1(
output reg [6:0] VAR2,
output reg [3:0] VAR4,
input wire [15:0] VAR5,
input wire rst,
input wire clk
);
reg [15:0] VAR1;
reg [3:0] VAR3;
always @ (posedge clk, posedge rst) begin
if (rst) begin
VAR1 <= 15'b0;
end else begin
VAR1 <= VAR1 + 15'b1;
end
end
always @ (posedge VAR1[15], posedge rst) begin
if ... | gpl-3.0 |
lab1-ufba/Genius | timer.v | 1,304 | module MODULE1(clk, VAR2, VAR3, ready);
input clk, VAR2;
input[1:0] VAR3;
output reg ready;
reg state;
reg VAR4;
reg [16:0] VAR6;
parameter VAR1 = 1'b0, VAR5 = 1'b1;
always @(*) begin
case(state)
VAR1:begin
if(VAR3 == 2'b01)begin
VAR4 = VAR5;
end
else if(VAR3 == 2'b10)begin
VAR4 = VAR5;
end
else if(VAR3 == 2'b11)begin
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311oi/sky130_fd_sc_hs__a311oi.pp.symbol.v | 1,369 | module MODULE1 (
input VAR5 ,
input VAR4 ,
input VAR8 ,
input VAR7 ,
input VAR6 ,
output VAR1 ,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_saturate.v | 2,705 | module MODULE1
parameter VAR2 = 20,
parameter VAR6 = 10
)
(
input signed [VAR4-1:0] VAR5,
output signed [VAR2-1:0] VAR3,
output VAR1
);
assign {VAR3,VAR1} = ( {VAR5[VAR4-1],|VAR5[VAR4-2:VAR6+VAR2-1]} ==2'b01) ?
{{1'b0,{VAR2-1{1'b1}}},1'b1} : ( {VAR5[VAR4-1],&VAR5[VAR4-2:VAR6+VAR2-1]} == 2'b10) ?
{{1'b1,{VAR2-1{1'b0}}},... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxbp/sky130_fd_sc_ms__sedfxbp_1.v | 2,564 | module MODULE1 (
VAR12 ,
VAR1 ,
VAR6 ,
VAR13 ,
VAR10 ,
VAR9 ,
VAR5 ,
VAR3,
VAR8,
VAR4 ,
VAR2
);
output VAR12 ;
output VAR1 ;
input VAR6 ;
input VAR13 ;
input VAR10 ;
input VAR9 ;
input VAR5 ;
input VAR3;
input VAR8;
input VAR4 ;
input VAR2 ;
VAR7 VAR11 (
.VAR12(VAR12),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR13(VAR13),
.VAR10(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfxbp/sky130_fd_sc_hs__dfxbp_1.v | 2,101 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR3 ,
VAR2 ,
VAR4,
VAR7
);
input VAR8 ;
input VAR5 ;
output VAR3 ;
output VAR2 ;
input VAR4;
input VAR7;
VAR6 VAR1 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR8,
VAR5 ,
VAR3 ,
VAR2
);
input VAR8;
input VAR5 ;
output VAR3... | apache-2.0 |
trevortheblack/NL16-BinaryCompression | buffer.v | 3,597 | module MODULE1 (
input wire [3:0] VAR7,
input wire VAR3,
output reg VAR6,
output reg VAR9,
output wire VAR4,
input wire VAR8,
input wire VAR5
);
reg [31:0] VAR2; reg [31:0] VAR1;
assign VAR4 = VAR1[29];
always @ (posedge VAR8 or negedge VAR5) begin
if(~VAR5) begin
VAR2 <= 32'b0;
end
else begin
if (VAR3) begin
VAR2 <= (... | apache-2.0 |
PyLCARS/PythonUberHDL | myHDL_ComputerFundamentals/Counters/ClockDivider.v | 1,354 | module MODULE1 (
VAR2,
VAR3,
VAR5,
clk,
rst
);
input [31:0] VAR2;
output VAR3;
wire VAR3;
output [31:0] VAR5;
wire [31:0] VAR5;
input clk;
input rst;
reg [31:0] VAR7 = 0;
reg VAR1 = 0;
always @(posedge clk, posedge rst) begin: VAR6
if (rst) begin
VAR7 <= 0;
end
else if ((({1'b0, VAR7}) == (({1'b0, VAR2}) - 1))) begin
V... | bsd-3-clause |
tmatsuya/milkymist-ml401 | cores/softusb/rtl/softusb.v | 3,031 | module MODULE1 #(
parameter VAR3 = 4'h0
) (
input VAR33,
input VAR34,
input VAR29,
input [13:0] VAR36,
input VAR19,
input [31:0] VAR28,
output [31:0] VAR6,
output irq,
input [31:0] VAR9,
output [31:0] VAR24,
input [31:0] VAR16,
input [3:0] VAR23,
input VAR8,
input VAR40,
output VAR20,
input VAR38,
output VAR15,
output ... | lgpl-3.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/lpddr2_cntrlr/lpddr2_cntrlr/lpddr2_cntrlr_p0_acv_hard_addr_cmd_pads.v | 9,245 | module MODULE1(
VAR28,
VAR83,
VAR2,
VAR118,
VAR34,
VAR20,
VAR89,
VAR106,
VAR101,
VAR116,
VAR98,
VAR93,
VAR123,
VAR120,
VAR29,
VAR84,
VAR8,
VAR75,
VAR70,
VAR126,
VAR40,
VAR60,
VAR113,
VAR37,
VAR64,
VAR1,
VAR55,
VAR94,
VAR73
);
parameter VAR59 = "";
parameter VAR121 = "";
parameter VAR103 = "";
parameter VAR7 = "";
param... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbn/sky130_fd_sc_hd__sdfbbn_2.v | 2,825 | module MODULE1 (
VAR9 ,
VAR14 ,
VAR7 ,
VAR1 ,
VAR4 ,
VAR2 ,
VAR11 ,
VAR5,
VAR6 ,
VAR8 ,
VAR10 ,
VAR12
);
output VAR9 ;
output VAR14 ;
input VAR7 ;
input VAR1 ;
input VAR4 ;
input VAR2 ;
input VAR11 ;
input VAR5;
input VAR6 ;
input VAR8 ;
input VAR10 ;
input VAR12 ;
VAR13 VAR3 (
.VAR9(VAR9),
.VAR14(VAR14),
.VAR7(VAR7),
... | apache-2.0 |
grindars/bfcore | BrainfuckWrapper.v | 1,981 | module MODULE1(
VAR3, VAR5,
VAR8, VAR29, VAR31, VAR1, VAR28, VAR6
);
parameter VAR26 = 1;
parameter VAR15 = 11;
parameter VAR7 = 11;
parameter VAR12 = 8;
parameter VAR25 = 7;
input VAR3;
input VAR5;
input [7:0] VAR8;
output [7:0] VAR29;
input VAR31;
output VAR1;
output VAR28;
input VAR6;
wire [VAR15 - 1:0] VAR9;
wire [... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3/ddr3_int_controller_phy.v | 14,647 | module MODULE1 (
VAR76,
VAR35,
VAR23,
VAR119,
VAR129,
VAR8,
VAR19,
VAR53,
VAR7,
VAR73,
VAR133,
VAR138,
VAR102,
VAR115,
VAR152,
VAR113,
VAR107,
VAR134,
VAR93,
VAR38,
VAR89,
VAR80,
VAR66,
VAR130,
VAR56,
VAR2,
VAR1,
VAR25,
VAR104,
VAR10,
VAR78,
VAR75,
VAR29,
VAR79,
VAR9,
VAR99,
VAR151,
VAR27,
VAR68,
VAR21,
VAR141,
VAR150,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fa/sky130_fd_sc_lp__fa.symbol.v | 1,291 | module MODULE1 (
input VAR5 ,
input VAR8 ,
input VAR9 ,
output VAR4,
output VAR3
);
supply1 VAR6;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4/sky130_fd_sc_hs__and4.functional.pp.v | 1,735 | module MODULE1 (
VAR3,
VAR13,
VAR4 ,
VAR10 ,
VAR1 ,
VAR8 ,
VAR11
);
input VAR3;
input VAR13;
output VAR4 ;
input VAR10 ;
input VAR1 ;
input VAR8 ;
input VAR11 ;
wire VAR2 ;
wire VAR6;
and VAR12 (VAR2 , VAR10, VAR1, VAR8, VAR11 );
VAR9 VAR7 (VAR6, VAR2, VAR3, VAR13);
buf VAR5 (VAR4 , VAR6 );
endmodule | apache-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/reg_grp.v | 5,680 | module MODULE1 #(parameter
VAR12 = 10,
VAR20 = 4
)
(
input VAR11,
input VAR23,
input [VAR12 -1:0] VAR25,
input [VAR1 -1:0] VAR5,
output reg VAR19,
output reg [VAR1 -1:0] VAR4,
output [VAR20 - 1 : 0] VAR13,
output [VAR20 - 1 : 0] VAR21,
output [VAR20 * (VAR12 - VAR2(VAR20)) -1:0] VAR29,
output [VAR20 * VAR1 -1:0] VAR3,
... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_sdio_device/rtl/wb_sdio_device.v | 24,106 | module MODULE1 (
input clk,
input rst,
input VAR34,
input VAR114,
input [3:0] VAR201,
input [31:0] VAR108,
input VAR252,
output reg VAR41,
output reg [31:0] VAR290,
input [31:0] VAR83,
output VAR57,
input VAR81,
inout VAR143,
inout [3:0] VAR261
);
localparam VAR94 = 32'h00000000;
localparam VAR162 = 32'h00000001;
local... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221ai/sky130_fd_sc_lp__o221ai.behavioral.pp.v | 2,212 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR13 ,
VAR7 ,
VAR3 ,
VAR2 ,
VAR11,
VAR4,
VAR19 ,
VAR16
);
output VAR9 ;
input VAR5 ;
input VAR13 ;
input VAR7 ;
input VAR3 ;
input VAR2 ;
input VAR11;
input VAR4;
input VAR19 ;
input VAR16 ;
wire VAR12 ;
wire VAR15 ;
wire VAR17 ;
wire VAR8;
or VAR6 (VAR12 , VAR3, VAR7 );
or VAR10 (VAR15 ... | apache-2.0 |
ptracton/Picoblaze | projects/timers/rtl/cpu.v | 2,786 | module MODULE1 (
VAR8, VAR20, VAR18, VAR19, VAR1,
clk, VAR4, interrupt, VAR17, VAR10
) ;
input clk;
input [7:0] VAR4;
output [7:0] VAR8;
output [7:0] VAR20;
output VAR18;
output VAR19;
input interrupt; output VAR1;
input VAR17;
input VAR10;
wire [11:0] address;
wire [17:0] VAR14;
wire [7:0] VAR20;
wire [7:0] VAR8;
wire... | mit |
545/Atari7800 | core/ag_6502/trunk/juke-box/chip1.v | 2,894 | module MODULE2(input clk,
input VAR13, input VAR46,
output wire VAR40, output wire VAR35);
reg VAR54 = 0, VAR17 = 0;
assign VAR40 = VAR17, VAR35 = VAR54;
always @(posedge clk) begin
case ({VAR13, VAR46})
2'b00: VAR54 <= 1;
2'b11: VAR54 <= 0;
2'b10: VAR17 <= 1;
2'b01: VAR17 <= 0;
endcase
end
endmodule
module MODULE3(inp... | gpl-2.0 |
SymbiFlow/prjxray | fuzzers/051-pip-imuxlout-bypalts/picorv32.v | 92,421 | module MODULE1 #(
parameter [ 0:0] VAR49 = 1,
parameter [ 0:0] VAR9 = 1,
parameter [ 0:0] VAR32 = 1,
parameter [ 0:0] VAR40 = 1,
parameter [ 0:0] VAR99 = 0,
parameter [ 0:0] VAR7 = 1,
parameter [ 0:0] VAR21 = 0,
parameter [ 0:0] VAR50 = 0,
parameter [ 0:0] VAR25 = 0,
parameter [ 0:0] VAR24 = 0,
parameter [ 0:0] VAR6 = ... | isc |
monotone-RK/FACE | MCSoC-15/4-way_4-parallel/ise/ipcore_dir/dram/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_wrcal.v | 53,935 | module MODULE1 #
(
parameter VAR34 = 100, parameter VAR208 = 2, parameter VAR49 = 2500,
parameter VAR76 = 64, parameter VAR41 = 3, parameter VAR135 = 8, parameter VAR87 = 8, parameter VAR226 = "VAR189", parameter VAR134 = "VAR170" )
(
input clk,
input rst,
input VAR223,
input VAR39,
input VAR192,
input VAR229,
input VA... | mit |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_spram_64x24.v | 11,038 | module MODULE1(
VAR32, VAR49, VAR4,
clk, rst, VAR19, VAR39, VAR27, addr, VAR44, VAR47
);
parameter VAR36 = 6;
parameter VAR54 = 24;
input VAR32;
input [VAR46 - 1:0] VAR4;
output VAR49;
input clk; input rst; input VAR19; input VAR39; input VAR27; input [VAR36-1:0] addr; input [VAR54-1:0] VAR44; output [VAR54-1:0] VAR47;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtp/sky130_fd_sc_hs__dfrtp.pp.symbol.v | 1,363 | module MODULE1 (
input VAR3 ,
output VAR1 ,
input VAR4,
input VAR5 ,
input VAR2 ,
input VAR6
);
endmodule | apache-2.0 |
sabertazimi/hust-lab | verilog/labs/lab5/src/_3bit_binary_multiplier.v | 2,304 | module MODULE1(
module 3bitbinarymultiplier
(
input VAR7,
input clk,
input [(VAR21-1):0] VAR23,
input [(VAR21-1):0] VAR28,
output [((VAR21*2)-1):0] VAR6,
output VAR11
);
wire VAR36, VAR14, VAR32, VAR25, VAR35;
wire VAR38;
wire [(VAR21-1):0] VAR4, VAR30;
wire VAR26;
wire VAR22, VAR5, VAR8;
wire [(VAR21-1):0] VAR13, VAR1... | mit |
CospanDesign/nysa-artemis-platform | artemis/slave/wb_nysa_artemis_platform/rtl/wb_nysa_artemis_platform.v | 39,161 | module MODULE1 #(
parameter VAR42 = 1,
parameter VAR70 = 1,
parameter VAR79 = 0,
parameter VAR156 = 0,
parameter VAR285 = 0
)(
input clk,
input rst,
input VAR99,
input VAR140,
input [3:0] VAR314,
input [31:0] VAR22,
input VAR217,
output reg VAR8,
output reg [31:0] VAR151,
input [31:0] VAR253,
output reg VAR204,
output ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2b/sky130_fd_sc_ms__nand2b.pp.symbol.v | 1,296 | module MODULE1 (
input VAR7 ,
input VAR6 ,
output VAR5 ,
input VAR2 ,
input VAR1,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/decap/sky130_fd_sc_hvl__decap.functional.v | 1,043 | module MODULE1 ();
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_seeed_tft/rtl/wb_seeed_tft.v | 18,948 | module MODULE1 #(
parameter VAR36 = 12
)(
input clk,
input rst,
output [31:0] VAR124,
input VAR73,
input VAR93,
input VAR69,
input [3:0] VAR26,
input [31:0] VAR62,
input [31:0] VAR2,
output reg [31:0] VAR78,
output reg VAR39,
output reg VAR35,
output VAR5,
output VAR84,
output VAR45,
output [3:0] VAR114,
output [31:0] ... | mit |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/clip_and_round_reg.v | 1,296 | module MODULE1
parameter VAR3=0,
parameter VAR4=0)
(input clk,
input [VAR2-1:0] in,
output reg [VAR3-1:0] out);
wire [VAR3-1:0] VAR5;
VAR1 #(.VAR2(VAR2),.VAR3(VAR3),.VAR4(VAR4))
VAR1 (.in(in),.out(VAR5));
always@(posedge clk)
out <= VAR5;
endmodule | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/RecComp_cnn_lab_convolve_kernel_1_0/hdl/verilog/convolve_kernel_fbkb.v | 2,143 | module MODULE1
VAR14 = 1,
VAR26 = 14,
VAR22 = 32,
VAR3 = 32,
VAR4 = 32
)(
input wire clk,
input wire reset,
input wire VAR28,
input wire [VAR22-1:0] VAR21,
input wire [VAR3-1:0] VAR16,
output wire [VAR4-1:0] dout
);
wire VAR8;
wire VAR5;
wire VAR15;
wire [31:0] VAR9;
wire VAR23;
wire [31:0] VAR2;
wire VAR20;
wire [31:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.blackbox.v | 1,437 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR6 ,
VAR3 ,
VAR1,
VAR5 ,
VAR4
);
output VAR7 ;
input VAR2 ;
input VAR6 ;
input VAR3 ;
input VAR1;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_1.behavioral.pp.v | 3,755 | module MODULE1( VAR11, VAR12, VAR5, VAR28, VAR6, VAR15 );
input VAR11, VAR12, VAR5;
inout VAR6, VAR15;
output VAR28;
reg VAR13;
VAR21 VAR30(.VAR11(VAR11),.VAR12(VAR12),.VAR5(VAR5),.VAR28(VAR28),.VAR6(VAR6),.VAR15(VAR15),.VAR13(VAR13));
VAR21 VAR7(.VAR11(VAR11),.VAR12(VAR12),.VAR5(VAR5),.VAR28(VAR28),.VAR6(VAR6),.VAR15(... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project_default.xpr/project_1/project_1.ipdefs/ip_0/hdl/verilog/convolve_kernel_fcud.v | 1,944 | module MODULE1
VAR14 = 1,
VAR6 = 4,
VAR22 = 32,
VAR13 = 32,
VAR2 = 32
)(
input wire clk,
input wire reset,
input wire VAR24,
input wire [VAR22-1:0] VAR5,
input wire [VAR13-1:0] VAR8,
output wire [VAR2-1:0] dout
);
wire VAR4;
wire VAR10;
wire VAR7;
wire [31:0] VAR1;
wire VAR25;
wire [31:0] VAR16;
wire VAR15;
wire [31:0]... | mit |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cpu/apu/apu_pulse.v | 6,875 | module MODULE1
parameter [0:0] VAR22 = 1'b0 )
(
input wire VAR44, input wire VAR45, input wire VAR31, input wire VAR30, input wire VAR35, input wire VAR28, input wire [1:0] VAR51, input wire [7:0] din, input wire VAR11, output wire [3:0] VAR26, output wire VAR29 );
wire VAR5;
wire VAR54;
wire [3:0] VAR37;
VAR33 VAR21(
... | mit |
chriswynnyk/american-put-verilog | american_put_stratix/src/mem_2k.v | 9,336 | module MODULE1 (
VAR39,
VAR38,
VAR13,
VAR47,
VAR36,
VAR10,
VAR4);
input [63:0] VAR39;
input [10:0] VAR38;
input VAR13;
input [10:0] VAR47;
input VAR36;
input VAR10;
output [63:0] VAR4;
wire [63:0] VAR11;
wire [63:0] VAR4 = VAR11[63:0];
VAR34 VAR20 (
.VAR14 (VAR10),
.VAR30 (VAR36),
.VAR54 (VAR13),
.VAR18 (VAR47),
.VAR41... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2b/sky130_fd_sc_hdll__nand2b.behavioral.pp.v | 1,956 | module MODULE1 (
VAR12 ,
VAR9 ,
VAR10 ,
VAR13,
VAR14,
VAR3 ,
VAR11
);
output VAR12 ;
input VAR9 ;
input VAR10 ;
input VAR13;
input VAR14;
input VAR3 ;
input VAR11 ;
wire VAR5 ;
wire VAR7 ;
wire VAR6;
not VAR15 (VAR5 , VAR10 );
or VAR4 (VAR7 , VAR5, VAR9 );
VAR1 VAR8 (VAR6, VAR7, VAR13, VAR14);
buf VAR2 (VAR12 , VAR6 );... | apache-2.0 |
ncos/Xilinx-Verilog | GYRACC/src/GYRO/seven_seg_decoder.v | 3,608 | module MODULE1(
VAR5,
VAR3,
VAR6,
VAR2
);
input [3:0] VAR5;
input [1:0] VAR3;
output [6:0] VAR6;
input VAR2;
wire [6:0] VAR7;
wire [6:0] VAR4;
wire [6:0] VAR1;
assign VAR6 = (VAR3 == 2'b11 & VAR2 == 1'b0) ? 7'b0001001 : VAR1;
assign VAR1 = (VAR2 == 1'b1) ? VAR7 : VAR4;
assign VAR7 = (VAR5 == 4'b0000) ? 7'b1000000 : (VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrbn/sky130_fd_sc_hd__dlrbn.functional.v | 1,942 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR12,
VAR5 ,
VAR15
);
output VAR6 ;
output VAR2 ;
input VAR12;
input VAR5 ;
input VAR15 ;
wire VAR13 ;
wire VAR8;
wire VAR9 ;
not VAR7 (VAR13 , VAR12 );
not VAR11 (VAR8, VAR15 );
VAR4 VAR3 VAR1 (VAR9 , VAR5, VAR8, VAR13);
buf VAR14 (VAR6 , VAR9 );
not VAR10 (VAR2 , VAR9 );
endmodule | apache-2.0 |
mbus/mbus | releases/mbus_example-v1.1/verilog/mbc_header.v | 2,008 | module MODULE1
(
VAR2
);
input VAR2;
always @(VAR2) begin
if (VAR2) begin
("%VAR1[1;34m",27);
("%VAR1[0m",27);
end
else begin
("%VAR1[1;34m",27);
("%VAR1[0m",27);
end
end
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111ai/sky130_fd_sc_lp__o2111ai.blackbox.v | 1,402 | module MODULE1 (
VAR4 ,
VAR1,
VAR9,
VAR6,
VAR10,
VAR7
);
output VAR4 ;
input VAR1;
input VAR9;
input VAR6;
input VAR10;
input VAR7;
supply1 VAR5;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/chris.final/Qsys/soc_design/synthesis/submodules/soc_design_mm_interconnect_0_avalon_st_adapter_001.v | 6,176 | module MODULE1 #(
parameter VAR20 = 34,
parameter VAR23 = 0,
parameter VAR1 = 34,
parameter VAR16 = 0,
parameter VAR13 = 0,
parameter VAR5 = 0,
parameter VAR10 = 1,
parameter VAR4 = 1,
parameter VAR17 = 0,
parameter VAR25 = 34,
parameter VAR9 = 0,
parameter VAR15 = 1,
parameter VAR14 = 0,
parameter VAR18 = 1,
parameter... | gpl-2.0 |
Marcoslz22/Tercer_Proyecto | PixCounter.v | 1,825 | module MODULE1(
VAR2, VAR4, VAR8, VAR6 );
parameter VAR5 = 10; parameter VAR7 = 5; parameter VAR3 = 10;
input VAR2; input VAR6; input [9:0]VAR4; output reg [VAR5 - 1: 0] VAR8;
VAR1 begin VAR8 = 0;
end
always@(posedge VAR2) begin if (VAR6) begin if ((VAR4 > VAR7) && (VAR4 <= VAR3-1))
end
VAR8 <= VAR8 + 1; else
VAR8 <= 0... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_4.functional.v | 1,142 | module MODULE1( VAR3, VAR9, VAR10 );
input VAR9, VAR3;
output VAR10;
wire VAR8;
not VAR6( VAR8, VAR3 );
wire VAR11;
and VAR2( VAR11, VAR8, VAR9 );
wire VAR12;
not VAR5( VAR12, VAR9 );
wire VAR1;
and VAR7( VAR1, VAR12, VAR3 );
or VAR4( VAR10, VAR11, VAR1 );
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/mig_7series_v1_8_ddr_phy_oclkdelay_cal.v | 46,589 | module MODULE1 #
(
parameter VAR141 = 100,
parameter VAR149 = 2500,
parameter VAR9 = 4,
parameter VAR117 = "VAR105",
parameter VAR75 = 8,
parameter VAR138 = 3,
parameter VAR11 = 8,
parameter VAR59 = 64,
parameter VAR7 = "VAR167",
parameter VAR156 = "VAR114"
)
(
input clk,
input rst,
input VAR15,
input VAR118,
input [5:... | mit |
h-j-13/MyNote | Programming language/Verilog/sync_FIFO/Source_Code/FIFO_3.v | 2,418 | module MODULE1(
VAR18,
VAR6,
VAR4,
VAR3,
VAR7,
VAR9,
VAR19,
VAR14,
VAR2,
clk,
rst
);
parameter VAR16=32;
parameter VAR13=8;
parameter VAR5=3;
parameter VAR11=2;
parameter VAR8=6;
parameter VAR1=4;
output [VAR16-1:0] VAR18;
output VAR6,VAR4,VAR3;
output VAR7,VAR9;
input[VAR16-1:0] VAR19;
input VAR14,VAR2;
input clk,rst;... | gpl-3.0 |
m-labs/milkymist | cores/conbus/rtl/conbus_arb5.v | 2,041 | module MODULE1(
input VAR1,
input VAR3,
input [4:0] req,
output [2:0] VAR2
);
reg [2:0] state;
reg [2:0] VAR4;
assign VAR2 = state;
always @(posedge VAR1) begin
if(VAR3)
state <= 3'd0;
end
else
state <= VAR4;
end
always @(*) begin
VAR4 = state;
case(state)
3'd0: begin
if(~req[0]) begin
if(req[1]) VAR4 = 3'd1;
end
else ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxbp/sky130_fd_sc_ms__sedfxbp.pp.blackbox.v | 1,455 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR7 ,
VAR5 ,
VAR2 ,
VAR11 ,
VAR9 ,
VAR8,
VAR4,
VAR1 ,
VAR10
);
output VAR6 ;
output VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR2 ;
input VAR11 ;
input VAR9 ;
input VAR8;
input VAR4;
input VAR1 ;
input VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a311o/sky130_fd_sc_ls__a311o.behavioral.pp.v | 2,064 | module MODULE1 (
VAR18 ,
VAR14 ,
VAR8 ,
VAR11 ,
VAR12 ,
VAR16 ,
VAR9,
VAR3,
VAR1 ,
VAR13
);
output VAR18 ;
input VAR14 ;
input VAR8 ;
input VAR11 ;
input VAR12 ;
input VAR16 ;
input VAR9;
input VAR3;
input VAR1 ;
input VAR13 ;
wire VAR6 ;
wire VAR10 ;
wire VAR15;
and VAR5 (VAR6 , VAR11, VAR14, VAR8 );
or VAR7 (VAR10 , ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4b/sky130_fd_sc_ls__nand4b.behavioral.pp.v | 1,998 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR12 ,
VAR14 ,
VAR15 ,
VAR7,
VAR6,
VAR16 ,
VAR8
);
output VAR5 ;
input VAR2 ;
input VAR12 ;
input VAR14 ;
input VAR15 ;
input VAR7;
input VAR6;
input VAR16 ;
input VAR8 ;
wire VAR3 ;
wire VAR9 ;
wire VAR13;
not VAR1 (VAR3 , VAR2 );
nand VAR10 (VAR9 , VAR15, VAR14, VAR12, VAR3 );
VAR11 VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor3/sky130_fd_sc_hd__xnor3.blackbox.v | 1,269 | module MODULE1 (
VAR2,
VAR4,
VAR3,
VAR5
);
output VAR2;
input VAR4;
input VAR3;
input VAR5;
supply1 VAR6;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/maj3/sky130_fd_sc_ls__maj3.functional.pp.v | 2,186 | module MODULE1 (
VAR1 ,
VAR17 ,
VAR12 ,
VAR8 ,
VAR19,
VAR6,
VAR14 ,
VAR9
);
output VAR1 ;
input VAR17 ;
input VAR12 ;
input VAR8 ;
input VAR19;
input VAR6;
input VAR14 ;
input VAR9 ;
wire VAR13 ;
wire VAR10 ;
wire VAR16 ;
wire VAR7 ;
wire VAR18;
or VAR3 (VAR13 , VAR12, VAR17 );
and VAR20 (VAR10 , VAR13, VAR8 );
and VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkbuf/sky130_fd_sc_hdll__clkbuf.blackbox.v | 1,236 | module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
supply1 VAR5;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3b/sky130_fd_sc_lp__nor3b.functional.pp.v | 1,995 | module MODULE1 (
VAR15 ,
VAR11 ,
VAR4 ,
VAR10 ,
VAR8,
VAR1,
VAR2 ,
VAR3
);
output VAR15 ;
input VAR11 ;
input VAR4 ;
input VAR10 ;
input VAR8;
input VAR1;
input VAR2 ;
input VAR3 ;
wire VAR12 ;
wire VAR9 ;
wire VAR6;
nor VAR5 (VAR12 , VAR11, VAR4 );
and VAR13 (VAR9 , VAR10, VAR12 );
VAR16 VAR14 (VAR6, VAR9, VAR8, VAR1)... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/phy/phy_rddata_sync.v | 23,639 | module MODULE1 #
(
parameter VAR22 = 100, parameter VAR39 = 64, parameter VAR27 = 8, parameter VAR1 = 8, parameter VAR5 = 4, parameter VAR44 = 4, parameter VAR71 = 4, parameter VAR11 = 4, parameter VAR14 = 32'h03020100, parameter VAR61 = 32'h07060504, parameter VAR55 = 0, parameter VAR25 = 0 )
(
input clk,
input [3:0] ... | lgpl-3.0 |
monotone-RK/FACE | MCSoC-15/4-way_2-parallel/ise/ipcore_dir/dram/user_design/rtl/ui/mig_7series_v1_9_ui_wr_data.v | 21,329 | module MODULE1 #
(
parameter VAR6 = 100,
parameter VAR12 = 256,
parameter VAR11 = 32,
parameter VAR36 = "VAR81",
parameter VAR32 = 2 ,
parameter VAR80 = "VAR81",
parameter VAR50 = 5
)
(
VAR40, VAR76, VAR88, VAR74, VAR18,
VAR33,
rst, clk, VAR105, VAR14, VAR64, VAR60,
VAR56, VAR101, VAR52, VAR98, VAR78,
VAR67, VAR10
);
i... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_2.behavioral.pp.v | 2,030 | module MODULE1( VAR3, VAR4, VAR7, VAR9, VAR2, VAR6, VAR10 );
input VAR2, VAR9, VAR7, VAR3;
inout VAR6, VAR10;
output VAR4;
VAR5 VAR1(.VAR3(VAR3),.VAR4(VAR4),.VAR7(VAR7),.VAR9(VAR9),.VAR2(VAR2),.VAR6(VAR6),.VAR10(VAR10));
VAR5 VAR8(.VAR3(VAR3),.VAR4(VAR4),.VAR7(VAR7),.VAR9(VAR9),.VAR2(VAR2),.VAR6(VAR6),.VAR10(VAR10)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xnor2/sky130_fd_sc_hvl__xnor2.pp.blackbox.v | 1,305 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR1 ,
VAR6,
VAR3,
VAR7 ,
VAR2
);
output VAR5 ;
input VAR4 ;
input VAR1 ;
input VAR6;
input VAR3;
input VAR7 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlstp/sky130_fd_sc_lp__srdlstp.symbol.v | 1,440 | module MODULE1 (
input VAR1 ,
output VAR9 ,
input VAR10 ,
input VAR2 ,
input VAR5
);
supply1 VAR7;
supply1 VAR6 ;
supply0 VAR4 ;
supply1 VAR3 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_4.behavioral.pp.v | 8,974 | module MODULE1( VAR48, VAR72, VAR64, VAR71, VAR38, VAR32, VAR89 );
input VAR71, VAR64, VAR48, VAR72;
inout VAR32, VAR89;
output VAR38;
reg VAR58;
VAR21 VAR14(.VAR48(VAR48),.VAR72(VAR72),.VAR64(VAR64),.VAR71(VAR71),.VAR38(VAR38),.VAR32(VAR32),.VAR89(VAR89),.VAR58(VAR58));
VAR21 VAR20(.VAR48(VAR48),.VAR72(VAR72),.VAR64(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.v | 2,201 | module MODULE1 (
VAR1,
VAR3 ,
VAR6 ,
VAR2 ,
VAR4
);
output VAR1;
input VAR3 ;
input VAR6 ;
input VAR2 ;
input VAR4 ;
VAR5 VAR7 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR1,
VAR3
);
output VAR1;
input VAR3 ;
supply1 VAR6;
supply1 VAR2 ;
supply0 VAR4 ;
VAR5 VAR7 (
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fill/sky130_fd_sc_hd__fill.functional.pp.v | 1,147 | module MODULE1 (
VAR4,
VAR1,
VAR3 ,
VAR2
);
input VAR4;
input VAR1;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_arbdatadp.v | 17,544 | module MODULE1(
VAR23, VAR38, VAR22,
VAR97, VAR101, VAR84,
VAR26, VAR20, VAR91,
VAR4, VAR43, VAR9,
VAR31, VAR100, VAR98,
VAR52, VAR14, VAR94,
VAR16, VAR87, VAR2,
VAR72, VAR67, VAR68, VAR11, VAR80
);
input [63:0] VAR4;
input [63:0] VAR43 ;
input [63:0] VAR9; input VAR31;
input VAR100; input VAR98; input VAR52; input VAR... | gpl-2.0 |
ptracton/wb_soc_template | rtl/XILINX/MMCME2_BASE.v | 4,855 | module MODULE1 (
VAR59,
VAR19,
VAR38,
VAR33,
VAR1,
VAR13,
VAR31,
VAR28,
VAR35,
VAR71,
VAR69,
VAR41,
VAR6,
VAR52,
VAR30,
VAR43,
VAR34,
VAR24
);
parameter VAR53 = "VAR60";
parameter real VAR61 = 5.000;
parameter real VAR8 = 0.000;
parameter real VAR48 = 0.000;
parameter real VAR39 = 1.000;
parameter real VAR20 = 0.500;
p... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.v | 2,411 | module MODULE1 (
VAR1 ,
VAR3,
VAR5,
VAR4 ,
VAR7 ,
VAR11,
VAR9,
VAR10 ,
VAR8
);
output VAR1 ;
input VAR3;
input VAR5;
input VAR4 ;
input VAR7 ;
input VAR11;
input VAR9;
input VAR10 ;
input VAR8 ;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR8... | apache-2.0 |
omicronns/studies-sys-rek | de1-soc-template/v/sdram_pll/sdram_pll_0002.v | 2,731 | module MODULE1(
input wire VAR2,
input wire rst,
output wire VAR73,
output wire VAR71,
output wire VAR62,
output wire VAR41,
output wire VAR38
);
VAR16 #(
.VAR74("false"),
.VAR40("50.0 VAR48"),
.VAR17("VAR72"),
.VAR11(4),
.VAR37("100.000000 VAR48"),
.VAR67("0 VAR57"),
.VAR36(50),
.VAR25("100.000000 VAR48"),
.VAR50("750... | mit |
alexforencich/verilog-ethernet | lib/axis/rtl/axis_ll_bridge.v | 2,482 | module MODULE1 #
(
parameter VAR6 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR6-1:0] VAR1,
input wire VAR7,
output wire VAR8,
input wire VAR4,
output wire [VAR6-1:0] VAR11,
output wire VAR9,
output wire VAR3,
output wire VAR10,
input wire VAR5
);
reg VAR12 = 1'b1;
always @(posedge clk) begin
if (rst) begin
V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor2/sky130_fd_sc_hd__xnor2.blackbox.v | 1,274 | module MODULE1 (
VAR7,
VAR6,
VAR2
);
output VAR7;
input VAR6;
input VAR2;
supply1 VAR3;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a221oi/sky130_fd_sc_hdll__a221oi_4.v | 2,473 | module MODULE2 (
VAR4 ,
VAR2 ,
VAR11 ,
VAR12 ,
VAR7 ,
VAR5 ,
VAR8,
VAR6,
VAR1 ,
VAR9
);
output VAR4 ;
input VAR2 ;
input VAR11 ;
input VAR12 ;
input VAR7 ;
input VAR5 ;
input VAR8;
input VAR6;
input VAR1 ;
input VAR9 ;
VAR3 VAR10 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21bai/sky130_fd_sc_hd__o21bai.pp.blackbox.v | 1,398 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR8 ,
VAR1,
VAR2,
VAR5,
VAR3 ,
VAR4
);
output VAR7 ;
input VAR6 ;
input VAR8 ;
input VAR1;
input VAR2;
input VAR5;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.v | 2,458 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR3 ,
VAR12 ,
VAR2 ,
VAR5 ,
VAR7,
VAR4,
VAR1 ,
VAR10
);
output VAR6 ;
input VAR8 ;
input VAR3 ;
input VAR12 ;
input VAR2 ;
input VAR5 ;
input VAR7;
input VAR4;
input VAR1 ;
input VAR10 ;
VAR9 VAR11 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR12(VAR12),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VA... | apache-2.0 |
takeshineshiro/fpga_linear_128 | db/LVDS_AD_lvds_rx.v | 14,682 | module MODULE1
(
VAR1,
VAR8,
VAR3,
VAR6) ;
input VAR1;
input [7:0] VAR8;
output [7:0] VAR3;
output [7:0] VAR6;
reg [7:0] VAR4;
reg [7:0] VAR2;
reg [7:0] VAR9;
reg [7:0] VAR7;
reg [7:0] VAR5; | mit |
peteg944/music-fpga | Enlightened Main Project/ipcore_dir/Clock48MHZ.v | 7,564 | module MODULE1
( input VAR38,
output VAR3,
output VAR84,
output VAR63,
output VAR11
);
VAR80 VAR59
(.VAR32 (VAR75),
.VAR24 (VAR38));
wire [15:0] VAR30;
wire VAR78;
wire VAR73;
wire VAR35;
wire VAR36;
wire VAR48;
wire VAR53;
wire VAR60;
wire VAR31;
wire VAR64;
wire VAR62;
wire VAR55;
wire VAR14;
wire VAR50;
wire VAR10;
... | mit |
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