repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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xcthulhu/periphondemand | src/library/components/uart16550/hdl/raminfr.v | 5,856 | module MODULE1
(clk, VAR3, VAR4, VAR2, VAR6, VAR9);
parameter VAR7 = 4;
parameter VAR8 = 8;
parameter VAR1 = 16;
input clk;
input VAR3;
input [VAR7-1:0] VAR4;
input [VAR7-1:0] VAR2;
input [VAR8-1:0] VAR6;
output [VAR8-1:0] VAR9;
reg [VAR8-1:0] VAR5 [VAR1-1:0];
wire [VAR8-1:0] VAR9;
wire [VAR8-1:0] VAR6;
wire [VAR7-1:0]... | lgpl-2.1 |
h-j-13/MyNote | Programming language/Verilog/sync_FIFO/FIFO.v | 7,279 |
module MODULE1(VAR22, reset, read, write, VAR26, VAR25, VAR5, VAR15);
parameter VAR27 = 128; parameter VAR18 = 7; parameter VAR21 = 4; parameter VAR31 = 7'b1111111;
parameter
VAR20 = 7'b1111110,
VAR7 = 7'b0110000,
VAR29 = 7'b1101101,
VAR16 = 7'b0000110,
VAR11 = 7'b0110011,
VAR13 = 7'b1011011,
VAR30 = 7'b1011111,
VAR4... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/buffer_pool.v | 11,281 | module MODULE1
parameter VAR119 = 64)
(input VAR123,
input VAR116,
input VAR114,
input VAR101,
input [15:0] VAR49,
input [31:0] VAR77,
output [31:0] VAR2,
output reg VAR112,
output VAR27,
output VAR39,
input VAR1,
input VAR72,
input VAR136, input [7:0] VAR25, input [31:0] VAR53,
output [31:0] VAR58,
output VAR37,
outpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3b/sky130_fd_sc_hd__nand3b_2.v | 2,229 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR5 ,
VAR10 ,
VAR7,
VAR8,
VAR3 ,
VAR1
);
output VAR4 ;
input VAR9 ;
input VAR5 ;
input VAR10 ;
input VAR7;
input VAR8;
input VAR3 ;
input VAR1 ;
VAR2 VAR6 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_4.behavioral.pp.v | 6,220 | module MODULE1( VAR52, VAR49, VAR61, VAR21, VAR64, VAR47, VAR12 );
input VAR49, VAR52, VAR61, VAR21;
inout VAR47, VAR12;
output VAR64;
reg VAR10;
VAR32 VAR41(.VAR52(VAR52),.VAR49(VAR49),.VAR61(VAR61),.VAR21(VAR21),.VAR64(VAR64),.VAR47(VAR47),.VAR12(VAR12),.VAR10(VAR10));
VAR32 VAR46(.VAR52(VAR52),.VAR49(VAR49),.VAR61(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3.symbol.v | 1,321 | module MODULE1 (
input VAR3,
output VAR2
);
supply1 VAR4;
supply0 VAR1;
endmodule | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_sdd1/cheat.v | 11,678 | module MODULE1(
input clk,
input [7:0] VAR53,
input [23:0] VAR48,
input [7:0] VAR26,
input VAR43,
input VAR18,
input VAR51,
input VAR10,
input VAR39,
input VAR7,
input VAR4,
input VAR6,
input VAR61,
input VAR34,
input VAR14,
input VAR62,
input [2:0] VAR55,
input VAR25,
input [31:0] VAR44,
output [7:0] VAR24,
output VAR... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_pipe_reset.v | 16,020 | module MODULE1 #
(
parameter VAR10 = "VAR43", parameter VAR61 = "VAR17", parameter VAR16 = "VAR57", parameter VAR33 = 1, parameter VAR38 = 6'd63, parameter VAR19 = 1
)
(
input VAR41,
input VAR22,
input VAR37,
input VAR5,
input [VAR33-1:0] VAR50,
input VAR64,
input [VAR33-1:0] VAR2,
input [VAR33-1:0] VAR48,
input VAR56,... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_dcm.v | 32,490 | module MODULE3(
VAR39, VAR73, VAR46, VAR75, VAR41, VAR58, VAR32,
VAR8, VAR64, VAR30, VAR5, VAR28, VAR47, VAR65,
VAR23, VAR1, VAR71, VAR21, VAR14, VAR38, VAR19,
VAR17, VAR66, VAR70, VAR42, VAR13, VAR63,
VAR53, VAR7, VAR72, VAR22, VAR43, VAR33,
VAR67, VAR57
);
output [31:0] VAR39;
output [31:0] VAR73; output [31:0] VAR46... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21bai/sky130_fd_sc_ms__o21bai.functional.v | 1,558 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR9 ,
VAR3
);
output VAR6 ;
input VAR7 ;
input VAR9 ;
input VAR3;
wire VAR5 ;
wire VAR11 ;
wire VAR1;
not VAR10 (VAR5 , VAR3 );
or VAR8 (VAR11 , VAR9, VAR7 );
nand VAR2 (VAR1, VAR5, VAR11 );
buf VAR4 (VAR6 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222oi/sky130_fd_sc_hs__a222oi_1.v | 2,415 | module MODULE2 (
VAR10 ,
VAR7 ,
VAR3 ,
VAR4 ,
VAR11 ,
VAR2 ,
VAR6 ,
VAR1,
VAR5
);
output VAR10 ;
input VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR11 ;
input VAR2 ;
input VAR6 ;
input VAR1;
input VAR5;
VAR9 VAR8 (
.VAR10(VAR10),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
... | apache-2.0 |
mlarouche/sd2snes | verilog/sd2snes_cx4/cx4.v | 26,899 | module MODULE1(
input [7:0] VAR10,
output [7:0] VAR39,
input [12:0] VAR54,
input VAR25,
input VAR5,
input VAR36,
input VAR50,
input [7:0] VAR28,
output [23:0] VAR21,
output VAR42,
input VAR38,
output VAR34,
output [2:0] VAR35,
input VAR29
);
reg [2:0] VAR12;
parameter VAR48 = 2'b00;
parameter VAR22 = 2'b01;
parameter V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32ai/sky130_fd_sc_lp__o32ai_0.v | 2,441 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR1 ,
VAR12 ,
VAR6 ,
VAR5 ,
VAR11,
VAR2,
VAR9 ,
VAR4
);
output VAR10 ;
input VAR7 ;
input VAR1 ;
input VAR12 ;
input VAR6 ;
input VAR5 ;
input VAR11;
input VAR2;
input VAR9 ;
input VAR4 ;
VAR8 VAR3 (
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR12(VAR12),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1... | apache-2.0 |
thinkoco/de1_soc_opencl | de1soc_sharedonly_vga/ip/TERASIC_IRM/TERASIC_IRM.v | 1,241 | module MODULE1(
clk, VAR4,
irq,
VAR16,
VAR15,
VAR3,
VAR11,
VAR7,
VAR8
);
input clk;
input VAR4;
output reg irq;
input VAR16;
input VAR15;
output [31:0] VAR3;
input VAR11;
input [31:0] VAR7;
input VAR8;
wire VAR5;
reg VAR14;
always @ (posedge clk or negedge VAR4)
begin
if (~VAR4)
VAR14 <= 1'b0;
end
else
VAR14 <= VAR5;
e... | apache-2.0 |
cybero/Verilog | src/PicoBlaze (kcpsm6)/Utilities/KCPSM6_Release9_30Sept14/UART_and_PicoTerm/uart_rx6.v | 14,468 | module MODULE1 (
input VAR58,
input VAR60,
output [7:0] VAR99,
input VAR7,
output VAR33,
output VAR78,
output VAR28,
input VAR72,
input clk );
wire [3:0] VAR30;
wire [3:0] VAR27;
wire VAR100;
wire VAR75;
wire VAR45;
wire VAR87;
wire VAR52;
wire VAR57;
wire VAR2;
wire VAR40;
wire VAR88;
wire VAR9;
wire VAR68;
wire [7:0]... | mit |
lbl-cal/StanfordNoC | router/src/clib/c_one_hot_therm_conv.v | 2,721 | module MODULE1
(VAR5, VAR2);
parameter VAR4 = 8;
localparam VAR8 = VAR6(VAR4);
input [0:VAR4-1] VAR5;
output [0:VAR4-1] VAR2;
wire [0:VAR4-1] VAR2;
genvar VAR3;
wire [0:(VAR8+1)*VAR4-1] VAR9;
assign VAR9[0:VAR4-1] = VAR5;
generate
for(VAR3 = 0; VAR3 < VAR8; VAR3 = VAR3 + 1)
begin:VAR7
wire [0:VAR4-1] VAR5;
assign VAR5 ... | bsd-2-clause |
asicguy/gplgpu | hdl/de/dex_top.v | 19,172 | module MODULE1
(
input VAR93, input VAR134, input VAR159, input [31:0] VAR60, input [31:0] VAR109, input [3:0] VAR111, input [3:0] VAR29, input [3:0] VAR78, input [3:0] VAR147, input VAR131, input VAR66, input VAR55, input VAR81, input [1:0] VAR106, input [1:0] VAR16, input VAR14, input VAR28, input VAR122, input VAR23... | gpl-3.0 |
apotocnik/redpitaya_guide | projects/4_frequency_counter/frequency_counter.v | 3,235 | module MODULE1 #
(
parameter VAR11 = 14,
parameter VAR10 = 32,
parameter VAR16 = 32,
parameter VAR15 = -100,
parameter VAR17 = -150
)
(
input [VAR10-1:0] VAR5,
input VAR6,
input clk,
input rst,
input [VAR16-1:0] VAR4,
output [VAR10-1:0] VAR1,
output VAR9,
output [VAR16-1:0] VAR14
);
wire signed [VAR11-1:0] VAR7;
reg st... | gpl-3.0 |
lbl-cal/StanfordNoC | router/src/clib/c_lfsr.v | 3,732 | module MODULE1
(clk, reset, VAR16, VAR6, VAR13, VAR12, VAR1, VAR10, VAR14);
parameter VAR8 = 32;
parameter VAR19 = 0;
parameter [VAR19:(VAR19+VAR8)-1] VAR23 = {VAR8{1'b1}};
parameter VAR4 = 1;
parameter VAR17 = VAR20;
input clk;
input reset;
input VAR16;
input VAR6;
input VAR13;
input [0:VAR8-1] VAR12;
input VAR1;
inpu... | bsd-2-clause |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/NIOS_SYSTEMV3/synthesis/submodules/NIOS_SYSTEMV3_CH0_YN1_U.v | 6,820 | module MODULE1 (
address,
VAR1,
clk,
VAR9,
VAR13,
VAR14,
VAR12,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input VAR1;
input clk;
input [ 13: 0] VAR9;
input VAR13;
input VAR14;
input [ 31: 0] VAR12;
wire VAR8;
reg [ 13: 0] VAR10;
reg [ 13: 0] VAR5;
wire [ 13: 0] VAR7;
reg [ 13: 0] VAR6;
wire VAR11;
wire [ 13... | gpl-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_02/02 verilog/PorPruebas/ModulosBasicos/PruebasFPGA/divisorprueba/anteconmutador.v | 1,148 | module MODULE1 (
input clk,
input [7:0] VAR6,
input VAR8,
output reg [3:0] VAR4,
output reg [3:0] VAR1,
output reg [3:0] VAR2,
output reg VAR5,
output reg VAR9,
output reg VAR7
);
reg [7:0] VAR3;
reg VAR10;
begin
begin
begin
begin
begin
end
begin
begin
end
begin
begin
begin
begin
begin
begin | gpl-3.0 |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v4_0_clk_ibuf.v | 4,796 | module MODULE1 #
(
parameter VAR8 = "VAR9",
parameter VAR22 = "VAR21"
)
(
input VAR5, input VAR14,
input VAR23,
output VAR4
);
wire VAR19 ;
generate
if (VAR8 == "VAR9") begin: VAR15
VAR11 #
(
.VAR2 (VAR22),
.VAR7 ("VAR18")
)
VAR3
(
.VAR6 (VAR5),
.VAR10 (VAR14),
.VAR20 (VAR19)
);
end else if (VAR8 == "VAR13") begin: VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0p/sky130_fd_sc_lp__iso0p.pp.symbol.v | 1,267 | module MODULE1 (
input VAR1 ,
output VAR2 ,
input VAR3,
input VAR6,
input VAR7 ,
input VAR5 ,
input VAR4
);
endmodule | apache-2.0 |
everskar2013/PentiumX | Hardware/Code/Muliti_cycle_Cpu.v | 4,127 | module MODULE1(
clk,
reset,
VAR35,
VAR5,
VAR3,
VAR21,
VAR10,
VAR49,
VAR20,
VAR27,
VAR51,
VAR31,
VAR8,
state,
VAR6,
VAR40,
VAR26,
VAR29
);
input wire clk, reset, VAR35;
input wire [31: 0] VAR5;
input wire [ 3: 0] VAR3; input wire VAR21;
output wire [31: 0] VAR49, VAR20; output wire [31: 0] VAR51, VAR31;
output wire [ 4:... | mit |
vipinkmenon/fpgadriver | src/hw/fpga/source/enet_if/v7_ethernet_controller.v | 7,865 | module MODULE1 #(
parameter VAR51 = 48'h001F293A10FD,
VAR13 = 48'hAABBCCDDEEFF,
VAR29 = 16'd1024,
VAR40=48'hAABBCCDDEEFF)
(
input VAR15,
input VAR1,
output VAR62,
input VAR45, input VAR60, output VAR64, output VAR67, input VAR38, input VAR35,
output VAR10,
output VAR42,
input VAR27,
output VAR73,
output VAR21,
output V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xor3/sky130_fd_sc_ls__xor3_1.v | 2,199 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR2 ,
VAR7 ,
VAR5,
VAR6,
VAR8 ,
VAR3
);
output VAR1 ;
input VAR10 ;
input VAR2 ;
input VAR7 ;
input VAR5;
input VAR6;
input VAR8 ;
input VAR3 ;
VAR4 VAR9 (
.VAR1(VAR1),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/lr0.v | 2,084 | module MODULE1(clk, addr, VAR6, VAR21, VAR16, en, reset);
input clk;
input [13:2] addr;
input [31:0] VAR6;
output [31:0] VAR21;
input [3:0] VAR16;
input en;
input reset;
VAR2 VAR5(
.address (addr[13:2]),
.VAR13 (en),
.VAR18 (clk),
.VAR12 (VAR6[3:0]),
.VAR14 (VAR16[0]),
.VAR10 (VAR21[3:0])
);
VAR2 VAR25(
.address (addr... | mit |
GSejas/Karatsuba_FPU | Resultados/CORDIC/CORDIC_Arch3_Vivado/CORDIC_Arch3_Vivado.srcs/sources_1/imports/Floating-Point-Unit-master/Coprocesador_CORDIC_RTL/sine_cosine_CORDIC/Mux_3x1_b.v | 1,031 | module MODULE1 #(parameter VAR2=32)
(
input wire [1:0] select,
input wire [VAR2-1:0] VAR1,
input wire [VAR2-1:0] VAR4,
input wire [VAR2-1:0] VAR5,
output reg [VAR2-1:0] VAR3
);
always @*
begin
case(select)
2'b00: VAR3 <= VAR1;
2'b01: VAR3 <= VAR4;
2'b10: VAR3 <= VAR5;
2'b11: VAR3 <= {VAR2{1'b0}};
default : VAR3 <= VAR1... | gpl-3.0 |
red0bear/CRCAHB | rtl/crc_comb.v | 3,427 | module MODULE1
parameter VAR2 = 8, parameter VAR8 = 8'hff )(
output [VAR2 - 1 : 0] VAR3, input VAR9, input [VAR2 - 1 : 0] VAR7, input [VAR2 - 1 : 0] VAR12, input [VAR2 - 2 : 0] VAR10
);
wire [VAR2 - 2 : 0] VAR4;
wire [VAR2 - 1 : 0] VAR11;
wire [VAR2 - 2 : 0] VAR1;
wire [VAR2 - 2 : 0] VAR6;
generate
genvar VAR5;
for(VAR... | gpl-3.0 |
binary-logic/vj-uart | rtl/reset.v | 1,416 | module MODULE1 (
input VAR2,
output VAR3
);
reg [3:0] VAR1 = 4'b1111;
assign VAR3 = (VAR1 == 1'b0);
always @(posedge VAR2)
begin
if( VAR1 > 1'b0 ) VAR1 = VAR1 - 1'b1;
end
endmodule | gpl-3.0 |
eda-globetrotter/PicenoDecoders | final/src/tosynth Folder/alu_mult.v | 52,028 | module MODULE1(VAR16,VAR22,VAR19,VAR28,VAR3);
output [0:127] VAR3;
input [0:127] VAR16;
input [0:127] VAR22;
input [0:1] VAR19;
input [0:4] VAR28;
parameter VAR2 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR3;
reg [0:127] VAR10;
reg [0:15] VAR17;
reg [0:15] VAR30;
reg [0:15] VAR15;
reg [0:15] VAR18;
reg [0:1... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_sdram/rtl/sdram_clkgen.v | 3,600 | module MODULE1 (
input clk,
input rst,
output VAR25,
output VAR40,
output VAR39
);
wire VAR49;
wire VAR41;
wire VAR44;
wire VAR28;
wire VAR61;
wire VAR35;
wire VAR7;
wire VAR45;
wire VAR9;
VAR4 #(
.VAR56 ("VAR21" ),
.VAR2 ("VAR60" ),
.VAR24 ("VAR33" ),
.VAR5 (1 ),
.VAR30 (18 ),
.VAR18 (0.000 ),
.VAR16 (9 ),
.VAR31 (180... | mit |
jakubfi/mera400f | src/iobus.v | 6,497 | module MODULE1(
input VAR82,
input VAR35,
input VAR9,
output VAR91,
output VAR2,
input VAR32,
input VAR101,
output VAR33,
input VAR132,
input VAR26,
input VAR128,
input VAR125,
input VAR130,
input VAR119,
input [0:3] VAR89,
input [0:15] VAR39,
input [0:15] VAR68,
output VAR18,
output VAR30,
output din,
output VAR115,
o... | gpl-2.0 |
mdsalman729/flexpret_project | src/uart/Register.v | 4,738 | module MODULE1(VAR3, VAR8, VAR16, VAR1, VAR15, VAR9);
parameter VAR17 = 32,
VAR10 = {VAR17{1'VAR2}},
VAR7 = 0,
VAR11 = 0,
VAR12 = {VAR17{1'b0}},
VAR13 = {VAR17{1'b1}};
input VAR3, VAR1, VAR8, VAR16;
input [VAR17-1:0] VAR15;
output reg [VAR17-1:0] VAR9 = VAR10;
generate if (VAR7) begin:VAR4
if (VAR11) begin:VAR14
always... | bsd-3-clause |
ShirmanXia/EE469SPRING16 | lab3/db/ip/nios_system/submodules/nios_system_sram_addr.v | 2,294 | module MODULE1 (
address,
VAR8,
clk,
VAR9,
VAR4,
VAR7,
VAR5,
VAR6
)
;
output [ 10: 0] VAR5;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input VAR8;
input clk;
input VAR9;
input VAR4;
input [ 31: 0] VAR7;
wire VAR1;
reg [ 10: 0] VAR3;
wire [ 10: 0] VAR5;
wire [ 10: 0] VAR2;
wire [ 31: 0] VAR6;
assign VAR1 = 1;
assign V... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_axis_fifo/util_axis_fifo.v | 6,004 | module MODULE1 (
input VAR4,
input VAR8,
input VAR19,
output VAR1,
output [VAR14-1:0] VAR16,
output [VAR6:0] VAR17,
input VAR34,
input VAR10,
output VAR30,
input VAR32,
input [VAR14-1:0] VAR12,
output VAR24,
output [VAR6:0] VAR2
);
parameter VAR14 = 64;
parameter VAR23 = 1;
parameter VAR6 = 4;
parameter VAR3 = 1;
gener... | gpl-3.0 |
egyp7/mor1kx | rtl/verilog/mor1kx_execute_alu.v | 27,159 | module MODULE1
parameter VAR26 = 32,
parameter VAR94 = "VAR90",
parameter VAR33 = "VAR89",
parameter VAR132 = "VAR54",
parameter VAR53 = "VAR90",
parameter VAR71 = "VAR90",
parameter VAR63 = "VAR89",
parameter VAR28 = "VAR90",
parameter VAR84 = "VAR90",
parameter VAR52 = "VAR90",
parameter VAR129 = "VAR90",
parameter V... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_pwrgood_pp_p/sky130_fd_sc_hvl__udp_pwrgood_pp_p.blackbox.v | 1,255 | module MODULE1 (
VAR1,
VAR2 ,
VAR3
);
output VAR1;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_2.behavioral.v | 1,495 | module MODULE1( VAR6, VAR7, VAR2, VAR3 );
input VAR3, VAR2, VAR6;
output VAR7;
VAR5 VAR4(.VAR6(VAR6),.VAR7(VAR7),.VAR2(VAR2),.VAR3(VAR3));
VAR5 VAR1(.VAR6(VAR6),.VAR7(VAR7),.VAR2(VAR2),.VAR3(VAR3)); | apache-2.0 |
bargei/NoC264 | NoC264_2x2/mkOutPortFIFO.v | 20,764 | module MODULE1(VAR30,
VAR42,
VAR51,
VAR13,
VAR79,
VAR3,
VAR10,
VAR37,
VAR29,
VAR66,
VAR73,
VAR50,
VAR26,
VAR6,
VAR61,
VAR53,
VAR54);
input VAR30;
input VAR42;
input [2 : 0] VAR51;
input VAR13;
output VAR79;
input VAR3;
output VAR10;
output [2 : 0] VAR37;
output VAR29;
output VAR66;
output VAR73;
output VAR50;
output VA... | mit |
hoglet67/AtomFpga | src/xilinx/ICAP_core.v | 16,424 | module MODULE1
(
input VAR22,
input [3:0] VAR48,
input VAR67,
input VAR32,
input [3:0] VAR35,
output [3:0] VAR56,
output [3:0] VAR62,
output VAR57,
);
reg [1:0] clk;
reg VAR28;
reg [15:0] VAR54;
reg VAR50;
reg VAR36;
wire [15:0] VAR23;
reg [15:0] VAR6;
reg [15:0] VAR45;
reg VAR38;
reg VAR20;
reg [3:0] VAR49 = 4'b0000;... | apache-2.0 |
cpulabs/mist1032sa | src/lib/mist1032sa_sync_fifo.v | 1,853 | module MODULE1
parameter VAR2 = 16,
parameter VAR8 = 4,
parameter VAR17 = 2
)(
input wire VAR13,
input wire VAR1,
input wire VAR16,
output wire [VAR17-1:0] VAR9,
input wire VAR11,
input wire [VAR2-1:0] VAR6,
output wire VAR15,
input wire VAR14,
output wire [VAR2-1:0] VAR5,
output wire VAR10
);
wire [VAR17:0] VAR3;
reg ... | bsd-2-clause |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_m00_regslice_8/synth/system_m00_regslice_8.v | 10,967 | module MODULE1 (
VAR49,
VAR86,
VAR31,
VAR48,
VAR89,
VAR19,
VAR10,
VAR6,
VAR64,
VAR28,
VAR50,
VAR114,
VAR75,
VAR8,
VAR73,
VAR95,
VAR47,
VAR97,
VAR33,
VAR67,
VAR15,
VAR30,
VAR104,
VAR55,
VAR77,
VAR78,
VAR90,
VAR18,
VAR99,
VAR83,
VAR91,
VAR54,
VAR37,
VAR85,
VAR20,
VAR44,
VAR103,
VAR101,
VAR46,
VAR39
);
input wire VAR49;
i... | bsd-2-clause |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_pm.v | 7,536 | module MODULE1(
clk, rst, VAR6, VAR20, VAR21, VAR2, VAR29,
VAR1, VAR26, VAR23, VAR25, VAR22,
VAR8, VAR10, VAR4, VAR27, VAR18
);
input clk; input rst; input VAR6; input VAR20; input [31:0] VAR21; input [31:0] VAR2; output [31:0] VAR29;
input VAR26; output [3:0] VAR1; output VAR23; output VAR25; output VAR22; output VAR8... | apache-2.0 |
briburrell/amica | device/bitstream/bitstream.srcs/sources_1/imports/bitstream/sha256_transform.v | 5,081 | module MODULE2 #(
parameter VAR23 = 7'd64 ) (
input clk,
input VAR17,
input [5:0] VAR5,
input [255:0] VAR24,
input [511:0] VAR25,
output reg [255:0] VAR2
);
localparam VAR14 = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/alt_mem_ddrx_input_if.v | 10,391 | module MODULE1
VAR50 = 64,
VAR69 = 8,
VAR68 = 33,
VAR59 = 3,
VAR74 = 1,
VAR21 = 2,
VAR80 = "VAR35"
)
(
VAR12,
VAR52,
VAR9,
VAR75,
VAR4,
VAR49,
VAR6,
VAR83,
VAR39,
VAR38,
VAR64,
VAR29,
VAR58,
VAR17,
VAR31,
VAR19,
VAR55,
VAR24,
VAR8,
VAR54,
VAR57,
VAR23,
VAR61,
VAR41,
VAR46,
VAR42,
VAR18,
VAR32,
VAR63,
VAR11,
VAR28,
VAR4... | lgpl-3.0 |
davidjabon/AXI-Peripheral-Library | Four_Digit_Seven_Segment_Display_2.0/src/seven_segment_display_x_4.v | 2,256 | module MODULE1(
input [15:0] VAR2,
input [3:0] VAR6,
input clk,
output reg [6:0] VAR7,
output reg VAR1,
output reg [3:0] VAR3
);
wire [1:0] counter;
reg [3:0] VAR5;
reg [19:0] VAR4;
assign counter = VAR4[19:18];
always @(posedge clk)
case(counter)
0: {VAR5, VAR1, VAR3} = {VAR2[3:0], ~VAR6[0], 4'b1110};
1: {VAR5, VAR1, ... | gpl-2.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/proyecto-final/i2s_out.v | 1,768 | module MODULE1(input VAR6, input reset, input[15:0] VAR8,
input[15:0] VAR9, output VAR3, output VAR1, output VAR5, output reg VAR2);
wire[5:0] VAR7 = 6'd1; wire[5:0] VAR10 = 6'd63; reg [3:0] VAR4;
begin
begin
begin
begin
end
begin
begin
begin
end
begin | mit |
Microsoft/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/pcie_dma_engine/non_posted_pkt_slicer.v | 14,243 | module MODULE1(
input clk,
input rst,
input VAR18,
input VAR31,
input [31:0] VAR44,
input [31:0] VAR10,
input [63:0] VAR9,
input [2:0] VAR1, input VAR14,
input [63:0] VAR29,
output reg VAR37,
input ack,
output reg VAR6,
output reg [31:0] VAR4,
output reg [63:0] VAR3,
output [9:0] VAR34
);
localparam VAR19 = 4'h0;
local... | bsd-2-clause |
luebbers/reconos | support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/plb_tft_cntlr_ref_v1_00_d/hdl/verilog/plb_tft_cntlr_ref.v | 18,021 | module MODULE1 (
VAR193, VAR114,
VAR92, VAR39, VAR104, VAR101, VAR119, VAR206, VAR56, VAR53, VAR43, VAR115, VAR66, VAR170, VAR9, VAR209, VAR76,
VAR173, VAR73, VAR70, VAR191, VAR137, VAR172, VAR47,
VAR153, VAR131, VAR199, VAR95,
VAR161, VAR77, VAR60, VAR196, VAR163,
VAR215, VAR27, VAR136, VAR31, VAR12, VAR74, VAR141,
VA... | gpl-3.0 |
dk00/old-stuff | csie/09computer-architecture/project/code/dcache_one_way_example/CPU.v | 1,183 | module MODULE1
(
VAR16,
VAR19,
VAR1,
VAR2,
VAR17,
VAR29,
VAR28,
VAR4,
VAR10
);
input VAR16;
input VAR19;
input VAR1;
input [256-1:0] VAR2;
input VAR17;
output [256-1:0] VAR29;
output [32-1:0] VAR28;
output VAR4;
output VAR10;
VAR14 VAR14
(
.VAR16(VAR16),
.VAR19(VAR19),
.VAR1(VAR1),
.VAR33(),
.VAR18(),
.VAR7(),
.VAR24()... | unlicense |
glennchid/font5-firmware | src/verilog/synthesis/DCM1.v | 3,269 | module MODULE1(VAR8,
VAR61,
VAR43,
VAR3,
VAR26,
VAR1);
input VAR8;
input VAR61;
output VAR43;
output VAR3;
output VAR26;
output VAR1;
wire VAR50;
wire VAR38;
wire VAR70;
wire VAR40;
wire VAR16;
wire [6:0] VAR48;
wire [15:0] VAR64;
assign VAR16 = 0;
assign VAR48 = 7'b0000000;
assign VAR64 = 16'b0000000000000000;
assign ... | gpl-3.0 |
asicguy/gplgpu | hdl/lucy_tc/de3d_tc_store.v | 5,413 | module MODULE1
(
input VAR5,
input VAR46,
input VAR51,
input [3:0] VAR17,
input [209:0] VAR10,
input [17:0] VAR44,
input [17:0] VAR12,
input [17:0] VAR7,
input [17:0] VAR23,
input VAR45,
input VAR21,
input VAR11,
input VAR25,
input [2:0] VAR3,
input [4:0] VAR22,
input VAR16,
input [3:0] VAR47,
input [11:0] VAR49,
input... | gpl-3.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/v/QM.v | 52,160 | module MODULE1
(
VAR29, VAR5, VAR28, VAR23, VAR27, VAR10, VAR9,
VAR3, VAR30, VAR1, VAR2, VAR18, VAR13, VAR22, VAR15
);
parameter VAR12 = 16 ; parameter VAR8 = 16 ; parameter VAR24 = 32;
input VAR3;
input VAR30;
input signed [VAR8-1:0] VAR1;
input signed [VAR8-1:0] VAR2;
input VAR18;
input [6:0] VAR13, VAR22, VAR15;
out... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtp/sky130_fd_sc_hs__dfrtp_1.v | 2,184 | module MODULE2 (
VAR7,
VAR8 ,
VAR3 ,
VAR5 ,
VAR6 ,
VAR4
);
input VAR7;
input VAR8 ;
input VAR3 ;
output VAR5 ;
input VAR6 ;
input VAR4 ;
VAR1 VAR2 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR7,
VAR8 ,
VAR3 ,
VAR5
);
input VAR7;
input VAR8 ;
input VAR3 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/edfxbp/sky130_fd_sc_lp__edfxbp.behavioral.v | 2,290 | module MODULE1 (
VAR2 ,
VAR18,
VAR19,
VAR3 ,
VAR9
);
output VAR2 ;
output VAR18;
input VAR19;
input VAR3 ;
input VAR9 ;
supply1 VAR13;
supply0 VAR23;
supply1 VAR22 ;
supply0 VAR6 ;
wire VAR21 ;
reg VAR7 ;
wire VAR10 ;
wire VAR14 ;
wire VAR15;
wire VAR8 ;
wire VAR20 ;
wire VAR1 ;
VAR5 VAR16 (VAR8, VAR21, VAR10, VAR14 );... | apache-2.0 |
bkboggy/MIPS | EX_MEM.v | 1,431 | module MODULE1(input clk,
input [1:0] VAR5,
input [2:0] VAR11,
input [31:0] VAR8,
input VAR2,
input [31:0] VAR1,
input [31:0] VAR14,
input [4:0] VAR6,
output reg [1:0] VAR9,
output reg [2:0] VAR12,
output reg [31:0] VAR13,
output reg VAR3,
output reg [31:0] VAR4,
output reg [31:0] VAR10,
output reg [4:0] VAR7);
begin | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/atlys/rtl/verilog/xilinx_ddr2/mcb_soft_calibration_top.v | 12,394 | module MODULE1 # (
parameter VAR88 = 10'h512, parameter VAR31 = "VAR84", parameter VAR47 = 1'b0, parameter VAR27 = 1'b0, parameter VAR74 = 1'b0, parameter VAR44 = "VAR68", parameter VAR94 = "VAR65" )
(
input wire VAR10, input wire VAR98, input wire VAR38, output wire VAR82, input wire VAR28, input wire VAR6,
input wire... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_engine_selector.v | 5,012 | module MODULE1
parameter VAR9 = 4'd12
)
(
input VAR5,
input VAR15,
input [VAR9-1:0] VAR7,
output VAR12, output [3:0] VAR1 );
reg [3:0] VAR4=0, VAR4=0;
reg [3:0] VAR16=0, VAR16=0;
reg VAR2=0, VAR2=0;
reg [3:0] VAR17=0, VAR17=0;
reg [3:0] VAR3=0, VAR3=0;
reg VAR6=0, VAR6=0;
reg VAR8=0, VAR8=0;
wire VAR11;
reg VAR13=0, VA... | gpl-3.0 |
stevenokm/mor1kx | rtl/verilog/pfpu32/pfpu32_cmp.v | 7,444 | module MODULE1
(
input VAR27,
input [VAR38-1:0] VAR5,
input VAR3,
input [9:0] VAR9,
input [23:0] VAR32,
input VAR14,
input VAR18,
input VAR10,
input VAR23,
input VAR11,
input [9:0] VAR19,
input [23:0] VAR34,
input VAR1,
input VAR39,
input VAR21,
input VAR12,
output VAR7,
output VAR6,
output VAR24, VAR2, VAR15, VAR13
);... | mpl-2.0 |
phasza/axi_spi_if | clk_gen.v | 1,294 | module MODULE1 (
input VAR3,
input VAR2,
input VAR6,
input [3:0] VAR1,
output VAR5
);
reg VAR7;
reg [3:0] VAR4;
always@(posedge VAR3,negedge VAR2)
begin
if (!VAR2)
begin
VAR4 <= 0;
VAR7 <= 0;
end
else if(VAR6)
begin
if(VAR4 == VAR1-1)
begin
VAR7 <= ~VAR7;
VAR4 <= 0;
end
else
VAR4 <= VAR4 +1;
end
else
VAR7 <= 0;
end
ass... | gpl-3.0 |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axi_data_fifo.v | 30,138 | module MODULE1 #
(
parameter VAR10 = "VAR6",
parameter integer VAR168 = 0,
parameter integer VAR320 = 4,
parameter integer VAR127 = 32,
parameter integer VAR219 = 32,
parameter integer VAR106 = 0,
parameter integer VAR167 = 1,
parameter integer VAR336 = 1,
parameter integer VAR199 = 1,
parameter integer VAR130 = 1,
par... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32ai/sky130_fd_sc_hd__o32ai.behavioral.pp.v | 2,191 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR9 ,
VAR13 ,
VAR19 ,
VAR11 ,
VAR17,
VAR20,
VAR3 ,
VAR4
);
output VAR8 ;
input VAR2 ;
input VAR9 ;
input VAR13 ;
input VAR19 ;
input VAR11 ;
input VAR17;
input VAR20;
input VAR3 ;
input VAR4 ;
wire VAR16 ;
wire VAR12 ;
wire VAR7 ;
wire VAR10;
nor VAR1 (VAR16 , VAR13, VAR2, VAR9 );
nor VA... | apache-2.0 |
mmicko/grom8 | alu.v | 2,068 | module MODULE1(
input clk,
input [7:0] VAR12,
input [7:0] VAR4,
input [3:0] VAR1,
output reg [7:0] VAR20,
output reg VAR22,
output reg VAR23,
output reg VAR13
);
localparam VAR7 = 4'b0000;
localparam VAR11 = 4'b0001;
localparam VAR8 = 4'b0010;
localparam VAR18 = 4'b0011;
localparam VAR16 = 4'b0100;
localparam VAR3 = 4'... | mit |
aquaxis/FPGAMAG18 | modules/fmrv32im_v1/src/fmrv32im.v | 25,056 | module MODULE1
parameter VAR238 = 0
)
(
input VAR153,
input VAR183,
input VAR213,
output VAR259,
output [31:0] VAR227,
input [31:0] VAR281,
input VAR13,
input VAR292,
output VAR271,
output [3:0] VAR17,
output [31:0] VAR285,
output [31:0] VAR225,
input [31:0] VAR230,
input VAR79,
input VAR266,
input VAR267
);
wire [31:0... | mit |
walkthetalk/fsref | ip/fscmos/src/fscmos.v | 1,304 | module MODULE1 #
(
parameter integer VAR6 = 8,
parameter integer VAR1 = 8
)
(
input wire VAR9,
input wire VAR4,
input wire VAR2,
input wire [VAR6-1:0] VAR7,
output wire VAR8,
output wire[VAR1-1:0] VAR13,
output wire VAR3,
output wire VAR10,
output wire VAR11,
output wire VAR5
);
assign VAR8= (VAR2 && ~VAR4);
assign VAR... | gpl-3.0 |
liqimai/Assignment1-Calculator | Floating-Number-Division/divider_v2.v | 1,824 | module MODULE1(VAR5,VAR8,VAR9);
input wire [31:0] VAR5;
input wire [31:0] VAR8;
output reg [31:0] VAR9;
reg [47:0]VAR2;
reg [23:0]VAR6;
reg [25:0]VAR10;
reg [25:0] VAR3;
reg [8:0]VAR4;
reg [8:0]VAR7;
integer VAR1; always @(VAR5 or VAR8) begin
VAR9=0;
VAR3=0;
VAR2={1,VAR5[22:0],24'b0};
VAR6={1,VAR8[22:0]};
VAR4=VAR5[30:... | gpl-2.0 |
praveendath92/securePUF | source/Cumulative_Sums.v | 1,506 | module MODULE1(
input wire clk,
input wire rst,
input wire rand,
output reg VAR3
);
parameter VAR2 = 20000, VAR1 = 397, VAR7 = -397;
reg [14:0] VAR6, VAR8, VAR11;
reg signed [15:0] VAR4;
wire [14:0] VAR10;
reg [14:0] VAR9;
assign VAR10 = VAR4[15]? (-VAR4) : VAR4;
always @(posedge clk)
if (rst) begin
VAR6 <= 15'VAR5;
VA... | gpl-2.0 |
cpulabs/mist1032isa | src/core/execute/execute_load_data.v | 1,126 | module MODULE1(
input wire [3:0] VAR12,
input wire [1:0] VAR4,
input wire [31:0] VAR8,
output wire [31:0] VAR9
);
assign VAR9 = VAR3(
VAR12,
VAR4,
VAR8
);
function [31:0] VAR3;
input [3:0] VAR11;
input [1:0] VAR6;
input [31:0] VAR2;
reg [7:0] VAR10, VAR7, VAR5, VAR1;
begin
if(VAR11 == 4'hf)begin
VAR3 = VAR2;
end
else i... | bsd-2-clause |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | Verilog_AES/AES/Decryption.v | 5,977 | module MODULE1
parameter VAR16 = 4,
parameter VAR11 = 8,
parameter VAR17 = 64
)(
input clk,
input rst,
input VAR18,
input[VAR11-1:0] VAR1,
input[VAR11-1:0] VAR25,
output reg VAR9,
output reg VAR19,
output reg[VAR16-1:0] VAR7,
output reg[VAR16-1:0] VAR26,
output reg[VAR11-1:0] VAR14
);
parameter VAR21 = VAR11/2; paramet... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a311o/sky130_fd_sc_lp__a311o.pp.symbol.v | 1,394 | module MODULE1 (
input VAR6 ,
input VAR8 ,
input VAR1 ,
input VAR7 ,
input VAR2 ,
output VAR9 ,
input VAR10 ,
input VAR5,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3b/sky130_fd_sc_ls__or3b.pp.blackbox.v | 1,308 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR6 ,
VAR5 ,
VAR3,
VAR4,
VAR7 ,
VAR2
);
output VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR3;
input VAR4;
input VAR7 ;
input VAR2 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_32.behavioral.v | 1,027 | module MODULE1( );
VAR1 VAR3();
VAR1 VAR2(); | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbus_common/rtl/bw_io_dtl_padx8.v | 12,556 | module MODULE1(VAR69 ,VAR46 ,VAR75 ,
VAR67 ,VAR30 ,VAR18 ,VAR21 ,
VAR17 ,VAR48 ,VAR79 ,VAR76 ,VAR63 ,
VAR2 ,clk ,VAR35 ,VAR74 ,VAR12 ,VAR43 ,VAR36 ,VAR9 ,ref ,VAR28 ,
VAR49 ,VAR77 ,VAR19 ,VAR70 ,VAR40 ,VAR23 ,VAR62 );
output [7:0] VAR40 ;
input [1:0] VAR69 ;
input [1:0] VAR46 ;
input [1:0] VAR75 ;
input [1:0] VAR67 ;
i... | gpl-2.0 |
manu3193/ControladorElevadorTDD | MaquinaEstados.v | 4,373 | module MODULE1(
clk, reset, state,
VAR19, VAR21, VAR7, VAR25,
VAR3, VAR1,
VAR9,
VAR26,
VAR23,
VAR16,
VAR18,
VAR11,
VAR8,
VAR10,
VAR12,
VAR4,
ready
);
input wire clk, reset;
input wire [1:0] VAR19;
input VAR21, VAR7, VAR25;
output reg VAR3, VAR1, ready, VAR9, VAR26;
output reg VAR23,
VAR16,
VAR18,
VAR11,
VAR8,
VAR10,
VA... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/acl_fp_div_double.v | 103,346 | module MODULE1
(
VAR193,
VAR124,
VAR98,
VAR140,
VAR128,
VAR86) ;
input VAR193;
input VAR124;
input VAR98;
input [63:0] VAR140;
input [63:0] VAR128;
output [63:0] VAR86;
tri0 VAR193;
tri1 VAR124;
wire [8:0] VAR269;
reg VAR250;
reg VAR170;
reg VAR154;
reg VAR20;
reg VAR47;
reg VAR84;
reg VAR207;
reg VAR107;
reg VAR92;
re... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4/sky130_fd_sc_lp__nor4_0.v | 2,275 | module MODULE2 (
VAR3 ,
VAR8 ,
VAR7 ,
VAR11 ,
VAR1 ,
VAR5,
VAR2,
VAR6 ,
VAR9
);
output VAR3 ;
input VAR8 ;
input VAR7 ;
input VAR11 ;
input VAR1 ;
input VAR5;
input VAR2;
input VAR6 ;
input VAR9 ;
VAR10 VAR4 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR... | apache-2.0 |
alexforencich/verilog-ethernet | rtl/axis_eth_fcs.v | 3,824 | module MODULE1 #
(
parameter VAR9 = 8,
parameter VAR6 = (VAR9>8),
parameter VAR1 = (VAR9/8)
)
(
input wire clk,
input wire rst,
input wire [VAR9-1:0] VAR5,
input wire [VAR1-1:0] VAR8,
input wire VAR3,
output wire VAR11,
input wire VAR10,
input wire VAR4,
output wire [31:0] VAR7,
output wire VAR2
); | mit |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/fpgaTop_illite.v | 1,096 | module MODULE1(
input wire VAR5, input wire VAR20, input wire VAR2, input wire VAR16, input wire VAR1, output wire [7:0] VAR3, output wire [7:0] VAR18,
input wire [7:0] VAR12,
input wire [7:0] VAR9,
output wire [2:0] VAR4, input wire VAR10, output wire VAR15 );
VAR6 VAR11(
.VAR5 (VAR5),
.VAR20 (VAR20),
.VAR2 (VAR2),
.V... | lgpl-3.0 |
The-OpenROAD-Project/asap7 | asap7sc7p5t_27/Verilog/asap7sc7p5t_INVBUF_LVT_TT_201020.v | 17,210 | module MODULE1 (VAR1, VAR2);
output VAR1;
input VAR2;
buf (VAR1, VAR2); | bsd-3-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/rtl/ctu_clsp.v | 71,479 | module MODULE1(
VAR256, VAR383, VAR158, VAR103,
VAR446, VAR329, VAR186, VAR317,
VAR245, VAR349, VAR237, VAR187,
VAR117, VAR137, VAR121,
VAR156, VAR304, VAR9,
VAR320, VAR73, VAR407,
VAR28, VAR299, VAR88,
VAR8, VAR140, VAR274,
VAR390, VAR36, VAR167,
VAR6, VAR394, VAR34,
VAR382, VAR282, VAR31,
VAR235, VAR209, VAR337,
VAR9... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_4.functional.v | 1,064 | module MODULE1( VAR5, VAR10, VAR4, VAR12, VAR1 );
input VAR4, VAR10, VAR5, VAR1;
output VAR12;
or VAR8( VAR3, VAR10, VAR5 );
VAR9( VAR6, 1'b0, 1'b0, VAR4, VAR3, VAR1 );
wire VAR11;
not VAR2( VAR11, VAR6 );
or VAR7( VAR12, VAR4, VAR11 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41o/sky130_fd_sc_hs__a41o_4.v | 2,299 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR1 ,
VAR4 ,
VAR8 ,
VAR5 ,
VAR2,
VAR9
);
output VAR3 ;
input VAR6 ;
input VAR1 ;
input VAR4 ;
input VAR8 ;
input VAR5 ;
input VAR2;
input VAR9;
VAR10 VAR7 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR9(VAR9)
);
endmodule
module MODULE2 ... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/arb_row_col.v | 12,632 | module MODULE1 #
(
parameter VAR11 = 100,
parameter VAR52 = "1T",
parameter VAR62 = "VAR76",
parameter VAR10 = 4,
parameter VAR19 = 2,
parameter VAR57 = 2
)
(
VAR72, VAR32, VAR30, VAR54,
VAR56, VAR61, VAR29,
VAR13, VAR58, VAR9, VAR48, VAR27,
VAR59, VAR41, VAR18, VAR4,
clk, rst, VAR24, VAR28, VAR65, VAR6,
VAR35, VAR51
)... | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/minsoc_startup/spi_top.v | 8,550 | module MODULE1
(
VAR5, VAR33, VAR46, VAR10, VAR41, VAR35,
VAR6, VAR20, VAR36, VAR47,
VAR13, VAR52, VAR28, VAR29
);
parameter VAR53 = 2;
parameter VAR55 = 0;
parameter VAR48 = 1;
input VAR5; input VAR33; input [4:2] VAR46; input [31:0] VAR10; output [31:0] VAR41; input [3:0] VAR35; input VAR6; input VAR20; input VAR36; ... | gpl-2.0 |
CospanDesign/nysa-artemis-pcie-platform | artemis_pcie/slave/wb_artemis_pcie_platform/rtl/ppfifo_pcie_host_interface.v | 16,658 | module MODULE1 (
input rst,
input clk,
input VAR71,
input VAR6,
output VAR34,
output reg VAR58,
output reg [31:0] VAR35,
output reg [31:0] VAR25,
output reg [31:0] VAR20,
output reg [27:0] VAR7,
output reg VAR57,
input VAR61,
input [31:0] VAR44,
input [31:0] VAR68,
input [31:0] VAR11,
input [27:0] VAR31,
input VAR54,
o... | mit |
gyurco/ZX_Spectrum-128K_MIST | divmmc.v | 4,048 | module MODULE1
(
input VAR1,
input [1:0] VAR5,
input VAR8,
input VAR2,
input VAR4,
input VAR17,
input VAR27,
input VAR25,
input [15:0] addr,
input [7:0] din,
output [7:0] dout,
input enable,
input VAR28,
output VAR10,
output VAR6,
output VAR15,
output [3:0] VAR14,
output reg VAR39,
output VAR19,
input VAR11,
output VAR... | gpl-2.0 |
yupferris/hello-everyweeks | uart.v | 2,657 | module MODULE1(
input clk,
input reset,
input [7:0] VAR11,
input VAR5,
output reg VAR4,
output reg VAR7);
parameter VAR9 = 50000000;
parameter VAR6 = 9600;
parameter VAR3 = 16;
parameter VAR14 = ((VAR6 << (VAR3 - 4)) + (VAR9 >> 5)) / (VAR9 >> 4);
reg [VAR3:0] VAR12;
always @(posedge clk or posedge reset)
if (reset)
VAR... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32a/sky130_fd_sc_hd__o32a_1.v | 2,428 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR8 ,
VAR6 ,
VAR4 ,
VAR11 ,
VAR1,
VAR2,
VAR9 ,
VAR3
);
output VAR7 ;
input VAR5 ;
input VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR11 ;
input VAR1;
input VAR2;
input VAR9 ;
input VAR3 ;
VAR12 VAR10 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR1(VAR... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/fab/sirv_icb1to8_bus.v | 28,570 | module MODULE1 # (
parameter VAR242 = 0, parameter VAR92 = 1,
parameter VAR54 = 32,
parameter VAR214 = 32,
parameter VAR34 = 1,
parameter VAR221 = 1,
parameter VAR124 = 32'h00001000,
parameter VAR125 = 12,
parameter VAR199 = 32'h00001000,
parameter VAR183 = 12,
parameter VAR80 = 32'h00001000,
parameter VAR223 = 12,
par... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4/sky130_fd_sc_hdll__nand4.behavioral.v | 1,416 | module MODULE1 (
VAR3,
VAR10,
VAR9,
VAR2,
VAR5
);
output VAR3;
input VAR10;
input VAR9;
input VAR2;
input VAR5;
supply1 VAR7;
supply0 VAR1;
supply1 VAR11 ;
supply0 VAR6 ;
wire VAR4;
nand VAR12 (VAR4, VAR5, VAR2, VAR9, VAR10 );
buf VAR8 (VAR3 , VAR4 );
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/syn/src/spare/build1/mult.v | 4,611 | module MODULE1 (VAR4,VAR3,VAR5,VAR2,VAR1);
output [0:127] VAR1;
input [0:127] VAR4;
input [0:127] VAR3;
input [0:1] VAR5;
input [0:4] VAR2;
reg [0:127] VAR1;
always @(VAR4 or VAR3 or VAR5 or VAR2)
begin
case(VAR2)
begin
case(VAR5)
VAR1[0:15]=VAR4[0:7]*VAR3[0:7];
VAR1[16:31]=VAR4[16:23]*VAR3[16:23];
VAR1[32:47]=VAR4[32:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3.pp.blackbox.v | 1,344 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR6,
VAR3,
VAR2 ,
VAR5
);
output VAR1 ;
input VAR4 ;
input VAR6;
input VAR3;
input VAR2 ;
input VAR5 ;
endmodule | apache-2.0 |
amiq-consulting/amiq_blog | amiq_sv_c_python_how_to_connect_systemverilog_with_python/amiq_mux2_1.v | 1,162 | module MODULE1(input clk, input sel, input VAR3, input VAR2, output reg out);
VAR1 out=0;
always@(posedge clk) begin
out<=sel?VAR2:VAR3;
end
endmodule | apache-2.0 |
bigboyq/proxmark3 | fpga/fpga_hf.v | 6,446 | module MODULE1(
input VAR22, output VAR68, input VAR48, input VAR99,
input VAR28, input VAR97, input VAR43,
output VAR85, output VAR40,
output VAR42, output VAR76, output VAR1, output VAR84,
input [7:0] VAR92, output VAR33, output VAR58,
output VAR101, output VAR49, input VAR26, output VAR78,
input VAR56, input VAR102,... | gpl-2.0 |
dm-urievich/afc-smm | software/third-patry/pipelined_fft_256/trunk/SRC/fft16.v | 21,488 | module MODULE1 ( VAR32 ,VAR204 ,VAR52 ,VAR55 ,VAR87 ,VAR137 ,VAR35 ,VAR211 ,VAR170 );
input VAR55 ; wire VAR55 ;
input VAR52 ;
wire VAR52 ;
input VAR87 ;
wire VAR87 ;
input [VAR78-1:0] VAR204 ;
wire [VAR78-1:0] VAR204 ;
input VAR35 ;
wire VAR35 ;
input [VAR78-1:0] VAR211 ;
wire [VAR78-1:0] VAR211 ;
output [VAR78+3:0] V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4bb/sky130_fd_sc_hdll__nand4bb_4.v | 2,350 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR5 ,
VAR7 ,
VAR6 ,
VAR2,
VAR8,
VAR10 ,
VAR11
);
output VAR4 ;
input VAR1 ;
input VAR5 ;
input VAR7 ;
input VAR6 ;
input VAR2;
input VAR8;
input VAR10 ;
input VAR11 ;
VAR9 VAR3 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR10(VAR10),
.VA... | apache-2.0 |
DeanoC/ice40k-zpu | icestick_top.v | 4,091 | module MODULE2(
output [7:0] VAR42,
input VAR7, VAR32, VAR53,
input [8:0] VAR41,
);
parameter VAR11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR40 = 256'h00000000000000000000000000000000000... | mit |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CORESPI/4.2.116/bfm_apb.v | 8,916 | module MODULE1 (VAR69, VAR116, VAR149, VAR99, VAR125, VAR74, VAR117, VAR158, VAR168, VAR98, VAR100, VAR65, VAR123, VAR124, VAR118, VAR55, VAR57, VAR157, VAR52, VAR11, VAR32, VAR70, VAR25, VAR4, VAR139, VAR71, VAR148);
parameter VAR127 = 0;
parameter VAR83 = 16384;
parameter VAR140 = 1024;
parameter VAR134 = 65536;
par... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/response_handler.v | 3,398 | module MODULE1 (
input clk,
input VAR3,
input VAR8,
output VAR14,
input [1:0] VAR4,
output reg [VAR5-1:0] VAR16,
input [VAR5-1:0] VAR15,
input VAR2,
input enable,
output reg VAR12,
input VAR1,
output VAR10,
input VAR6,
output VAR7,
output [1:0] VAR11
);
parameter VAR5 = 3;
assign VAR11 = VAR4;
assign VAR7 = VAR1;
wire ... | gpl-3.0 |
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