repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
cliffordwolf/yosys | techlibs/ecp5/cells_map.v | 15,010 | module \VAR95 (input VAR39, VAR44, output VAR59);
parameter VAR10 = 1'VAR69;
generate if (VAR10 === 1'b1)
VAR42 #(.VAR37("VAR23"), .VAR48("1"), .VAR63("VAR60"), .VAR6("VAR13"), .VAR96("VAR113")) VAR74 (.VAR29(VAR44), .VAR13(1'b0), .VAR49(VAR39), .VAR59(VAR59));
else
VAR42 #(.VAR37("VAR23"), .VAR48("1"), .VAR63("VAR60")... | isc |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v | 9,160 | module MODULE1 (clk, rst, VAR18, VAR2, VAR13, VAR5, VAR16,
posedge, negedge, VAR11, VAR19,
VAR10, VAR21,
VAR1, VAR7, VAR8, VAR15, VAR3);
input clk; input rst; input [3:0] VAR18; input [3:0] VAR2; input [VAR4-1:0] VAR13; input VAR5; input VAR16; input posedge; input negedge; input VAR11; input VAR19; output VAR10; outpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ebufn/sky130_fd_sc_lp__ebufn.pp.symbol.v | 1,327 | module MODULE1 (
input VAR6 ,
output VAR3 ,
input VAR7,
input VAR4 ,
input VAR5,
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
duttondj/DigitalDesignI-P3 | keypressed.v | 5,258 | module MODULE1(VAR1, reset, VAR2, VAR3);
input VAR1; input reset; input VAR2; output reg VAR3;
reg [1:0] VAR7, VAR5;
parameter [1:0] VAR4 = 2'b00, VAR10 = 2'b01, VAR8 = 2'b10;
always @(posedge VAR1 or negedge reset) begin
if (reset == 1'b0)
VAR7 <= VAR4;
end
else
VAR7 <= VAR5;
end
always @(VAR7, VAR2) begin
VAR5 = VAR7... | mit |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/correlator/correlator_SDP.v | 6,669 | module MODULE1
parameter VAR12 = VAR6+VAR6, parameter VAR40 = VAR12-1,
parameter VAR44 = 120'hb1a191817161b0a090807060,
parameter VAR5 = 12, parameter VAR11 = 4,
parameter VAR51 = VAR11 - 1,
parameter VAR49 = 3)
(
input VAR27,
input VAR47, input en, input [23:0] VAR31,
input [23:0] VAR26,
input [VAR51:0] rd,
input [VAR... | lgpl-3.0 |
zhangly/azpr_cpu | rtl/bus/rtl/bus_slave_mux.v | 3,171 | module MODULE1 (
input wire VAR15, input wire VAR26, input wire VAR24, input wire VAR1, input wire VAR22, input wire VAR6, input wire VAR25, input wire VAR2,
input wire [VAR18] VAR17, input wire VAR29, input wire [VAR18] VAR20, input wire VAR8, input wire [VAR18] VAR16, input wire VAR23, input wire [VAR18] VAR4, input ... | mit |
kwantam/multiexp-a5gx | verilog/mpfe_rst.v | 3,375 | module MODULE1
( input VAR12
, input VAR16
, input VAR15
, input VAR1
, input VAR18
, input VAR2
, input VAR4
, output VAR11
, output VAR7
, output VAR13
);
localparam VAR6 = 26'h000000f;
localparam VAR6 = 26'h3ffffff;
reg VAR17[1:0];
assign VAR7 = VAR17[1];
reg VAR8[1:0];
assign VAR13 = VAR8[1];
reg [25:0] VAR10;
reg ... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x8_125/source/cmm_errman_nfl.v | 5,531 | module MODULE1 (
VAR2, VAR7,
VAR3,
VAR1,
rst,
clk
);
output VAR2;
output VAR7;
input VAR3;
input VAR1;
input rst;
input clk;
parameter VAR4 = 1;
reg VAR8;
reg VAR6;
always @(VAR3 or VAR1) begin
case ({VAR3, VAR1}) 2'b10: begin VAR8 = 1'b0;
VAR6 = 1'b1;
end
2'b11: begin VAR8 = 1'b1;
VAR6 = 1'b0;
end
2'b00: begin VAR8 = ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41ai/sky130_fd_sc_ls__o41ai.behavioral.v | 1,571 | module MODULE1 (
VAR4 ,
VAR12,
VAR2,
VAR3,
VAR11,
VAR6
);
output VAR4 ;
input VAR12;
input VAR2;
input VAR3;
input VAR11;
input VAR6;
supply1 VAR7;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR9 ;
wire VAR13 ;
wire VAR15;
or VAR14 (VAR13 , VAR11, VAR3, VAR2, VAR12 );
nand VAR10 (VAR15, VAR6, VAR13 );
buf VAR1 (VAR4 , VAR15 ... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/V2NFC100DDR_v1_0_0/81152d2e/src/NPCG_Toggle_BNC_P_program.v | 11,088 | module MODULE1
(
parameter VAR38 = 4
)
(
VAR27 ,
VAR54 ,
VAR15 ,
VAR9 ,
VAR46 ,
VAR36 ,
VAR49 ,
VAR50 ,
VAR20 ,
VAR53 ,
VAR56 ,
VAR22 ,
VAR12 ,
VAR6 ,
VAR33 ,
VAR21 ,
VAR42 ,
VAR43 ,
VAR2 ,
VAR34 ,
VAR41 ,
VAR52 ,
VAR23 ,
VAR1 ,
VAR24 ,
VAR4 ,
VAR39 ,
VAR35 ,
VAR7
);
input VAR27 ;
input VAR54 ;
input [5:0] VAR15 ;
inpu... | gpl-3.0 |
takeshineshiro/fpga_linear_128 | Transmit.v | 18,763 | module MODULE1(
input VAR35, input [7:0] VAR6, input [1:0] VAR18, input VAR51, input VAR52, output reg VAR54, output reg [15:0] VAR19,
output reg [15:0] VAR45,
output reg VAR43,
output reg VAR28,
output reg VAR22,
output reg VAR49,
output reg [3:0] VAR20,
output reg [2:0] VAR16,
output reg VAR14,
output reg VAR53,
outp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_2.v | 2,695 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR13 ,
VAR1 ,
VAR2 ,
VAR7 ,
VAR8,
VAR10 ,
VAR4 ,
VAR6 ,
VAR12
);
output VAR9 ;
output VAR3 ;
input VAR13 ;
input VAR1 ;
input VAR2 ;
input VAR7 ;
input VAR8;
input VAR10 ;
input VAR4 ;
input VAR6 ;
input VAR12 ;
VAR5 VAR11 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR13(VAR13),
.VAR1(VAR1),
.VAR2(VAR... | apache-2.0 |
LorhanSohaky/UFSCar | 2017/lab_cd/relatorio5/codigo/maquina.v | 2,365 | module MODULE2 ( VAR4, VAR2, VAR23, VAR1, VAR24, VAR11, VAR25, VAR8, VAR10 );
input VAR4, VAR2, VAR23, VAR1, VAR24, VAR10;
output VAR11, VAR25;
output [6:0] VAR8;
reg [1:0] VAR15;
reg [4:0] VAR14;
reg [6:0] VAR6;
reg VAR13, VAR3;
parameter VAR20 = 2'b00, VAR5 = 2'b01, VAR22 = 2'b10, VAR12 = 2'b11;
VAR17 VAR15 = VAR20;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufinv/sky130_fd_sc_hdll__bufinv_16.v | 2,066 | module MODULE2 (
VAR1 ,
VAR5 ,
VAR7,
VAR6,
VAR2 ,
VAR4
);
output VAR1 ;
input VAR5 ;
input VAR7;
input VAR6;
input VAR2 ;
input VAR4 ;
VAR3 VAR8 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR1,
VAR5
);
output VAR1;
input VAR5;
supply1 VAR7;
supply0 VAR6;... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_auto_pc_1/synth/OpenSSD2_auto_pc_1.v | 16,755 | module MODULE1 (
VAR21,
VAR97,
VAR92,
VAR43,
VAR18,
VAR44,
VAR38,
VAR31,
VAR91,
VAR49,
VAR7,
VAR32,
VAR106,
VAR54,
VAR27,
VAR112,
VAR16,
VAR65,
VAR93,
VAR81,
VAR26,
VAR39,
VAR47,
VAR105,
VAR80,
VAR57,
VAR5,
VAR78,
VAR77,
VAR84,
VAR6,
VAR28,
VAR70,
VAR2,
VAR95,
VAR104,
VAR83,
VAR79,
VAR61,
VAR82,
VAR42,
VAR34,
VAR62,
VA... | gpl-3.0 |
alexforencich/verilog-ethernet | rtl/xgmii_baser_dec_64.v | 13,823 | module MODULE1 #
(
parameter VAR3 = 64,
parameter VAR1 = (VAR3/8),
parameter VAR2 = 2
)
(
input wire clk,
input wire rst,
input wire [VAR3-1:0] VAR6,
input wire [VAR2-1:0] VAR4,
output wire [VAR3-1:0] VAR8,
output wire [VAR1-1:0] VAR9,
output wire VAR7,
output wire VAR5
); | mit |
mrehkopf/sd2snes | verilog/sd2snes_dsp/ctx.v | 20,809 | module MODULE1(
input VAR70,
input reset,
input [23:0] VAR97, input [7:0] VAR64, input VAR106, input VAR113, input VAR49, input VAR66, input [7:0] VAR112,
output VAR46,
output VAR39,
output VAR92,
output VAR38,
input VAR104,
input VAR1,
output [23:0] VAR103, output [15:0] VAR11, output VAR68,
output VAR76
);
reg [7:0] ... | gpl-2.0 |
jotego/jt12 | hdl/jt12_acc.v | 3,213 | module MODULE1(
input rst,
input clk,
input VAR12 ,
input signed [8:0] VAR19,
input [ 1:0] VAR13,
input VAR16,
input VAR14,
input VAR1,
input VAR5,
input VAR29,
input VAR15,
input [2:0] VAR7,
input VAR4, input signed [8:0] VAR11,
output reg signed [11:0] VAR22,
output reg signed [11:0] VAR30
);
reg VAR28;
always @(*) b... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41ai/sky130_fd_sc_lp__o41ai_lp.v | 2,432 | module MODULE2 (
VAR12 ,
VAR8 ,
VAR3 ,
VAR7 ,
VAR2 ,
VAR10 ,
VAR9,
VAR1,
VAR5 ,
VAR11
);
output VAR12 ;
input VAR8 ;
input VAR3 ;
input VAR7 ;
input VAR2 ;
input VAR10 ;
input VAR9;
input VAR1;
input VAR5 ;
input VAR11 ;
VAR4 VAR6 (
.VAR12(VAR12),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_mmcm_drp.v | 7,437 | module MODULE1 (
clk,
VAR1,
VAR30,
VAR36,
VAR21,
VAR26,
VAR9,
VAR60,
VAR42,
VAR19,
VAR82,
VAR3,
VAR32);
parameter VAR63 = 0;
localparam VAR50 = 0;
localparam VAR57 = 1;
parameter VAR53 = 1.667;
parameter VAR72 = 6;
parameter VAR71 = 12.000;
parameter VAR75 = 2.000;
parameter VAR76 = 6;
input clk;
input VAR1;
output VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp.behavioral.pp.v | 3,061 | module MODULE1 (
VAR20 ,
VAR18 ,
VAR5 ,
VAR15 ,
VAR11 ,
VAR28 ,
VAR14,
VAR23 ,
VAR24 ,
VAR10 ,
VAR2
);
output VAR20 ;
output VAR18 ;
input VAR5 ;
input VAR15 ;
input VAR11 ;
input VAR28 ;
input VAR14;
input VAR23 ;
input VAR24 ;
input VAR10 ;
input VAR2 ;
wire VAR8 ;
wire VAR26 ;
wire VAR32 ;
reg VAR19 ;
wire VAR25 ;
w... | apache-2.0 |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_AWSF1/mkRISCV_MBox.v | 31,274 | module MODULE1(VAR152,
VAR180,
VAR141,
VAR129,
VAR68,
VAR61,
VAR16,
VAR133,
VAR76,
VAR183,
VAR78,
VAR181,
VAR56,
VAR62,
valid,
word);
input VAR152;
input VAR180;
input [3 : 0] VAR141;
input VAR129;
output VAR68;
input VAR61;
output VAR16;
input VAR133;
output VAR76;
input VAR183;
input [2 : 0] VAR78;
input [63 : 0] VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sedfxtp/sky130_fd_sc_hd__sedfxtp_4.v | 2,466 | module MODULE1 (
VAR12 ,
VAR1 ,
VAR2 ,
VAR4 ,
VAR11 ,
VAR10 ,
VAR7,
VAR9,
VAR8 ,
VAR3
);
output VAR12 ;
input VAR1 ;
input VAR2 ;
input VAR4 ;
input VAR11 ;
input VAR10 ;
input VAR7;
input VAR9;
input VAR8 ;
input VAR3 ;
VAR5 VAR6 (
.VAR12(VAR12),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR10(VAR10),
.VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_4.behavioral.v | 2,716 | module MODULE1( VAR7, VAR4, VAR21, VAR22 );
input VAR21, VAR4, VAR7;
output VAR22;
reg VAR8;
VAR16 VAR24(.VAR7(VAR7),.VAR4(VAR4),.VAR21(VAR21),.VAR22(VAR22),.VAR8(VAR8));
VAR16 VAR2(.VAR7(VAR7),.VAR4(VAR4),.VAR21(VAR21),.VAR22(VAR22),.VAR8(VAR8));
not VAR17(VAR23,VAR4);
not VAR12(VAR9,VAR7);
and VAR13(VAR6,VAR9,VAR23);... | apache-2.0 |
denis4net/hw_design | 3/src/uart.v | 3,266 | module MODULE2(input [28:0] VAR6, input rst, input clk, output VAR9);
parameter VAR5 = 50000000;
reg [28:0] VAR26;
wire [28:0] VAR13 = VAR26[28] ? (VAR6) : (VAR6 - VAR5);
always @(posedge clk or posedge rst)
VAR26 <= (rst) ? ((VAR6 - VAR5) >>> 1 ) : VAR26+VAR13;
assign VAR9 = ~VAR26[28] & ~rst; endmodule
module MODULE1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/einvn/sky130_fd_sc_hvl__einvn.functional.pp.v | 1,881 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR13,
VAR12,
VAR5,
VAR8 ,
VAR6
);
output VAR1 ;
input VAR7 ;
input VAR13;
input VAR12;
input VAR5;
input VAR8 ;
input VAR6 ;
wire VAR2 ;
wire VAR4;
VAR9 VAR11 (VAR2 , VAR7, VAR12, VAR5 );
VAR9 VAR3 (VAR4, VAR13, VAR12, VAR5 );
notif0 VAR10 (VAR1 , VAR2, VAR4);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and2/gf180mcu_fd_sc_mcu7t5v0__and2_2.behavioral.pp.v | 1,244 | module MODULE1( VAR5, VAR6, VAR2, VAR3, VAR7 );
input VAR5, VAR6;
inout VAR3, VAR7;
output VAR2;
VAR1 VAR4(.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR3(VAR3),.VAR7(VAR7));
VAR1 VAR8(.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR3(VAR3),.VAR7(VAR7)); | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/MakeResetA.v | 2,832 | module MODULE1 (
VAR11,
VAR7,
VAR6,
VAR4,
VAR8,
VAR12
);
parameter VAR9 = 2 ; parameter VAR13 = 1 ;
input VAR11 ;
input VAR7 ;
input VAR6 ;
output VAR4 ;
input VAR8 ;
output VAR12 ;
reg rst ;
wire VAR12 ;
assign VAR4 = rst == VAR10 ;
VAR5 #(VAR9) VAR2 (.VAR11(VAR8),
.VAR1(rst),
.VAR12(VAR12));
always@(posedge VAR11 or ... | lgpl-3.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/atlys/rtl/verilog/dvi_gen/dvi_encoder.v | 3,542 | module MODULE1 (
input wire VAR5, input wire VAR22, input wire VAR13, input wire [7:0] VAR8, input wire [7:0] VAR24, input wire [7:0] VAR9, input wire VAR19, input wire VAR12, input wire VAR20, output wire [4:0] VAR15,
output wire [4:0] VAR18,
output wire [4:0] VAR26);
wire [9:0] VAR16 ;
wire [9:0] VAR27 ;
wire [9:0] V... | gpl-2.0 |
SiLab-Bonn/pyBAR | firmware/mmc3_beast_eth/src/mmc3_beast_eth.v | 24,446 | module MODULE1(
input wire VAR248,
input wire VAR266,
output wire [3:0] VAR286,
output wire VAR88,
output wire VAR264,
input wire [3:0] VAR242,
input wire VAR134,
input wire VAR223,
output wire VAR182,
inout wire VAR206,
output wire VAR58,
output wire [7:0] VAR25,
output wire VAR185, VAR69,
output wire VAR73, VAR46,
in... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hs__udp_dff_ps_pp_pg_n.blackbox.v | 1,437 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR5 ,
VAR2 ,
VAR6,
VAR1 ,
VAR4
);
output VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR2 ;
input VAR6;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfstp/sky130_fd_sc_lp__srsdfstp.pp.blackbox.v | 1,560 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR11 ,
VAR5 ,
VAR8 ,
VAR1 ,
VAR4,
VAR12 ,
VAR6 ,
VAR7 ,
VAR9 ,
VAR10
);
output VAR2 ;
input VAR3 ;
input VAR11 ;
input VAR5 ;
input VAR8 ;
input VAR1 ;
input VAR4;
input VAR12 ;
input VAR6 ;
input VAR7 ;
input VAR9 ;
input VAR10 ;
endmodule | apache-2.0 |
olofk/wb_intercon | rtl/verilog/wb_data_resize.v | 3,191 | module MODULE1
input [VAR22-1:0] VAR30,
input [3:0] VAR24,
input VAR3,
input VAR2,
input VAR27,
input [2:0] VAR15,
input [1:0] VAR16,
output [VAR22-1:0] VAR29,
output VAR11,
output VAR18,
output VAR25,
output [VAR10-1:0] VAR8,
output [VAR13-1:0] VAR4,
output VAR17,
output VAR20,
output VAR7,
output [2:0] VAR6,
output [... | lgpl-3.0 |
kyzhai/NUNY | src/hardware/lab3/synthesis/submodules/lab3_onchip_memory2_0.v | 2,931 | module MODULE1 (
address,
VAR1,
VAR23,
clk,
VAR25,
reset,
VAR11,
write,
VAR10,
VAR16
)
;
parameter VAR12 = "MODULE1.VAR20";
output [ 31: 0] VAR16;
input [ 15: 0] address;
input [ 3: 0] VAR1;
input VAR23;
input clk;
input VAR25;
input reset;
input VAR11;
input write;
input [ 31: 0] VAR10;
wire VAR28;
wire [ 31: 0] VAR16... | gpl-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_axi_gpio_pullup_0/system_axi_gpio_pullup_0_stub.v | 2,345 | module MODULE1(VAR12, VAR14, VAR7,
VAR15, VAR10, VAR16, VAR19, VAR22, VAR18,
VAR11, VAR20, VAR3, VAR21, VAR17, VAR1,
VAR5, VAR13, VAR6, VAR9, VAR4, VAR2, VAR8)
;
input VAR12;
input VAR14;
input [8:0]VAR7;
input VAR15;
output VAR10;
input [31:0]VAR16;
input [3:0]VAR19;
input VAR22;
output VAR18;
output [1:0]VAR11;
outpu... | apache-2.0 |
fpgasystems/Centaur | rtl/mem/spl_pt_mem.v | 2,541 | module MODULE1 #(
parameter VAR4 = 32,
parameter VAR1 = 8
) (
input wire clk,
input wire VAR5,
input wire VAR3,
input wire [VAR1-1:0] VAR8,
input wire [VAR4-1:0] VAR11,
output reg [VAR4-1:0] VAR2,
input wire VAR9,
input wire [VAR1-1:0] VAR10,
output reg [VAR4-1:0] VAR6
);
reg [VAR4-1:0] VAR7[0:2**VAR1-1];
reg [VAR4-1:0... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_input_if.v | 9,597 | module MODULE1
VAR52 = 64,
VAR13 = 8,
VAR10 = 33,
VAR15 = 3,
VAR80 = 1,
VAR74 = 2,
VAR58 = "VAR4"
)
(
VAR33,
VAR5,
VAR60,
VAR49,
VAR27,
VAR67,
VAR20,
VAR22,
VAR16,
VAR51,
VAR66,
VAR9,
VAR39,
VAR29,
VAR6,
VAR42,
VAR64,
VAR38,
VAR62,
VAR81,
VAR3,
VAR84,
VAR11,
VAR36,
VAR18,
VAR35,
VAR28,
VAR44,
VAR30,
VAR63,
VAR26,
VAR77... | lgpl-3.0 |
cafe-alpha/wascafe | v13/wasca_10m08sc_20191205_abus_divide/wasca/synthesis/submodules/altera_int_osc.v | 2,608 | module MODULE1
(
VAR13,
VAR4);
parameter VAR8 = "VAR3 10";
parameter VAR2 = "08";
parameter VAR10 = "VAR6";
output VAR13;
input VAR4;
wire VAR1;
assign VAR13 = VAR1;
generate
if (VAR8 == "VAR3 10") begin
VAR9 # ( .VAR7(VAR2),
.VAR11(VAR10)
) VAR5 (
.VAR13(VAR1),
.VAR12(),
.VAR4(VAR4));
end
endgenerate
endmodule | gpl-2.0 |
toomij/DE2Labs | Lab4/counter_26bit.v | 2,093 | module MODULE1 (VAR18, VAR23, VAR13, VAR30);
input VAR18, VAR23, VAR13;
output [25:0] VAR30;
wire [25:0] VAR3, VAR2;
VAR22 VAR11 (VAR18, VAR23, VAR13, VAR2[0]);
assign VAR3[0] = VAR18 & VAR2[0];
VAR22 VAR24 (VAR3[0], VAR23, VAR13, VAR2[1]);
assign VAR3[1] = VAR3[0] & VAR2[1];
VAR22 VAR14 (VAR3[1], VAR23, VAR13, VAR2[2]... | gpl-2.0 |
kernelpanics/Grad | CORDIC-Natural-Logarithm/Verilog/Natural-Logarithm/shift_mux.v | 1,213 | module MODULE1#(parameter VAR1=26, parameter VAR15=5)(
input wire [VAR1-1:0] VAR9,
input wire VAR2,
input wire VAR7,
output wire [VAR1-1:0] VAR8
);
genvar VAR14;
generate for (VAR14=0; VAR14<=VAR1-1 ; VAR14=VAR14+1) begin
localparam VAR12=(2**VAR15)+VAR14;
case (VAR12>VAR1-1)
1'b1:begin
VAR6 #(.VAR5(1)) VAR10(
.VAR3(VA... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_005bits.v | 1,917 | module MODULE1 (
clk,
VAR13, VAR11, VAR19, VAR9, VAR16, VAR2, VAR10, VAR8,
sum,
);
input clk;
input [VAR31+0-1:0] VAR13, VAR11, VAR19, VAR9, VAR16, VAR2, VAR10, VAR8;
output [VAR31 :0] sum;
reg [VAR31 :0] sum;
wire [VAR31+3-1:0] VAR17;
wire [VAR31+2-1:0] VAR28, VAR30;
wire [VAR31+1-1:0] VAR5, VAR20, VAR21, VAR6;
reg [V... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/vfabric_fpextend.v | 1,514 | module MODULE1(VAR10, VAR8,
VAR9, VAR4, VAR5,
VAR6, VAR3, VAR2);
parameter VAR7 = 32;
parameter VAR1 = 64;
input VAR10, VAR8;
input [VAR7-1:0] VAR9;
input VAR4;
output VAR5;
output [VAR1-1:0] VAR6;
input VAR3;
output VAR2;
assign VAR6 = {VAR9[VAR7-1], 3'b0, VAR9[30:23], 29'b0, VAR9[22:0]};
assign VAR5 = VAR3;
assign VA... | mit |
skalldri/mips-verilog | register-file/data_memory.v | 2,952 | module MODULE1 (clk, addr, din, dout, VAR4, VAR13, VAR9, VAR7, enable);
parameter VAR1 = "VAR11.VAR3";
input clk;
input [31:0] addr;
input [31:0] din;
input [2:0] VAR13;
input VAR9; input enable;
output reg VAR7;
output reg [31:0] dout;
output reg [31:0] VAR4;
reg [7:0] VAR6[0:VAR2];
reg [31:0] VAR12 = 'hffff; reg [5:0... | gpl-2.0 |
anderson1008/NOCulator | hring/hw/buffered/src/vcr_ugal_sniffer.v | 3,505 | module MODULE1(
VAR1,
clk, reset, VAR6, VAR17
);
parameter VAR20 = 8;
parameter VAR29 = 1;
parameter VAR35 = 2;
localparam VAR8 = VAR29 * VAR35;
parameter VAR16 = 1;
localparam VAR19 = VAR8 * VAR16;
localparam VAR9 = VAR15(VAR19);
parameter VAR22 = VAR12;
localparam VAR38
= (VAR22 == VAR13) ?
(1 + VAR9 + 1 + 1) :
(VAR2... | mit |
freecores/eco32 | fpga/src/dsp/dspmem.v | 5,863 | module MODULE1(VAR24, VAR32, VAR29, VAR14, en, wr,
clk, VAR20,
VAR28, VAR55, VAR1, VAR36,
VAR38, VAR18, VAR50,
VAR52, VAR23, VAR39,
VAR49, VAR51, VAR27,
VAR45, VAR2, VAR21);
input [4:0] VAR24;
input [6:0] VAR32;
input [15:0] VAR29;
output [15:0] VAR14;
input en;
input wr;
input clk;
input VAR20;
input [4:0] VAR28;
inpu... | bsd-2-clause |
SymbiFlow/fpga-tool-perf | src/picosoc/progmem.v | 26,802 | module MODULE1
(
input wire clk,
input wire VAR4,
input wire valid,
output wire ready,
input wire [31:0] addr,
output wire [31:0] VAR2
);
localparam VAR7 = 10; localparam VAR5 = 1 << VAR7;
localparam VAR8 = 32'h00100000;
wire [VAR7-1:0] VAR1;
reg [31:0] VAR6;
reg [31:0] VAR3[0:VAR5]; | isc |
alexforencich/verilog-axis | rtl/axis_stat_counter.v | 12,272 | module MODULE1 #
(
parameter VAR53 = 64,
parameter VAR38 = (VAR53>8),
parameter VAR18 = ((VAR53+7)/8),
parameter VAR5 = 1,
parameter VAR32 = 16,
parameter VAR45 = 1,
parameter VAR15 = 32,
parameter VAR48 = 1,
parameter VAR57 = 32,
parameter VAR34 = 1,
parameter VAR39 = 32
)
(
input wire clk,
input wire rst,
input wire ... | mit |
eda-globetrotter/MarcheProcessor | final/src/datamem.v | 2,672 | module MODULE1 (VAR3,VAR1,VAR2,clk,VAR4);
output [0:127] VAR3;
input [0:127] VAR1;
input [0:31] VAR2;
input clk;
input [0:1] VAR4;
reg [0:127] VAR3;
reg [127:0] MODULE1 [255:0];
begin
begin
begin
begin
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfstp/sky130_fd_sc_ls__dfstp.pp.symbol.v | 1,386 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR7,
input VAR3 ,
input VAR5 ,
input VAR8 ,
input VAR1 ,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp.pp.symbol.v | 1,506 | module MODULE1 (
input VAR3 ,
output VAR1 ,
input VAR6 ,
input VAR4 ,
input VAR7 ,
input VAR8,
input VAR9 ,
input VAR2 ,
input VAR10 ,
input VAR5 ,
input VAR11
);
endmodule | apache-2.0 |
P3Stor/P3Stor | pcie/core/trn_rx_128.v | 17,171 | module MODULE1 #(
parameter VAR87 = 100
)(
input VAR40,
input VAR47,
input VAR25,
input VAR86,
output [6:0] VAR27,
output[127:0] VAR77,
output VAR30,
output VAR85,
output VAR71,
output VAR44,
output [1:0] VAR36,
output VAR19,
output VAR69,
input VAR94,
input VAR65,
input [6:0] VAR88,
input [63:0] VAR11,
input VAR34,
in... | gpl-2.0 |
Cognoscan/VerilogCogs | sinc3Filter.v | 1,749 | module MODULE1
parameter VAR7 = 16 )
(
input clk,
input en, input in,
output reg signed [3*VAR3(VAR7):0] out
);
localparam VAR8 = VAR3(VAR7)-1;
wire signed [3:0] VAR6;
reg [(3*VAR7)-1:0] VAR5;
reg signed [(3+1*VAR8):0] VAR1 = 'd0;
reg signed [(3+2*VAR8):0] VAR4 = 'd0;
integer VAR2; | apache-2.0 |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_15/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axi_protocol_converter.v | 40,353 | module MODULE1 #(
parameter VAR146 = "VAR96",
parameter integer VAR163 = 0,
parameter integer VAR222 = 0,
parameter integer VAR55 = 0,
parameter integer VAR77 = 4,
parameter integer VAR117 = 32,
parameter integer VAR246 = 32,
parameter integer VAR62 = 1,
parameter integer VAR190 = 1,
parameter integer VAR115 = 0,
param... | mit |
TUM-LIS/faultify | software/host/davester_combinational_extractor/yosys_saed90nm.v | 6,355 | module MODULE7 (input VAR16, VAR24, output VAR12, VAR5, input VAR14, VAR7);
endmodule
module MODULE21 (input VAR16, VAR24, output VAR12, VAR5, input VAR14, VAR7);
endmodule
module MODULE48 (input VAR16, VAR24, output VAR12, VAR5, input VAR17, VAR14, VAR7);
endmodule
module MODULE62 (input VAR16, VAR24, output VAR12, VA... | gpl-2.0 |
sehugg/8bitworkshop | presets/verilog/cpu6502.v | 36,383 | module MODULE1( clk, reset, VAR135, VAR188, VAR40, VAR184, VAR50, VAR126, VAR193 );
input clk; input reset; output reg [15:0] VAR135; input [7:0] VAR188; output [7:0] VAR40; output VAR184; input VAR50; input VAR126; input VAR193;
reg [15:0] VAR190; reg [7:0] VAR149; reg [7:0] VAR194; wire [7:0] VAR114;
reg [7:0] VAR20;... | gpl-3.0 |
osecpu/fpga | controller.v | 3,321 | module MODULE1(clk, reset,
VAR6, VAR14, VAR27,
VAR16, VAR12, VAR5,
VAR4, VAR19,
VAR3, VAR18);
input clk, reset;
input [31:0] VAR6;
input VAR27;
input VAR3;
input [15:0] VAR18;
output reg [15:0] VAR14;
output reg [31:0] VAR16 = 0;
output reg [31:0] VAR12 = 0;
output reg [3:0] VAR5 = 0;
output reg [7:0] VAR4 = 0;
output ... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/hps_sdram_p0_iss_probe.v | 1,741 | module MODULE1 (
VAR24
);
parameter VAR10 = 1;
parameter VAR2 = "VAR23";
input [VAR10-1:0] VAR24;
VAR33 VAR13 (
.VAR26 (VAR24),
.VAR11 ()
,
.VAR21 (),
.VAR15 (),
.VAR28 (),
.VAR22 (),
.VAR14 (),
.VAR20 (),
.VAR34 (),
.VAR25 (),
.VAR27 (),
.VAR7 (),
.VAR6 (),
.VAR16 (),
.VAR18 (),
.VAR29 (),
.VAR5 (),
.VAR17 (),
.VAR9 (... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_sata/rtl/wb_sata.v | 37,849 | module MODULE1 (
input clk,
input rst,
input VAR213,
input VAR264,
input VAR71,
input VAR268,
input [3:0] VAR51,
input [31:0] VAR73,
input VAR96,
output reg VAR80,
output reg [31:0] VAR209,
input [31:0] VAR90,
output reg VAR118,
output [31:0] VAR97,
output VAR15,
output VAR242,
output VAR115,
output VAR23,
input VAR105... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4b/sky130_fd_sc_ms__or4b.blackbox.v | 1,316 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR6 ,
VAR5 ,
VAR1
);
output VAR8 ;
input VAR3 ;
input VAR6 ;
input VAR5 ;
input VAR1;
supply1 VAR9;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnrnq/gf180mcu_fd_sc_mcu9t5v0__dffnrnq_4.behavioral.v | 3,689 | module MODULE1( VAR13, VAR31, VAR10, VAR6 );
input VAR13, VAR31, VAR10;
output VAR6;
reg VAR23;
VAR27 VAR18(.VAR13(VAR13),.VAR31(VAR31),.VAR10(VAR10),.VAR6(VAR6),.VAR23(VAR23));
VAR27 VAR21(.VAR13(VAR13),.VAR31(VAR31),.VAR10(VAR10),.VAR6(VAR6),.VAR23(VAR23));
not VAR8(VAR26,VAR31);
and VAR29(VAR19,VAR10,VAR26);
and VAR... | apache-2.0 |
DeadWitcher/amber-de0-nano | hw/vlog/amber25/a25_shifter.v | 19,392 | module MODULE1 #(
parameter VAR11 = 1
)(
input [31:0] VAR5,
input VAR8,
input [7:0] VAR4, input VAR2, input [1:0] VAR6,
output [31:0] VAR21,
output VAR16
);
wire [32:0] VAR19;
wire [32:0] VAR10;
wire [32:0] VAR17;
wire [32:0] VAR12;
generate
if (VAR11 == 1) begin : VAR22
assign VAR19 = VAR2 ? {VAR8, VAR5 } :
VAR4 == 8'... | lgpl-2.1 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_01/02 verilog/periferico_audio/peripheral_audio.v | 1,547 | module MODULE1(clk , rst , din , VAR4 , addr, dout, VAR5, VAR10, VAR2,VAR11,VAR8,VAR7 );
input clk;
input rst;
input [15:0]din;
input VAR4;
input [3:0]addr; output [15:0]dout;
output VAR10;
output VAR5;
output VAR2;
input VAR11;
output VAR8;
output VAR7;
reg [2:0] VAR3;
VAR9 VAR6(.reset(rst), .clk(clk), .VAR2(VAR2),.VA... | gpl-3.0 |
osrf/wandrr | firmware/motor_controller/fpga/fpadd.v | 139,666 | module MODULE1
(
VAR8,
VAR3,
VAR13,
VAR7,
VAR4,
VAR10) ;
input VAR8;
input VAR3;
input VAR13;
input [25:0] VAR7;
input [4:0] VAR4;
output [25:0] VAR10;
tri0 VAR8;
tri1 VAR3;
tri0 VAR13;
reg [0:0] VAR11;
reg [25:0] VAR5;
wire [5:0] VAR6;
wire VAR12;
wire [15:0] VAR1;
wire [155:0] VAR2;
wire [4:0] VAR14;
wire [129:0] VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkbuf/sky130_fd_sc_hs__clkbuf.functional.v | 1,661 | module MODULE1 (
VAR6,
VAR2,
VAR7 ,
VAR1
);
input VAR6;
input VAR2;
output VAR7 ;
input VAR1 ;
wire VAR8 ;
wire VAR10;
buf VAR5 (VAR8 , VAR1 );
VAR9 VAR3 (VAR10, VAR8, VAR6, VAR2);
buf VAR4 (VAR7 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32o/sky130_fd_sc_hs__a32o.pp.symbol.v | 1,398 | module MODULE1 (
input VAR7 ,
input VAR4 ,
input VAR8 ,
input VAR2 ,
input VAR1 ,
output VAR5 ,
input VAR6,
input VAR3
);
endmodule | apache-2.0 |
secworks/cmac | src/rtl/cmac.v | 8,968 | module MODULE1(
input wire clk,
input wire VAR63,
input wire VAR56,
input wire VAR35,
input wire [7 : 0] address,
input wire [31 : 0] VAR32,
output wire [31 : 0] VAR40
);
localparam VAR14 = 8'h00;
localparam VAR61 = 8'h01;
localparam VAR33 = 8'h02;
localparam VAR59 = 8'h08;
localparam VAR20 = 0;
localparam VAR34 = 1;
l... | bsd-2-clause |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2/ddr2_example_top.v | 7,181 | module MODULE1 (
VAR32,
VAR24,
VAR51,
VAR4,
VAR20,
VAR39,
VAR29,
VAR63,
VAR41,
VAR26,
VAR56,
VAR70,
VAR9,
VAR34,
VAR58,
VAR2,
VAR53,
VAR57,
VAR49,
VAR66
)
;
output [ 12: 0] VAR51;
output [ 1: 0] VAR4;
output VAR20;
output [ 0: 0] VAR39;
inout [ 0: 0] VAR29;
inout [ 0: 0] VAR63;
output [ 0: 0] VAR41;
output [ 1: 0] VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4b/sky130_fd_sc_ls__and4b_2.v | 2,300 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR6 ,
VAR5 ,
VAR3 ,
VAR7,
VAR1,
VAR11 ,
VAR2
);
output VAR8 ;
input VAR10 ;
input VAR6 ;
input VAR5 ;
input VAR3 ;
input VAR7;
input VAR1;
input VAR11 ;
input VAR2 ;
VAR9 VAR4 (
.VAR8(VAR8),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR11(VAR11),
.... | apache-2.0 |
sh-chris110/chris | FPGA/uCos/system/synthesis/submodules/system_pll_0.v | 2,144 | module MODULE1(
input wire VAR34,
input wire rst,
output wire VAR69,
output wire VAR50,
output wire VAR35
);
VAR26 #(
.VAR10("false"),
.VAR54("50.0 VAR58"),
.VAR25("VAR29"),
.VAR20(2),
.VAR42("100.000000 VAR58"),
.VAR23("0 VAR2"),
.VAR40(50),
.VAR55("100.000000 VAR58"),
.VAR45("8250 VAR2"),
.VAR27(50),
.VAR60("0 VAR58"... | gpl-2.0 |
kevintownsend/R3 | coregen/fifo_64x512_hf.v | 23,622 | module MODULE1 (
clk, VAR22, rst, VAR146, VAR106, VAR95, VAR101, VAR34, dout, din
);
input clk;
input VAR22;
input rst;
output VAR146;
input VAR106;
output VAR95;
output VAR101;
output VAR34;
output [63 : 0] dout;
input [63 : 0] din;
wire VAR17;
wire VAR9;
wire \VAR14/VAR88/VAR30.VAR11/VAR27.VAR77/VAR72/VAR7 ;
wire \VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfxbp/sky130_fd_sc_hvl__dfxbp.symbol.v | 1,342 | module MODULE1 (
input VAR7 ,
output VAR8 ,
output VAR1,
input VAR6
);
supply1 VAR2;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fa/sky130_fd_sc_lp__fa_4.v | 2,278 | module MODULE2 (
VAR9,
VAR4 ,
VAR2 ,
VAR8 ,
VAR7 ,
VAR1,
VAR6,
VAR10 ,
VAR5
);
output VAR9;
output VAR4 ;
input VAR2 ;
input VAR8 ;
input VAR7 ;
input VAR1;
input VAR6;
input VAR10 ;
input VAR5 ;
VAR11 VAR3 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR5... | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_sdd1/DCM_Scope.v | 2,859 | module MODULE1(VAR17,
VAR36,
VAR15,
VAR10,
VAR39,
VAR8,
VAR35);
input VAR17;
input VAR36;
output VAR15;
output VAR10;
output VAR39;
output VAR8;
output VAR35;
wire VAR55;
wire VAR60;
wire VAR54;
wire VAR41;
wire VAR6;
wire VAR29;
assign VAR29 = 0;
assign VAR39 = VAR41;
assign VAR8 = VAR60;
VAR34 VAR38 (.VAR5(VAR55),
.V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/edfxbp/sky130_fd_sc_lp__edfxbp.blackbox.v | 1,378 | module MODULE1 (
VAR7 ,
VAR1,
VAR2,
VAR6 ,
VAR8
);
output VAR7 ;
output VAR1;
input VAR2;
input VAR6 ;
input VAR8 ;
supply1 VAR5;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Voters/Processor_Voter.v | 2,764 | module MODULE1(
input [1853:0] VAR4,
input [1853:0] VAR5,
input [1853:0] VAR14,
output [1853:0] VAR9
);
VAR3 #(.VAR20(2)) VAR13 (
.VAR12 (VAR4[1:0]),
.VAR16 (VAR5[1:0]),
.VAR7 (VAR14[1:0]),
.VAR11 (VAR9[1:0])
);
VAR3 #(.VAR20(193)) VAR17 (
.VAR12 (VAR4[194:2]),
.VAR16 (VAR5[194:2]),
.VAR7 (VAR14[194:2]),
.VAR11 (VAR9[1... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/rtl/ctu_dft_jtag_tap.v | 11,988 | module MODULE1(
VAR28, VAR82, VAR39, VAR61,
VAR43, VAR49, VAR13,
VAR77, VAR19, VAR84, VAR27,
VAR79, VAR46, VAR59, VAR15, VAR42, VAR16, VAR68, VAR57
);
input VAR79;
input VAR46;
input VAR59;
input VAR15;
input VAR42;
input VAR16;
input VAR68;
input VAR57;
output [VAR32-1:0] VAR28;
output [VAR32-1:0] VAR82;
output VAR39;... | gpl-2.0 |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_2/blk_mem_gen_2_stub.v | 1,426 | module MODULE1(VAR5, VAR8, VAR3, VAR6, VAR4, VAR7, VAR1, VAR2)
;
input VAR5;
input [0:0]VAR8;
input [11:0]VAR3;
input [31:0]VAR6;
input VAR4;
input VAR7;
input [13:0]VAR1;
output [7:0]VAR2;
endmodule | mit |
hitomi2500/wasca | fpga_firmware/wasca/synthesis/submodules/wasca_mm_interconnect_0_avalon_st_adapter.v | 6,149 | module MODULE1 #(
parameter VAR23 = 18,
parameter VAR6 = 0,
parameter VAR4 = 18,
parameter VAR13 = 0,
parameter VAR7 = 0,
parameter VAR1 = 0,
parameter VAR15 = 1,
parameter VAR12 = 1,
parameter VAR14 = 0,
parameter VAR8 = 18,
parameter VAR2 = 0,
parameter VAR18 = 1,
parameter VAR11 = 0,
parameter VAR19 = 1,
parameter V... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/phy/phy_top.v | 50,123 | module MODULE1 #
(
parameter VAR76 = 100,
parameter VAR147 = 2, parameter VAR116 = 3333, parameter VAR194 = 300.0, parameter VAR109 = "VAR252", parameter [7:0] VAR268 = 8'b00000001,
parameter [7:0] VAR299 = 8'b00000000,
parameter VAR79 = 2, parameter VAR264 = 1, parameter VAR281 = 10, parameter VAR317 = 1, parameter VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a311o/sky130_fd_sc_ls__a311o_1.v | 2,437 | module MODULE2 (
VAR12 ,
VAR2 ,
VAR4 ,
VAR1 ,
VAR9 ,
VAR3 ,
VAR8,
VAR11,
VAR6 ,
VAR10
);
output VAR12 ;
input VAR2 ;
input VAR4 ;
input VAR1 ;
input VAR9 ;
input VAR3 ;
input VAR8;
input VAR11;
input VAR6 ;
input VAR10 ;
VAR5 VAR7 (
.VAR12(VAR12),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(V... | apache-2.0 |
MarcoVogt/basil | firmware/modules/i2c/i2c.v | 1,553 | module MODULE1 #(
parameter VAR4 = 16'h0000,
parameter VAR23 = 16'h0000,
parameter VAR6 = 16,
parameter VAR20 = 1
)(
input wire VAR2,
input wire VAR9,
input wire [VAR6-1:0] VAR21,
inout wire [7:0] VAR11,
input wire VAR13,
input wire VAR10,
input wire VAR12,
inout wire VAR16,
inout wire VAR8
);
wire VAR24, VAR18;
wire [... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinv/sky130_fd_sc_lp__clkinv_4.v | 2,036 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR3,
VAR6,
VAR8 ,
VAR7
);
output VAR4 ;
input VAR5 ;
input VAR3;
input VAR6;
input VAR8 ;
input VAR7 ;
VAR2 VAR1 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR4,
VAR5
);
output VAR4;
input VAR5;
supply1 VAR3;
supply0 VAR6;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3.functional.v | 1,344 | module MODULE1 (
VAR4,
VAR1
);
output VAR4;
input VAR1;
wire VAR2;
not VAR5 (VAR2, VAR1 );
buf VAR3 (VAR4 , VAR2 );
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_switch.v | 15,284 | module MODULE1 #
(
parameter VAR36 = 4,
parameter VAR29 = 4,
parameter VAR3 = 8,
parameter VAR11 = (VAR3>8),
parameter VAR17 = (VAR3/8),
parameter VAR1 = 0,
parameter VAR7 = 8,
parameter VAR9 = VAR35(VAR29),
parameter VAR14 = 1,
parameter VAR37 = 1,
parameter VAR33 = 0,
parameter VAR6 = 0,
parameter VAR16 = {VAR29{{VAR... | mit |
Gifts/descrypt-ztex-bruteforcer | user_cores/des/src/shifts_s1.v | 1,583 | module MODULE2(
input [55:0] VAR1,
output [55:0] VAR5
);
parameter VAR6 = 1;
wire [27:0] VAR3;
wire [27:0] VAR2;
wire [55:0] VAR4;
assign VAR3 = VAR1[55:28];
assign VAR2 = VAR1[27:0];
assign VAR4 = {(VAR3 << VAR6) | (VAR3 >> (28-VAR6)), (VAR2 << VAR6) | (VAR2 >> (28-VAR6))};
assign VAR5 = VAR4;
endmodule
module MODULE1... | gpl-3.0 |
EmbeddedANT/XILINX_Spartan3AN-StarterKit | Spartan3AN_PicoBlaze_LCD/picouser/PicoBlaze_OutReg.v | 2,076 | module MODULE1
(
clk,
reset,
VAR6,
VAR5,
VAR4,
VAR3);
input wire clk;
input wire reset;
input wire [7:0] VAR6;
input wire VAR5;
input wire [7:0] VAR4;
output reg [7:0] VAR3;
reg VAR2=1;
always @ (*)
begin
if (VAR5 == 1)
begin
case (VAR6)
VAR1: VAR2 = 1;
default: VAR2 = 0;
endcase
end
else
VAR2=0;
end
always @ (posedge ... | gpl-3.0 |
ellore/processor | comm_fpga_fx2.v | 9,024 | module
MODULE1(
input wire VAR25, output reg VAR2, inout wire[7:0] VAR42,
output wire VAR16, input wire VAR7,
output wire VAR43, input wire VAR3, output reg VAR6,
output wire[6:0] VAR29,
output wire[7:0] VAR28, output reg VAR15, input wire VAR8,
input wire[7:0] VAR31, input wire VAR19, output reg VAR20 );
localparam[3:... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x8_125/example_design/xilinx_pci_exp_ep.v | 18,588 | module MODULE1
(
VAR79,
VAR128,
VAR148,
VAR119,
VAR93,
VAR44,
VAR28,
VAR116
);
output [(8 - 1):0] VAR79;
output [(8 - 1):0] VAR128;
input [(8 - 1):0] VAR148;
input [(8 - 1):0] VAR119;
input VAR93;
input VAR44;
input VAR28;
output VAR116;
wire VAR54;
wire VAR113;
wire VAR104; wire VAR36;
wire VAR16;
wire VAR59;
wire [(6... | lgpl-3.0 |
audiocircuit/NCSU-Low-Power-RFID | rfid-verilog/tag/rx.v | 3,605 | module MODULE1 (reset, clk, VAR25, VAR24, VAR23, VAR14, VAR11, VAR9);
input reset, clk, VAR25;
output VAR24, VAR23, VAR14, VAR9;
output [9:0] VAR11;
reg VAR24, VAR23, VAR9;
reg [9:0] VAR11, VAR22;
parameter VAR17 = 5'd0;
parameter VAR6 = 5'd1;
parameter VAR5 = 5'd2;
parameter VAR18 = 5'd4;
parameter VAR15 = 5'd8;
reg [... | gpl-3.0 |
cafe-alpha/wascafe | v10/fpga_firmware/wasca/synthesis/submodules/wasca_onchip_memory2_0.v | 2,943 | module MODULE1 (
address,
VAR13,
VAR11,
clk,
VAR1,
reset,
VAR34,
write,
VAR15,
VAR21
)
;
parameter VAR35 = "MODULE1.VAR27";
output [ 31: 0] VAR21;
input [ 11: 0] address;
input [ 3: 0] VAR13;
input VAR11;
input clk;
input VAR1;
input reset;
input VAR34;
input write;
input [ 31: 0] VAR15;
wire VAR28;
wire [ 31: 0] VAR21... | gpl-2.0 |
DigitalLogicSummerTerm2015/mips-cpu-pipeline | ppcpu/IDEXreg.v | 2,051 | module MODULE1(clk,VAR19,VAR2,VAR3,VAR30,VAR29,VAR27,
VAR20,VAR7,VAR23,VAR9,VAR8,VAR32,VAR26,VAR5,VAR10,
VAR4,VAR28,VAR18,VAR21,VAR1,VAR11,VAR14,VAR15,VAR31,
VAR25,VAR24,VAR16,VAR6,VAR12,VAR22,VAR17,VAR13);
input clk;
input [31:0] VAR19;
input VAR2;
input [31:0] VAR3;
input [31:0] VAR30;
input [31:0] VAR29;
input [31:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2i/sky130_fd_sc_hs__mux2i.functional.v | 1,848 | module MODULE1 (
VAR12,
VAR8,
VAR4 ,
VAR1 ,
VAR13 ,
VAR2
);
input VAR12;
input VAR8;
output VAR4 ;
input VAR1 ;
input VAR13 ;
input VAR2 ;
wire VAR6;
wire VAR11 ;
VAR3 VAR10 (VAR6, VAR1, VAR13, VAR2 );
VAR5 VAR9 (VAR11 , VAR6, VAR12, VAR8);
buf VAR7 (VAR4 , VAR11 );
endmodule | apache-2.0 |
ptracton/Picoblaze | library/timers/timer_regs.v | 3,522 | module MODULE1 (
VAR16, interrupt, VAR13, VAR15,
VAR2,
clk, reset, VAR14, VAR9, VAR3, VAR6,
VAR21
) ;
parameter VAR11 = 8'h00;
input clk;
input reset;
input [7:0] VAR14;
input [7:0] VAR9;
output [7:0] VAR16;
input VAR3;
input VAR6;
output interrupt;
output VAR13;
output [31:0] VAR15;
output VAR2;
input VAR21;
reg inter... | mit |
jotego/jt51 | syn/xilinx/contra_snd/hdl/fake_tone.v | 1,765 | module MODULE1(
input rst,
input clk,
input VAR17,
output VAR11
);
wire [15:0] VAR19, VAR14;
wire VAR5, VAR7;
MODULE2 MODULE1( .rst(rst), .clk(clk), .VAR19(VAR19) );
MODULE3 MODULE2( .rst(rst), .VAR17(VAR17), .VAR20(VAR19), .VAR5(VAR5), .VAR7(VAR7) );
VAR2 VAR21( .rst(rst), .VAR5(VAR5), .VAR4(VAR7), .VAR17(VAR17), .VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o22a/sky130_fd_sc_hvl__o22a.behavioral.pp.v | 2,167 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR17 ,
VAR19 ,
VAR7 ,
VAR15,
VAR1,
VAR9 ,
VAR12
);
output VAR3 ;
input VAR2 ;
input VAR17 ;
input VAR19 ;
input VAR7 ;
input VAR15;
input VAR1;
input VAR9 ;
input VAR12 ;
wire VAR14 ;
wire VAR4 ;
wire VAR10 ;
wire VAR6;
or VAR18 (VAR14 , VAR17, VAR2 );
or VAR11 (VAR4 , VAR7, VAR19 );
and... | apache-2.0 |
cafe-alpha/wascafe | v12/fpga_firmware/wasca/synthesis/submodules/wasca_nios2_gen2_0_cpu_debug_slave_wrapper.v | 9,436 | module MODULE1 (
VAR26,
VAR23,
clk,
VAR48,
VAR6,
VAR49,
VAR5,
VAR45,
VAR55,
VAR41,
VAR9,
VAR28,
VAR29,
VAR16,
VAR42,
VAR17,
VAR21,
VAR2,
VAR3,
VAR22,
VAR53,
VAR27,
VAR39,
VAR19,
VAR10,
VAR50,
VAR13,
VAR12,
VAR56,
VAR31,
VAR43,
VAR15,
VAR37
)
;
output [ 37: 0] VAR53;
output VAR27;
output VAR39;
output VAR19;
output VAR1... | gpl-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_mem2x.v | 10,688 | module MODULE2
parameter VAR84=1,
parameter VAR71=32,
parameter VAR83="VAR34",
parameter VAR57 = "VAR140", parameter VAR43 = "VAR81" )
(
input clk,
input VAR92,
input VAR102,
input [VAR71-1:0] VAR133,
input [VAR71-1:0] VAR125,
input [VAR71-1:0] VAR90,
input [VAR71-1:0] VAR79,
input [VAR71/8-1:0] VAR16,
input [VAR71/8-1... | mit |
asicguy/gplgpu | hdl/hbi/hbi_addr_data.v | 11,348 | module MODULE1
(
input VAR35, input VAR57, input [31:0] VAR9, input [3:0] VAR33, input VAR15, input VAR29, input VAR6, input VAR1, input VAR55, input VAR25,
input VAR10,
input [11:9] VAR53,
input [11:9] VAR18,
input [2:0] VAR40,
input VAR48,
input VAR19,
input VAR34,
input VAR14,
output reg [31:0] VAR38, output reg [31... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapmet1/sky130_fd_sc_ms__tapmet1.symbol.v | 1,243 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31a/sky130_fd_sc_hs__o31a.pp.blackbox.v | 1,315 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR7 ,
VAR1 ,
VAR2 ,
VAR5,
VAR6
);
output VAR4 ;
input VAR3 ;
input VAR7 ;
input VAR1 ;
input VAR2 ;
input VAR5;
input VAR6;
endmodule | apache-2.0 |
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