repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211ai/sky130_fd_sc_ms__o211ai.symbol.v | 1,375 | module MODULE1 (
input VAR4,
input VAR7,
input VAR3,
input VAR6,
output VAR2
);
supply1 VAR8;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/xgmii_interleave.v | 2,118 | module MODULE1
(
input wire [63:0] VAR1,
input wire [7:0] VAR2,
output wire [72:0] VAR3
);
assign VAR3[7:0] = VAR1[7:0];
assign VAR3[8] = VAR2[0];
assign VAR3[16:9] = VAR1[15:8];
assign VAR3[17] = VAR2[1];
assign VAR3[25:18] = VAR1[23:16];
assign VAR3[26] = VAR2[2];
assign VAR3[34:27] = VAR1[31:24];
assign VAR3[35] = V... | mit |
CospanDesign/nysa-sata | rtl/link/cont_controller.v | 15,242 | module MODULE1 (
input rst, input clk,
input VAR55,
input VAR32,
input VAR53,
input [31:0] VAR27,
input VAR62,
output [31:0] VAR25,
output VAR73,
input [31:0] VAR43,
input [3:0] VAR20,
output VAR50,
output VAR38,
output VAR60,
output VAR4,
output VAR22,
output VAR10,
output VAR70,
output VAR12,
output VAR5,
output VAR7... | mit |
varunnagpaal/Digital-Hardware-Modelling | tutorials/xilinx/hls/ug871-design-files/Using_IP_with_Zynq/lab1/hls_macc/vhls_prj/solution1/impl/ip/hdl/verilog/hls_macc_mul_32s_bkb.v | 1,628 | module MODULE2(clk, VAR19, VAR15, VAR13, VAR18);
input clk;
input VAR19;
input[32 - 1 : 0] VAR15;
input[32 - 1 : 0] VAR13;
output[32 - 1 : 0] VAR18;
reg signed [32 - 1 : 0] VAR1;
reg signed [32 - 1 : 0] VAR17;
wire signed [32 - 1 : 0] VAR4;
reg signed [32 - 1 : 0] VAR20;
reg signed [32 - 1 : 0] VAR16;
reg signed [32 - ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_1.functional.pp.v | 1,864 | module MODULE1( VAR26, VAR8, VAR25, VAR23, VAR18, VAR14, VAR22, VAR9, VAR15 );
input VAR18, VAR14, VAR22, VAR25, VAR8, VAR26;
inout VAR9, VAR15;
output VAR23;
wire VAR10;
not VAR19( VAR10, VAR18 );
wire VAR13;
not VAR20( VAR13, VAR14 );
wire VAR1;
not VAR21( VAR1, VAR22 );
wire VAR3;
and VAR6( VAR3, VAR10, VAR13, VAR1 ... | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_cx4/dac_buf.v | 9,139 | module MODULE1 (
VAR23,
VAR56,
VAR53,
VAR55,
VAR52,
VAR47);
input VAR23;
input [7:0] VAR56;
input [8:0] VAR53;
input [10:0] VAR55;
input VAR52;
output [31:0] VAR47;
tri1 VAR23;
tri0 VAR52;
wire [31:0] VAR12;
wire [31:0] VAR47 = VAR12[31:0];
VAR61 VAR34 (
.VAR18 (VAR55),
.VAR57 (VAR53),
.VAR15 (VAR23),
.VAR4 (VAR56),
.V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21bai/sky130_fd_sc_lp__o21bai.pp.blackbox.v | 1,398 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR1 ,
VAR6,
VAR4,
VAR7,
VAR5 ,
VAR8
);
output VAR3 ;
input VAR2 ;
input VAR1 ;
input VAR6;
input VAR4;
input VAR7;
input VAR5 ;
input VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlclkp/sky130_fd_sc_ms__dlclkp.behavioral.v | 1,903 | module MODULE1 (
VAR2,
VAR17,
VAR16
);
output VAR2;
input VAR17;
input VAR16 ;
supply1 VAR14;
supply0 VAR15;
supply1 VAR8 ;
supply0 VAR4 ;
wire VAR7 ;
wire VAR13 ;
wire VAR9 ;
wire VAR10;
reg VAR11 ;
wire VAR6 ;
not VAR5 (VAR13 , VAR9 );
VAR3 VAR12 (VAR7 , VAR10, VAR13, VAR11, VAR14, VAR15);
and VAR1 (VAR2 , VAR7, VAR9... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_1.behavioral.v | 2,557 | module MODULE1( VAR4, VAR3, VAR7, VAR2 );
input VAR3, VAR4, VAR7;
output VAR2;
VAR5 VAR1(.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR2(VAR2));
VAR5 VAR6(.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR2(VAR2)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.functional.v | 1,919 | module MODULE1 (
VAR14 ,
VAR4 ,
VAR9 ,
VAR15 ,
VAR7 ,
VAR2
);
output VAR14 ;
input VAR4 ;
input VAR9 ;
input VAR15 ;
input VAR7 ;
input VAR2;
wire VAR16 ;
wire VAR11 ;
wire VAR13;
not VAR1 (VAR11 , VAR2 );
VAR6 VAR5 (VAR13, VAR9, VAR15, VAR7 );
VAR12 VAR3 VAR10 (VAR16 , VAR13, VAR4, VAR11);
buf VAR8 (VAR14 , VAR16 );
e... | apache-2.0 |
P3Stor/P3Stor | pcie/app/v6_pci_exp_128b_app.v | 23,708 | module MODULE1
(
input VAR114,
input VAR242,
input VAR138,
input [5:0] VAR282,
input VAR190,
input VAR199,
input VAR201,
output [127:0] VAR28,
output [1:0] VAR68,
output VAR30,
output VAR159,
output VAR169,
output VAR106,
output VAR132,
output VAR83,
output VAR229,
input [127:0] VAR53,
input [1:0] VAR168,
input VAR144,... | gpl-2.0 |
ptracton/pmodacl2 | soc/xilinx/LUT6_2.v | 5,649 | module MODULE1 (VAR28, VAR16, VAR20, VAR3, VAR5, VAR13, VAR23, VAR31);
parameter VAR11 = 64'h0000000000000000;
parameter VAR1 = "VAR8";
input VAR20, VAR3, VAR5, VAR13, VAR23, VAR31;
output VAR28, VAR16;
reg [63:0] VAR21 = VAR11;
reg [31:0] VAR14, VAR6;
reg VAR18, VAR29, VAR9;
reg VAR19, VAR26;
wire VAR17, VAR33, VAR22,... | mit |
eclay42/cs220-galois-aig-rewriting | adder16_strash.v | 6,203 | module MODULE1 (
VAR146, VAR50, VAR158, VAR166, VAR192, VAR151, VAR41, VAR106, VAR179, VAR71, VAR83, VAR28, VAR156, VAR88, VAR32, VAR36,
b0, b1, VAR187, VAR157, VAR15, VAR84, VAR11, VAR100, VAR82, VAR22, b10, b11, VAR163, VAR120, VAR184, VAR177,
VAR90, VAR153, VAR78, VAR74, VAR16, VAR59, VAR97, VAR122, VAR3, VAR64, VAR... | mit |
sittner/lcnc-mdsio | vhdl/source/can/can_registers.v | 37,372 | module MODULE1
(
clk,
rst,
VAR58,
VAR112,
addr,
VAR124,
VAR1,
VAR24,
VAR63,
VAR144,
VAR189,
VAR146,
VAR85,
VAR101,
VAR70,
VAR59,
VAR51,
VAR69,
VAR134,
VAR57,
VAR81,
VAR9,
VAR61,
VAR121,
VAR156,
VAR79,
VAR41,
VAR34,
VAR138,
VAR37,
VAR113,
VAR116,
VAR55,
VAR94,
VAR148,
VAR11,
VAR110,
VAR73,
VAR147,
VAR185,
VAR184,
VAR31,... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_20.behavioral.v | 1,113 | module MODULE1( VAR1, VAR4 );
input VAR1;
output VAR4;
VAR5 VAR3(.VAR1(VAR1),.VAR4(VAR4));
VAR5 VAR2(.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
freecores/tiny_tate_bilinear_pairing | group_size_is_151_bits/rtl/const.v | 1,353 | module MODULE1 (clk, addr, out, VAR1);
input clk;
input [5:0] addr;
output reg [197:0] out;
output reg VAR1;
always @ (posedge clk)
begin
VAR1 <= 1;
case (addr)
1: out <= 198'd0;
2: out <= 198'd1;
4: out <= {6'b000101, 192'd0};
8: out <= {6'b001001, 192'd0};
16: out <= {6'b010101, 192'd0};
default:
begin out <= 198'd0;... | apache-2.0 |
545/Atari7800 | core/ag_6502/trunk/fighter/ag_main.v | 4,429 | module MODULE1(input VAR2, input[10:0] VAR4, input VAR3, input VAR8, output[7:0] VAR5, input[7:0] VAR9);
reg[7:0] VAR6[0:2047];
reg[7:0] VAR1;
assign VAR5 = VAR3? VAR1: 8'VAR7; | gpl-2.0 |
UCLONG/NetEmulation | onehot_to_bin.v | 1,866 | module MODULE1 (VAR10,VAR9);
parameter VAR3 = 16;
parameter VAR6 = VAR5(VAR3-1);
input [VAR3-1:0] VAR10;
output [VAR6-1:0] VAR9;
genvar VAR8,VAR7;
generate
for (VAR7=0; VAR7<VAR6; VAR7=VAR7+1)
begin : VAR4
wire [VAR3-1:0] VAR1;
for (VAR8=0; VAR8<VAR3; VAR8=VAR8+1)
begin : VAR2
assign VAR1[VAR8] = VAR8[VAR7];
end
assign... | gpl-3.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/source/rtl/KOA_c.v | 9,996 | module MODULE1
(
input wire [VAR26-1:0] VAR1,
input wire [VAR26-1:0] VAR18,
output wire [2*VAR26-1:0] VAR20
);
wire [VAR26/2+1:0] VAR14;
wire [VAR26/2+1:0] VAR24;
wire [2*(VAR26/2)-1:0] VAR10;
wire [2*(VAR26/2+1)-1:0] VAR25;
wire [2*(VAR26/2+2)-1:0] VAR17;
wire [2*(VAR26/2+2)-1:0] VAR12;
wire [2*(VAR26/2+2)-1:0] VAR31;... | gpl-3.0 |
tmatsuya/milkymist-ml401 | boards/gen_capabilities.v | 2,327 | module MODULE1(
output [31:0] VAR3
);
wire VAR10;
wire VAR12;
wire VAR5;
wire VAR9;
wire VAR7;
wire VAR13;
wire VAR14;
wire VAR8;
wire VAR17;
wire VAR2;
wire VAR16;
wire VAR15;
wire VAR4;
wire VAR6;
wire VAR1;
assign VAR3 = {
17'd0,
VAR1,
VAR6,
VAR4,
VAR15,
VAR16,
VAR2,
VAR17,
VAR8,
VAR14,
VAR13,
VAR7,
VAR9,
VAR5,
VAR1... | lgpl-3.0 |
kyzhai/NUNY | src/hardware/rain_bb.v | 4,968 | module MODULE1 (
address,
VAR1,
VAR2);
input [11:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
chaohu/Daily-Learning | Verilog/lab2/lab2_2/lab2_2_1/lab2_2_1.srcs/sources_1/new/lab1_4_2.v | 1,052 | module MODULE1(
input [3:0] VAR1,
output [6:0] VAR2
);
assign VAR2[6] = (VAR1[2]&(~VAR1[1])&(~VAR1[0]))|((~VAR1[3])&(~VAR1[2])&(~VAR1[1])&VAR1[0]);
assign VAR2[5] = (VAR1[2]&(~VAR1[1])&VAR1[0])|(VAR1[2]&VAR1[1]&(~VAR1[0]));
assign VAR2[4] = (~VAR1[3])&(~VAR1[2])&VAR1[1]&(~VAR1[0]);
assign VAR2[3] = (VAR1[2]&(~VAR1[1])&... | mit |
jcrono/sd-host | src/register_set/register_block.v | 5,747 | module MODULE1(
input logic clk,
input logic reset,
input logic VAR43,
input logic [1:0] req,
input logic [7:0] address,
input logic [31:0] VAR3,
output logic ack,
output logic [31:0] VAR44,
output logic [15:0] VAR42,
output logic [15:0] VAR34,
output logic [15:0] VAR4,
output logic [15:0] VAR32,
output logic [15:0] VA... | gpl-3.0 |
timtian090/Playground | UVM/UVMPlayground/Lab4/Lab4-Project/TF_BCD_Segment_Decoder.v | 5,843 | module MODULE1();
localparam VAR2 = 500000000; localparam VAR1 = ((1.0 / VAR2) * 1000000000.0) / 2.0;
reg VAR3;
begin
begin
begin
begin
begin
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/probe_p/sky130_fd_sc_hvl__probe_p.blackbox.v | 1,247 | module MODULE1 (
VAR2,
VAR5
);
output VAR2;
input VAR5;
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
joaocarlos/udlx-verilog | rtl/data_memory_controll/data_memory_controll.v | 14,798 | module MODULE1
parameter VAR13 = 32,
parameter VAR36 = 32,
parameter VAR25 = 32,
parameter VAR20 = 20,
parameter VAR7 = 4,
parameter VAR29 = 2,
parameter VAR2 = 25
)
(
input clk,
input VAR14,
input VAR44,
input VAR43,
input [VAR36-1:0] VAR51,
output reg [VAR13-1:0] VAR69,
input [VAR13-1:0] VAR56,
output reg VAR24,
outp... | lgpl-3.0 |
mdsalman729/flexpret_project | src/uart/ShiftRegister.v | 5,896 | module MODULE1(VAR14, VAR7, VAR10, VAR8, VAR2, VAR17, VAR22, VAR3);
parameter VAR20 = 32, VAR9 = 1, VAR6 = 0,
VAR4 = {VAR20{1'VAR19}},
VAR12 = 0;
input VAR14, VAR7, VAR10, VAR8;
input [VAR20-1:0] VAR2;
input [VAR9-1:0] VAR17;
output [VAR20-1:0] VAR22;
output [VAR9-1:0] VAR3;
assign VAR3 = VAR6 ? VAR22[VAR9-1:0] : VAR22... | bsd-3-clause |
aabdelfattah/alhaitham-hardware | Sdram_Control/command.v | 18,262 | module MODULE1(
VAR27,
VAR26,
VAR39,
VAR46,
VAR28,
VAR15,
VAR36,
VAR44,
VAR43,
VAR10,
VAR14,
VAR42,
VAR53,
VAR2,
VAR6,
VAR58,
VAR34,
VAR19,
VAR37,
VAR38,
VAR35,
VAR21,
VAR40
);
input VAR27; input VAR26; input [VAR55-1:0] VAR39; input VAR46; input VAR28; input VAR15; input VAR36; input VAR44; input VAR43; input VAR10; i... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/or1200/or1200_spram_512x20.v | 8,768 | module MODULE1(
VAR15, VAR18, VAR40,
clk, rst, VAR21, VAR11, VAR32, addr, VAR30, VAR51
);
parameter VAR10 = 9;
parameter VAR27 = 20;
input VAR15;
input [VAR43 - 1:0] VAR40;
output VAR18;
input clk; input rst; input VAR21; input VAR11; input VAR32; input [VAR10-1:0] addr; input [VAR27-1:0] VAR30; output [VAR27-1:0] VAR5... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2o/sky130_fd_sc_ms__a2bb2o.behavioral.pp.v | 2,231 | module MODULE1 (
VAR7 ,
VAR15,
VAR19,
VAR14 ,
VAR3 ,
VAR4,
VAR11,
VAR12 ,
VAR2
);
output VAR7 ;
input VAR15;
input VAR19;
input VAR14 ;
input VAR3 ;
input VAR4;
input VAR11;
input VAR12 ;
input VAR2 ;
wire VAR1 ;
wire VAR9 ;
wire VAR13 ;
wire VAR17;
and VAR16 (VAR1 , VAR14, VAR3 );
nor VAR18 (VAR9 , VAR15, VAR19 );
or ... | apache-2.0 |
siavooshpayandehazad/property_evaluation | DUTs/Y86_seq.v | 2,851 | module MODULE1(
input clk,
input rst,
output [31:0] VAR40,
input [31:0] VAR20,
output [31:0] VAR34,
output VAR29, VAR11,
output [7:0] VAR42);
reg [5:1] VAR41;
wire [4:0] VAR25={ VAR41[4:1], VAR41[5] };
always @(posedge clk) begin
if(rst)
VAR41<='b10000;
end
else
VAR41<={ VAR25[4], VAR25[3], VAR25[2], VAR25[1], VAR25[0]... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_4.functional.v | 3,002 | module MODULE1( VAR8, VAR32, VAR34, VAR7, VAR23, VAR14, VAR22 );
input VAR14, VAR22, VAR7, VAR23, VAR32, VAR34;
output VAR8;
wire VAR19;
not VAR31( VAR19, VAR14 );
wire VAR17;
not VAR12( VAR17, VAR7 );
wire VAR18;
not VAR4( VAR18, VAR32 );
wire VAR1;
and VAR25( VAR1, VAR19, VAR17, VAR18 );
wire VAR15;
not VAR21( VAR15,... | apache-2.0 |
jas0n1ee/THU-DSD | FB/flappy_bird.v | 14,966 | module MODULE2(
VAR150, VAR12, VAR48, VAR73, VAR64, VAR134, VAR151, VAR47, VAR87, VAR85, VAR142, VAR141, VAR147, VAR38, VAR60, VAR90, VAR145, VAR68, VAR28, VAR4, VAR37, VAR109, VAR137, VAR32, VAR82, VAR105, VAR106, VAR5, VAR139, VAR108, VAR123, VAR130, VAR25, VAR74, VAR118, VAR122, VAR129, VAR146, VAR112, VAR133, VAR13... | mit |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/background_painter.v | 4,017 | module MODULE1(
input wire [9:0] VAR12,
input wire [8:0] VAR4,
input wire [11:0] VAR10,
input wire [32:0] VAR8,
input wire [4:0] VAR18,
output reg [2:0] VAR2,
output reg [3:0] VAR14,
output reg [3:0] VAR15,
output reg [1:0] VAR17,
output reg [2:0] VAR13,
output reg [7:0] VAR3
);
parameter [7:0]VAR1 = 8'b11111111;
param... | mit |
SymbiFlow/fpga-tool-perf | third_party/daisho-usb3/usb3_scramble.v | 4,369 | module MODULE1 (
input wire VAR13,
input wire VAR37,
input wire VAR21,
input wire enable,
input wire VAR23,
input wire VAR32,
input wire [3:0] VAR30,
input wire [31:0] VAR31,
input wire VAR22,
output reg VAR17,
output reg [3:0] VAR36,
output reg [31:0] VAR24,
output reg VAR25
);
reg VAR6;
reg VAR12;
wire VAR2 = { (VAR1... | isc |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_fp_convert_to_half.v | 6,688 | module MODULE1(VAR18, VAR4, VAR16, VAR17, VAR10, VAR6, VAR13, VAR5, enable);
parameter VAR24 = 1;
parameter VAR9 = 0;
input VAR18, VAR4;
input [31:0] VAR16;
output [15:0] VAR17;
input VAR10, VAR13, enable;
output VAR6, VAR5;
wire VAR22;
reg VAR1;
wire VAR19;
wire VAR2;
reg VAR25;
wire VAR15;
reg [4:0] VAR21;
reg [13:0]... | mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_auto_pc_3/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v | 3,925 | module MODULE1 #
(
parameter integer VAR3 = 4,
parameter integer VAR10 = 32
)
(
input wire clk ,
input wire reset ,
input wire [VAR3-1:0] VAR16 ,
input wire [VAR10-1:0] VAR1 ,
input wire [7:0] VAR7 ,
input wire [2:0] VAR20 ,
input wire [1:0] VAR25 ,
input wire VAR14 ,
output wire VAR12 ,
output wire VAR27 ,
output wire... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfrbp/sky130_fd_sc_hvl__sdfrbp.pp.symbol.v | 1,549 | module MODULE1 (
input VAR9 ,
output VAR11 ,
output VAR7 ,
input VAR10,
input VAR4 ,
input VAR3 ,
input VAR8 ,
input VAR1 ,
input VAR5 ,
input VAR2 ,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor2/sky130_fd_sc_lp__xnor2_2.v | 2,132 | module MODULE2 (
VAR3 ,
VAR1 ,
VAR8 ,
VAR7,
VAR2,
VAR9 ,
VAR5
);
output VAR3 ;
input VAR1 ;
input VAR8 ;
input VAR7;
input VAR2;
input VAR9 ;
input VAR5 ;
VAR6 VAR4 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR3,
VAR1,
VAR8
);
output VAR3;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and2b/sky130_fd_sc_hs__and2b.symbol.v | 1,255 | module MODULE1 (
input VAR5,
input VAR2 ,
output VAR4
);
supply1 VAR3;
supply0 VAR1;
endmodule | apache-2.0 |
samueltardieu/rforth1 | spi-interface/shix/shix-spi.v | 18,499 | module MODULE1 (VAR4, reset, VAR19, VAR36, VAR25,
VAR29, VAR8, VAR26, VAR34,
VAR31, VAR72, VAR13, VAR106,
VAR97, VAR35, VAR78, VAR20,
VAR57, VAR71, VAR111, VAR74,
VAR23, VAR66, VAR100, VAR65,
VAR73, VAR62, VAR7, VAR105,
VAR101, VAR58, VAR70, VAR51,
VAR91, VAR11, VAR9, VAR89,
VAR99, VAR77, enable, irq, VAR110, VAR15,
VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4b/sky130_fd_sc_lp__or4b_lp.v | 2,299 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR9 ,
VAR4 ,
VAR11 ,
VAR6,
VAR3,
VAR10 ,
VAR2
);
output VAR5 ;
input VAR1 ;
input VAR9 ;
input VAR4 ;
input VAR11 ;
input VAR6;
input VAR3;
input VAR10 ;
input VAR2 ;
VAR8 VAR7 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR10(VAR10),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbp/sky130_fd_sc_ms__dlxbp.behavioral.v | 1,963 | module MODULE1 (
VAR4 ,
VAR11 ,
VAR9 ,
VAR2
);
output VAR4 ;
output VAR11 ;
input VAR9 ;
input VAR2;
supply1 VAR12;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR16 ;
wire VAR17 ;
wire VAR6;
wire VAR8 ;
reg VAR15 ;
wire VAR10 ;
VAR14 VAR13 (VAR17 , VAR8, VAR6, VAR15, VAR12, VAR3);
buf VAR1 (VAR4 , VAR17 );
not VAR5 (VAR11 , ... | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/SyncResetA.v | 2,811 | module MODULE1 (
VAR3,
VAR9,
VAR6
);
parameter VAR2 = 1 ;
input VAR9 ;
input VAR3 ;
output VAR6 ;
reg [VAR2:0] VAR8 ;
wire [VAR2+1:0] VAR4 = {VAR8, ~ VAR5} ;
assign VAR6 = VAR8[VAR2] ;
always @( posedge VAR9 or VAR1 VAR3 )
begin
if (VAR3 == VAR5)
begin
VAR8 <= VAR7 {VAR2+1 {VAR5}} ;
end
else
begin
VAR8 <= VAR7 VAR4[VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4b/sky130_fd_sc_hd__nor4b_2.v | 2,302 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR10 ,
VAR6 ,
VAR11 ,
VAR7,
VAR3,
VAR2 ,
VAR1
);
output VAR5 ;
input VAR4 ;
input VAR10 ;
input VAR6 ;
input VAR11 ;
input VAR7;
input VAR3;
input VAR2 ;
input VAR1 ;
VAR9 VAR8 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR2(VAR2),
.... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_1.behavioral.v | 1,098 | module MODULE1( VAR1, VAR3 );
input VAR1;
output VAR3;
VAR2 VAR5(.VAR1(VAR1),.VAR3(VAR3));
VAR2 VAR4(.VAR1(VAR1),.VAR3(VAR3)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor3/sky130_fd_sc_ms__xnor3_1.v | 2,184 | module MODULE2 (
VAR3 ,
VAR1 ,
VAR2 ,
VAR5 ,
VAR8,
VAR4,
VAR9 ,
VAR6
);
output VAR3 ;
input VAR1 ;
input VAR2 ;
input VAR5 ;
input VAR8;
input VAR4;
input VAR9 ;
input VAR6 ;
VAR7 VAR10 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE2 (... | apache-2.0 |
borti4938/n64rgb | generalRGBmod/firmware/rtl/n64_vdemux.v | 3,579 | module MODULE1(
VAR18,
VAR9,
VAR21,
VAR2,
VAR22,
VAR10
);
input VAR18;
input VAR9;
input [VAR23-1:0] VAR21;
input [ 4:0] VAR2;
output reg [VAR4] VAR22; output reg [VAR4] VAR10;
wire [1:0] VAR3 = VAR2[4:3];
wire VAR15 = VAR2[ 2];
wire VAR5 = VAR2[ 1];
wire VAR14 = VAR2[ 0];
reg VAR16 = 1'b0;
reg VAR6 = 1'b0;
reg VAR13 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtp/sky130_fd_sc_ls__dlrtp_4.v | 2,362 | module MODULE2 (
VAR8 ,
VAR5,
VAR9 ,
VAR10 ,
VAR4 ,
VAR7 ,
VAR2 ,
VAR1
);
output VAR8 ;
input VAR5;
input VAR9 ;
input VAR10 ;
input VAR4 ;
input VAR7 ;
input VAR2 ;
input VAR1 ;
VAR6 VAR3 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODU... | apache-2.0 |
xarteaga/7A35T_Arty_RemoteLedControl | fpga/hw_system/ip_repo/massive_pwm_1.0/hdl/massive_pwm_v1_0_S00_AXI.v | 23,529 | module MODULE1 #
(
parameter integer VAR15 = 4,
parameter integer VAR69 = 32,
parameter integer VAR62 = 6
)
(
input wire clk,
input wire rst,
output wire [3*VAR15-1 : 0] VAR34,
input wire VAR33,
input wire VAR22,
input wire [VAR62-1 : 0] VAR55,
input wire [2 : 0] VAR66,
input wire VAR5,
output wire VAR8,
input wire [VA... | mit |
myriadrf/A2300 | hdl/wca/hal/WcaUsbFx3IF.v | 8,258 | module MODULE1(
input VAR47, input reset,
input VAR44, input VAR28, input VAR53, input VAR31, output VAR25, output VAR45, output [VAR30-1:0] addr, output VAR52, output VAR8, output VAR3, output clk, inout [31:0] VAR35, inout [3:0] VAR16,
inout [31:0] VAR40, input [(VAR30+1):0] VAR2, output [6:0] VAR5
);
parameter VAR30... | gpl-2.0 |
olajep/oh | src/adi/hdl/library/axi_dmac/axi_dmac_regmap.v | 8,829 | module MODULE1 #(
parameter VAR63 = 0,
parameter VAR88 = 0,
parameter VAR23 = 1,
parameter VAR37 = 1,
parameter VAR89 = 7,
parameter VAR61 = 32,
parameter VAR78 = 24,
parameter VAR56 = 3,
parameter VAR1 = 0,
parameter VAR70 = 1,
parameter VAR34 = 1,
parameter VAR79 = 0,
parameter VAR15 = 0
) (
input VAR42,
input VAR51,... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_hps_0.v | 7,235 | module MODULE1 #(
parameter VAR42 = 0,
parameter VAR52 = 1
) (
output wire VAR19, input wire VAR51, output wire [11:0] VAR27, output wire [29:0] VAR2, output wire [3:0] VAR46, output wire [2:0] VAR33, output wire [1:0] VAR4, output wire [1:0] VAR31, output wire [3:0] VAR24, output wire [2:0] VAR26, output wire VAR38, i... | gpl-3.0 |
kulp/tenyr | hw/verilog/ram.v | 1,345 | module MODULE1(
VAR15, VAR27, VAR25, VAR21, VAR7, VAR17, VAR26, VAR23,
VAR11, VAR5, VAR20, VAR19, VAR9, VAR2
);
parameter VAR3 = 0;
parameter VAR8 = 0;
parameter VAR1 = 0;
parameter VAR12 = 0;
parameter VAR4 = "default.VAR13";
parameter VAR22 = 32; parameter VAR10 = 10; parameter VAR6 = 32;
parameter VAR18 = 1 << VAR10... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50.pp.blackbox.v | 1,309 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR2,
VAR6,
VAR5 ,
VAR1
);
output VAR3 ;
input VAR4 ;
input VAR2;
input VAR6;
input VAR5 ;
input VAR1 ;
endmodule | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_gmultp2_32x32.v | 5,043 | module MODULE1 ( VAR7, VAR5, VAR1, VAR4, VAR2 );
input [VAR10-1:0] VAR7;
input [VAR10-1:0] VAR5;
input VAR1;
input VAR4;
output [VAR6-1:0] VAR2;
reg [VAR6-1:0] VAR3;
reg [VAR6-1:0] VAR9;
integer VAR8;
integer VAR11;
always @(VAR7)
VAR8 <= VAR7;
always @(VAR5)
VAR11 <= VAR5;
always @(posedge VAR1 or posedge VAR4)
if (VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a31o/sky130_fd_sc_ms__a31o.behavioral.v | 1,530 | module MODULE1 (
VAR7 ,
VAR9,
VAR12,
VAR4,
VAR11
);
output VAR7 ;
input VAR9;
input VAR12;
input VAR4;
input VAR11;
supply1 VAR10;
supply0 VAR3;
supply1 VAR13 ;
supply0 VAR5 ;
wire VAR1 ;
wire VAR6;
and VAR2 (VAR1 , VAR4, VAR9, VAR12 );
or VAR14 (VAR6, VAR1, VAR11 );
buf VAR8 (VAR7 , VAR6 );
endmodule | apache-2.0 |
omicronns/studies-sys-rek | de1-soc-template/v/SEG7_LUT_6.v | 2,245 | module MODULE1 ( VAR14,VAR5,VAR13,VAR6,VAR4,VAR9,VAR10 );
input [23:0] VAR10;
output [6:0] VAR14,VAR5,VAR13,VAR6,VAR4,VAR9;
VAR11 VAR8 ( VAR14,VAR10[3:0] );
VAR11 VAR3 ( VAR5,VAR10[7:4] );
VAR11 VAR2 ( VAR13,VAR10[11:8] );
VAR11 VAR1 ( VAR6,VAR10[15:12] );
VAR11 VAR12 ( VAR4,VAR10[19:16] );
VAR11 VAR7 ( VAR9,VAR10[23:2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221a/sky130_fd_sc_hs__o221a.functional.pp.v | 2,100 | module MODULE1 (
VAR18,
VAR9,
VAR2 ,
VAR10 ,
VAR16 ,
VAR17 ,
VAR13 ,
VAR14
);
input VAR18;
input VAR9;
output VAR2 ;
input VAR10 ;
input VAR16 ;
input VAR17 ;
input VAR13 ;
input VAR14 ;
wire VAR13 VAR6 ;
wire VAR13 VAR3 ;
wire VAR12 ;
wire VAR5;
or VAR1 (VAR6 , VAR13, VAR17 );
or VAR4 (VAR3 , VAR16, VAR10 );
and VAR15... | apache-2.0 |
cr88192/bgbtech_bjx1core | smalltst/compdec/ModFbMem.v | 3,458 | module MODULE1(VAR24, reset,
VAR13, VAR2, VAR6,
VAR7, VAR4, VAR16, VAR18, VAR11);
input VAR24;
input reset;
input[13:0] VAR13;
output[31:0] VAR2;
output[31:0] VAR6;
input[39:0] VAR7;
inout[31:0] VAR4;
input VAR16;
input VAR18;
output VAR11;
reg VAR14; reg[31:0] VAR9; wire VAR10;
assign VAR11 = (VAR16 && VAR10) ? VAR14 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311ai/sky130_fd_sc_hs__o311ai.blackbox.v | 1,345 | module MODULE1 (
VAR5 ,
VAR6,
VAR2,
VAR4,
VAR3,
VAR8
);
output VAR5 ;
input VAR6;
input VAR2;
input VAR4;
input VAR3;
input VAR8;
supply1 VAR7;
supply0 VAR1;
endmodule | apache-2.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/nios_system_rs232_0.v | 9,887 | module MODULE1 (
clk,
reset,
address,
VAR13,
VAR36,
read,
write,
VAR6,
VAR24,
irq,
VAR30,
VAR29
);
parameter VAR8 = 9; parameter VAR16 = 434;
parameter VAR33 = 217;
parameter VAR26 = 10; parameter VAR12 = 8; parameter VAR19 = 1'b0;
input clk;
input reset;
input address;
input VAR13;
input [ 3: 0] VAR36;
input read;
inp... | mit |
asicguy/gplgpu | hdl/math/log2_table.v | 4,867 | module MODULE1
(
input clk, input VAR2, input [31:0] VAR9,
output [9:0] VAR17
);
reg [3:0] VAR15;
reg [5:0] VAR3;
wire VAR5;
wire [9:0] VAR7;
assign VAR7 = VAR9[17:8];
assign VAR5 = |VAR9[31:18];
always @(posedge clk) begin
casex ({VAR5, VAR7})
11'VAR21, 11'VAR10: begin if(VAR2 && VAR7[9]) begin
VAR15 <= 4'h9;
VAR3 <= ... | gpl-3.0 |
jcrono/sd-host | src/dat/DAT.v | 3,050 | module MODULE1(
input logic VAR15, input logic VAR9, input logic VAR44, input logic VAR25,
input logic reset,
input logic[3:0] VAR27,
input logic VAR10,
input logic [15:0] timeout ,
input logic VAR42,
input logic VAR19,
input logic [31:0] VAR39, input logic VAR11, output wire VAR17, output wire VAR21, output wire VAR46... | gpl-3.0 |
h-j-13/MyNote | Programming language/Verilog/sync_FIFO/Source_Code/FIFO_1.v | 2,386 | module MODULE1(VAR5,reset,read,write,VAR2,VAR1,VAR7,VAR6);
input VAR5,reset,read,write; input [15:0]VAR2; output[15:0]VAR1; output VAR7,VAR6;
reg [15:0]VAR1; reg [15:0]VAR8[15:0]; reg [3:0]VAR4,VAR3,counter;
wire VAR7,VAR6;
always@(posedge VAR5) if(reset) begin
VAR4 = 0;
VAR3 = 0;
counter = 0;
VAR1 = 0;
end
else
case({... | gpl-3.0 |
fpgasystems/Centaur | rtl/fthread_shell/fpga_setup.v | 7,927 | module MODULE1 (
input wire clk,
input wire VAR1,
output reg VAR22,
input wire VAR30,
input wire [13:0] VAR32,
input wire [31:0] VAR35,
input wire VAR52,
output reg VAR2,
output reg [VAR48-1:0] VAR24,
output reg [31:0] VAR23,
output reg [511:0] VAR29,
input wire [1:0] VAR40,
output wire VAR16,
output wire [31:0] VAR46,... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_ILC/interrupt_latency_counter_171/synth/state_machine_counter.v | 3,447 | module MODULE1 #(
parameter VAR8 = 1'b1
)(
clk,
VAR5,
VAR12,
VAR11,
VAR3,
VAR7,
enable,
VAR1,
VAR9,
VAR6
);
input wire clk;
input wire VAR5;
input wire VAR12;
input wire VAR11;
input wire VAR3;
input wire VAR7;
output reg enable;
output reg VAR9;
output reg VAR6;
output reg VAR1;
reg [1:0] state ;
reg [1:0] VAR4 ;
loca... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn.functional.pp.v | 2,366 | module MODULE1 (
VAR22 ,
VAR6 ,
VAR18 ,
VAR11 ,
VAR8 ,
VAR15,
VAR12,
VAR4 ,
VAR9 ,
VAR5 ,
VAR10 ,
VAR16
);
output VAR22 ;
input VAR6 ;
input VAR18 ;
input VAR11 ;
input VAR8 ;
input VAR15;
input VAR12;
input VAR4 ;
input VAR9 ;
input VAR5 ;
input VAR10 ;
input VAR16 ;
wire VAR7 ;
wire VAR21 ;
wire VAR14;
not VAR3 (VAR2... | apache-2.0 |
azonenberg/antikernel-ipcores | dataflow/SingleClockShiftRegisterFifo.v | 9,409 | module MODULE1(
clk,
wr, din,
rd, dout,
VAR5, VAR4, VAR7, VAR3, VAR8, VAR12, reset
, VAR11
);
parameter VAR6 = 32;
parameter VAR1 = 32;
localparam VAR9 = VAR2(VAR1);
parameter VAR10 = 0;
parameter VAR13 = 1;
input wire clk;
input wire wr;
input wire[VAR6-1:0] din;
input wire rd;
output wire[VAR6-1:0] dout;
output reg V... | bsd-3-clause |
pdear/verilib | components/src/components-ff.v | 2,219 | module MODULE2 #(
parameter VAR1 = 1,
parameter VAR4 = 0
) (
input clk,
input rst,
input en,
input [VAR1-1:0] VAR2,
output [VAR1-1:0] VAR5
);
reg [VAR1-1:0] VAR3 = VAR4;
always @ (posedge clk) begin
if (rst == 1'b1)
VAR3 <= VAR4;
end
else if (en == 1'b1)
VAR3 <= VAR2;
end
assign VAR5 = VAR3;
endmodule
module MODULE3 #(... | lgpl-3.0 |
olofk/oh | elink/hdl/etx_core.v | 11,266 | module MODULE1(
VAR52, VAR36, VAR33, VAR77, VAR40, VAR31,
VAR76, VAR26,
reset, clk, VAR10, VAR77, VAR31, VAR67,
VAR59, VAR50, VAR70, VAR32, VAR1,
VAR28
);
parameter VAR13 = 32;
parameter VAR71 = 32;
parameter VAR65 = 104;
parameter VAR8 = 6;
parameter VAR19 = 12'h000;
input reset;
input clk;
output VAR52;
output VAR36;... | gpl-3.0 |
csail-csg/recycle-bsv-lib | src/v/EHRU_3.v | 2,260 | module MODULE1 (
VAR4,
VAR5,
VAR1,
VAR6,
VAR15,
VAR3,
VAR8,
VAR16,
VAR12,
VAR7
);
parameter VAR13 = 1;
parameter VAR14 = 0;
input VAR4;
output [VAR13-1:0] VAR5;
input [VAR13-1:0] VAR1;
input VAR6;
output [VAR13-1:0] VAR15;
input [VAR13-1:0] VAR3;
input VAR8;
output [VAR13-1:0] VAR16;
input [VAR13-1:0] VAR12;
input VAR7... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s18/sky130_fd_sc_hd__clkdlybuf4s18.functional.v | 1,343 | module MODULE1 (
VAR2,
VAR4
);
output VAR2;
input VAR4;
wire VAR1;
buf VAR3 (VAR1, VAR4 );
buf VAR5 (VAR2 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probec_p/sky130_fd_sc_hd__probec_p.functional.v | 1,269 | module MODULE1 (
VAR4,
VAR1
);
output VAR4;
input VAR1;
wire VAR3;
buf VAR5 (VAR3, VAR1 );
buf VAR2 (VAR4 , VAR3 );
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_071.v | 1,522 | module MODULE1 (
VAR10,
VAR3
);
input [31:0] VAR10;
output [31:0]
VAR3;
wire [31:0]
VAR8,
VAR14,
VAR5,
VAR9,
VAR2,
VAR7,
VAR13,
VAR6,
VAR1;
assign VAR8 = VAR10;
assign VAR1 = VAR6 << 2;
assign VAR6 = VAR7 - VAR13;
assign VAR9 = VAR8 << 12;
assign VAR2 = VAR8 + VAR9;
assign VAR7 = VAR2 + VAR14;
assign VAR13 = VAR5 << 3;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2b/sky130_fd_sc_hs__nand2b.symbol.v | 1,261 | module MODULE1 (
input VAR1,
input VAR2 ,
output VAR4
);
supply1 VAR5;
supply0 VAR3;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_databuf_pa.v | 2,030 | module MODULE1(
VAR3, VAR2,
VAR1, VAR4
);
output [123:0]VAR3;
output VAR2;
input [123:0]VAR1;
input VAR4;
assign VAR3 = VAR1;
assign VAR2 = VAR4;
endmodule | gpl-2.0 |
sagarduwal/programming | computer_architecture/Unspecified/de.v | 1,150 | module MODULE2(VAR8,VAR3,VAR6,VAR10,VAR9,VAR2,VAR5,VAR12,VAR7,VAR4,VAR11,VAR1);
input VAR1,VAR7,VAR4,VAR11;
output VAR8,VAR3,VAR6,VAR10,VAR9,VAR2,VAR5,VAR12;
assign VAR8=(VAR1&(!VAR7)&(!VAR4)&(!VAR11));
assign VAR3=(VAR1&(!VAR7)&(!VAR4)&(VAR11));
assign VAR6=(VAR1&(!VAR4)&(VAR7)&(!VAR11));
assign VAR10= (VAR1&(!VAR7)&(... | gpl-3.0 |
sudov/options-accel | xillinux-eval-zedboard-1.1/system/hdl/system_stub.v | 17,351 | module MODULE2
(
VAR62,
VAR84,
VAR86,
VAR89,
VAR69,
VAR41,
VAR36,
VAR64,
VAR25,
VAR40,
VAR8,
VAR2,
VAR31,
VAR48,
VAR3,
VAR63,
VAR49,
VAR71,
VAR42,
VAR9,
VAR73,
VAR88,
VAR38,
VAR23,
VAR29,
VAR54,
VAR56,
VAR43,
VAR82,
VAR1,
VAR52,
VAR80,
VAR87,
VAR32,
VAR58,
VAR53,
VAR59,
VAR46,
VAR5,
VAR61,
VAR30,
VAR24,
VAR55,
VAR12,
V... | apache-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_fp_fptoui_double.v | 36,189 | module MODULE1
(
VAR18,
VAR4,
VAR7,
VAR5,
VAR12,
VAR13) ;
input VAR18;
input VAR4;
input VAR7;
input [83:0] VAR5;
input [6:0] VAR12;
output [83:0] VAR13;
tri0 VAR18;
tri1 VAR4;
tri0 VAR7;
reg [1:0] VAR15;
reg [83:0] VAR10;
reg [83:0] VAR17;
reg VAR11;
reg VAR3;
reg VAR1;
wire [7:0] VAR14;
wire VAR6;
wire [63:0] VAR8;
w... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdlclkp/sky130_fd_sc_lp__sdlclkp.behavioral.v | 2,265 | module MODULE1 (
VAR10,
VAR6 ,
VAR15,
VAR2
);
output VAR10;
input VAR6 ;
input VAR15;
input VAR2 ;
supply1 VAR13;
supply0 VAR9;
supply1 VAR16 ;
supply0 VAR20 ;
wire VAR17 ;
wire VAR5 ;
wire VAR7 ;
wire VAR21 ;
wire VAR4 ;
wire VAR22 ;
wire VAR1;
reg VAR3 ;
not VAR19 (VAR5 , VAR17 );
not VAR8 (VAR7 , VAR21 );
nor VAR12 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311o/sky130_fd_sc_ms__a311o.blackbox.v | 1,388 | module MODULE1 (
VAR5 ,
VAR1,
VAR10,
VAR4,
VAR9,
VAR8
);
output VAR5 ;
input VAR1;
input VAR10;
input VAR4;
input VAR9;
input VAR8;
supply1 VAR6;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
ElegantLin/My-CPU | project_4/project_4.srcs/sources_1/imports/Chapter11/mem_wb.v | 4,716 | module MODULE1(
input wire clk,
input wire rst,
input wire[5:0] VAR21,
input wire VAR13,
input wire[VAR8] VAR22,
input wire VAR19,
input wire[VAR7] VAR18,
input wire[VAR7] VAR32,
input wire[VAR7] VAR27,
input wire VAR23,
input wire VAR28,
input wire VAR2,
input wire VAR12,
input wire[4:0] VAR10,
input wire[VAR7] VAR20,... | gpl-3.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/acl_toggle_detect.v | 4,134 | module MODULE1
parameter VAR3=13, parameter VAR7=10 )
(
input logic clk,
input logic VAR4,
input logic valid,
input logic [VAR3-1:0] VAR9,
output logic [VAR7-1:0] VAR5[VAR3+1]
);
logic [VAR3-1:0] VAR1;
logic [VAR3-1:0] VAR8;
logic VAR11;
always@(posedge clk or negedge VAR4)
if (!VAR4)
VAR1<={VAR3{1'b0}};
else if (valid... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvpwrvgnd/sky130_fd_sc_ms__tapvpwrvgnd.functional.v | 1,067 | module MODULE1 ();
endmodule | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_auto_pc_0/zybo_zynq_design_auto_pc_0_stub.v | 4,617 | module MODULE1(VAR42, VAR26, VAR25, VAR21,
VAR14, VAR32, VAR41, VAR15, VAR16, VAR57,
VAR53, VAR36, VAR19, VAR30, VAR6, VAR48, VAR13,
VAR22, VAR33, VAR4, VAR17, VAR45, VAR46, VAR20,
VAR7, VAR5, VAR58, VAR35, VAR51, VAR47,
VAR54, VAR38, VAR29, VAR56, VAR39, VAR28, VAR59,
VAR3, VAR23, VAR24, VAR52, VAR44, VAR49,
VAR10, VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxtp/sky130_fd_sc_lp__dfxtp.behavioral.v | 1,760 | module MODULE1 (
VAR4 ,
VAR3,
VAR15
);
output VAR4 ;
input VAR3;
input VAR15 ;
supply1 VAR6;
supply0 VAR12;
supply1 VAR5 ;
supply0 VAR7 ;
wire VAR8 ;
reg VAR11 ;
wire VAR13 ;
wire VAR1;
wire VAR9 ;
VAR14 VAR10 (VAR8 , VAR13, VAR1, VAR11, VAR6, VAR12);
assign VAR9 = ( VAR6 === 1'b1 );
buf VAR2 (VAR4 , VAR8 );
endmodule | apache-2.0 |
richard42/CoCo3FPGA | buffer_dp.v | 9,835 | module MODULE1 (
VAR29,
VAR12,
VAR56,
VAR31,
VAR13,
VAR32,
VAR11);
input [7:0] VAR29;
input [8:0] VAR12;
input VAR56;
input [8:0] VAR31;
input VAR13;
input VAR32;
output [7:0] VAR11;
tri1 VAR13;
tri0 VAR32;
wire [7:0] VAR22;
wire [7:0] VAR11 = VAR22[7:0];
VAR47 VAR26 (
.VAR33 (VAR32),
.VAR61 (VAR13),
.VAR59 (VAR56),
.V... | bsd-3-clause |
jairov4/accel-oil | solution_spartan6/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/verilog/nfa_accept_samples_generic_hw_slv0_if.v | 14,765 | module MODULE1
VAR23 = 7,
VAR68 = 32
)(
input wire VAR55,
input wire VAR34,
input wire [VAR23-1:0] VAR3,
input wire VAR9,
output wire VAR5,
input wire [VAR68-1:0] VAR64,
input wire [VAR68/8-1:0] VAR77,
input wire VAR25,
output wire VAR44,
output wire [1:0] VAR60,
output wire VAR87,
input wire VAR47,
input wire [VAR23-1... | lgpl-3.0 |
queq/just-stuff | pov/TopFixed/charComp.v | 2,244 | module MODULE1(VAR2, VAR6, VAR4, VAR3, VAR1, VAR7, VAR5);
input [6:0] VAR2;
input VAR6;
output reg VAR4, VAR3, VAR1, VAR7,VAR5;
always @(VAR2 or VAR6) begin
if(VAR6==0) begin
case (VAR2)
7'b0000100:begin
VAR4=1;
VAR3=0;
VAR1=0;
VAR7=0;
VAR5=0;
end
7'b1101110:begin
VAR4=0;
VAR3=1;
VAR1=0;
VAR7=0;
VAR5=0;
end
7'b1001110:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/probec_p/sky130_fd_sc_hvl__probec_p.functional.pp.v | 1,801 | module MODULE1 (
VAR6 ,
VAR12 ,
VAR2,
VAR10,
VAR4 ,
VAR3
);
output VAR6 ;
input VAR12 ;
input VAR2;
input VAR10;
input VAR4 ;
input VAR3 ;
wire VAR5 ;
wire VAR7;
buf VAR1 (VAR5 , VAR12 );
VAR8 VAR11 (VAR7, VAR5, VAR2, VAR10);
buf VAR9 (VAR6 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4bb/sky130_fd_sc_hd__nand4bb_1.v | 2,334 | module MODULE2 (
VAR1 ,
VAR2 ,
VAR8 ,
VAR10 ,
VAR5 ,
VAR3,
VAR7,
VAR6 ,
VAR9
);
output VAR1 ;
input VAR2 ;
input VAR8 ;
input VAR10 ;
input VAR5 ;
input VAR3;
input VAR7;
input VAR6 ;
input VAR9 ;
VAR4 VAR11 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_mem2reg.v | 12,736 | module MODULE1(addr, VAR14, VAR22, VAR6);
parameter VAR17 = VAR12;
input [1:0] addr;
input [VAR28-1:0] VAR14;
input [VAR17-1:0] VAR22;
output [VAR17-1:0] VAR6;
reg [7:0] VAR3;
reg [7:0] VAR8;
reg [7:0] VAR5;
reg [7:0] VAR13;
reg [VAR17-1:0] VAR19;
reg [3:0] VAR21, VAR2,
VAR15, VAR25;
assign VAR6 = {VAR3, VAR8, VAR5, VA... | apache-2.0 |
MeshSr/onetswitch30 | ons30-app52-ref_ofshw/vivado/onets_7030_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/core/onet_core_logic.v | 34,099 | module MODULE1(
input clk, input reset,
input VAR25,
output VAR174,
input [31:0] VAR188,
input VAR215,
input VAR144,
input [3:0] VAR127,
output VAR96,
output VAR253,
output [31:0] VAR6,
output VAR263,
output VAR173,
output [3:0] VAR148,
input VAR105,
input VAR183,
output VAR47,
input [31:0] VAR53,
input VAR94,
input VA... | lgpl-2.1 |
ridecore/ridecore | src/fpga/rrf.v | 3,187 | module MODULE1(
input wire clk,
input wire reset,
input wire [VAR29-1:0] VAR26,
input wire [VAR29-1:0] VAR9,
input wire [VAR29-1:0] VAR18,
input wire [VAR29-1:0] VAR21,
input wire [VAR29-1:0] VAR34,
input wire [VAR29-1:0] VAR10,
output wire VAR37,
output wire VAR14,
output wire VAR40,
output wire VAR2,
output wire [VAR... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd/sky130_fd_sc_hs__tapvgnd_1.v | 1,813 | module MODULE2 (
VAR1,
VAR4
);
input VAR1;
input VAR4;
VAR3 VAR2 (
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE2 ();
supply1 VAR1;
supply0 VAR4;
VAR3 VAR2 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.v | 2,074 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR4,
VAR6,
VAR3 ,
VAR1
);
output VAR8 ;
input VAR2 ;
input VAR4;
input VAR6;
input VAR3 ;
input VAR1 ;
VAR5 VAR7 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR8,
VAR2
);
output VAR8;
input VAR2;
supply1 VAR4;
supply0 VAR6;... | apache-2.0 |
cpulabs/mist1032isa | src/core/execute/execute_shift.v | 13,834 | module MODULE1 #(
parameter VAR25 = 32
)(
input wire [2:0] VAR6,
input wire [VAR25-1:0] VAR13,
input wire [VAR25-1:0] VAR16,
output wire [VAR25-1:0] VAR22,
output wire VAR20,
output wire VAR17,
output wire VAR27,
output wire VAR8,
output wire VAR14
);
function [31:0] VAR26;
input [31:0] VAR19;
input [4:0] VAR11;
begin
... | bsd-2-clause |
takeshineshiro/fpga_linear_128 | DPRAM_bb.v | 7,846 | module MODULE1 (
VAR2,
VAR7,
VAR6,
VAR5,
VAR4,
VAR1,
VAR3);
input [11:0] VAR2;
input [8:0] VAR7;
input VAR6;
input [8:0] VAR5;
input VAR4;
input VAR1;
output [11:0] VAR3;
tri1 VAR1;
endmodule | mit |
plindstroem/oh | xilibs/hdl/BUFR.v | 1,273 | module MODULE1 (
VAR3,
VAR2, VAR4, VAR5
);
parameter VAR8=4;
parameter VAR10=0;
input VAR2; input VAR4; input VAR5; output VAR3;
VAR9 VAR9 (
.VAR1 (VAR3),
.VAR6 (VAR2),
.VAR7 (4'b0010), .reset (VAR5)
);
endmodule | gpl-3.0 |
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