repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
hydai/Verilog-Practice | DigitalDesign/hw4_FIFO/fifo.v | 1,532 | module MODULE1 (
input clk,
input VAR16,
input VAR1,
input VAR7,
input [7:0] VAR11,
output VAR20,
output VAR4,
output VAR24,
output VAR25,
output VAR9,
output [7:0] VAR5
);
wire [4:0] addr;
wire VAR23;
wire VAR18;
wire VAR14;
wire [7:0] VAR19;
VAR2 VAR17 (
.clk(clk),
.VAR16(VAR16),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR20(VAR2... | mit |
hsnuonly/PikachuVolleyFPGA | VGA.ip_user_files/ip/KeyboardCtrl_0/KeyboardCtrl_0_stub.v | 1,420 | module MODULE1(VAR6, VAR5, VAR4, valid, VAR3, VAR1, VAR2, rst, clk)
;
output [7:0]VAR6;
output VAR5;
output VAR4;
output valid;
output VAR3;
inout VAR1;
inout VAR2;
input rst;
input clk;
endmodule | gpl-3.0 |
freecores/tiny_tate_bilinear_pairing | group_size_is_151_bits/rtl/cubic.v | 10,353 | module MODULE1(VAR2, VAR1);
input [193:0] VAR2;
output [193:0] VAR1;
assign VAR1[1:0] = VAR2[1:0];
assign VAR1[3:2] = VAR2[131:130];
assign VAR1[5:4] = VAR2[67:66];
assign VAR1[7:6] = VAR2[3:2];
assign VAR1[9:8] = VAR2[133:132];
assign VAR1[11:10] = VAR2[69:68];
assign VAR1[13:12] = VAR2[5:4];
assign VAR1[15:14] = VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbn/sky130_fd_sc_hs__sdfbbn.pp.blackbox.v | 1,493 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR1 ,
VAR2 ,
VAR10 ,
VAR6 ,
VAR8 ,
VAR4,
VAR5 ,
VAR7
);
output VAR9 ;
output VAR3 ;
input VAR1 ;
input VAR2 ;
input VAR10 ;
input VAR6 ;
input VAR8 ;
input VAR4;
input VAR5 ;
input VAR7 ;
endmodule | apache-2.0 |
James534/SubZero | SubZero/fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/DE0_Nano_SOPC_sw.v | 4,239 | module MODULE1 (
address,
VAR9,
clk,
VAR12,
VAR10,
VAR6,
VAR15,
irq,
VAR8
)
;
output irq;
output [ 31: 0] VAR8;
input [ 1: 0] address;
input VAR9;
input clk;
input [ 3: 0] VAR12;
input VAR10;
input VAR6;
input [ 31: 0] VAR15;
wire VAR14;
reg [ 3: 0] VAR7;
reg [ 3: 0] VAR11;
wire [ 3: 0] VAR13;
reg [ 3: 0] VAR3;
wire VA... | mit |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/pcie_7x_v1_8_gtp_pipe_rate.v | 13,110 | module MODULE1 #
(
parameter VAR11 = 4'd15
)
(
input VAR41,
input VAR6,
input VAR39,
input [ 1:0] VAR43,
input VAR28,
input VAR33,
input VAR23,
input VAR26,
output VAR17,
output [ 2:0] VAR27,
output VAR1,
output VAR40,
output VAR9,
output [23:0] VAR3
);
reg VAR12;
reg [ 1:0] VAR36;
reg VAR18;
reg VAR24;
reg VAR2;
reg V... | mit |
trivoldus28/pulsarch-verilog | design/sys/edk_bee3/pcores/aurora_201_pcore_v1_00_a/hdl/verilog/aurora_201_error_detect.v | 8,378 | module MODULE1
(
VAR17,
VAR10,
VAR11,
VAR3,
VAR12,
VAR8,
VAR16,
VAR18,
VAR4,
VAR7
);
input VAR17;
output VAR10;
output VAR11;
output VAR3;
input VAR12;
input [1:0] VAR8;
input [1:0] VAR16;
input VAR18;
input VAR4;
input VAR7;
reg VAR3;
reg VAR11;
reg [0:1] VAR13;
reg VAR6;
reg [0:1] VAR1;
reg [0:1] VAR5;
reg VAR14; reg... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/diode/sky130_fd_sc_ls__diode.behavioral.v | 1,177 | module MODULE1 (
VAR2
);
input VAR2;
supply1 VAR1;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
niketancm/tsea26 | lab2-3/rtl/combined_agu.v | 9,443 | module MODULE1
parameter VAR107 = VAR12,
parameter VAR95 = VAR123,
parameter VAR29 = VAR109,
parameter VAR101 = VAR28,
parameter VAR18 = VAR85)
(
input wire VAR11,
input wire VAR86,
input wire [VAR107-1:0] VAR118,
input wire [VAR19-1:0] VAR73,
input wire [VAR19-1:0] VAR35,
output reg [VAR95-1:0] VAR125,
output wire VAR... | gpl-2.0 |
MarcoVogt/basil | firmware/modules/fei4_rx/receiver_logic.v | 6,700 | module MODULE1
parameter VAR87 = 10
)
(
input wire VAR73,
input wire VAR26,
input wire VAR33,
input wire VAR86,
input wire VAR25,
input wire VAR80,
input wire read,
output wire [23:0] VAR11,
output wire VAR37,
output wire VAR94,
output wire VAR14,
output reg [7:0] VAR89,
output reg [7:0] VAR28,
output reg [15:0] VAR31,... | bsd-3-clause |
CospanDesign/nysa-verilog | verilog/generic/blk_mem.v | 1,508 | module MODULE1 #(
parameter VAR4 = 8,
parameter VAR3 = 4,
parameter VAR1 = 0
)(
input VAR6,
input VAR2,
input [VAR3 - 1 :0] VAR9,
input [VAR4 - 1:0] VAR12,
input VAR8,
input [VAR3 - 1:0] VAR7,
output [VAR4 - 1:0] VAR11
);
reg [VAR4 - 1:0] VAR10 [0:2 ** VAR3];
reg [VAR4 - 1:0] dout;
assign VAR11 = dout;
integer VAR5;
be... | mit |
danyq/cis-driver | ice40/top.v | 3,800 | module MODULE1(
input VAR5,
input [7:0] VAR10,
output VAR1,
output reg VAR8,
output reg VAR11,
output reg VAR3,
output reg VAR14,
output reg VAR2,
output [7:0] VAR9,
output reg VAR4,
output reg VAR7,
output reg VAR6
);
reg [3:0] VAR12;
reg [12:0] VAR13;
assign VAR1 = 'b0;
assign VAR1 = 'b1;
assign VAR9 = VAR10; | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.v | 2,461 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR2 ,
VAR1 ,
VAR3 ,
VAR12 ,
VAR8,
VAR11,
VAR9 ,
VAR10
);
output VAR7 ;
input VAR5 ;
input VAR2 ;
input VAR1 ;
input VAR3 ;
input VAR12 ;
input VAR8;
input VAR11;
input VAR9 ;
input VAR10 ;
VAR4 VAR6 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR12(VAR12),
.VAR8(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxbp/sky130_fd_sc_hs__edfxbp.functional.pp.v | 1,766 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR10 ,
VAR13 ,
VAR12 ,
VAR5,
VAR9
);
output VAR8 ;
output VAR3 ;
input VAR10 ;
input VAR13 ;
input VAR12 ;
input VAR5;
input VAR9;
wire VAR4;
VAR2 VAR6 VAR11 (VAR4 , VAR13, VAR10, VAR12, VAR5, VAR9);
buf VAR1 (VAR8 , VAR4 );
not VAR7 (VAR3 , VAR4 );
endmodule | apache-2.0 |
jairov4/accel-oil | solution_virtex5/syn/verilog/nfa_accept_samples_generic_hw.v | 55,753 | module MODULE1 (
VAR215,
VAR35,
VAR233,
VAR192,
VAR276,
VAR95,
VAR240,
VAR236,
VAR29,
VAR113,
VAR48,
VAR259,
VAR146,
VAR122,
VAR256,
VAR191,
VAR110,
VAR42,
VAR20,
VAR282,
VAR220,
VAR143,
VAR144,
VAR160,
VAR108,
VAR137,
VAR312,
VAR107,
VAR115,
VAR105,
VAR31,
VAR245,
VAR296,
VAR168,
VAR221,
VAR249,
VAR13,
VAR247,
VAR64,
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_gpiov2/sky130_fd_io__top_gpiov2.pp.symbol.v | 2,784 | module MODULE1 (
input VAR27 ,
output VAR25 ,
input VAR36 ,
output VAR1 ,
input VAR14 ,
inout VAR10 ,
inout VAR31 ,
inout VAR11 ,
inout VAR37 ,
inout VAR3 ,
inout VAR4 ,
input VAR18 ,
input VAR12 ,
input VAR8 ,
input [2:0] VAR7 ,
input VAR22 ,
input VAR33 ,
input VAR6 ,
input VAR23 ,
input VAR17,
input VAR26 ,
input VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3/sky130_fd_sc_ms__nand3_2.v | 2,175 | module MODULE2 (
VAR1 ,
VAR8 ,
VAR6 ,
VAR3 ,
VAR5,
VAR10,
VAR9 ,
VAR7
);
output VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR3 ;
input VAR5;
input VAR10;
input VAR9 ;
input VAR7 ;
VAR2 VAR4 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41oi/sky130_fd_sc_ls__a41oi.pp.blackbox.v | 1,423 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR3 ,
VAR8 ,
VAR6 ,
VAR5 ,
VAR10,
VAR4,
VAR2 ,
VAR1
);
output VAR7 ;
input VAR9 ;
input VAR3 ;
input VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR10;
input VAR4;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/verilog/axi_vdma_v6_2_axis_register_slice_v1_0_axisc_register_slice.v | 19,753 | module MODULE1 #
(
parameter VAR25 = "VAR5",
parameter VAR17 = 32,
parameter VAR16 = 32'h00000000
)
(
input wire VAR14,
input wire VAR18,
input wire VAR8,
input wire [VAR17-1:0] VAR4,
input wire VAR21,
output wire VAR10,
output wire [VAR17-1:0] VAR22,
output wire VAR23,
input wire VAR13
);
generate
if (VAR16 == 32'h000... | gpl-3.0 |
Canaan-Creative/MM | verilog/superkdf9/components/lm32_top/spiprog.v | 7,145 | module MODULE1 (input VAR13 ,
input VAR31 ,
output VAR1 ,
input VAR34 ,
input VAR40 ,
input VAR19 ,
input VAR35 ,
input VAR5 ,
input VAR30 ,
output VAR24 ,
output VAR4 ,
output VAR11 ,
input VAR27);
wire VAR41 ;
wire VAR33;
wire VAR9;
wire VAR29 ;
wire VAR22;
wire VAR18;
wire [7:0] VAR37 ;
wire [8:0] VAR23 ;
wire [8:0]... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4b/sky130_fd_sc_hdll__nand4b_2.v | 2,327 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR10 ,
VAR2 ,
VAR6 ,
VAR7,
VAR11,
VAR9 ,
VAR8
);
output VAR1 ;
input VAR4 ;
input VAR10 ;
input VAR2 ;
input VAR6 ;
input VAR7;
input VAR11;
input VAR9 ;
input VAR8 ;
VAR3 VAR5 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR9(VAR9),
.... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/Computer_System/synthesis/submodules/altera_up_edge_detection_nonmaximum_suppression.v | 7,019 | module MODULE1 (
clk,
reset,
VAR3,
VAR9,
VAR20
);
parameter VAR21 = 640;
input clk;
input reset;
input [ 9: 0] VAR3;
input VAR9;
output [ 7: 0] VAR20;
wire [ 9: 0] VAR13[ 1: 0];
reg [ 9: 0] VAR1[ 2: 0];
reg [ 9: 0] VAR4[ 2: 0];
reg [ 9: 0] VAR2[ 2: 0];
reg [ 7: 0] VAR7[ 4: 0];
reg [ 8: 0] VAR15[ 2: 0];
reg [ 7: 0] VAR1... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_2.behavioral.pp.v | 2,782 | module MODULE1( VAR17, VAR12, VAR13, VAR3, VAR20, VAR24 );
input VAR13, VAR12, VAR17;
inout VAR20, VAR24;
output VAR3;
reg VAR10;
VAR25 VAR26(.VAR17(VAR17),.VAR12(VAR12),.VAR13(VAR13),.VAR3(VAR3),.VAR20(VAR20),.VAR24(VAR24),.VAR10(VAR10));
VAR25 VAR22(.VAR17(VAR17),.VAR12(VAR12),.VAR13(VAR13),.VAR3(VAR3),.VAR20(VAR20),... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/984e004bd8bf2d97/ip_design_processing_system7_0_0_stub.v | 5,531 | module MODULE1(VAR40, VAR18, VAR28, VAR46,
VAR41, VAR36, VAR10, VAR17, VAR39, VAR19,
VAR73, VAR63, VAR25, VAR32,
VAR49, VAR74, VAR61, VAR62, VAR50,
VAR59, VAR70, VAR14, VAR65, VAR55,
VAR57, VAR45, VAR44, VAR3,
VAR7, VAR24, VAR20, VAR68, VAR75,
VAR34, VAR35, VAR12, VAR42, VAR1,
VAR56, VAR48, VAR30, VAR21, VAR64,
VAR47, ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4b/sky130_fd_sc_ls__nor4b.pp.blackbox.v | 1,341 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR7 ,
VAR4 ,
VAR5 ,
VAR8,
VAR3,
VAR2 ,
VAR1
);
output VAR6 ;
input VAR9 ;
input VAR7 ;
input VAR4 ;
input VAR5 ;
input VAR8;
input VAR3;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
andykarpov/radio-86rk-wxeda | src/sdram/SDRAM_Controller.v | 2,954 | module MODULE1(
input VAR17, input reset, inout [15:0] VAR7, output reg[11:0] VAR30, output VAR31, output VAR14, output reg VAR26, output reg VAR21, output reg VAR12, output VAR10, output VAR22, output VAR27, input [21:0] VAR33,
input [15:0] VAR29,
input rd,
input VAR13,
output reg [15:0] VAR1
);
parameter VAR9 = 4'd0;... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4b/sky130_fd_sc_hdll__nand4b.pp.blackbox.v | 1,355 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR3 ,
VAR6 ,
VAR9 ,
VAR4,
VAR2,
VAR1 ,
VAR7
);
output VAR5 ;
input VAR8 ;
input VAR3 ;
input VAR6 ;
input VAR9 ;
input VAR4;
input VAR2;
input VAR1 ;
input VAR7 ;
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | example/KC705/fpga_gmii/rtl/fpga.v | 5,451 | module MODULE1 (
input wire VAR72,
input wire VAR66,
input wire reset,
input wire VAR105,
input wire VAR55,
input wire VAR39,
input wire VAR86,
input wire VAR8,
input wire [3:0] VAR35,
output wire [7:0] VAR30,
input wire VAR50,
input wire [7:0] VAR26,
input wire VAR77,
input wire VAR21,
output wire VAR24,
input wire VA... | mit |
aquaxis/FPGAMAG18 | fmrv32im-artya7.nonos/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ip/fmrv32im_artya7_dbussel_upgraded_ipi_0/synth/fmrv32im_artya7_dbussel_upgraded_ipi_0.v | 7,075 | module MODULE1 (
VAR12,
VAR24,
VAR15,
VAR2,
VAR5,
VAR10,
VAR6,
VAR14,
VAR30,
VAR1,
VAR26,
VAR19,
VAR27,
VAR9,
VAR28,
VAR16,
VAR22,
VAR18,
VAR23,
VAR29,
VAR8,
VAR11,
VAR7,
VAR13,
VAR3,
VAR17,
VAR20,
VAR4
);
output wire VAR12;
input wire VAR24;
input wire [3 : 0] VAR15;
input wire [31 : 0] VAR2;
input wire [31 : 0] VAR5;... | mit |
bluespec/Flute | src_SSITH_P2/Verilog_RTL/mkPTW.v | 35,107 | module MODULE1(VAR28,
VAR128,
VAR75,
VAR190,
VAR11,
VAR63,
VAR181,
VAR136,
VAR161,
VAR98,
VAR171,
VAR82,
VAR67,
VAR145,
VAR195,
VAR2,
VAR41,
VAR94,
VAR7,
VAR64);
parameter [2 : 0] VAR139 = 3'b0;
input VAR28;
input VAR128;
input [127 : 0] VAR75;
input VAR190;
output VAR11;
input VAR63;
output [131 : 0] VAR181;
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufbuf/sky130_fd_sc_lp__bufbuf.symbol.v | 1,258 | module MODULE1 (
input VAR5,
output VAR4
);
supply1 VAR1;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
lsnow/mips32 | data_ram.v | 1,306 | module MODULE1(
clk, rst, VAR2, VAR7, VAR9, VAR6,
VAR1);
input clk, rst;
input VAR2;
input VAR7;
input [31:0] VAR9;
input [31:0] VAR6;
output reg [31:0] VAR1;
reg VAR8;
integer VAR5;
reg [31:0] VAR3 [2<<10 - 1:0];
wire [9:0] VAR4 = VAR9[9:0];
always @(posedge clk) begin
if(rst) begin
for (VAR5 = 0; VAR5 < 1024; VAR5 = ... | gpl-2.0 |
JakeMercer/mac | mii.v | 1,893 | module MODULE1
(
input wire reset,
output wire VAR26,
output reg [3:0] VAR11,
output wire VAR8,
input wire VAR28,
input wire VAR4,
input wire [3:0] VAR10,
input wire VAR16,
input wire VAR15,
input wire VAR14,
input wire VAR2,
input wire VAR18,
input wire [7:0] VAR21,
input wire VAR13,
output wire VAR22,
output wire VAR... | mit |
fzyz999/5-stage-MIPS | datapath/dm.v | 1,192 | module MODULE1( addr, VAR2, VAR1, clk, rd ) ;
input [12:2] addr ; input [31:0] VAR2 ;
input [3:0] VAR1 ;
input clk ;
output [31:0] rd ;
reg [31:0] MODULE1[2047:0] ;
always @(posedge clk) begin
if (VAR1==4'b1111) begin
MODULE1[addr]<=VAR2;
end else if (VAR1==4'b0011) begin
MODULE1[addr]<={MODULE1[addr][31:16],VAR2[15:0]... | mit |
SWORDfpga/ComputerOrganizationDesign | labs/lab04/lab04/Code/IO/port/GPIO_IO.v | 1,123 | module MODULE1(input clk, input rst, input VAR10, input VAR9, input [31:0] VAR7, output reg[1:0] VAR4, output [15:0] VAR6, output wire VAR3, output wire VAR2, output wire VAR8, output wire VAR1, output reg[13:0] VAR5 );
endmodule | gpl-3.0 |
fbelavenuto/msx1fpga | src/audio/jt51/jt51_op.v | 9,164 | module MODULE1(
input VAR22,
input VAR13,
input clk, input [9:0] VAR66,
input [2:0] VAR20,
input [2:0] VAR2,
input [9:0] VAR57,
input VAR56,
input VAR26,
input VAR64,
input VAR63,
input VAR37,
input VAR71,
input VAR53,
input VAR25,
input VAR68,
output signed [13:0] VAR44
);
wire signed [13:0] VAR54, VAR28, VAR39;
VAR45... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/bufinv/sky130_fd_sc_ls__bufinv.functional.v | 1,259 | module MODULE1 (
VAR5,
VAR2
);
output VAR5;
input VAR2;
wire VAR1;
not VAR4 (VAR1, VAR2 );
buf VAR3 (VAR5 , VAR1 );
endmodule | apache-2.0 |
rohit21122012/CPU | ALU/Arith/UnSigned/UAdder/UAdder.v | 3,813 | module MODULE2 (out,VAR26,VAR30,VAR7,VAR18,VAR5);
output [31:0]out;
output VAR26,VAR30;
input [31:0] VAR7,VAR18;
input VAR5;
wire [6:0] VAR27;
MODULE1 MODULE4(out[3:0],VAR27[0],VAR7[3:0],VAR18[3:0],VAR5);
MODULE1 MODULE5(out[7:4],VAR27[1],VAR7[7:4],VAR18[7:4],VAR27[0]);
MODULE1 MODULE1(out[11:8],VAR27[2],VAR7[11:8],VAR... | mit |
atalbb/sha1 | SHA1_core.srcs/sources_1/new/Msg_In.v | 2,146 | module MODULE1(input clk,
input rst,
input VAR3,
input [31:0]VAR1,
output reg VAR4,
output reg [511:0]VAR5
);
reg [9:0]VAR2;
always@(posedge clk or negedge rst) begin
if(rst == 0) begin
VAR4 <= 0;
VAR5 <= 0;
VAR2 <= 0;
end else begin
if(VAR3)
if(VAR2 < 17)
VAR2 <= VAR2 + 1;
end
end
always@(VAR2) begin
if(VAR2 == 1)
VAR... | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/fp_compare.v | 21,288 | module MODULE1
(
VAR24,
VAR97,
VAR15,
VAR91,
VAR66,
VAR85) ;
output VAR24;
output VAR97;
output VAR15;
input VAR91;
input [31:0] VAR66;
input [31:0] VAR85;
reg VAR17;
reg VAR78;
reg VAR89;
reg VAR77;
reg VAR105;
reg VAR39;
reg VAR8;
reg VAR37;
reg VAR3;
reg VAR7;
reg VAR16;
reg VAR69;
reg VAR55;
reg VAR14;
reg [1:0] VA... | apache-2.0 |
mammenx/pegasus | wxp/dgn/rtl/common/pkt_ff_async/pkt_ff_rptr.v | 3,085 | module MODULE1 #(VAR3 = 8)
(
clk,
VAR6,
VAR2,
VAR4
);
input clk;
input VAR6;
input VAR2;
output [VAR3-1:0] VAR4;
VAR1 VAR8
(
.clk (clk),
.VAR6 (VAR6),
.VAR7 ({VAR3{1'b0}}),
.en (VAR2),
.VAR5 (),
.VAR10 (VAR4)
);
endmodule | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_2.behavioral.pp.v | 3,372 | module MODULE1( VAR10, VAR7, VAR8, VAR4, VAR6, VAR1, VAR3, VAR5 );
input VAR6, VAR1, VAR4, VAR8, VAR7;
inout VAR3, VAR5;
output VAR10;
VAR2 VAR11(.VAR10(VAR10),.VAR7(VAR7),.VAR8(VAR8),.VAR4(VAR4),.VAR6(VAR6),.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5));
VAR2 VAR9(.VAR10(VAR10),.VAR7(VAR7),.VAR8(VAR8),.VAR4(VAR4),.VAR6(VAR6),.V... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/source/pcie_7x_v1_3_pipe_rate.v | 34,830 | module MODULE1 #
(
parameter VAR53 = "1.1", parameter VAR62 = "VAR33", parameter VAR46 = "VAR49", parameter VAR107 = "VAR51", parameter VAR102 = "VAR51", parameter VAR90 = "VAR49", parameter VAR74 = 4'd15
)
(
input VAR16,
input VAR101,
input VAR1,
input [ 1:0] VAR98,
input VAR54,
input VAR67,
input VAR84,
input VAR76,
... | lgpl-3.0 |
jameshegarty/rigel | platform/verilator/RAMB16_S4_S4.v | 3,525 | module MODULE1(
input VAR43,
input VAR79,
input VAR74,
input VAR69,
input [11:0] VAR32,
input [3:0] VAR27,
output [3:0] VAR38,
input VAR46,
input VAR73,
input VAR84,
input VAR85,
input [11:0] VAR35,
input [3:0] VAR15,
output [3:0] VAR23);
parameter VAR61 = "VAR4";
parameter VAR65 = "VAR4";
parameter VAR3=256'd0;
parame... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/dma_queue/nf2_dma_bus_fsm.v | 14,273 | module MODULE1
parameter VAR16 = 4,
parameter VAR28=11)
(
input [1:0] VAR10,
input [3:0] VAR71,
output reg [1:0] VAR45,
input VAR19,
input [VAR48-1:0] VAR61,
output reg VAR6,
output reg VAR44,
output reg [VAR48-1:0] VAR14,
input VAR21,
output reg VAR49,
input [VAR16-1:0] VAR81,
input [VAR16-1:0] VAR79,
input VAR31,
inp... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_2.functional.v | 1,676 | module MODULE1( VAR3, VAR19, VAR4, VAR17, VAR10, VAR12 );
input VAR10, VAR12, VAR17, VAR4, VAR19;
output VAR3;
wire VAR21;
not VAR9( VAR21, VAR10 );
wire VAR14;
not VAR11( VAR14, VAR12 );
wire VAR16;
and VAR20( VAR16, VAR21, VAR14 );
wire VAR15;
not VAR13( VAR15, VAR17 );
wire VAR18;
not VAR7( VAR18, VAR4 );
wire VAR1;... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Dynamic_Saturation_block1.v | 2,315 | module MODULE1
(
VAR10,
VAR1,
VAR3,
VAR11,
VAR2
);
input signed [17:0] VAR10; input signed [35:0] VAR1; input signed [17:0] VAR3; output signed [35:0] VAR11; output VAR2;
wire signed [35:0] VAR5; wire VAR12;
wire signed [35:0] VAR6; wire VAR7;
wire signed [35:0] VAR13; wire signed [35:0] VAR9; wire signed [35:0] VAR14;... | gpl-3.0 |
LordRafa/Sobel-FPGA | SISSources/V/FrameWriter.v | 1,543 | module MODULE1 (
input clk,
input rst,
input [23:0] VAR17,
input VAR4,
output wire VAR11,
input wire VAR7,
input wire VAR12,
output wire [VAR9-1:0] VAR16,
output wire VAR1,
input wire [VAR3:0] VAR15,
input VAR13,
output VAR2
);
parameter VAR9 = 32;
parameter VAR6 = 256;
parameter VAR3 = 8;
reg VAR5;
wire VAR14;
wire VA... | gpl-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/acl_debug_mem.v | 3,166 | module MODULE1
parameter VAR6=16,
parameter VAR19=10
)
(
input logic clk,
input logic VAR11,
input logic write,
input logic [VAR6-1:0] VAR10[VAR19]
);
localparam VAR16=VAR21(VAR19);
logic [VAR16-1:0] addr;
logic VAR54;
always@(posedge clk or negedge VAR11)
if (!VAR11)
addr <= {VAR16{1'b0}};
else if (addr != {VAR16{1'b0... | mit |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/hdl/verilog/channel_error_detect.v | 4,788 | module MODULE1
(
VAR14,
VAR7,
VAR5,
VAR6,
VAR3,
VAR10,
VAR4,
VAR9
);
input [0:1] VAR14;
input VAR7;
input VAR5;
input VAR6;
input VAR3;
output VAR10;
output VAR4;
output VAR9;
reg VAR10;
reg VAR4;
reg VAR9;
reg [0:1] VAR13;
reg VAR1;
wire VAR2;
wire VAR12;
wire VAR11;
always @(posedge VAR6)
begin
VAR13 <= VAR8 VAR14;
V... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd1/sky130_fd_sc_hdll__dlygate4sd1_1.v | 2,135 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR4,
VAR6,
VAR2 ,
VAR3
);
output VAR8 ;
input VAR5 ;
input VAR4;
input VAR6;
input VAR2 ;
input VAR3 ;
VAR1 VAR7 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR8,
VAR5
);
output VAR8;
input VAR5;
supply1 VAR4;
supply0 VAR6;... | apache-2.0 |
audiocircuit/NCSU-Low-Power-RFID | Memory/FIFO.v | 23,595 | module MODULE1(
input wire clk,
input wire reset,
input wire write,
input wire read,
input wire [7:0] VAR5,
output reg [7:0] VAR9,
output wire VAR6,
output wire VAR7
);
reg [4:0] VAR3;
reg [4:0] VAR1;
reg [7:0] memory [0:15];
wire VAR4;
wire [3:0] VAR8;
assign VAR7 = (VAR1 == VAR3) ? 1'b1 : 1'b0;
assign VAR6 = ((VAR1[3... | gpl-3.0 |
fabianmcg/usbc_tcpc | src/hardReset.v | 3,623 | module MODULE1(output wire VAR6,
output wire VAR24,
output wire VAR7,
output wire VAR3,
output wire VAR15,
output wire VAR17,
output wire VAR20,
output wire VAR2,
input wire [2:0] VAR21,
input wire VAR13,
input wire VAR1,
input wire VAR23,
input wire VAR13,
input wire VAR18,
input wire VAR22);
wire VAR8;
wire VAR9;
reg... | mit |
SiLab-Bonn/monopix_daq | firmware/src/pulse_gen640/pulse_gen640.v | 1,665 | module MODULE1
parameter VAR18 = 16'h0000,
parameter VAR14 = 16'h0000,
parameter VAR24 = 16,
parameter VAR3 = 4,
parameter VAR25 =2
)(
input wire VAR5,
input wire [VAR24-1:0] VAR15,
inout wire [7:0] VAR20,
input wire VAR12,
input wire VAR22,
input wire VAR28,
input wire VAR10,
input wire VAR9,
input wire VAR2,
input wi... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/ddr2_infrastructure_eco20100512.v | 9,435 | module MODULE1 #
(
parameter VAR73 = 3000,
parameter VAR49 = "VAR27",
parameter VAR11 = "VAR119",
parameter VAR96 = 0,
parameter VAR115 = 1
)
(
input VAR12,
input VAR107,
input VAR25,
input VAR14,
input VAR78,
input VAR104,
output VAR9,
output VAR102,
output VAR84,
output VAR16,
input VAR92,
input VAR32,
output VAR93,
... | lgpl-3.0 |
luebbers/reconos | support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/plb_tft_cntlr_ref_v1_00_e/hdl/verilog/plb_tft_cntlr_ref.v | 18,149 | module MODULE1 (
VAR27, VAR103,
VAR187, VAR115, VAR2, VAR44, VAR204, VAR56, VAR68, VAR168, VAR166, VAR177, VAR70, VAR30, VAR137, VAR219, VAR41,
VAR52, VAR34, VAR47, VAR63, VAR107, VAR4, VAR3,
VAR7, VAR158, VAR200, VAR23,
VAR16, VAR117, VAR48, VAR121, VAR222,
VAR186, VAR101, VAR143, VAR87, VAR108, VAR85, VAR84,
VAR24, V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgnd/sky130_fd_sc_ls__tapvgnd.functional.v | 1,097 | module MODULE1 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlxtn/sky130_fd_sc_hdll__dlxtn.blackbox.v | 1,308 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR6
);
output VAR7 ;
input VAR1 ;
input VAR6;
supply1 VAR2;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41ai/sky130_fd_sc_hd__o41ai.functional.pp.v | 2,059 | module MODULE1 (
VAR12 ,
VAR3 ,
VAR2 ,
VAR4 ,
VAR16 ,
VAR15 ,
VAR13,
VAR18,
VAR7 ,
VAR11
);
output VAR12 ;
input VAR3 ;
input VAR2 ;
input VAR4 ;
input VAR16 ;
input VAR15 ;
input VAR13;
input VAR18;
input VAR7 ;
input VAR11 ;
wire VAR10 ;
wire VAR6 ;
wire VAR1;
or VAR5 (VAR10 , VAR16, VAR4, VAR2, VAR3 );
nand VAR14 (V... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9152/axi_ad9152_core.v | 7,305 | module MODULE1 (
VAR58,
VAR50,
VAR33,
VAR11,
VAR55,
VAR49,
VAR24,
VAR13,
VAR16,
VAR14,
VAR67,
VAR9,
VAR47,
VAR26,
VAR35,
VAR40,
VAR31,
VAR46,
VAR66,
VAR76,
VAR53,
VAR54,
VAR17,
VAR32,
VAR27,
VAR60,
VAR21,
VAR19);
parameter VAR68 = 0;
parameter VAR20 = 0;
input VAR58;
output VAR50;
output [15:0] VAR33;
output [15:0] VAR... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_dcd.v | 23,313 | module MODULE1 (
VAR49, VAR83, VAR9, VAR4,
VAR102, VAR12,
VAR36, VAR86,
VAR21, VAR25,
VAR113, VAR10, VAR120, VAR13,
VAR93, VAR41, VAR66,
VAR39, VAR17, VAR96,
VAR124, VAR87, VAR115, VAR122, VAR40, VAR114, VAR75,
VAR104, VAR1, VAR43,
VAR91, VAR116, VAR90
) ;
input [10:3] VAR113; input [10:3] VAR10;
input VAR120; input VA... | gpl-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/buffer/packt_buffer.v | 13,682 | module MODULE1(
clk,
reset,
VAR42,
VAR62,
VAR16,
VAR98,
VAR29,
VAR82,
VAR27,
VAR54,
VAR5,
VAR80,
VAR92,
VAR63,
VAR85,
VAR69,
VAR7,
VAR70
);
input clk;
input reset;
input VAR42;
input [138:0] VAR62;
input VAR16;
input [31:0] VAR98;
output VAR29;
output [31:0] VAR82;
output VAR27;
input VAR54;
input VAR5;
input [31:0] VA... | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/uart_regs.v | 29,213 | module MODULE1 (clk,
VAR44, VAR124, VAR10, VAR72, VAR83, VAR87,
VAR109,
VAR160,
VAR59, VAR98,
VAR71, VAR154, VAR156, VAR101, VAR76, VAR21, VAR20, VAR136, VAR95, VAR105, VAR91,
VAR120, VAR165, VAR112
, VAR144
);
output VAR109;
input clk;
input VAR44;
input [VAR34-1:0] VAR124;
input [7:0] VAR10;
output [7:0] VAR72;
input... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22oi/sky130_fd_sc_lp__a22oi_1.v | 2,352 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR6 ,
VAR3 ,
VAR10 ,
VAR8,
VAR4,
VAR1 ,
VAR11
);
output VAR5 ;
input VAR2 ;
input VAR6 ;
input VAR3 ;
input VAR10 ;
input VAR8;
input VAR4;
input VAR1 ;
input VAR11 ;
VAR7 VAR9 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR1(VAR1),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2/sky130_fd_sc_ms__nor2.blackbox.v | 1,233 | module MODULE1 (
VAR5,
VAR7,
VAR3
);
output VAR5;
input VAR7;
input VAR3;
supply1 VAR1;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/atlas_linux_ghrd/ip/altsource_probe/hps_reset_bb.v | 3,120 | module MODULE1 (
VAR2,
VAR1,
VAR3);
input VAR2;
input VAR1;
output [2:0] VAR3;
endmodule | gpl-2.0 |
sh-chris110/chris | FPGA/chris.system.dma.ok/Qsys/soc_design/synthesis/submodules/chris_pipelined.v | 1,352 | module MODULE1 (
input wire [3:0] VAR8, input wire VAR1, output wire [31:0] VAR2, output wire VAR7, input wire VAR6, input wire [31:0] VAR5, output wire VAR11, input wire [3:0] VAR10, input wire VAR9, input wire VAR4, output wire VAR3 );
assign VAR2 = 32'b00000000000000000000000000000000;
assign VAR11 = 1'b0;
assign VA... | gpl-2.0 |
fbalakirev/red-pitaya-notes | cores/gpio_level_trigger_v1_0/gpio_level_trigger.v | 2,225 | module MODULE1 #
(
parameter integer VAR4 = 16
parameter integer VAR12 = 32
)
(
input wire VAR1,
input wire VAR6,
input wire [VAR12-1:0] VAR27,
input wire VAR18,
output wire VAR28,
input wire VAR5,
output wire [VAR12-1:0] VAR23,
output wire VAR7,
inout wire [VAR4-1:0] VAR29,
input wire VAR19,
input wire [31:0] delay,
o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp.blackbox.v | 1,352 | module MODULE1 (
VAR3 ,
VAR1,
VAR7 ,
VAR5,
VAR6
);
output VAR3 ;
input VAR1;
input VAR7 ;
input VAR5;
input VAR6;
supply1 VAR4;
supply0 VAR2;
supply1 VAR9 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111o/sky130_fd_sc_lp__a2111o_2.v | 2,448 | module MODULE2 (
VAR8 ,
VAR10 ,
VAR5 ,
VAR7 ,
VAR1 ,
VAR12 ,
VAR2,
VAR6,
VAR4 ,
VAR11
);
output VAR8 ;
input VAR10 ;
input VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR12 ;
input VAR2;
input VAR6;
input VAR4 ;
input VAR11 ;
VAR9 VAR3 (
.VAR8(VAR8),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR12(VAR12),
.VAR2... | apache-2.0 |
sabertazimi/hust-lab | architecture/design/fpga/src/data_to_segment.v | 1,260 | module MODULE1
(
input [(VAR5-1):0] VAR2,
output [(VAR5*2)-1:0] VAR12
);
VAR13 VAR7 (
.VAR6(VAR2[3:0]),
.VAR12(VAR12[7:0])
);
VAR13 VAR11 (
.VAR6(VAR2[7:4]),
.VAR12(VAR12[15:8])
);
VAR13 VAR10 (
.VAR6(VAR2[11:8]),
.VAR12(VAR12[23:16])
);
VAR13 VAR4 (
.VAR6(VAR2[15:12]),
.VAR12(VAR12[31:24])
);
VAR13 VAR1 (
.VAR6(VAR2[1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2a/sky130_fd_sc_ls__o2bb2a.functional.pp.v | 2,171 | module MODULE1 (
VAR2 ,
VAR10,
VAR5,
VAR6 ,
VAR17 ,
VAR15,
VAR16,
VAR19 ,
VAR7
);
output VAR2 ;
input VAR10;
input VAR5;
input VAR6 ;
input VAR17 ;
input VAR15;
input VAR16;
input VAR19 ;
input VAR7 ;
wire VAR18 ;
wire VAR9 ;
wire VAR11 ;
wire VAR4;
nand VAR1 (VAR18 , VAR5, VAR10 );
or VAR8 (VAR9 , VAR17, VAR6 );
and V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill/sky130_fd_sc_ms__fill.pp.blackbox.v | 1,173 | module MODULE1 (
VAR2,
VAR1,
VAR3 ,
VAR4
);
input VAR2;
input VAR1;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
cpulabs/mist1032isa | src/core/pipeline_control/pipeline_control_idt_read.v | 3,969 | module MODULE1(
input wire VAR35,
input wire VAR3,
input wire VAR37,
input wire [31:0] VAR14,
input wire VAR22,
output wire VAR5,
output wire VAR30,
output wire VAR20,
input wire VAR34,
output wire [1:0] VAR19, output wire VAR36, output wire [13:0] VAR28,
output wire [1:0] VAR15,
output wire [31:0] VAR25,
output wire [... | bsd-2-clause |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cmn/vga_sync/vga_sync.v | 5,772 | module MODULE1
(
input wire clk, input wire rst,
output wire VAR11, output wire VAR19, output wire en, output wire [9:0] VAR29, output wire [9:0] VAR27, output wire [9:0] VAR10, output wire [9:0] VAR16 );
localparam VAR6 = 640; localparam VAR15 = 16; localparam VAR3 = 96; localparam VAR2 = 48; localparam VAR7 = 480; lo... | mit |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_fpu_div.v | 5,527 | module MODULE1
(
VAR33,
VAR14,
VAR12,
VAR15,
VAR20,
VAR6,
VAR29,
VAR22,
VAR23,
VAR9,
VAR5
);
parameter VAR36 = 32;
parameter VAR25 = 0; parameter VAR26 = 11; parameter VAR10 = 23;
parameter VAR27 = 8;
parameter VAR11 = 31'd0;
parameter VAR16 = 31'b1111111100000000000000000000000;
parameter VAR3 = 31'b111111111000000000... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_2.functional.v | 1,046 | module MODULE1( VAR1, VAR5, VAR6 );
input VAR1, VAR5;
output VAR6;
wire VAR4;
not VAR2( VAR4, VAR1 );
wire VAR3;
not VAR8( VAR3, VAR5 );
or VAR7( VAR6, VAR4, VAR3 );
endmodule | apache-2.0 |
dhytxz/PolyPC | hardware/ip_repo/hapara_bram_dma_dup_1.0/hapara_bram_dma_dup_v1_0.v | 1,824 | module MODULE1 #
(
parameter integer VAR11 = 32
)
(
input [VAR11 - 1 : 0] VAR20,
input [VAR11 - 1 : 0] VAR22,
output [VAR11 - 1 : 0] VAR3,
input [VAR11 / 8 - 1 : 0] VAR19,
input VAR5,
input VAR14,
input VAR2,
output [VAR11 - 1 : 0] VAR18,
output [VAR11 - 1 : 0] VAR8,
input [VAR11 - 1 : 0] VAR7,
output [VAR11 / 8 - 1 : ... | gpl-2.0 |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/a1f5/src/fmrv32im_axis_uart.v | 28,009 | module MODULE9
(
input VAR88,
input VAR55,
input [15:0] VAR197,
input [3:0] VAR158,
input [2:0] VAR52,
input VAR3,
output VAR97,
input [31:0] VAR156,
input [3:0] VAR160,
input VAR201,
output VAR200,
output VAR21,
input VAR151,
output [1:0] VAR62,
input [15:0] VAR75,
input [3:0] VAR117,
input [2:0] VAR163,
input VAR86,
... | mit |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/ip/base_zynq_design_auto_pc_0/synth/base_zynq_design_auto_pc_0.v | 12,826 | module MODULE1 (
VAR41,
VAR17,
VAR13,
VAR75,
VAR104,
VAR70,
VAR71,
VAR48,
VAR73,
VAR76,
VAR39,
VAR6,
VAR80,
VAR22,
VAR87,
VAR85,
VAR44,
VAR53,
VAR91,
VAR46,
VAR67,
VAR28,
VAR51,
VAR32,
VAR105,
VAR37,
VAR58,
VAR90,
VAR77,
VAR9,
VAR45,
VAR52,
VAR84,
VAR2,
VAR15,
VAR97,
VAR20,
VAR82,
VAR1,
VAR102,
VAR7,
VAR69,
VAR26,
VAR1... | gpl-3.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v | 11,251 | module MODULE1
parameter VAR17 = 32,
parameter VAR29 = 8,
parameter VAR57 = 10,
parameter VAR69 = 1,
parameter VAR7 = 4,
parameter VAR86 = 4,
parameter VAR8 = 2,
parameter VAR10 = 2,
parameter VAR51 = VAR17 / VAR29
)
(
input VAR44,
input VAR19,
input VAR60,
input VAR13,
output VAR30,
output [VAR17-1:0] VAR63,
output VA... | mit |
travisg/cpu | rtl/lib/library.v | 4,060 | module MODULE2 (
input [1:0] in,
output VAR22, VAR2, VAR8, VAR11
);
reg [3:0] out;
assign VAR22 = out[0];
assign VAR2 = out[1];
assign VAR8 = out[2];
assign VAR11 = out[3];
always @
case (in)
3'b000: out = 8'b00000001;
3'b001: out = 8'b00000010;
3'b010: out = 8'b00000100;
3'b011: out = 8'b00001000;
3'b100: out = 8'b000... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32o/sky130_fd_sc_hdll__a32o.pp.symbol.v | 1,439 | module MODULE1 (
input VAR9 ,
input VAR3 ,
input VAR10 ,
input VAR4 ,
input VAR6 ,
output VAR5 ,
input VAR1 ,
input VAR7,
input VAR2,
input VAR8
);
endmodule | apache-2.0 |
teknohog/rautanoppa | DE2-115/hwrandom.v | 1,465 | module MODULE2 (VAR15, VAR18, VAR4, VAR16, VAR6);
module MODULE2 (VAR15, VAR18, VAR6);
parameter VAR9 = VAR9;
parameter VAR9 = 1;
input VAR6;
wire reset;
assign reset = ~VAR6;
input VAR15;
wire clk;
output [VAR9-1:0] VAR18;
parameter VAR7 = 50000000;
VAR14 VAR10 (VAR15, clk);
parameter VAR2 = VAR2;
parameter VAR2 = 241... | gpl-3.0 |
asicguy/gplgpu | hdl/hbi/hbi_dout_stage.v | 8,444 | module MODULE1
(
input VAR41, input [31:0] VAR9, input [31:0] VAR21,
input [31:0] VAR5, input [31:0] VAR39, input [31:0] VAR8, input VAR1, input VAR25, input VAR46, input VAR24, input VAR29,
input VAR16, input [3:0] VAR32,
input VAR28, input VAR23, input VAR26,
input [31:0] VAR40, input VAR14,
input VAR45,
input VAR34,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22ai/sky130_fd_sc_hdll__o22ai_4.v | 2,368 | module MODULE2 (
VAR9 ,
VAR10 ,
VAR7 ,
VAR2 ,
VAR11 ,
VAR5,
VAR8,
VAR6 ,
VAR4
);
output VAR9 ;
input VAR10 ;
input VAR7 ;
input VAR2 ;
input VAR11 ;
input VAR5;
input VAR8;
input VAR6 ;
input VAR4 ;
VAR1 VAR3 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.... | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axic_fifo.v | 4,625 | module MODULE1 #
(
parameter VAR11 = "VAR21",
parameter integer VAR5 = 5, parameter integer VAR3 = 64, parameter VAR9 = "lut" )
(
input wire VAR17, input wire VAR12, input wire [VAR3-1:0] VAR10, input wire VAR6, output wire VAR13, output wire [VAR3-1:0] VAR22, output wire VAR2, input wire VAR18 );
VAR19 #(
.VAR11(VAR11... | gpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_std.v | 36,310 | module MODULE1 #
(
parameter VAR77 = 100,
parameter VAR237 = 64,
parameter VAR301 = "VAR265",
parameter VAR238 = "0", parameter VAR36 = 3, parameter VAR294 = 2, parameter VAR29 = "8", parameter VAR193 = "VAR213", parameter VAR101 = "VAR284", parameter VAR11 = 1, parameter VAR281 = 5,
parameter VAR86 = 12, parameter VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxtp/sky130_fd_sc_hs__edfxtp.functional.pp.v | 1,641 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR6 ,
VAR8 ,
VAR5,
VAR11
);
output VAR3 ;
input VAR4 ;
input VAR6 ;
input VAR8 ;
input VAR5;
input VAR11;
wire VAR2;
VAR7 VAR1 VAR10 (VAR2 , VAR6, VAR4, VAR8, VAR5, VAR11);
buf VAR9 (VAR3 , VAR2 );
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v | 9,397 | module MODULE1 (
VAR17, VAR8, VAR49, VAR12, VAR46, VAR59,
VAR11, VAR53, VAR48, VAR13, VAR61, VAR47,
VAR25, VAR41, VAR55, VAR4, VAR40, VAR26,
VAR57, VAR65, VAR16
);
parameter VAR35 = 32; parameter VAR32 = 32;
parameter VAR22 = 0; parameter VAR44 = 1;
output [VAR32-1:2] VAR47; output [31:0] VAR61; output [3:0] VAR13; out... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41a/sky130_fd_sc_hs__o41a.behavioral.pp.v | 1,948 | module MODULE1 (
VAR6,
VAR9,
VAR7 ,
VAR2 ,
VAR11 ,
VAR1 ,
VAR16 ,
VAR13
);
input VAR6;
input VAR9;
output VAR7 ;
input VAR2 ;
input VAR11 ;
input VAR1 ;
input VAR16 ;
input VAR13 ;
wire VAR16 VAR3 ;
wire VAR12 ;
wire VAR8;
or VAR5 (VAR3 , VAR16, VAR1, VAR11, VAR2 );
and VAR14 (VAR12 , VAR3, VAR13 );
VAR4 VAR10 (VAR8, V... | apache-2.0 |
jedimatt42/pi-messaging | hardware/tipi-speech/ise/tipi_top.v | 5,589 | module MODULE1(
output VAR54,
input[0:3] VAR62,
output VAR21,
output VAR23,
output VAR67,
output VAR34,
output VAR50,
output VAR55,
output VAR26,
input VAR49,
input VAR19,
input VAR53,
input VAR47,
input VAR43,
output VAR1,
output VAR56,
input VAR25,
input VAR44,
input VAR17,
input VAR40,
input VAR37,
output VAR30,
out... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4/sky130_fd_sc_hdll__nand4.symbol.v | 1,302 | module MODULE1 (
input VAR9,
input VAR4,
input VAR8,
input VAR3,
output VAR1
);
supply1 VAR7;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/ddr2/ddr2_usr_top.v | 7,016 | module MODULE1 #
(
parameter VAR10 = 2,
parameter VAR36 = 0,
parameter VAR20 = 10,
parameter VAR37 = 72,
parameter VAR3 = 8,
parameter VAR35 = 144,
parameter VAR43 = 0,
parameter VAR15 = 9,
parameter VAR24 = 14
)
(
input VAR21,
input VAR26, input VAR2,
input VAR16,
input [VAR37-1:0] VAR18,
input [VAR37-1:0] VAR8,
input... | mit |
oere/progressive-learning-platform | reference/hw/verilog/mod_sseg.v | 2,184 | module MODULE1(rst, clk, VAR7, VAR8, VAR12, VAR10, VAR4, din, VAR11, dout, VAR13, VAR5);
input rst;
input clk;
input VAR7,VAR8;
input [31:0] VAR12, VAR10;
input [1:0] VAR4;
input [31:0] din;
output [31:0] VAR11, dout;
output reg [3:0] VAR13;
output [7:0] VAR5;
wire [31:0] VAR1, VAR2;
assign VAR11 = VAR1;
assign dout = ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregrbp/sky130_fd_sc_lp__sregrbp.functional.v | 1,997 | module MODULE1 (
VAR11 ,
VAR16 ,
VAR8 ,
VAR13 ,
VAR7 ,
VAR6 ,
VAR4
);
output VAR11 ;
output VAR16 ;
input VAR8 ;
input VAR13 ;
input VAR7 ;
input VAR6 ;
input VAR4;
wire VAR14 ;
wire reset ;
wire VAR9;
not VAR15 (reset , VAR4 );
VAR12 VAR1 (VAR9, VAR13, VAR7, VAR6 );
VAR2 VAR5 VAR3 (VAR14 , VAR9, VAR8, reset);
buf VAR1... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/flop_rptrs_xb1.v | 33,057 | module MODULE1(
VAR59, VAR32, VAR34, VAR7, VAR48,
VAR29, VAR61, VAR3, VAR62,
VAR82, VAR17, VAR52, VAR74, VAR12, VAR51,
VAR5, VAR43, VAR11, VAR68, VAR28, VAR13,
VAR75
);
output [25:0] VAR62; output VAR3; output VAR61; output VAR29; output VAR48; output VAR7; output VAR34; output VAR32; output [5:0] VAR59;
input VAR75; i... | gpl-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/clock_gen/mmcm_drp.v | 21,398 | module MODULE1
parameter VAR5 = 5,
parameter VAR77 = 0,
parameter VAR27 = "VAR22",
parameter VAR56 = 1,
parameter VAR33 = 1,
parameter VAR74 = 0,
parameter VAR54 = 50000,
parameter VAR63 = 5,
parameter VAR46 = 0,
parameter VAR32 = "VAR22",
parameter VAR14 = 1,
parameter VAR72 = 1,
parameter VAR9 = 0,
parameter VAR44 = ... | mit |
gigglesninja/digital-system-design | Lab3_part2/ipcore_dir/mult12x12.v | 8,083 | module MODULE2 (
VAR56, VAR36, VAR2
);
output [23 : 0] VAR56;
input [11 : 0] VAR36;
input [11 : 0] VAR2;
wire \VAR16/VAR15 ;
wire \VAR16/VAR32 ;
wire \VAR44/VAR51<34>VAR30 ;
wire \VAR44/VAR51<33>VAR30 ;
wire \VAR44/VAR51<32>VAR30 ;
wire \VAR44/VAR51<31>VAR30 ;
wire \VAR44/VAR51<30>VAR30 ;
wire \VAR44/VAR51<29>VAR30 ;
w... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_barrier.v | 5,951 | module MODULE1
(
input VAR15
,input VAR12
,input [VAR17-1:0] VAR11 ,output [VAR17-1:0] VAR23
,input [VAR17-1:0] VAR6
,input [VAR18-1:0] VAR1
);
wire [VAR17:0] VAR3;
wire VAR5;
wire VAR10 = VAR3[VAR1];
wire VAR14, VAR22;
wire VAR19 = & (~VAR6 | VAR3[VAR17-1:0]); wire VAR7 = | (VAR6 & VAR3[VAR17-1:0]);
wire VAR16 = VAR22... | bsd-3-clause |
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