repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
jhennessy/parallella-hw-old | fpga/hdl/axi/axi_elink_if.v | 12,111 | module MODULE1 (
VAR83, VAR65, VAR34, VAR24,
VAR26, VAR21, VAR27,
VAR63, VAR49, VAR20,
VAR53, VAR64, VAR36,
VAR80, VAR99, VAR57,
VAR76, VAR81, VAR87,
VAR39, VAR67, VAR18,
VAR28, VAR82, VAR7,
VAR72, VAR38, VAR45,
VAR85, VAR25, VAR5,
VAR8, VAR55, reset, VAR3, VAR52,
VAR32, VAR58, VAR47,
VAR68, VAR30, VAR22,
VAR70, VAR46,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvp/sky130_fd_sc_ls__einvp_8.v | 2,130 | module MODULE2 (
VAR2 ,
VAR9 ,
VAR4 ,
VAR6,
VAR5,
VAR3 ,
VAR8
);
output VAR2 ;
input VAR9 ;
input VAR4 ;
input VAR6;
input VAR5;
input VAR3 ;
input VAR8 ;
VAR7 VAR1 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR2 ,
VAR9 ,
VAR4
);
output VAR2... | apache-2.0 |
hakehuang/pycpld | ips/ip/i2c_master/I2C_wr.v | 10,645 | module MODULE1(
VAR37,VAR14,ack,VAR9,clk,VAR1,VAR42,VAR44
);
input VAR9,VAR1,VAR42,clk;
output VAR14,ack;
inout [7:0] VAR44;
inout VAR37;
reg VAR20,VAR49;
reg[7:0] VAR10;
reg VAR14,ack,VAR50,VAR34,VAR53;
reg VAR48;
reg VAR39;
reg[8:0] VAR5;
reg[9:0] VAR6;
reg VAR36;
reg[6:0] VAR7;
reg[7:0] VAR12;
reg[7:0] VAR19;
reg[7:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfbbn/sky130_fd_sc_ls__sdfbbn.functional.v | 2,393 | module MODULE1 (
VAR6 ,
VAR19 ,
VAR21 ,
VAR1 ,
VAR17 ,
VAR15 ,
VAR13 ,
VAR3
);
output VAR6 ;
output VAR19 ;
input VAR21 ;
input VAR1 ;
input VAR17 ;
input VAR15 ;
input VAR13 ;
input VAR3;
wire VAR2 ;
wire VAR4 ;
wire VAR12 ;
wire VAR8 ;
wire VAR16;
not VAR23 (VAR2 , VAR3 );
not VAR7 (VAR4 , VAR13 );
not VAR5 (VAR12 , ... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/pcie_7x_v1_8_rxeq_scan.v | 13,367 | module MODULE1 #
(
parameter VAR20 = "VAR40", parameter VAR27 = 1, parameter VAR32 = 22'd3125000 )
(
input VAR46,
input VAR5,
input [ 1:0] VAR33,
input [ 2:0] VAR6,
input VAR41,
input [ 3:0] VAR1,
input [17:0] VAR8,
input VAR24,
input [ 5:0] VAR12,
input [ 5:0] VAR29,
output VAR31,
output [17:0] VAR30,
output VAR22,
ou... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinv/sky130_fd_sc_hdll__clkinv.pp.blackbox.v | 1,259 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR2,
VAR1,
VAR3 ,
VAR6
);
output VAR4 ;
input VAR5 ;
input VAR2;
input VAR1;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Instructions/Instructions_stub.v | 1,278 | module MODULE1(VAR1, VAR3, VAR2)
;
input VAR1;
input [9:0]VAR3;
output [799:0]VAR2;
endmodule | gpl-3.0 |
hmdgharb/5-Staged-MIPS-Pipeline | IF_STAGE.v | 1,045 | module MODULE1(
input clk,
input rst,
input VAR25,
input [5:0] VAR8,
input VAR4,
input VAR27,
output [7:0] VAR26,
output [15:0] VAR18
);
wire[7:0] VAR15;
wire[7:0] VAR21;
wire[7:0] VAR17;
wire[7:0] VAR14;
wire[7:0] VAR36;
wire[1:0] VAR2;
assign VAR2 = {VAR27, VAR4};
VAR5 VAR9(
.VAR7(VAR8),
.VAR12(VAR36)
);
VAR16 VAR19(... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/yf32/shifter.v | 5,040 | module MODULE1 (VAR10, VAR13, VAR20, VAR17);
input [31:0] VAR10;
input [ 4:0] VAR13;
input [ 1:0] VAR20;
output [31:0] VAR17;
wire [31: 0] VAR2 ;
wire [31: 0] VAR12 ;
wire [31: 0] VAR19 ;
wire [31: 0] VAR11 ;
wire [31: 0] VAR16;
wire [31: 0] VAR7 ;
wire [31: 0] VAR15 ;
wire [31: 0] VAR1 ;
wire [31: 0] VAR4 ;
wire [31: ... | mit |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/soc_system_sw_pio.v | 1,867 | module MODULE1 (
address,
clk,
VAR3,
VAR4,
VAR1
)
;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input clk;
input [ 9: 0] VAR3;
input VAR4;
wire VAR2;
wire [ 9: 0] VAR5;
wire [ 9: 0] VAR6;
reg [ 31: 0] VAR1;
assign VAR2 = 1;
assign VAR6 = {10 {(address == 0)}} & VAR5;
always @(posedge clk or negedge VAR4)
begin
if (VAR... | gpl-2.0 |
jkff90/design | avlst_n_to_1.v | 1,820 | module MODULE1 #(
parameter VAR15 = 8,
parameter VAR11 = 16,
)(
input VAR8,
input VAR2,
output VAR5,
input VAR12,
input [VAR15*VAR11-1:0] VAR14,
input VAR4,
output VAR3,
output [VAR11-1:0] VAR10
);
reg ready;
reg valid;
reg [VAR11-1:0] VAR6;
reg [VAR11-1:0] buffer [0:VAR15-1];
assign VAR5 = read;
assign VAR3 = valid;
a... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_processing_system7_0_2/zynq_design_1_processing_system7_0_2_stub.v | 5,382 | module MODULE1(VAR3, VAR53,
VAR61, VAR10, VAR11, VAR1,
VAR52, VAR29, VAR37, VAR15,
VAR39, VAR59, VAR13, VAR48, VAR30,
VAR36, VAR51, VAR55, VAR27,
VAR42, VAR35, VAR65, VAR20, VAR58,
VAR41, VAR12, VAR66, VAR62, VAR8,
VAR19, VAR32, VAR44, VAR33, VAR18,
VAR4, VAR45, VAR57, VAR63,
VAR56, VAR9, VAR47, VAR7, VAR43,
VAR60, VAR... | mit |
aap/pdp6 | verilog/memif_d.v | 1,569 | module MODULE1(
input wire clk,
input wire reset,
input wire [1:0] VAR9,
input wire VAR5,
input wire VAR13,
input wire [31:0] VAR6,
output reg [31:0] VAR4,
output wire VAR2,
output wire [31:0] VAR17,
output reg VAR15,
output reg VAR1,
output wire [63:0] VAR7,
input wire [63:0] VAR11,
input wire VAR18
);
reg [31:0] addr... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21bo/sky130_fd_sc_lp__a21bo_0.v | 2,318 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR5 ,
VAR6,
VAR2,
VAR4,
VAR10 ,
VAR1
);
output VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR6;
input VAR2;
input VAR4;
input VAR10 ;
input VAR1 ;
VAR8 VAR9 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR1(VAR1)
);
endmodule
module MODULE1 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50.functional.v | 1,343 | module MODULE1 (
VAR3,
VAR2
);
output VAR3;
input VAR2;
wire VAR5;
buf VAR4 (VAR5, VAR2 );
buf VAR1 (VAR3 , VAR5 );
endmodule | apache-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/clk_gen_83M.v | 7,435 | module MODULE1
( input VAR17,
output VAR72,
output VAR83,
output VAR23,
input VAR77,
output VAR2
);
VAR21 VAR30
(.VAR89 (VAR27),
.VAR70 (VAR17));
wire [15:0] VAR34;
wire VAR64;
wire VAR28;
wire VAR43;
wire VAR37;
wire VAR66;
wire VAR56;
wire VAR58;
wire VAR3;
wire VAR54;
wire VAR82;
wire VAR26;
wire VAR42;
wire VAR11;
... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/example_design/PIO_TO_CTRL.v | 3,734 | module MODULE1 #(
parameter VAR6 = 1
) (
input clk,
input VAR5,
input VAR2,
input VAR3,
input VAR4,
output reg VAR1
);
reg VAR7;
always @ ( posedge clk ) begin
if (!VAR5 )
begin
end
else
begin
if (!VAR7 && VAR2)
end
else if (VAR3)
end
end
always @ ( posedge clk ) begin
if (!VAR5 )
begin
end
else
begin
if ( VAR4 && !VAR... | lgpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi/bench/verilog/spi_slave_model.v | 3,637 | module MODULE1 (rst, VAR5, VAR7, VAR1, VAR4);
input rst; input VAR5; input VAR7; input VAR1; output VAR4;
reg VAR4;
reg VAR2; reg VAR6; reg [31:0] VAR3;
parameter VAR8 = 1;
always @(posedge(VAR7 && !VAR2) or negedge(VAR7 && VAR2) or rst)
begin
if (rst)
VAR3 <= #VAR8 32'b0;
end
else if (!VAR5)
VAR3 <= #VAR8 {VAR3[30:0],... | gpl-2.0 |
manu3193/ControladorElevadorTDD | Divisor_Frecuencia.v | 4,046 | module MODULE1 (
input VAR3, output VAR1
);
reg[31:0] VAR2 = 0; reg VAR1=0;
always @(posedge VAR3)
begin
if (VAR2 == 50000000-1) begin
VAR1 <= ~VAR1;
VAR2 <=0;
end
else
begin
VAR2 <= VAR2 + 1; end
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0n/sky130_fd_sc_lp__inputiso0n.behavioral.pp.v | 1,760 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR1,
VAR2 ,
VAR7 ,
VAR4 ,
VAR11
);
output VAR5 ;
input VAR10 ;
input VAR1;
input VAR2 ;
input VAR7 ;
input VAR4 ;
input VAR11 ;
wire VAR6;
and VAR8 (VAR6, VAR10, VAR1 );
VAR9 VAR3 (VAR5 , VAR6, VAR2, VAR7);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_one_hot.v | 1,881 | module MODULE1 #(parameter VAR9(VAR24)
, parameter VAR9(VAR12)
, parameter VAR19=VAR13(VAR12,1)
)
(input VAR14
, input VAR4
, input [VAR19-1:0] VAR5
, input [VAR24-1:0] VAR21
, input [VAR19-1:0] VAR23
, output logic [VAR24-1:0] VAR16
);
logic [VAR19-1:0][VAR24-1:0] VAR6;
wire VAR7 = VAR4;
for (genvar VAR2 = 0; VAR2 < V... | bsd-3-clause |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/uart/uart_rx.v | 3,407 | module MODULE1 (
input wire clk,
input wire reset,
output wire VAR25,
output reg VAR12,
output reg [VAR19] VAR4,
input wire VAR2
);
reg [VAR18] state;
reg [VAR23] VAR6;
reg [VAR5] VAR17;
assign VAR25 = (state != VAR20) ? VAR24 : VAR1;
always @(posedge clk or VAR11 reset) begin
if (reset == VAR7) begin
VAR12 <= VAR1;
VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2b/sky130_fd_sc_ls__nor2b.functional.pp.v | 1,969 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR2 ,
VAR1,
VAR11,
VAR7 ,
VAR9
);
output VAR6 ;
input VAR8 ;
input VAR2 ;
input VAR1;
input VAR11;
input VAR7 ;
input VAR9 ;
wire VAR15 ;
wire VAR5 ;
wire VAR12;
not VAR10 (VAR15 , VAR8 );
and VAR3 (VAR5 , VAR15, VAR2 );
VAR4 VAR13 (VAR12, VAR5, VAR1, VAR11);
buf VAR14 (VAR6 , VAR12 );
e... | apache-2.0 |
ineganov/bare_system | hard/datapath.v | 14,890 | module MODULE1 ( input VAR141,
input VAR114,
input VAR112,
input VAR56,
input VAR47, input VAR37, input VAR32, input VAR65, input [1:0] VAR119, input VAR85, input VAR44, input VAR105, input VAR134, input VAR79, input VAR39, input VAR18, input VAR118, input VAR30, input VAR21, input [6:0] VAR42, input [1:0] VAR4, input ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211o/sky130_fd_sc_lp__a211o.behavioral.pp.v | 2,032 | module MODULE1 (
VAR10 ,
VAR15 ,
VAR12 ,
VAR2 ,
VAR3 ,
VAR17,
VAR14,
VAR6 ,
VAR5
);
output VAR10 ;
input VAR15 ;
input VAR12 ;
input VAR2 ;
input VAR3 ;
input VAR17;
input VAR14;
input VAR6 ;
input VAR5 ;
wire VAR4 ;
wire VAR8 ;
wire VAR13;
and VAR16 (VAR4 , VAR15, VAR12 );
or VAR1 (VAR8 , VAR4, VAR3, VAR2 );
VAR11 VAR... | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_dsp/dac_buf.v | 9,164 | module MODULE1 (
VAR32,
VAR55,
VAR56,
VAR11,
VAR27,
VAR59);
input VAR32;
input [7:0] VAR55;
input [8:0] VAR56;
input [10:0] VAR11;
input VAR27;
output [31:0] VAR59;
tri1 VAR32;
tri0 VAR27;
wire [31:0] VAR2;
wire [31:0] VAR59 = VAR2[31:0];
VAR1 VAR26 (
.VAR5 (VAR11),
.VAR10 (VAR56),
.VAR25 (VAR32),
.VAR57 (VAR55),
.VAR5... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.v | 2,226 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR10 ,
VAR5 ,
VAR7,
VAR9,
VAR8 ,
VAR4
);
output VAR3 ;
output VAR6 ;
input VAR10 ;
input VAR5 ;
input VAR7;
input VAR9;
input VAR8 ;
input VAR4 ;
VAR2 VAR1 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4)
);
endmodule
module MODUL... | apache-2.0 |
HFoxtail/Mu80 | trunk/video.v | 2,285 | module MODULE1(
input wire VAR15,
input wire [7:0] VAR11,
output reg [13:0] addr,
output reg [4:0] VAR8,
output reg [5:0] VAR2,
output reg [4:0] VAR12,
output reg VAR14,
output reg VAR10
);
reg [9:0] VAR1;
reg [9:0] VAR7;
reg [7:0] VAR5;
reg [7:0] VAR6;
reg [7:0] VAR3;
wire [9:0] VAR13 = VAR1 - 8'd48;
wire [9:0] VAR9 =... | gpl-3.0 |
drom/quark | v/tail_offset.v | 3,858 | module MODULE1 (VAR21, VAR24, VAR59, VAR12, VAR44, VAR54, VAR3, VAR67, VAR32, VAR16, VAR41, VAR36, VAR46, VAR10, VAR6, VAR66, VAR51);
input [63:0] VAR21;
output [3:0] VAR24, VAR59, VAR12, VAR44, VAR54, VAR3, VAR67, VAR32, VAR16, VAR41, VAR36, VAR46, VAR10, VAR6, VAR66, VAR51;
reg [3:0] VAR24, VAR23, VAR52, VAR68, VAR76... | mit |
mlab-upenn/pvs | hdl_harness/clock_transmitter.v | 3,692 | module MODULE1
(
VAR12,
VAR2,
counter,
VAR27,
VAR14,
VAR15,
VAR1
);
input VAR12;
input VAR2;
input [31:0] counter;
input [7:0] VAR27;
input VAR14;
output VAR15;
output VAR1;
parameter VAR7 = 0;
parameter VAR9 = 1;
parameter VAR22 = 2;
parameter VAR17 = 3;
parameter VAR19 = 4;
reg[3:0] state = 4'd0;
reg[7:0] VAR3 = 8'd0... | gpl-3.0 |
robinsonb5/SegaToCD32 | SegaToCD32.cydsn/CD32Shifter/CD32Shifter.v | 7,121 | module MODULE1 (
output VAR9,
output VAR46,
output VAR31,
input VAR38,
input VAR33,
input VAR48
);
localparam VAR12=3'b000;
localparam VAR42=3'b001;
localparam VAR19=3'b010;
localparam VAR28=3'b011;
reg[2:0] VAR40;
localparam VAR10=2'b00;
localparam VAR27=2'b01;
localparam VAR36=2'b11;
reg[1:0] VAR18;
wire VAR35;
assig... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinv/sky130_fd_sc_hdll__clkinv_8.v | 2,052 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR5,
VAR1,
VAR6 ,
VAR4
);
output VAR8 ;
input VAR3 ;
input VAR5;
input VAR1;
input VAR6 ;
input VAR4 ;
VAR2 VAR7 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR8,
VAR3
);
output VAR8;
input VAR3;
supply1 VAR5;
supply0 VAR1;... | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/verilog/image_filter_mul_8ns_24ns_31_3.v | 1,411 | module MODULE1(clk, VAR5, VAR12, VAR10, VAR7);
input clk;
input VAR5;
input[8 - 1 : 0] VAR12; input[24 - 1 : 0] VAR10; output[31 - 1 : 0] VAR7;
reg [8 - 1 : 0] VAR11;
reg [24 - 1 : 0] VAR1;
wire [31 - 1 : 0] VAR9;
reg [31 - 1 : 0] VAR8;
assign VAR7 = VAR8;
assign VAR9 = VAR11 * VAR1;
always @ (posedge clk) begin
if (VA... | gpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/011J1G2/hdl/j1soc.v | 4,224 | module MODULE1#(
parameter VAR41 = "../VAR26/VAR30/VAR6.VAR11" )
(VAR22, VAR19,
VAR5, VAR32,
VAR43, VAR20,VAR8,VAR15,VAR46,VAR27, VAR47,VAR9);
input VAR5, VAR32;
output VAR22;
output VAR19;
input VAR20;
output VAR43;
output VAR15;
output VAR8;
output VAR46;
input VAR27;
output VAR14;
input VAR42;
wire VAR24; wire VAR28... | gpl-3.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_sram_cs.v | 1,884 | module MODULE1 (
address,
clk,
VAR4,
VAR5,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input VAR4;
input VAR5;
wire VAR1;
wire VAR2;
wire VAR6;
reg [ 31: 0] VAR3;
assign VAR1 = 1;
assign VAR6 = {1 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR5)
begin
if (VAR5 == 0)
VAR3 <= 0;
end
el... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrbp/sky130_fd_sc_ls__sdfrbp.behavioral.pp.v | 3,037 | module MODULE1 (
VAR4 ,
VAR28 ,
VAR12 ,
VAR30 ,
VAR17 ,
VAR29 ,
VAR33,
VAR1 ,
VAR7 ,
VAR9 ,
VAR31
);
output VAR4 ;
output VAR28 ;
input VAR12 ;
input VAR30 ;
input VAR17 ;
input VAR29 ;
input VAR33;
input VAR1 ;
input VAR7 ;
input VAR9 ;
input VAR31 ;
wire VAR23 ;
wire VAR10 ;
wire VAR8 ;
reg VAR26 ;
wire VAR3 ;
wire V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxtp/sky130_fd_sc_ms__dfxtp.blackbox.v | 1,262 | module MODULE1 (
VAR4 ,
VAR6,
VAR3
);
output VAR4 ;
input VAR6;
input VAR3 ;
supply1 VAR5;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc.pp.symbol.v | 1,359 | module MODULE1 (
input VAR1 ,
output VAR7 ,
input VAR5,
input VAR6 ,
input VAR4 ,
input VAR2 ,
input VAR3
);
endmodule | apache-2.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/soc_system/synthesis/submodules/altera_reset_controller.v | 12,017 | module MODULE1
parameter VAR72 = 6,
parameter VAR63 = 0,
parameter VAR45 = 0,
parameter VAR16 = 0,
parameter VAR44 = 0,
parameter VAR12 = 0,
parameter VAR62 = 0,
parameter VAR64 = 0,
parameter VAR17 = 0,
parameter VAR48 = 0,
parameter VAR78 = 0,
parameter VAR65 = 0,
parameter VAR35 = 0,
parameter VAR22 = 0,
parameter V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221o/sky130_fd_sc_ms__a221o.pp.blackbox.v | 1,428 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR1 ,
VAR8 ,
VAR4 ,
VAR2 ,
VAR7,
VAR6,
VAR3 ,
VAR10
);
output VAR9 ;
input VAR5 ;
input VAR1 ;
input VAR8 ;
input VAR4 ;
input VAR2 ;
input VAR7;
input VAR6;
input VAR3 ;
input VAR10 ;
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_obc1/main.v | 23,107 | module MODULE1(
output [22:0] VAR173,
output VAR116,
input VAR62,
output VAR250,
input VAR268,
output [21:0] VAR173,
output VAR349,
output VAR32,
output VAR277,
output VAR93,
output VAR141,
input VAR82,
input VAR256,
input [23:0] VAR30,
input VAR246,
input VAR52,
input VAR121,
inout [7:0] VAR244,
input VAR162,
input VA... | gpl-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_addr_arbiter.v | 13,806 | module MODULE1 #
(
parameter VAR37 = "none",
parameter integer VAR39 = 1,
parameter integer VAR56 = 1,
parameter integer VAR66 = 1,
parameter integer VAR11 = 1,
parameter [VAR39*32-1:0] VAR23 = {VAR39{32'h00000000}}
)
(
input wire VAR22,
input wire VAR43,
input wire [VAR39*VAR11-1:0] VAR32,
input wire [VAR39*VAR66-1:0]... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/phy/of_pre_fifo.v | 8,233 | module MODULE1 #
(
parameter VAR9 = 100, parameter VAR12 = 4, parameter VAR29 = 32 )
(
input clk, input rst, input VAR31, input VAR30, input [VAR29-1:0] din, output VAR25, output [VAR29-1:0] dout );
localparam VAR33
= (VAR12 == 2) ? 1 :
((VAR12 == 3) || (VAR12 == 4)) ? 2 :
(((VAR12 == 5) || (VAR12 == 6) ||
(VAR12 == 7)... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/macro_sparecell/sky130_fd_sc_hd__macro_sparecell.symbol.v | 1,426 | module MODULE1 (
output VAR4
);
supply0 VAR3;
supply0 VAR1 ;
supply1 VAR2 ;
supply1 VAR5;
endmodule | apache-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Cache/L1/Cache_Control.v | 8,716 | module MODULE1(
input [29:0] VAR31,
input [3:0] VAR13,
input VAR27,
output VAR2,
input VAR5,
output VAR15,
output [29:0] VAR36,
output VAR7,
output VAR38,
input VAR1,
output [3:0] VAR37,
output [6:0] VAR18,
output [3:0] VAR45,
input VAR43,
output VAR12,
output VAR32,
input VAR30,
input [18:0] VAR8,
output VAR17,
output... | lgpl-3.0 |
Jawanga/ece385final | finalproject/synthesis/submodules/finalproject_cpu_jtag_debug_module_tck.v | 8,421 | module MODULE1 (
VAR24,
VAR27,
VAR26,
VAR11,
VAR17,
VAR37,
VAR14,
VAR35,
VAR20,
VAR1,
VAR23,
VAR28,
VAR12,
VAR29,
VAR2,
VAR6,
VAR8,
VAR5,
VAR16,
VAR21,
VAR4,
VAR22,
VAR34,
VAR40,
VAR15,
VAR3,
VAR31,
VAR7,
VAR19,
VAR33,
VAR25
)
;
output [ 1: 0] VAR31;
output VAR7;
output [ 37: 0] VAR19;
output VAR33;
output VAR25;
input... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_controller.v | 4,421 | module MODULE1(
clk ,
VAR10 ,
VAR12 ,
VAR13 ,
VAR9 ,
state
);
input clk ;
input VAR10 ;
input VAR12 ;
output reg VAR13 ;
output reg [8:0] VAR9 ;
output reg [2:0] state ;
parameter VAR17 = 3'b000, VAR8 = 3'b001, VAR1 = 3'b011,VAR3 =3'b010;
parameter VAR4 = 3'b110, VAR5 = 3'b111, VAR16 = 3'b101,VAR14 =3'b100;
reg [2:0] V... | gpl-3.0 |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/5d65/src/fmrv32im_csr.v | 18,676 | module MODULE1
(
input VAR52,
input VAR6,
input [11:0] VAR44,
input VAR71,
input [31:0] VAR85,
input [31:0] VAR60,
output reg [31:0] VAR78,
input VAR106,
input VAR34,
input [31:0] VAR33,
input VAR74,
input [11:0] VAR23,
input [31:0] VAR42,
input [31:0] VAR41,
input VAR49,
input VAR116,
output wire [31:0] VAR28,
output ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3/sky130_fd_sc_hd__and3.behavioral.v | 1,371 | module MODULE1 (
VAR9,
VAR1,
VAR11,
VAR10
);
output VAR9;
input VAR1;
input VAR11;
input VAR10;
supply1 VAR8;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR6 ;
wire VAR3;
and VAR7 (VAR3, VAR10, VAR1, VAR11 );
buf VAR4 (VAR9 , VAR3 );
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/ciaa_ps2keyboard_map.v | 32,967 | module MODULE1
(
input clk, input VAR21,
input reset, input enable, input [7:0] VAR4, output valid, output [7:0] VAR7, output VAR13, output VAR37, output VAR12, output VAR24, output reg VAR27 = 0, output reg [7:0] VAR29, output reg VAR36, output reg VAR26, output reg [5:0] VAR28, output reg VAR38, output [5:0] VAR39,
o... | gpl-3.0 |
asicguy/gplgpu | hdl/hbi/hbi_lut_u.v | 21,645 | module MODULE1
(
input VAR4,
input [7:0] VAR5,
output reg [9:0] VAR3,
output reg [9:0] VAR2
);
reg [7:0] VAR1;
always @(posedge VAR4) begin
case(VAR5)
8'd0: VAR3 <= 10'h244;
8'd1: VAR3 <= 10'h248;
8'd2: VAR3 <= 10'h24B;
8'd3: VAR3 <= 10'h24F;
8'd4: VAR3 <= 10'h252;
8'd5: VAR3 <= 10'h256;
8'd6: VAR3 <= 10'h259;
8'd7: VA... | gpl-3.0 |
cpulabs/mist1032isa | src/core/execute/execute_jump.v | 6,502 | module MODULE1(
input wire VAR42,
input wire VAR2,
input wire VAR21,
input wire VAR15,
input wire VAR24,
input wire VAR25,
input wire VAR12,
input wire VAR40,
input wire VAR6,
input wire VAR16,
input wire VAR19,
input wire VAR39,
input wire [31:0] VAR8,
input wire VAR28,
input wire VAR44,
input wire VAR3,
input wire VA... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ba/sky130_fd_sc_lp__o21ba_1.v | 2,316 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR4 ,
VAR9,
VAR1,
VAR5,
VAR8 ,
VAR10
);
output VAR2 ;
input VAR6 ;
input VAR4 ;
input VAR9;
input VAR1;
input VAR5;
input VAR8 ;
input VAR10 ;
VAR3 VAR7 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10(VAR10)
);
endmodule
module MODULE1 ... | apache-2.0 |
jameshegarty/rigel | platform/camera/vsrc/MMIO_slave.v | 8,994 | module MODULE1(
input VAR15,
input VAR111,
output VAR12,
input [31:0] VAR110,
input [11:0] VAR78,
output VAR81,
input VAR93,
input [31:0] VAR97,
input [11:0] VAR96,
output VAR34,
input VAR10,
output [11:0] VAR48,
input VAR65,
output [1:0] VAR49,
output VAR86,
output [31:0] VAR56,
output [11:0] VAR88,
output VAR3,
input... | mit |
prernaa/CPUVerilog | mem_wb.v | 2,140 | module MODULE1(clk, VAR8, VAR4,
VAR20, VAR12, VAR10, VAR2,
VAR5, VAR25, VAR11, VAR1, VAR17, VAR26,
VAR9, VAR21,
VAR16, VAR7,
VAR27, VAR22
);
input clk;
input VAR8;
input VAR4;
input VAR20;
input [3:0] VAR12;
input [15:0] VAR10;
input [15:0] VAR2;
input [15:0] VAR16;
input VAR27;
input VAR9;
output VAR21;
output VAR5;
o... | mit |
mistryalok/Zedboard | learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/generic_baseblocks_v2_1/da89d453/hdl/verilog/generic_baseblocks_v2_1_carry.v | 4,334 | module MODULE1 #
(
parameter VAR7 = "VAR3"
)
(
input wire VAR9,
input wire VAR2,
input wire VAR4,
output wire VAR6
);
generate
if ( VAR7 == "VAR11" ) begin : VAR13
assign VAR6 = (VAR9 & VAR2) | (VAR4 & ~VAR2);
end else begin : VAR1
VAR10 VAR12
(
.VAR5 (VAR6),
.VAR8 (VAR9),
.VAR4 (VAR4),
.VAR2 (VAR2)
);
end
endgenerate
... | gpl-3.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_hps_0.v | 31,602 | module MODULE1 #(
parameter VAR47 = 2,
parameter VAR101 = 2
) (
output wire VAR118, input wire VAR119, input wire VAR43, input wire VAR124, input wire [27:0] VAR115, input wire VAR126, input wire [7:0] VAR100, input wire [31:0] VAR26, input wire [3:0] VAR165, input wire [2:0] VAR59, input wire [1:0] VAR145, input wire ... | gpl-2.0 |
azonenberg/openfpga | hdl/xc2c-model/ConfigurableEdgeLatch.v | 3,129 | module MODULE1(
VAR3, clk, VAR7, VAR1, VAR6, VAR2
);
input wire VAR3;
input wire clk;
output wire VAR6;
input wire VAR7;
input wire VAR1;
input wire VAR2;
reg VAR4;
always @ begin
if(!clk)
VAR5 <= VAR3;
if(VAR7)
VAR5 <= VAR1;
end
assign VAR6 = VAR2 ? VAR4 : VAR5;
endmodule | lgpl-2.1 |
cafe-alpha/wascafe | v11/fpga_firmware/wasca/synthesis/submodules/sd_crc_16.v | 1,434 | module MODULE1(VAR6, VAR1, VAR4, VAR5, VAR3);
input VAR6; input VAR1;
input VAR4; input VAR5; output reg [15:0] VAR3;
wire VAR2;
assign VAR2 = VAR6 ^ VAR3[15];
always @(posedge VAR4 or posedge VAR5) begin
if (VAR5) begin
VAR3 = 0;
end
else begin
if (VAR1==1) begin
VAR3[15] = VAR3[14];
VAR3[14] = VAR3[13];
VAR3[13] = VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32a/sky130_fd_sc_ms__o32a_2.v | 2,428 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR3 ,
VAR9 ,
VAR5 ,
VAR8 ,
VAR10,
VAR11,
VAR1 ,
VAR4
);
output VAR2 ;
input VAR7 ;
input VAR3 ;
input VAR9 ;
input VAR5 ;
input VAR8 ;
input VAR10;
input VAR11;
input VAR1 ;
input VAR4 ;
VAR6 VAR12 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10(VAR... | apache-2.0 |
plindstroem/oh | xilibs/hdl/ISERDESE2.v | 3,518 | module MODULE1 (
VAR30, VAR39, VAR32, VAR2, VAR9, VAR33, VAR31, VAR45, VAR27, VAR34, VAR16,
VAR11, VAR44, VAR47, VAR24, VAR22, VAR8, VAR25, VAR7, VAR36,
VAR41, VAR19, VAR29, VAR28, VAR35, VAR5, VAR4, VAR12
);
parameter VAR43 = 0; parameter VAR20 = 0; parameter VAR21 = 0; parameter VAR46 = 0; parameter VAR1 = 0; paramet... | gpl-3.0 |
mcoughli/root_of_trust | experiments/secure_filesystem/secure_filesystem_hls/solution1/syn/verilog/filesystem_encrypbkb.v | 1,969 | module MODULE1 (VAR18, VAR8, VAR14, VAR4, VAR11, VAR19, VAR3, VAR15, VAR1, VAR9, clk);
parameter VAR20 = 128;
parameter VAR10 = 5;
parameter VAR2 = 32;
input[VAR10-1:0] VAR18;
input VAR8;
input[VAR20-1:0] VAR14;
input VAR4;
output reg[VAR20-1:0] VAR11;
input[VAR10-1:0] VAR19;
input VAR3;
input[VAR20-1:0] VAR15;
input V... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_jesd_align/util_jesd_align.v | 3,275 | module MODULE1 (
VAR7,
VAR9,
VAR1,
VAR3,
VAR8);
parameter VAR10 = 2;
input VAR7;
input [ 3:0] VAR9;
input [((VAR10*32)-1):0] VAR1;
output [((VAR10* 1)-1):0] VAR3;
output [((VAR10*32)-1):0] VAR8;
genvar VAR2;
generate
for (VAR2 = 0; VAR2 < VAR10; VAR2 = VAR2 + 1) begin: VAR5
VAR4 VAR6 (
.VAR7 (VAR7),
.VAR9 (VAR9),
.VAR1... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/NVMeHostController4L/src/pcie_hcmd_cq.v | 8,265 | module MODULE1 # (
parameter VAR10 = 128,
parameter VAR3 = 36
)
(
input VAR60,
input VAR87,
output [6:0] VAR31,
input [19:0] VAR91,
input [VAR3-1:2] VAR55,
input [7:0] VAR37,
output [7:0] VAR68,
output [7:0] VAR33,
output [7:0] VAR38,
output [7:0] VAR44,
output [7:0] VAR61,
output [7:0] VAR83,
output [7:0] VAR95,
outpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3/sky130_fd_sc_hd__nand3.symbol.v | 1,280 | module MODULE1 (
input VAR6,
input VAR8,
input VAR3,
output VAR5
);
supply1 VAR7;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_receivecontrol.v | 13,701 | module MODULE1 (VAR51, VAR55, VAR49, VAR44, VAR22, VAR45, VAR53,
VAR38, VAR11, VAR26, VAR10, VAR32, VAR17,
VAR48, VAR43, VAR59, VAR13,
VAR31, VAR18, VAR23, VAR20,
VAR7, VAR42, VAR8
);
input VAR51;
input VAR55;
input VAR49;
input VAR44;
input [7:0] VAR22;
input VAR45;
input VAR53;
input VAR38;
input VAR11;
input VAR26;
... | gpl-2.0 |
ultraembedded/altor32 | rtl/peripheral/uart.v | 9,016 | module MODULE1
(
VAR13,
VAR24,
VAR11,
VAR5,
VAR7,
VAR19,
VAR1,
VAR21,
VAR8,
VAR14,
VAR10
);
parameter [31:0] VAR15 = 278;
input VAR13 ;
input VAR24 ;
input [7:0] VAR19 ;
output [7:0] VAR21 ;
input VAR1 ;
input VAR8 ;
output VAR11 ;
output VAR5 ;
output VAR7 ;
input VAR14 ;
output VAR10 ;
parameter VAR4 = VAR15;
paramet... | lgpl-3.0 |
jameshegarty/rigel | platform/camera2.0/vsrc/DramReaderBuf.v | 4,591 | module MODULE1(
input VAR40,
input VAR28,
output VAR39,
output reg VAR8,
input VAR14,
output reg [31:0] VAR1,
output [1:0] VAR42,
output [3:0] VAR11,
output [1:0] VAR19,
input VAR21,
output VAR38,
input VAR6,
input [63:0] VAR16,
input [1:0] VAR22,
input VAR18,
output reg VAR24,
input [31:0] VAR9,
input [31:0] VAR2,
out... | mit |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_wdog.v | 11,018 | module MODULE1(
input VAR69,
input reset,
input VAR52,
input [31:0] VAR124,
output [31:0] VAR94,
input VAR131,
input [31:0] VAR21,
output [31:0] VAR73,
input VAR19,
input [31:0] VAR98,
output [31:0] VAR55,
input VAR10,
input [15:0] VAR72,
output [15:0] VAR121,
input VAR41,
input [15:0] VAR34,
output [15:0] VAR50,
input... | apache-2.0 |
cthulhuology/avm | alu.v | 2,573 | module MODULE1 (
input VAR6,
input [7:0] VAR2,
input [VAR4-1:0] VAR8,
input [VAR4-1:0] VAR1,
output [VAR4-1:0] VAR7,
output [VAR4-1:0] VAR3);
reg [VAR4-1:0] VAR8;
reg [VAR4-1:0] VAR1;
reg [VAR4*2-1:0] VAR5;
assign VAR7 = VAR8;
assign VAR3 = VAR1;
always @(posedge VAR6) begin
case(VAR2)
8'b00000100:
VAR8 <= - VAR8;
8'b0... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/inv/sky130_fd_sc_ms__inv.behavioral.v | 1,321 | module MODULE1 (
VAR3,
VAR4
);
output VAR3;
input VAR4;
supply1 VAR8;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR6 ;
wire VAR9;
not VAR2 (VAR9, VAR4 );
buf VAR1 (VAR3 , VAR9 );
endmodule | apache-2.0 |
hoglet67/CoPro6502 | src/amber23/a23_alu.v | 7,595 | module MODULE1 (
input [31:0] VAR32,
input [31:0] VAR2,
input VAR36,
input VAR31,
input [8:0] VAR1,
output [31:0] VAR26,
output [3:0] VAR9 );
wire [31:0] VAR28, VAR10, VAR13;
wire [31:0] VAR24, VAR15, VAR3;
wire [31:0] VAR30, VAR6;
wire [31:0] VAR16, VAR22;
wire [32:0] VAR19;
wire VAR34;
wire VAR33;
wire [1:0] VAR14;
w... | gpl-3.0 |
CospanDesign/vivado-ip-cores | ip/axi_lite_i2c/sources_1/i2c_master_bit_ctrl.v | 20,675 | module MODULE1 (
input clk, input rst, input VAR25, input VAR50,
input [15:0] VAR8,
input [ 3:0] VAR31, output reg VAR5, output reg VAR27, output reg VAR6,
input din,
output reg dout = 0,
input VAR11, output VAR21, output reg VAR14, input VAR9, output VAR44, output reg VAR7 );
reg [ 1:0] VAR10, VAR16; reg [ 2:0] VAR30,... | mit |
ptracton/wb_soc_template | rtl/ZIP/rtl/busdelay.v | 6,251 | module MODULE1(VAR22,
VAR9, VAR23, VAR4, VAR26, VAR28, VAR5,
VAR27, VAR18, VAR6, VAR12,
VAR29, VAR7, VAR13, VAR17,VAR2,VAR11,
VAR24, VAR19, VAR16, VAR1);
parameter VAR20=32, VAR30=32, VAR31 = 0;
input wire VAR22;
input wire VAR9, VAR23, VAR4;
input wire [(VAR20-1):0] VAR26;
input wire [(VAR30-1):0] VAR28;
input wire [(... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ai/sky130_fd_sc_lp__o21ai.behavioral.v | 1,530 | module MODULE1 (
VAR5 ,
VAR9,
VAR10,
VAR3
);
output VAR5 ;
input VAR9;
input VAR10;
input VAR3;
supply1 VAR13;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR4 ;
wire VAR11 ;
wire VAR12;
or VAR1 (VAR11 , VAR10, VAR9 );
nand VAR8 (VAR12, VAR3, VAR11 );
buf VAR2 (VAR5 , VAR12 );
endmodule | apache-2.0 |
P3Stor/P3Stor | pcie/IP core/gc_command_fifo.v | 13,466 | module MODULE1(
clk,
rst,
din,
VAR20,
VAR152,
dout,
VAR258,
VAR305,
VAR392,
VAR285
);
input clk;
input rst;
input [28 : 0] din;
input VAR20;
input VAR152;
output [28 : 0] dout;
output VAR258;
output VAR305;
output [4 : 0] VAR392;
output VAR285;
VAR23 #(
.VAR95(0),
.VAR174(0),
.VAR220(0),
.VAR4(0),
.VAR102(0),
.VAR58(0)... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyc/gf180mcu_fd_sc_mcu7t5v0__dlyc_1.behavioral.v | 1,098 | module MODULE1( VAR3, VAR2 );
input VAR3;
output VAR2;
VAR4 VAR5(.VAR3(VAR3),.VAR2(VAR2));
VAR4 VAR1(.VAR3(VAR3),.VAR2(VAR2)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_1.functional.v | 1,838 | module MODULE1( VAR3, VAR19, VAR8, VAR7, VAR1, VAR17, VAR2 );
input VAR1, VAR17, VAR2, VAR8, VAR19, VAR3;
output VAR7;
wire VAR12;
not VAR14( VAR12, VAR1 );
wire VAR18;
not VAR23( VAR18, VAR17 );
wire VAR24;
not VAR5( VAR24, VAR2 );
wire VAR20;
and VAR4( VAR20, VAR12, VAR18, VAR24 );
wire VAR10;
not VAR9( VAR10, VAR8 )... | apache-2.0 |
sirchuckalot/zet | cores/speaker/wm8731/speaker_i2c_controller.v | 4,169 | module MODULE1 (
VAR12,
VAR2, VAR13, VAR10, VAR5, VAR9, VAR14, VAR4, VAR1
);
input VAR12;
input [23:0]VAR10;
input VAR5;
input VAR1;
input VAR14;
inout VAR13;
output VAR2;
output VAR9;
output VAR4;
reg VAR17;
reg VAR3;
reg VAR9;
reg [23:0]VAR7;
reg [5:0]VAR11;
wire VAR2=VAR3 | ( ((VAR11 >= 4) & (VAR11 <=30))? ~VAR12 :1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrbp/sky130_fd_sc_hs__dfrbp.symbol.v | 1,387 | module MODULE1 (
input VAR3 ,
output VAR4 ,
output VAR2 ,
input VAR6,
input VAR5
);
supply1 VAR1;
supply0 VAR7;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2o/sky130_fd_sc_ls__a2bb2o_1.v | 2,463 | module MODULE2 (
VAR6 ,
VAR10,
VAR7,
VAR1 ,
VAR3 ,
VAR5,
VAR4,
VAR9 ,
VAR8
);
output VAR6 ;
input VAR10;
input VAR7;
input VAR1 ;
input VAR3 ;
input VAR5;
input VAR4;
input VAR9 ;
input VAR8 ;
VAR11 VAR2 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR8(VA... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/common/rtl/swrvr_clib.v | 21,511 | module MODULE5 (din, clk, VAR21, VAR13, VAR16, VAR9);
parameter VAR25 = 1;
input [VAR25-1:0] din ; input clk ;
output [VAR25-1:0] VAR21 ;
input VAR13 ; input [VAR25-1:0] VAR16 ; output [VAR25-1:0] VAR9 ;
reg [VAR25-1:0] VAR21 ;
always @ (posedge clk)
VAR21[VAR25-1:0] <= din[VAR25-1:0] ;
always @ (posedge clk)
VAR21[VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111o/sky130_fd_sc_ls__a2111o.functional.pp.v | 2,070 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR9 ,
VAR13 ,
VAR7 ,
VAR11 ,
VAR1,
VAR16,
VAR18 ,
VAR12
);
output VAR3 ;
input VAR8 ;
input VAR9 ;
input VAR13 ;
input VAR7 ;
input VAR11 ;
input VAR1;
input VAR16;
input VAR18 ;
input VAR12 ;
wire VAR15 ;
wire VAR4 ;
wire VAR10;
and VAR6 (VAR15 , VAR8, VAR9 );
or VAR5 (VAR4 , VAR7, VAR1... | apache-2.0 |
jmacneal/Design-Project | Display/Audio_Controller/Altera_UP_Audio_Bit_Counter.v | 3,924 | module MODULE1 (
clk,
reset,
VAR6,
VAR1,
VAR8,
VAR3,
VAR4
);
parameter VAR5 = 5'd31;
input clk;
input reset;
input VAR6;
input VAR1;
input VAR8;
input VAR3;
output reg VAR4;
wire VAR2;
reg [4:0] VAR7;
always @(posedge clk)
begin
if (reset == 1'b1)
VAR7 <= 5'h00;
end
else if (VAR2 == 1'b1)
VAR7 <= VAR5;
else if ((VAR1 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxtp/sky130_fd_sc_ls__dfxtp.behavioral.pp.v | 1,788 | module MODULE1 (
VAR14 ,
VAR5 ,
VAR11 ,
VAR3,
VAR9,
VAR10 ,
VAR8
);
output VAR14 ;
input VAR5 ;
input VAR11 ;
input VAR3;
input VAR9;
input VAR10 ;
input VAR8 ;
wire VAR15 ;
reg VAR4 ;
wire VAR7 ;
wire VAR1;
wire VAR2 ;
VAR13 VAR12 (VAR15 , VAR7, VAR1, VAR4, VAR3, VAR9);
assign VAR2 = ( VAR3 === 1'b1 );
buf VAR6 (VAR14... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.v | 2,329 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR2 ,
VAR4,
VAR10 ,
VAR8 ,
VAR7 ,
VAR1
);
output VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR4;
input VAR10 ;
input VAR8 ;
input VAR7 ;
input VAR1 ;
VAR9 VAR3 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODU... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/atr_controller16.v | 2,660 | module MODULE1
(input VAR2, input VAR7,
input [5:0] VAR15, input [1:0] VAR19, input [15:0] VAR14, output [15:0] VAR11,
input VAR17, input VAR5, input VAR16, output reg VAR13,
input VAR6, input VAR8,
output [31:0] VAR4);
reg [3:0] state;
reg [31:0] VAR1 [0:15];
wire [3:0] VAR12 = { (VAR19[1] & VAR15[1]), (VAR19[0] & VAR... | gpl-2.0 |
nyaxt/dmix | mpemu.v | 2,155 | module MODULE2(
input wire clk,
input wire [23:0] VAR2,
input wire [23:0] VAR3,
output wire [27:0] VAR10);
VAR6 VAR6(
.clk(clk),
.VAR17(VAR2),
.VAR4(VAR3),
.VAR9(VAR10));
reg [23:0] VAR1[4:0];
reg [23:0] VAR7[4:0];
always @(posedge clk) begin
VAR1[0] <= VAR2;
VAR1[1] <= VAR1[0];
VAR1[2] <= VAR1[1];
VAR1[3] <= VAR1[2];
... | mit |
lynxis/lpc_sniffer | top.v | 3,052 | module MODULE1 #(parameter VAR60 = 33000000, parameter VAR1 = 921600)
(
input [3:0] VAR59,
input VAR36,
input VAR11,
input VAR40,
input VAR68,
input VAR15,
input VAR61,
output VAR52,
output VAR31,
output VAR51,
output VAR35,
output VAR26,
output VAR65,
output VAR21);
wire reset;
wire [3:0] VAR59;
wire [3:0] VAR23;
wire... | gpl-3.0 |
Fairyland0902/BlockyRoads | src/BlockyRoads/x7segbc.v | 3,227 | module MODULE1(
input wire clk,
input wire [31:0] VAR1,
output reg [ 6:0] VAR2,
output reg [ 7:0] VAR6,
output wire VAR8
);
wire [ 2:0] VAR5;
reg [ 4:0] VAR4;
wire [ 7:0] VAR7;
reg [19:0] VAR3;
assign VAR8 = 1;
assign VAR5 = VAR3[19:17];
assign VAR7[7] = VAR1[31] | VAR1[30] | VAR1[29] | VAR1[28];
assign VAR7[6] = VAR1[... | mit |
chebykinn/university | circuitry/lab3/src/hdl/mem_stage.v | 1,805 | module MODULE1 (
input clk,
input rst,
input VAR7,
input VAR18,
input [31:0] VAR8,
input [31:0] VAR12,
input [4:0] VAR4,
input VAR11,
input VAR9,
input VAR16,
output reg [4:0] VAR2,
output reg VAR17,
output reg VAR1,
output reg [31:0] VAR15,
output reg [31:0] VAR6,
output VAR5,
output VAR14,
output [31:0] VAR13,
output... | mit |
esonghori/TinyGarbled | circuit_synthesis/mips/Bus_Mux.v | 2,209 | module MODULE1
(
VAR15,
VAR10,
VAR12,
VAR9,
VAR2,
VAR5,
VAR6,
VAR11,
VAR4,
VAR3,
VAR8,
VAR14,
VAR13,
VAR7,
VAR1
);
input [15:0] VAR15;
input [31:0] VAR10;
input [1:0] VAR12;
output [31:0] VAR9;
reg [31:0] VAR9;
input [31:0] VAR2;
input [1:0] VAR5;
output [31:0] VAR6;
reg [31:0] VAR6;
input [31:0] VAR11;
input [31:0] VA... | gpl-3.0 |
jbelloncastro/amber_arm | hw/vlog/system/uart.v | 36,620 | module MODULE1 #(
parameter VAR70 = 32,
parameter VAR104 = 4
)(
input VAR21,
input [31:0] VAR55,
input [VAR104-1:0] VAR125,
input VAR102,
output [VAR70-1:0] VAR68,
input [VAR70-1:0] VAR82,
input VAR38,
input VAR7,
output VAR73,
output VAR44,
output VAR119,
input VAR72, output VAR30, output VAR48, input VAR18
);
localpa... | lgpl-3.0 |
peteasa/oh | src/common/hdl/oh_iddr.v | 1,317 | module MODULE1 #(parameter VAR2 = 1 )
(
input clk, input VAR5, input [VAR2-1:0] din, output reg [VAR2-1:0] VAR1, output reg [VAR2-1:0] VAR4 );
reg [VAR2-1:0] VAR6;
reg [VAR2-1:0] VAR3;
always @ (posedge clk)
if(VAR5)
VAR6[VAR2-1:0] <= din[VAR2-1:0];
always @ (negedge clk)
VAR3[VAR2-1:0] <= din[VAR2-1:0];
always @ (pose... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/ACA_II_N16_Q4_syn.v | 2,977 | module MODULE1 ( VAR76, VAR4, VAR67 );
input [15:0] VAR76;
input [15:0] VAR4;
output [16:0] VAR67;
wire VAR72, VAR50, VAR14, VAR52, VAR73, VAR25, VAR70, VAR13, VAR63, VAR71, VAR51, VAR53, VAR23, VAR47,
VAR16, VAR24, VAR22, VAR84, VAR75, VAR3, VAR54, VAR69, VAR9, VAR36, VAR41, VAR7, VAR48;
VAR18 VAR66 ( .VAR46(VAR4[7]),... | gpl-3.0 |
kyzhai/NUNY | src/hardware/lab3/synthesis/submodules/altera_avalon_st_pipeline_base.v | 4,581 | module MODULE1 (
clk,
reset,
VAR2,
VAR1,
VAR4,
VAR13,
VAR10,
VAR7
);
parameter VAR12 = 1;
parameter VAR11 = 8;
parameter VAR5 = 1;
localparam VAR16 = VAR12 * VAR11;
input clk;
input reset;
output VAR2;
input VAR1;
input [VAR16-1:0] VAR4;
input VAR13;
output VAR10;
output [VAR16-1:0] VAR7;
reg VAR6;
reg VAR8;
reg [VAR16... | gpl-2.0 |
marmolejo/zet | cores/csrbrg/rtl/csrbrg.v | 1,941 | module MODULE1(
input VAR4,
input VAR11,
input [3:1] VAR6,
input [15:0] VAR15,
output reg [15:0] VAR1,
input VAR7,
input VAR2,
input VAR3,
output reg VAR14,
output reg [2:0] VAR13,
output reg VAR17,
output reg [15:0] VAR8,
input [15:0] VAR12
);
always @(posedge VAR4) begin
VAR1 <= VAR12;
end
reg VAR5;
always @(posedge ... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/request_arb.v | 29,320 | module MODULE1 (
input VAR59,
input VAR205,
input VAR238,
output VAR109,
input [31:VAR201] VAR98,
input [31:VAR75] VAR202,
input [VAR124-1:0] VAR69,
input VAR212,
input VAR143,
output reg VAR188,
input enable,
input VAR211,
input VAR81,
input VAR99,
input VAR105,
input VAR223,
output [31:0] VAR213,
output [ 7:0] VAR147... | gpl-3.0 |
alexforencich/verilog-ethernet | example/ML605/fpga_sgmii/rtl/fpga.v | 10,653 | module MODULE1 (
input wire VAR17,
input wire VAR157,
input wire reset,
input wire VAR72,
input wire VAR52,
input wire VAR143,
input wire VAR181,
input wire VAR50,
input wire [7:0] VAR177,
output wire VAR88,
output wire VAR28,
output wire VAR165,
output wire VAR5,
output wire VAR111,
output wire [7:0] VAR131,
input wir... | mit |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_cpu_s0_mult_cell.v | 6,320 | module MODULE1 (
VAR6,
VAR48,
clk,
VAR27,
VAR53
)
;
output [ 31: 0] VAR53;
input [ 31: 0] VAR6;
input [ 31: 0] VAR48;
input clk;
input VAR27;
wire [ 31: 0] VAR53;
wire [ 31: 0] VAR46;
wire [ 15: 0] VAR11;
wire VAR50;
assign VAR50 = ~VAR27;
VAR2 VAR45
(
.VAR37 (VAR50),
.VAR9 (clk),
.VAR56 (VAR6[15 : 0]),
.VAR51 (VAR48[1... | gpl-2.0 |
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