repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
Anirudh94/Connect4-FPGA | Connect4/Grid_bb.v | 4,875 | module MODULE1 (
address,
VAR2,
VAR1);
input [14:0] address;
input VAR2;
output [2:0] VAR1;
tri1 VAR2;
endmodule | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_4.functional.pp.v | 1,184 | module MODULE1( VAR5, VAR2, VAR1, VAR13, VAR8 );
input VAR2, VAR5;
inout VAR13, VAR8;
output VAR1;
wire VAR3;
and VAR11( VAR3, VAR2, VAR5 );
wire VAR12;
not VAR10( VAR12, VAR2 );
wire VAR14;
not VAR7( VAR14, VAR5 );
wire VAR9;
and VAR6( VAR9, VAR12, VAR14 );
or VAR4( VAR1, VAR3, VAR9 );
endmodule | apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_axi_ethernetlite_0_0/system_axi_ethernetlite_0_0_stub.v | 2,859 | module MODULE1(VAR8, VAR27, VAR6,
VAR5, VAR23, VAR31, VAR15, VAR14, VAR34,
VAR25, VAR28, VAR24, VAR19, VAR18, VAR2,
VAR13, VAR4, VAR12, VAR26, VAR10, VAR20, VAR33,
VAR3, VAR11, VAR9, VAR7, VAR1, VAR21, VAR22, VAR17, VAR32,
VAR29, VAR30, VAR16)
;
input VAR8;
input VAR27;
output VAR6;
input [12:0]VAR5;
input VAR23;
outpu... | apache-2.0 |
GuzTech/swapforth | j1b/verilog/xilinx-top.v | 13,677 | module MODULE1 #(
parameter VAR9 = 72,
parameter VAR13 = 10
) (
input wire VAR2,
input wire VAR10,
input wire [VAR13-1:0] VAR4,
input wire [VAR9-1:0] VAR3,
output reg [VAR9-1:0] VAR1,
input wire VAR7,
input wire VAR12,
input wire [VAR13-1:0] VAR5,
input wire [VAR9-1:0] VAR6,
output reg [VAR9-1:0] VAR11
);
reg [VAR9-1:0... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp.symbol.v | 1,532 | module MODULE1 (
input VAR4 ,
output VAR2 ,
output VAR10 ,
input VAR6,
input VAR7 ,
input VAR5 ,
input VAR8
);
supply1 VAR9;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR11 ;
endmodule | apache-2.0 |
jayant-sharma/uart | hdl/TOP_UART.v | 1,963 | module MODULE1 (
input clk,
input rst,
input [VAR15-1:0] VAR14,
input [VAR15-1:0] VAR27,
input VAR19,
output VAR28,
output VAR23,
output [VAR15-1:0] VAR32,
output [VAR35-1:0] VAR2,
output [VAR15-1:0] VAR12
);
wire VAR31,VAR20,VAR3,VAR11,VAR7;
wire [VAR15-1:0] VAR36;
wire [VAR15-1:0] VAR30;
VAR10 VAR24 (
.VAR25 (clk),
.... | unlicense |
google/skywater-pdk-libs-sky130_fd_io | cells/top_ground_lvc_wpad/sky130_fd_io__top_ground_lvc_wpad.pp.symbol.v | 1,919 | module MODULE1 (
inout VAR12 ,
inout VAR14 ,
inout VAR9 ,
inout VAR19 ,
inout VAR16 ,
inout VAR13 ,
inout VAR4 ,
inout VAR6 ,
inout VAR17 ,
inout VAR11 ,
inout VAR1 ,
inout VAR20 ,
inout VAR5 ,
inout VAR18 ,
inout VAR3,
inout VAR2,
inout VAR8 ,
inout VAR10 ,
inout VAR7 ,
inout VAR15
);
endmodule | apache-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_jtag_uart_cpu_s0.v | 17,450 | module MODULE4 (
clk,
VAR45,
VAR35,
VAR43,
VAR38,
VAR19,
VAR14
)
;
output VAR43;
output [ 7: 0] VAR38;
output VAR19;
output [ 5: 0] VAR14;
input clk;
input [ 7: 0] VAR45;
input VAR35;
wire VAR43;
wire [ 7: 0] VAR38;
wire VAR19;
wire [ 5: 0] VAR14;
always @(posedge clk)
begin
if (VAR35)
("%VAR28", VAR45);
end
assign VAR... | gpl-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_system/synthesis/submodules/niosII_system_video_rgb_resampler_0.v | 7,569 | module MODULE1 (
clk,
reset,
VAR16,
VAR4,
VAR5,
VAR13,
VAR11,
VAR21,
VAR15,
VAR12,
VAR19,
VAR6,
VAR17,
VAR2
);
parameter VAR3 = 15;
parameter VAR14 = 29;
parameter VAR20 = 0;
parameter VAR1 = 1;
parameter VAR10 = 10'h3FF;
input clk;
input reset;
input [VAR3:0] VAR16;
input VAR4;
input VAR5;
input [VAR20:0] VAR13;
input... | gpl-2.0 |
Cognoscan/BoostDSP | verilog/src/smallFilters/SmallLpf2nd.v | 3,835 | module MODULE1 #(
parameter VAR2 = 8, parameter VAR5 = 8, parameter VAR11 = 16, parameter VAR4 = 1 )
(
input clk, input rst, input en, input signed [VAR11-1:0] VAR10, output signed [VAR11-1:0] VAR8 );
reg signed [VAR11+VAR2-1:0] VAR1;
reg signed [VAR11+VAR5-1:0] VAR12;
reg signed [VAR11+1:0] VAR7;
wire signed [VAR11-1:... | apache-2.0 |
e33b1711/rfnoc_pp_channelizer | sysgen_models/syntheses/checkpoint/sysgen/syntheses.v | 30,730 | module MODULE5 (
input VAR208,
input [32-1:0] VAR100,
input [1-1:0] VAR90,
input [1-1:0] VAR165,
input [8-1:0] VAR214,
input [1-1:0] VAR48,
input [1-1:0] VAR129
);
wire [1-1:0] VAR166;
wire [1-1:0] VAR236;
wire [1-1:0] VAR229;
wire [1-1:0] VAR173;
wire [8-1:0] VAR128;
wire VAR231;
wire [32-1:0] VAR58;
assign VAR231 = V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211o/sky130_fd_sc_hs__a211o.blackbox.v | 1,324 | module MODULE1 (
VAR4 ,
VAR6,
VAR2,
VAR3,
VAR7
);
output VAR4 ;
input VAR6;
input VAR2;
input VAR3;
input VAR7;
supply1 VAR1;
supply0 VAR5;
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/prj/src/blackboxes/ethmac.v | 3,141 | module MODULE1
(
VAR33, VAR42, VAR36, VAR29,
VAR10, VAR17, VAR34, VAR41, VAR19, VAR30, VAR44,
VAR5, VAR13, VAR16,
VAR26, VAR25, VAR37,
VAR7, VAR23, VAR1,
VAR9, VAR31,
VAR4, VAR3, VAR35, VAR6,
VAR2, VAR27, VAR32, VAR11, VAR24, VAR14,
VAR22, VAR40, VAR28, VAR12,
VAR21
,
VAR18, VAR20, VAR8 VAR43
);
parameter VAR15 = 1;
in... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_buf_fpio.v | 2,118 | module MODULE1(
VAR5, VAR4,
VAR3, VAR1
);
output [VAR2-1:0]VAR5;
output VAR4;
input [VAR2-1:0]VAR3;
input VAR1;
assign VAR5[VAR2-1:0] = VAR3[VAR2-1:0];
assign VAR4 = VAR1;
endmodule | gpl-2.0 |
danidim13/labo-digitales | Experimento4Final/Experimento4/Module_ROM.v | 3,085 | module MODULE1
(
input wire[15:0] VAR9,
output reg [27:0] VAR10
);
always @ ( VAR9 )
begin
case (VAR9)
0: VAR10 = { VAR12 ,24'd4000 };
1: VAR10 = { VAR17 ,VAR18, 16'h0001};
2: VAR10 = { VAR17 ,VAR7, 16'h0000};
3: VAR10 = { VAR17 ,VAR14, 16'h00ff };
4: VAR10 = { VAR17 ,VAR6, 13'b0,VAR13};
5: VAR10 = { VAR19 ,VAR4, 16'h0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi_2.v | 2,477 | module MODULE1 (
VAR6 ,
VAR5,
VAR4,
VAR11 ,
VAR3 ,
VAR9,
VAR1,
VAR10 ,
VAR8
);
output VAR6 ;
input VAR5;
input VAR4;
input VAR11 ;
input VAR3 ;
input VAR9;
input VAR1;
input VAR10 ;
input VAR8 ;
VAR2 VAR7 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR8... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/nsgpio16LE.v | 4,380 | module MODULE1
(input VAR7, input VAR9,
input VAR15, input VAR8, input [3:0] VAR17, input VAR20, input [15:0] VAR12,
output reg [15:0] VAR3, output reg VAR16,
input [31:0] VAR13, input [31:0] VAR5, input [31:0] VAR14,
inout [31:0] VAR4
);
reg [31:0] VAR2, VAR1, VAR6, VAR22, VAR11;
wire VAR19 = VAR15 & VAR8; wire VAR21 ... | gpl-2.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/amber23/a23_core.v | 21,458 | module MODULE1
(
input VAR183,
input VAR207, input VAR121,
input VAR78,
output [31:0] VAR119,
output [3:0] VAR140,
output VAR111,
input [31:0] VAR76,
output [31:0] VAR13,
output VAR9,
output VAR237,
input VAR156,
input VAR79
);
wire [31:0] VAR195;
wire VAR18;
wire [31:0] VAR84; wire [31:0] VAR213;
wire VAR151;
wire [31... | gpl-2.0 |
lvd2/zxevo | fpga/current/spihub/spi2.v | 6,522 | module MODULE1(
VAR4,
VAR2, VAR3, VAR1, VAR6,
VAR13, VAR11,
VAR9,
din, dout );
input VAR4;
output VAR2;
wire VAR2;
output VAR3;
input VAR1;
output reg VAR6;
input VAR13;
output VAR11;
input [1:0] VAR9;
input [7:0] din;
output reg [7:0] dout;
reg [4:0] counter;
wire VAR7;
reg [6:0] VAR14;
reg [7:0] VAR12;
wire VAR8;
wir... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxtp/sky130_fd_sc_ms__sdfxtp.symbol.v | 1,410 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR4,
input VAR6,
input VAR3
);
supply1 VAR9;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
mbus/mbus | mbus/verilog/mbus_master_wire_ctrl.v | 1,622 | module MODULE1(
input VAR8,
input VAR1,
input VAR3,
input VAR2,
output reg VAR7,
output reg VAR4,
input VAR6
);
always @ *
begin
if( !VAR8 )
VAR4 <= 1'b1;
end
else if (VAR2==VAR5)
VAR4 <= 1'b1;
else
VAR4 <= VAR3;
if ( !VAR8 )
VAR7 <= 1'b1;
else if (VAR6)
begin
VAR7 <= 0;
end
else
begin
if (VAR2==VAR5)
begin
VAR7 <= 1'b... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/example_design/PIO_TX_ENGINE.v | 14,405 | module MODULE1 #(
parameter VAR40 = 64,
parameter VAR37 = 1,
parameter VAR23 = VAR40 / 8
)(
input clk,
input VAR26,
input VAR25,
output reg [VAR40-1:0] VAR12,
output reg [VAR23-1:0] VAR8,
output reg VAR51,
output reg VAR13,
output VAR18,
input VAR11,
input VAR48,
output reg VAR47,
input [2:0] VAR4,
input VAR49,
input V... | lgpl-3.0 |
hanw/connectal | verilog/PutInverter.v | 1,813 | module MODULE1(VAR7,
VAR8,
VAR2,
VAR6,
VAR4,
VAR9,
VAR5,
VAR1
);
parameter VAR3 = 1;
input VAR7;
input VAR8;
output [VAR3-1 : 0] VAR9;
input [VAR3-1 : 0] VAR2;
input VAR5;
input VAR6;
output VAR1;
output VAR4;
assign VAR9 = VAR2;
assign VAR1 = VAR6;
assign VAR4 = VAR5;
endmodule | mit |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ip/fmrv32im_artya7_fmrv32im_0/synth/fmrv32im_artya7_fmrv32im_0.v | 4,816 | module MODULE1 (
VAR13,
VAR1,
VAR5,
VAR3,
VAR16,
VAR17,
VAR7,
VAR2,
VAR11,
VAR18,
VAR15,
VAR14,
VAR19,
VAR6,
VAR8,
VAR4
);
input wire VAR13;
input wire VAR1;
input wire VAR5;
output wire VAR3;
output wire [31 : 0] VAR16;
input wire [31 : 0] VAR17;
input wire VAR7;
input wire VAR2;
output wire VAR11;
output wire [3 : 0]... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/premuat3_8.v | 2,376 | module MODULE1(
enable,
VAR2,
VAR8,
VAR3,
VAR7,
VAR1,
VAR5,
VAR6,
VAR9,
VAR4,
o0,
o1,
o2,
o3,
o4,
o5,
o6,
o7
);
input enable;
input VAR2;
input signed [27:0] VAR8;
input signed [27:0] VAR3;
input signed [27:0] VAR7;
input signed [27:0] VAR1;
input signed [27:0] VAR5;
input signed [27:0] VAR6;
input signed [27:0] VAR9;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a311oi/sky130_fd_sc_ls__a311oi.functional.v | 1,485 | module MODULE1 (
VAR1 ,
VAR5,
VAR4,
VAR10,
VAR11,
VAR7
);
output VAR1 ;
input VAR5;
input VAR4;
input VAR10;
input VAR11;
input VAR7;
wire VAR8 ;
wire VAR6;
and VAR2 (VAR8 , VAR10, VAR5, VAR4 );
nor VAR9 (VAR6, VAR8, VAR11, VAR7);
buf VAR3 (VAR1 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2/sky130_fd_sc_ls__nor2.pp.blackbox.v | 1,260 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR6 ,
VAR3,
VAR7,
VAR2 ,
VAR5
);
output VAR1 ;
input VAR4 ;
input VAR6 ;
input VAR3;
input VAR7;
input VAR2 ;
input VAR5 ;
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_030.v | 1,493 | module MODULE2 (
VAR9,
VAR3
);
input [31:0] VAR9;
output [31:0]
VAR3;
wire [31:0]
VAR5,
VAR12,
VAR6,
VAR10,
VAR2,
VAR11,
VAR7,
VAR13;
assign VAR5 = VAR9;
assign VAR12 = VAR5 << 11;
assign VAR6 = VAR5 + VAR12;
assign VAR13 = VAR7 << 2;
assign VAR2 = VAR10 - VAR6;
assign VAR7 = VAR2 + VAR11;
assign VAR11 = VAR5 << 6;
ass... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxtp/sky130_fd_sc_ls__dlxtp_1.v | 2,162 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR3,
VAR7,
VAR9,
VAR4 ,
VAR1
);
output VAR8 ;
input VAR2 ;
input VAR3;
input VAR7;
input VAR9;
input VAR4 ;
input VAR1 ;
VAR6 VAR5 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR8 ,
VAR2 ,
VAR3
);
output VAR8 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dff_p_pp_pg_n/sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.blackbox.v | 1,399 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR1 ,
VAR5,
VAR6 ,
VAR2
);
output VAR3 ;
input VAR4 ;
input VAR1 ;
input VAR5;
input VAR6 ;
input VAR2 ;
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_tdd_sync.v | 4,011 | module MODULE1 (
clk, VAR1,
sync );
localparam VAR7 = 7;
parameter VAR6 = 100000000;
input clk;
input VAR1;
output sync;
reg [(VAR7-1):0] VAR4 = {VAR7{1'b1}};
reg [31:0] VAR2 = 32'h0;
reg VAR5 = 1'b0;
reg VAR3 = 1'b0;
assign sync = VAR5;
always @(posedge clk) begin
if (VAR1 == 1'b0) begin
VAR2 <= 32'h0;
VAR3 <= 1'b0;
e... | lgpl-3.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/cpu/jp.v | 3,994 | module MODULE1(
input clk, input rst,
input VAR4, input [15:0] VAR3, input VAR13, output reg [7:0] VAR6,
input [7:0] VAR2, input [7:0] VAR5 );
localparam [15:0] VAR1 = 16'h4016;
localparam [15:0] VAR12 = 16'h4017;
reg [15:0] VAR9;
wire VAR10;
reg VAR7;
reg [8:0] VAR8;
reg [8:0] VAR11;
assign VAR10 = (VAR9 != VAR3);
alw... | mit |
wgml/sysrek | skin_color_segm/src/rx_nok/phsaligner_nok.v | 9,095 | module MODULE1 # (
parameter VAR28 = 3, parameter VAR2 = 4, parameter VAR20 = 12, parameter VAR5 = "VAR29"
)
(
input wire rst,
input wire clk,
input wire [9:0] VAR25, output reg VAR24,
output reg VAR23,
output reg VAR22 );
localparam VAR1 = 10'b1101010100;
localparam VAR7 = 10'b0010101011;
localparam VAR9 = 10'b0101010... | gpl-2.0 |
oceanborn-mx/sirius | src.verilog/Matrix_Multiplication_Torus/Matrix_Multiplication_Torus/src/arreglo_torus.v | 1,975 | module MODULE1 (
input VAR53, input VAR47, input[3:0] VAR6,VAR13, input[3:0] VAR28,VAR32,
input[3:0] VAR66,VAR74, input[3:0] VAR36,VAR59,
input VAR71, input VAR19, input VAR67, input VAR17, input VAR52, output[7:0] VAR7,VAR69, output[7:0] VAR55,VAR65
);
wire[3:0] VAR14,VAR70,VAR60,VAR30;
wire[3:0] VAR54,VAR73,VAR56,VAR... | gpl-2.0 |
mossmann/unambiguous-encapsulation | code-search/verilog/lcbbc/lcbbc.v | 4,961 | module MODULE1
parameter VAR16=1024,
parameter VAR27=VAR4, parameter VAR33=VAR8(VAR16)
)
(input clk,
input rst, input [VAR4-1:0] VAR30,
input [VAR4/2-1:0] VAR34,
input VAR10,
output reg [VAR4-1:0] VAR37
);
localparam [2:0]
VAR31 = 0,
VAR22 = 1,
VAR1 = 2,
VAR28 = 3,
VAR3 = 4,
VAR15 = 5,
VAR19 = 6,
VAR26 = 7;
reg [2:0] s... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/decap/sky130_fd_sc_hd__decap_6.v | 1,870 | module MODULE1 (
VAR5,
VAR6,
VAR3 ,
VAR2
);
input VAR5;
input VAR6;
input VAR3 ;
input VAR2 ;
VAR1 VAR4 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE1 ();
supply1 VAR5;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR2 ;
VAR1 VAR4 ();
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_gt_es.v | 30,566 | module MODULE1 (
VAR84,
VAR8,
VAR101,
VAR129,
VAR99,
VAR94,
VAR71,
VAR26,
VAR97,
VAR124,
VAR111,
VAR73,
VAR79,
VAR5,
VAR59,
VAR126,
VAR87,
VAR9,
VAR4,
VAR62,
VAR22,
VAR74,
VAR54,
VAR76,
VAR12,
VAR130,
VAR6,
VAR47,
VAR72,
VAR18,
VAR92,
VAR122,
VAR52,
VAR23,
VAR66,
VAR49,
VAR56,
VAR135,
VAR57,
VAR13,
VAR25,
VAR81,
VAR51,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphe/sky130_fd_sc_ls__decaphe.functional.pp.v | 1,191 | module MODULE1 (
VAR3,
VAR2,
VAR1 ,
VAR4
);
input VAR3;
input VAR2;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3b/sky130_fd_sc_lp__nor3b_m.v | 2,251 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR9 ,
VAR3 ,
VAR10,
VAR1,
VAR7 ,
VAR5
);
output VAR8 ;
input VAR2 ;
input VAR9 ;
input VAR3 ;
input VAR10;
input VAR1;
input VAR7 ;
input VAR5 ;
VAR4 VAR6 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvn/sky130_fd_sc_hd__einvn.pp.blackbox.v | 1,289 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR7,
VAR4,
VAR5,
VAR3 ,
VAR6
);
output VAR2 ;
input VAR1 ;
input VAR7;
input VAR4;
input VAR5;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
schelleg/pynq_tutorial | Pynq-Z1/vivado/pynq_tutorial/ip/arduino_io_switch_1.0/src/arduino_switch_analog_bit.v | 2,729 | module MODULE1(
input [1:0] VAR8, input VAR14, output reg VAR10, output reg VAR2,
output VAR3, input VAR7, input VAR1, output VAR9, input VAR13, input VAR4, output VAR11, input VAR12, input VAR5 );
reg [2:0] VAR6;
assign {VAR11,VAR9, VAR3} = VAR6;
always @(VAR8, VAR7, VAR12, VAR13)
case (VAR8)
2'h0: VAR10 = VAR7; 2'h1:... | bsd-3-clause |
dries007/Basys3 | VGA/VGA.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_clk_wiz.v | 6,345 | module MODULE1
( input VAR26,
output VAR73
);
VAR42 VAR37
(.VAR39 (VAR25),
.VAR4 (VAR26));
wire [15:0] VAR65;
wire VAR58;
wire VAR69;
wire VAR21;
wire VAR79;
wire VAR59;
wire VAR64;
wire VAR48;
wire VAR34;
wire VAR7;
wire VAR49;
wire VAR53;
wire VAR32;
wire VAR28;
wire VAR61;
wire VAR22;
wire VAR52;
wire VAR72;
wire VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlya/gf180mcu_fd_sc_mcu9t5v0__dlya_1.behavioral.v | 1,098 | module MODULE1( VAR4, VAR3 );
input VAR4;
output VAR3;
VAR2 VAR5(.VAR4(VAR4),.VAR3(VAR3));
VAR2 VAR1(.VAR4(VAR4),.VAR3(VAR3)); | apache-2.0 |
olajep/oh | src/common/hdl/oh_clockor.v | 1,214 | module MODULE1 #(parameter VAR7 = 1) (
input [VAR7-1:0] VAR5, output VAR4
);
localparam VAR3 = VAR8;
generate
if(VAR3 & (VAR7==4))
begin : VAR10
VAR6 VAR2 (
.VAR4 (VAR4),
.VAR5 (VAR5[3:0]));
end else if(VAR3 & (VAR7==2))
begin : VAR10
VAR9 VAR2 (
.VAR4 (VAR4),
.VAR5 (VAR5[1:0]));
end else
begin : VAR1
assign VAR4... | mit |
praveendath92/securePUF | ipcore_dir/SysMon/example_design/SysMon_exdes.v | 4,831 | module MODULE1(
VAR22, VAR8, VAR9, VAR17, VAR2, VAR16, VAR21, VAR5, VAR19, VAR3, VAR18, VAR14, VAR10, VAR23, VAR15, VAR4);
input VAR15;
input VAR4;
input [6:0] VAR22;
input VAR8;
input VAR9;
input [15:0] VAR17;
input VAR2;
output VAR16;
output [4:0] VAR21;
output [15:0] VAR5;
output VAR19;
output VAR3;
output VAR18;
ou... | gpl-2.0 |
kielfriedt/ece472 | lab5/alu_ctl.v | 2,116 | module MODULE1(VAR5, VAR10, VAR1);
input [1:0] VAR5;
input [5:0] VAR10;
output [2:0] VAR1;
reg [2:0] VAR1;
parameter VAR2 = 6'd32;
parameter VAR13 = 6'd34;
parameter VAR8 = 6'd36;
parameter VAR12 = 6'd37;
parameter VAR9 = 6'd42;
parameter VAR14 = 3'b010;
parameter VAR6 = 3'b110;
parameter VAR7 = 3'b000;
parameter VAR4 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4/sky130_fd_sc_hs__nand4.blackbox.v | 1,245 | module MODULE1 (
VAR5,
VAR1,
VAR7,
VAR6,
VAR3
);
output VAR5;
input VAR1;
input VAR7;
input VAR6;
input VAR3;
supply1 VAR4;
supply0 VAR2;
endmodule | apache-2.0 |
jakubfi/mera400f | src/mem_dummy_sram.v | 1,286 | module MODULE1(
input clk,
output VAR23, VAR20, VAR12, VAR6, VAR15,
output [17:0] VAR11,
inout [15:0] VAR10,
input [0:3] VAR8,
input [0:15] VAR21,
output [0:15] VAR3,
input [0:15] VAR9,
input VAR22, VAR18, VAR17,
output VAR2
);
assign VAR23 = 0;
assign VAR6 = 0;
assign VAR15 = 0;
assign VAR12 = ~VAR19;
assign VAR20 = ~... | gpl-2.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/pcie_core/source/pcie_core_pipe_sync.v | 27,151 | module MODULE1 #
(
parameter VAR70 = "VAR90", parameter VAR35 = "VAR85", parameter VAR26 = "VAR3", parameter VAR13 = 0, parameter VAR92 = 0, parameter VAR41 = 1, parameter VAR16 = 3, parameter VAR43 = 0, parameter VAR45 = 0
)
(
input VAR107,
input VAR78,
input VAR29,
input VAR52,
input VAR25,
input VAR7,
input VAR1,
in... | lgpl-3.0 |
cybero/Verilog | src/BRAM + checker/rtl/bram_controller.v | 1,291 | module MODULE1(clk, reset, VAR4, VAR5, VAR2);
input wire clk, reset, VAR4;
output reg VAR5;
output reg [3:0] VAR2;
localparam [1:0]
VAR7 = 2'b00,
VAR3 = 2'b01,
VAR6 = 2'b10;
reg [1:0] VAR1;
reg [3:0] counter;
always@(posedge clk, posedge reset)
if(reset)
begin
VAR2<=0;
counter<=0;
VAR1<=VAR7;
VAR5<=0;
end
else begin
ca... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v | 7,550 | module MODULE1
parameter VAR16 = 8,
VAR21 = 8,
VAR19 = 0,
VAR2 = 0,
VAR15 = 1,
VAR40 = 0,
VAR1 = 1,
VAR22 = 2,
VAR32 = 2,
VAR37 = 1,
VAR24 = VAR16 / VAR21,
VAR10 = VAR30(VAR24)
)
(
input VAR14,
input VAR23,
input VAR34,
input VAR43,
output VAR27,
input VAR29,
input [VAR16 - 1 : 0] VAR13,
input [VAR15 - 1 : 0] VAR38,
in... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fahcin/sky130_fd_sc_hd__fahcin.blackbox.v | 1,332 | module MODULE1 (
VAR8,
VAR5 ,
VAR3 ,
VAR7 ,
VAR9
);
output VAR8;
output VAR5 ;
input VAR3 ;
input VAR7 ;
input VAR9 ;
supply1 VAR2;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111oi/sky130_fd_sc_hs__a2111oi.pp.blackbox.v | 1,382 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR4 ,
VAR1 ,
VAR7 ,
VAR8 ,
VAR5,
VAR3
);
output VAR6 ;
input VAR2 ;
input VAR4 ;
input VAR1 ;
input VAR7 ;
input VAR8 ;
input VAR5;
input VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a311o/sky130_fd_sc_ls__a311o.pp.blackbox.v | 1,421 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR4 ,
VAR1 ,
VAR2 ,
VAR7 ,
VAR5,
VAR8,
VAR10 ,
VAR9
);
output VAR3 ;
input VAR6 ;
input VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR7 ;
input VAR5;
input VAR8;
input VAR10 ;
input VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111a/sky130_fd_sc_ms__o2111a.symbol.v | 1,393 | module MODULE1 (
input VAR8,
input VAR9,
input VAR10,
input VAR1,
input VAR4,
output VAR2
);
supply1 VAR5;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
tmeissner/cryptocores | aes/rtl/verilog/aes.v | 1,539 | module MODULE1
parameter VAR5 = 0
)
(
input VAR7, input VAR3, input VAR9, input [0:127] VAR8, input [0:127] VAR1, input VAR2, output [0:127] VAR4, output VAR6 );
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a41o/sky130_fd_sc_ms__a41o.pp.blackbox.v | 1,415 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR4 ,
VAR10 ,
VAR9 ,
VAR1 ,
VAR2,
VAR5,
VAR8 ,
VAR3
);
output VAR7 ;
input VAR6 ;
input VAR4 ;
input VAR10 ;
input VAR9 ;
input VAR1 ;
input VAR2;
input VAR5;
input VAR8 ;
input VAR3 ;
endmodule | apache-2.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/hdl/verilog/ANN_sitofp_32ns_32_6.v | 1,561 | module MODULE1
VAR17 = 3,
VAR9 = 6,
VAR13 = 32,
VAR3 = 32
)(
input wire clk,
input wire reset,
input wire VAR8,
input wire [VAR13-1:0] VAR20,
output wire [VAR3-1:0] dout
);
wire VAR10;
wire VAR7;
wire VAR11;
wire [31:0] VAR2;
wire VAR18;
wire [31:0] VAR1;
reg [VAR13-1:0] VAR6;
VAR16 VAR15 (
.VAR10 ( VAR10 ),
.VAR7 ( VA... | gpl-3.0 |
dries007/Basys3 | FPGA-Z/FPGA-Z.srcs/sources_1/ip/Stack/Stack_stub.v | 1,224 | module MODULE1(VAR4, VAR2, clk, VAR3, VAR1)
;
input [9:0]VAR4;
input [15:0]VAR2;
input clk;
input VAR3;
output [15:0]VAR1;
endmodule | mit |
borti4938/n64rgb | advancedRGBmod/firmware/rtl/misc/ram2port.v | 3,069 | module MODULE1(
VAR23,
VAR20,
VAR2,
VAR16,
VAR4,
VAR9,
VAR12,
VAR22,
VAR7,
VAR25
);
parameter VAR18 = 1;
parameter VAR6 = 1024;
parameter VAR17 = 32;
input VAR23;
input VAR20;
input [VAR19-1:0] VAR2;
input [VAR14-1:0] VAR16;
input [ VAR17-1:0] VAR4;
input VAR9;
input VAR12;
input [VAR19-1:0] VAR22;
input [VAR14-1:0] VA... | gpl-3.0 |
parallella/oh | spi/hdl/spi_master_io.v | 5,941 | module MODULE1
(
input clk, input VAR13, input VAR49, input VAR51, input VAR21, input VAR1, input VAR46, input [7:0] VAR48, output reg [2:0] VAR31, input [7:0] VAR7, input VAR28, output VAR57, output [63:0] VAR34, output VAR37, output reg VAR27, output VAR20, output VAR5, input VAR30 );
reg VAR9;
reg VAR24;
reg VAR36;
... | mit |
muraj/trv_proc | rtl/trv_alu.v | 1,681 | module MODULE2
(
input wire [2:0] VAR6,
input wire [31:0] VAR3,
input wire [31:0] VAR4,
output wire VAR7
);
wire signed VAR5, VAR2;
VAR5 = VAR3;
VAR2 = VAR4;
always @* begin
VAR7 = 0;
case (VAR6)
VAR7 = VAR3 == VAR4;
VAR7 = VAR3 != VAR4;
VAR7 = VAR5 < VAR2;
VAR7 = !(VAR5 < VAR2);
VAR7 = VAR3 < VAR4;
VAR7 = !(VAR3 < VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.blackbox.v | 1,204 | module MODULE1 (
VAR3 ,
VAR2,
VAR4,
VAR1
);
output VAR3 ;
input VAR2;
input VAR4;
input VAR1 ;
endmodule | apache-2.0 |
LuckyChewie/SPI-Connection | FancySlave.v | 3,801 | module MODULE1 (VAR42, VAR20, VAR19, VAR45, VAR36, VAR39, VAR29, VAR49, VAR48, VAR18, VAR47, VAR28, VAR21, VAR31, VAR46, VAR54);
input VAR42;
input [17:0] VAR21;
input [1:0] VAR31;
output [6:0] VAR29, VAR49, VAR48, VAR18, VAR47, VAR28;
output [17:0] VAR46;
output [2:0] VAR54;
input VAR20;
input VAR19;
input VAR39;
outp... | mit |
ammelto/FPGAdventure | Adventure/vga_driver.v | 4,187 | module MODULE1(VAR7, VAR24, VAR1, VAR37, VAR11, VAR25, VAR13, VAR4, VAR29, VAR18, VAR2);
input VAR7;
output VAR24;
output VAR1;
output [2:0] VAR37;
output [2:0] VAR11;
output [1:0] VAR25;
reg VAR19 = 0;
reg VAR28 = 0;
input VAR2;
input [7:0] VAR29;
output VAR18;
output [9:0] VAR13;
output [8:0] VAR4;
parameter VAR17 = ... | mit |
AmeerAbdelhadi/Switched-Multiported-RAM | dpram.v | 4,491 | module MODULE1
integer VAR2;
reg [VAR8-1:0] VAR7 [0:VAR10-1]; VAR12
if (VAR15)
for (VAR2=0; VAR2<VAR10; VAR2=VAR2+1) VAR7[VAR2] = {VAR8{1'b0}};
else
if (VAR13 != "")
always @(posedge clk) begin
if (VAR9) begin
VAR7[VAR5] <= VAR6; VAR14 <= VAR6; end else
VAR14 <= VAR7[VAR5]; end
always @(posedge clk) begin
if (VAR4) beg... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and2b/sky130_fd_sc_hd__and2b.pp.blackbox.v | 1,287 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR1 ,
VAR5,
VAR3,
VAR2 ,
VAR7
);
output VAR4 ;
input VAR6 ;
input VAR1 ;
input VAR5;
input VAR3;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/omsp_system_1.v | 16,955 | module MODULE1 (
VAR77, VAR51,
VAR82, VAR84, VAR89, VAR109, VAR85,
VAR70, VAR7, VAR38, VAR114, VAR68,
VAR61, VAR54, VAR36, VAR99, VAR107,
VAR37, VAR74 );
input VAR77; input VAR51;
input [6:0] VAR82; input [6:0] VAR84; input VAR89; input VAR109; output VAR85;
input [15:0] VAR68; output [VAR100:0] VAR70; output VAR7; out... | bsd-3-clause |
takeshineshiro/fpga_linear_128 | DAS_RF.v | 9,464 | module MODULE1 (
VAR43,
VAR54,
VAR34,
VAR5,
VAR22,
VAR48);
input VAR43;
input [15:0] VAR54;
input [13:0] VAR34;
input [13:0] VAR5;
input VAR22;
output [15:0] VAR48;
tri1 VAR22;
wire [15:0] VAR38;
wire [15:0] VAR48 = VAR38[15:0];
VAR7 VAR4 (
.VAR2 (VAR22),
.VAR40 (VAR43),
.VAR6 (VAR5),
.VAR29 (VAR34),
.VAR23 (VAR54),
.V... | mit |
Kipsora/MIPS-CPU | source/machine/cpu/stages/ex-div.v | 4,162 | module MODULE1(
input wire VAR8,
input wire reset,
input wire VAR3,
input wire[VAR4] VAR12,
input wire[VAR4] VAR16,
input wire VAR20,
input wire VAR18,
output reg VAR2,
output reg[VAR21] VAR11
);
wire[VAR1] VAR14;
reg[VAR22] VAR15;
reg[VAR4] VAR19;
reg[5 : 0] VAR5;
reg[1 : 0] state;
assign VAR14 = {1'b0, VAR15[63 : 32]... | mit |
jbelloncastro/amber_arm | hw/vlog/ethmac/eth_rxstatem.v | 7,161 | module MODULE1 (VAR20, VAR16, VAR3, VAR9, VAR23, VAR24, VAR4, VAR6,
VAR8, VAR13, VAR10, VAR21, VAR14, VAR5,
VAR7
);
parameter VAR18 = 1;
input VAR20;
input VAR16;
input VAR3;
input VAR9;
input VAR23;
input VAR4;
input VAR24;
input VAR6;
input VAR8;
input VAR13;
output [1:0] VAR10;
output VAR21;
output VAR7;
output VAR1... | lgpl-3.0 |
anderson1008/NOCulator | hring/hw/buffered/src/c_mat_mult.v | 2,596 | module MODULE1
(VAR5, VAR1, VAR6);
parameter VAR7 = 1;
parameter VAR10 = 1;
parameter VAR3 = 1;
input [0:VAR7*VAR10-1] VAR5;
input [0:VAR10*VAR3-1] VAR1;
output [0:VAR7*VAR3-1] VAR6;
wire [0:VAR7*VAR3-1] VAR6;
generate
genvar VAR13;
for(VAR13 = 0; VAR13 < VAR7; VAR13 = VAR13 + 1)
begin:VAR11
genvar VAR2;
for(VAR2 = 0; ... | mit |
SI-RISCV/e200_opensource | rtl/e203/perips/i2c_master_top.v | 12,605 | module MODULE1(
VAR36, VAR20, VAR30, VAR31, VAR18, VAR33,
VAR27, VAR35, VAR3, VAR54, VAR41,
VAR49, VAR25, VAR14, VAR1, VAR39, VAR26 );
parameter VAR22 = 1'b0;
input VAR36; input VAR20; input VAR30; input [2:0] VAR31; input [7:0] VAR18; output [7:0] VAR33; input VAR27; input VAR35; input VAR3; output VAR54; output VAR41... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3/sky130_fd_sc_hs__nand3.functional.pp.v | 1,717 | module MODULE1 (
VAR8,
VAR12,
VAR10 ,
VAR6 ,
VAR1 ,
VAR4
);
input VAR8;
input VAR12;
output VAR10 ;
input VAR6 ;
input VAR1 ;
input VAR4 ;
wire VAR9 ;
wire VAR11;
nand VAR2 (VAR9 , VAR1, VAR6, VAR4 );
VAR3 VAR5 (VAR11, VAR9, VAR8, VAR12);
buf VAR7 (VAR10 , VAR11 );
endmodule | apache-2.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/freedm_bus/fb_txcounters.v | 4,234 | module MODULE1 (VAR23, VAR24,
VAR14, VAR15, VAR31, VAR13, VAR30, VAR21, VAR4,
VAR22, VAR33, VAR11,
VAR18, VAR2,
VAR20, VAR16, VAR9, VAR25, VAR7, VAR29
);
input VAR23; input VAR24; input VAR14; input VAR15; input VAR31; input VAR13;
input [1:0] VAR30;
input VAR21;
input [1:0] VAR4;
input [1:0] VAR22; input [1:0] VAR18; ... | gpl-3.0 |
rohit21122012/CPU | ALU/Arith/Signed/SAdder/mux48to16.v | 9,968 | module MODULE1(out , VAR4 , VAR13 ,VAR11, VAR14 ,VAR3,VAR10 ,VAR1);
output [31:0] out;
input [31:0] VAR4,VAR13,VAR11,VAR14;
input VAR3,VAR1,VAR10;
wire VAR7,VAR5;
wire [31:0] VAR12,VAR9,VAR2,VAR6;
not (VAR7,VAR3);
not (VAR8 , VAR10);
and (VAR12[0] ,VAR1,VAR8, VAR7 , VAR4[0]);
and (VAR12[1] ,VAR1,VAR8, VAR7 , VAR4[1]);
... | mit |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/flash_interface.v | 7,664 | module MODULE1(
input wire clk, input wire reset,
input wire [7:0] VAR5,
input wire VAR30,
input wire [8:0] VAR29,
output wire VAR22,
input wire [7:0] VAR42,
input wire VAR24,
output wire VAR8,
output wire [7:0] VAR37,
output wire VAR17,
input wire VAR10,
output wire VAR43,
input wire VAR7,
output wire VAR2,
output wir... | gpl-2.0 |
eda-globetrotter/PicenoDecoders | zhiyang_and_andrew/acs.v | 3,717 | module MODULE1 (VAR8, VAR5, VAR4, VAR9, VAR6, VAR11);
output [3:0] VAR8;
output VAR5;
input [3:0] VAR4;
input [1:0] VAR9;
input [3:0] VAR6;
input [1:0] VAR11;
reg [3:0] VAR8;
reg VAR5;
reg [3:0] VAR7;
reg [3:0] VAR2;
reg [4:0] VAR10;
reg [4:0] VAR1;
parameter VAR3 = 4'd15;
always @ (VAR4 or VAR9)
begin
VAR10 = VAR4 + V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor2/sky130_fd_sc_ms__xnor2_1.v | 2,132 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR4 ,
VAR7,
VAR1,
VAR6 ,
VAR5
);
output VAR2 ;
input VAR3 ;
input VAR4 ;
input VAR7;
input VAR1;
input VAR6 ;
input VAR5 ;
VAR9 VAR8 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR2,
VAR3,
VAR4
);
output VAR2;
... | apache-2.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v | 3,413 | module MODULE1
(
VAR33,
VAR6,
VAR10,
VAR12,
VAR11,
VAR15,
VAR32,
VAR2,
VAR13
);
parameter VAR41 = "";
parameter VAR18 = 0;
parameter VAR7 = "false";
parameter VAR4 = "false";
input VAR33;
input VAR6;
input VAR10;
input [VAR41-1:0] VAR12;
output VAR11;
output VAR15;
output VAR32;
output VAR2;
output VAR13;
wire VAR8;
wi... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/source/pcie_bram_top_v6.v | 5,909 | module MODULE1
parameter VAR24 = 0,
parameter VAR29 = 31,
parameter VAR28 = 24,
parameter VAR1 = 1,
parameter VAR4 = 2,
parameter VAR7 = 1,
parameter VAR32 = 'h1FFF,
parameter VAR2 = 1,
parameter VAR8 = 2,
parameter VAR5 = 1
)
(
input VAR3,
input VAR13,
input VAR20,
input [12:0] VAR18,
input [71:0] VAR30,
input VAR16,
... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/cmp_top.v | 74,906 | module MODULE1 ();
wire VAR79 ;
wire VAR293 ;
wire [2:0] VAR237 ;
wire [2:0] VAR28 ;
wire [2:0] VAR243 ;
wire [5:0] VAR102 ;
wire [5:0] VAR136 ;
wire [5:0] VAR220 ;
wire [5:0] VAR119 ;
wire [5:0] VAR109 ;
wire [5:0] VAR13 ;
wire [5:0] VAR269 ;
wire [5:0] VAR116 ;
wire [5:0] VAR118 ;
wire [5:0] VAR10 ;
wire [5:0] VAR135... | gpl-2.0 |
Murailab-arch/magukara | cores/asfifo/rtl/graycounter.v | 1,169 | module MODULE1
(output reg [VAR4-1:0] VAR1,
input wire VAR5, input wire rst,
input wire VAR3);
reg [VAR4-1:0] VAR2;
always @ (posedge VAR3)
if (rst) begin
VAR2 <= {VAR4{1'VAR6 0}} + 1; VAR1 <= {VAR4{1'VAR6 0}}; end
else if (VAR5) begin
VAR2 <= VAR2 + 1;
VAR1 <= {VAR2[VAR4-1],
VAR2[VAR4-2:0] ^ VAR2[VAR4-1:1]};
end
endmo... | gpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v | 1,994 | module MODULE1 (
address,
clk,
VAR5,
VAR6,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input VAR5;
input VAR6;
wire VAR4;
wire VAR2;
wire VAR1;
reg [ 31: 0] VAR3;
assign VAR4 = 1;
assign VAR1 = {1 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR6)
begin
if (VAR6 == 0)
VAR3 <= 0;
end
el... | gpl-3.0 |
The-OpenROAD-Project/asap7 | asap7sc7p5t_28/Verilog/asap7sc7p5t_OA_SLVT_TT_201020.v | 197,635 | module MODULE1 (VAR4, VAR8, VAR1, VAR3, VAR2);
output VAR4;
input VAR8, VAR1, VAR3, VAR2;
wire VAR10, VAR9, VAR6;
wire VAR5, VAR11, VAR7;
not (VAR5, VAR2);
not (VAR6, VAR3);
and (VAR11, VAR6, VAR5);
not (VAR9, VAR1);
not (VAR10, VAR8);
and (VAR7, VAR10, VAR9, VAR5);
or (VAR4, VAR7, VAR11); | bsd-3-clause |
merckhung/zet | cores/gpio/rtl/seg_7.v | 1,890 | module MODULE1 (
input [3:0] VAR2,
input en,
output reg [6:0] VAR1
);
always @(VAR2 or en)
if (!en) VAR1 <= 7'h3f;
else
case (VAR2)
4'h0: VAR1 <= {1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0};
4'h1: VAR1 <= {1'b1,1'b1,1'b1,1'b1,1'b0,1'b0,1'b1};
4'h2: VAR1 <= {1'b0,1'b1,1'b0,1'b0,1'b1,1'b0,1'b0};
4'h3: VAR1 <= {1'b0,1'b1,1'b1,1'... | gpl-3.0 |
kazuyamashi/cReComp | example/verilog/pwm_ctl.v | 1,431 | module MODULE1(
input clk,
input rst,
input [14:0] VAR2,
input [0:0] VAR3,
output [0:0] VAR5,
output [0:0] VAR7
);
parameter VAR6 = 19999;
reg VAR9;
reg VAR9;
reg en;
reg [14:0] in;
reg [31:0] counter;
wire [31:0] VAR1;
reg [31:0] VAR8;
VAR4 VAR8 = VAR6;
VAR4 in = VAR6;
assign VAR1 = VAR8 - in;
assign VAR5 = VAR9;
assi... | bsd-3-clause |
bigeagle/riffa | fpga/xilinx/zc706/riffa_wrapper_zc706.v | 37,829 | module MODULE1
parameter VAR225 = 128,
parameter VAR97 = 256,
parameter VAR41 = 5
)
(
input [VAR225-1:0] VAR217,
input [(VAR225/8)-1:0] VAR156,
input VAR231,
input VAR308,
output VAR38,
input [VAR204-1:0] VAR330,
output VAR141,
output VAR243,
output [VAR225-1:0] VAR127,
output [(VAR225/8)-1:0] VAR199,
output VAR55,
out... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/maj3/sky130_fd_sc_hd__maj3.functional.pp.v | 2,186 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR10 ,
VAR3 ,
VAR7,
VAR16,
VAR5 ,
VAR14
);
output VAR9 ;
input VAR8 ;
input VAR10 ;
input VAR3 ;
input VAR7;
input VAR16;
input VAR5 ;
input VAR14 ;
wire VAR6 ;
wire VAR20 ;
wire VAR15 ;
wire VAR13 ;
wire VAR17;
or VAR12 (VAR6 , VAR10, VAR8 );
and VAR11 (VAR20 , VAR6, VAR3 );
and VAR2 (V... | apache-2.0 |
Vudentz/zephyr | soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da_top.v | 6,394 | module MODULE1 (
input wire VAR17,
input wire VAR34,
output wire VAR2,
inout wire[3:0] VAR8,
output wire VAR22,
inout wire VAR28,
inout wire VAR21,
input wire VAR15,
output wire VAR3,
output wire VAR32,
output wire VAR18,
input wire VAR30,
output wire VAR10,
output wire [4:0] VAR5
);
reg [25:0] VAR36;
wire VAR24 ;
wire... | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/altera_avalon_st_clock_crosser.v | 5,027 | module MODULE1(
VAR15,
VAR7,
VAR28,
VAR20,
VAR29,
VAR18,
VAR2,
VAR9,
VAR25,
VAR5
);
parameter VAR22 = 1;
parameter VAR27 = 8;
parameter VAR3 = 2;
parameter VAR10 = 2;
parameter VAR32 = 1;
localparam VAR1 = VAR22 * VAR27;
input VAR15;
input VAR7;
output VAR28;
input VAR20;
input [VAR1-1:0] VAR29;
input VAR18;
input VAR2... | mit |
miguelgarcia/sase2017-hls-video | hdmi_in/repo/sase/hdl/verilog/my_video_filter_AXILiteS_s_axi.v | 10,073 | module MODULE1
VAR56 = 5,
VAR62 = 32
)(
input wire VAR41,
input wire VAR32,
input wire VAR6,
input wire [VAR56-1:0] VAR48,
input wire VAR46,
output wire VAR43,
input wire [VAR62-1:0] VAR40,
input wire [VAR62/8-1:0] VAR17,
input wire VAR57,
output wire VAR45,
output wire [1:0] VAR15,
output wire VAR27,
input wire VAR50,... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/usart.v | 8,297 | module MODULE1 #(
parameter VAR11 = 9,
parameter VAR12 = VAR38
) (
output VAR57,
input VAR46,
input VAR36,
input VAR5, input [3:0] VAR9, input [7:0] VAR60,
output [7:0] VAR35,
input VAR50,
input VAR58,
output VAR15,
input VAR54, output [15:0] VAR49, output [7:0] VAR26,
output VAR19 );
wire VAR42, VAR27;
wire [7:0] VAR1... | gpl-3.0 |
miyukki/spartan-3an-vga | ipcore_dir/dcm.v | 2,802 | module MODULE1(VAR34,
VAR57,
VAR5,
VAR35,
VAR41,
VAR48);
input VAR34;
input VAR57;
output VAR5;
output VAR35;
output VAR41;
output VAR48;
wire VAR32;
wire VAR15;
wire VAR54;
wire VAR50;
wire VAR37;
assign VAR37 = 0;
assign VAR35 = VAR54;
assign VAR41 = VAR32;
VAR21 VAR49 (.VAR19(VAR15),
.VAR22(VAR5));
VAR4 VAR53 (.VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4b/sky130_fd_sc_hs__and4b.behavioral.pp.v | 1,885 | module MODULE1 (
VAR3,
VAR15,
VAR9 ,
VAR10 ,
VAR12 ,
VAR11 ,
VAR5
);
input VAR3;
input VAR15;
output VAR9 ;
input VAR10 ;
input VAR12 ;
input VAR11 ;
input VAR5 ;
wire VAR5 VAR4 ;
wire VAR6 ;
wire VAR14;
not VAR1 (VAR4 , VAR10 );
and VAR8 (VAR6 , VAR4, VAR12, VAR11, VAR5 );
VAR7 VAR2 (VAR14, VAR6, VAR3, VAR15);
buf VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3/sky130_fd_sc_lp__and3_m.v | 2,161 | module MODULE2 (
VAR6 ,
VAR7 ,
VAR9 ,
VAR8 ,
VAR3,
VAR4,
VAR1 ,
VAR5
);
output VAR6 ;
input VAR7 ;
input VAR9 ;
input VAR8 ;
input VAR3;
input VAR4;
input VAR1 ;
input VAR5 ;
VAR10 VAR2 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE2 (... | apache-2.0 |
zeruniverse/Single-cycle_CPU | ISE project/ALU.v | 1,226 | module MODULE1(VAR4, VAR1, VAR12, VAR6, VAR2);
input wire [31:0] VAR4; input wire [31:0] VAR1; input wire [2:0] VAR12; output wire VAR6; output reg [31:0] VAR2; wire [31:0] VAR9;
wire [31:0] VAR8;
wire VAR11,VAR7; VAR10 VAR5(VAR4, VAR1, 0, VAR9, VAR11); VAR10 VAR3(VAR4, VAR1, 1, VAR8, VAR7); always @* begin
case(VAR12)... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22a/sky130_fd_sc_hs__o22a.blackbox.v | 1,320 | module MODULE1 (
VAR1 ,
VAR7,
VAR3,
VAR2,
VAR4
);
output VAR1 ;
input VAR7;
input VAR3;
input VAR2;
input VAR4;
supply1 VAR5;
supply0 VAR6;
endmodule | apache-2.0 |
brianbennett/fpga_nes | hw/src/vram.v | 2,353 | module MODULE1
(
input wire VAR10, input wire VAR4, input wire VAR7, input wire [10:0] VAR1, input wire [ 7:0] din, output wire [ 7:0] dout );
wire VAR2;
wire [7:0] VAR12;
VAR9 #(.VAR3(11),
.VAR13(8)) VAR14(
.clk(VAR10),
.VAR8(VAR2),
.VAR11(VAR1),
.VAR6(din),
.VAR5(VAR12)
);
assign VAR2 = (VAR4) ? ~VAR7 : 1'b0;
assign ... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_1.behavioral.pp.v | 7,224 | module MODULE1( VAR12, VAR9, VAR8, VAR7, VAR11, VAR10, VAR2, VAR1, VAR5 );
input VAR2, VAR10, VAR8, VAR11, VAR9, VAR12;
inout VAR1, VAR5;
output VAR7;
VAR6 VAR4(.VAR12(VAR12),.VAR9(VAR9),.VAR8(VAR8),.VAR7(VAR7),.VAR11(VAR11),.VAR10(VAR10),.VAR2(VAR2),.VAR1(VAR1),.VAR5(VAR5));
VAR6 VAR3(.VAR12(VAR12),.VAR9(VAR9),.VAR8(V... | apache-2.0 |
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