repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
Jawanga/ece385lab9 | lab9_soc/synthesis/submodules/lab9_soc_nios2_qsys_0_jtag_debug_module_tck.v | 8,596 | module MODULE1 (
VAR38,
VAR9,
VAR22,
VAR19,
VAR7,
VAR37,
VAR31,
VAR3,
VAR12,
VAR2,
VAR36,
VAR32,
VAR33,
VAR10,
VAR14,
VAR13,
VAR29,
VAR28,
VAR1,
VAR25,
VAR5,
VAR23,
VAR4,
VAR11,
VAR15,
VAR34,
VAR6,
VAR21,
VAR8,
VAR30,
VAR27
)
;
output [ 1: 0] VAR6;
output VAR21;
output [ 37: 0] VAR8;
output VAR30;
output VAR27;
input [... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/Multipliers/26bit/BinaryKOA/ks26.v | 2,789 | module MODULE1(VAR4, VAR12, VAR13);
input wire [25:0] VAR4;
input wire [25:0] VAR12;
output wire [50:0] VAR13;
wire [18:0] VAR5;
wire [30:0] VAR7;
wire [30:0] VAR1;
wire [15:0] VAR9;
wire [15:0] VAR3;
VAR2 VAR11(VAR4[15:0], VAR12[15:0], VAR7);
VAR6 VAR10(VAR4[25:16], VAR12[25:16], VAR5);
assign VAR9[9:0] = VAR4[25:16] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2/sky130_fd_sc_hs__nor2.functional.pp.v | 1,681 | module MODULE1 (
VAR6,
VAR1,
VAR7 ,
VAR5 ,
VAR8
);
input VAR6;
input VAR1;
output VAR7 ;
input VAR5 ;
input VAR8 ;
wire VAR10 ;
wire VAR11;
nor VAR4 (VAR10 , VAR5, VAR8 );
VAR9 VAR3 (VAR11, VAR10, VAR6, VAR1);
buf VAR2 (VAR7 , VAR11 );
endmodule | apache-2.0 |
olajep/oh | src/common/hdl/oh_clockmux.v | 1,186 | module MODULE1 #(parameter VAR6 = 1) (
input [VAR6-1:0] en, input [VAR6-1:0] VAR1, output VAR10
);
localparam VAR3 = VAR9;
generate
if(VAR3& (VAR6==2))
begin : VAR4
VAR8 VAR7 (.VAR1(VAR1[VAR6-1:0]),
.en(en[VAR6-1:0]),
.VAR10(VAR10));
end
else if(VAR3 & (VAR6==4))
begin : VAR4
VAR2 VAR7 (.VAR1(VAR1[VAR6-1:0]),
.en(en[VA... | mit |
olajep/oh | src/common/hdl/oh_ser2par.v | 1,168 | module MODULE1 #(parameter VAR6 = 64, parameter VAR5 = 1, parameter VAR1 = VAR8(VAR6/VAR5) )
(
input clk, input [VAR5-1:0] din, output reg [VAR6-1:0] dout, input VAR3, input VAR4 );
reg [VAR1-1:0] VAR2;
wire [VAR6-1:0] VAR7;
always @ (posedge clk)
if(VAR4 & VAR3)
dout[VAR6-1:0] <= {din[VAR5-1:0],dout[VAR6-1:VAR5]};
els... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s4s/sky130_fd_sc_hd__dlymetal6s4s.blackbox.v | 1,324 | module MODULE1 (
VAR3,
VAR1
);
output VAR3;
input VAR1;
supply1 VAR5;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
hanw/sonic-lite | hw/verilog/enc_dec/decoder.v | 37,401 | module MODULE1 (clk, VAR50, VAR67, VAR38, VAR15, VAR64, VAR51, VAR45);
input clk;
input[65:0] VAR50;
output[63:0] VAR67;
wire[63:0] VAR67;
output[7:0] VAR38;
wire[7:0] VAR38;
output [2:0] VAR15;
wire [2:0] VAR15;
input VAR64;
input VAR51;
output[7:0] VAR45;
wire[7:0] VAR45;
reg[7:0] VAR6;
reg[7:0] VAR23;
reg[7:0] VAR3;... | mit |
jbelloncastro/amber_arm | hw/vlog/amber23/a23_fetch.v | 8,195 | module MODULE1
(
input VAR25,
input [31:0] VAR30,
input VAR17,
input [31:0] VAR4, input [31:0] VAR29,
input VAR22,
output [31:0] VAR13,
input VAR16,
input VAR23, input [3:0] VAR19,
input VAR2, input VAR11, input VAR44, input [31:0] VAR1, input VAR9,
output VAR18,
output [31:0] VAR12,
output [3:0] VAR36,
output VAR7,
in... | lgpl-3.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/rx_queue.v | 18,554 | module MODULE1
parameter VAR120 = VAR113/8,
parameter VAR98 = 0,
parameter VAR131 = 'hff,
parameter VAR64 = 0
)
(output reg [VAR113-1:0] VAR42,
output reg [VAR120-1:0] VAR38,
output reg VAR121,
input VAR44,
input [7:0] VAR58,
input VAR89,
input VAR61,
input VAR25,
output VAR77,
output VAR23,
output VAR7,
output reg [11... | apache-2.0 |
takeshineshiro/fpga_linear_128 | mult8x8_bb.v | 3,861 | module MODULE1 (
VAR3,
VAR1,
VAR2);
input [7:0] VAR3;
input [7:0] VAR1;
output [15:0] VAR2;
endmodule | mit |
hoangt/multiported-ram | lvt_1ht.v | 9,400 | module MODULE1
localparam VAR43 = VAR7(VAR22); localparam VAR16 = VAR9 - 1;
reg [VAR43*VAR9-1:0] VAR3; reg [ VAR9-1:0] VAR39 ; always @(posedge clk) begin
VAR3 <= VAR41;
VAR39 <= VAR4 ;
end
reg [VAR43 -1:0] VAR31 [VAR9-1:0] ; reg [VAR43 -1:0] VAR14 [VAR9-1:0] ; wire [VAR16 *VAR40-1:0] VAR30 [VAR9-1:0] ; reg [VAR16 -1:0... | bsd-3-clause |
dcsun88/ntpserver-fpga | cpu/ip/cpu_auto_pc_0/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_w_axi3_conv.v | 10,416 | module MODULE1 #
(
parameter VAR33 = "none",
parameter integer VAR39 = 1,
parameter integer VAR6 = 32,
parameter integer VAR31 = 32,
parameter integer VAR21 = 0,
parameter integer VAR43 = 1,
parameter integer VAR32 = 1,
parameter integer VAR34 = 1
)
(
input wire VAR25,
input wire VAR4,
input wire VAR9,
input wire [VAR3... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai.symbol.v | 1,358 | module MODULE1 (
input VAR6,
input VAR1,
input VAR2 ,
input VAR7 ,
output VAR3
);
supply1 VAR4;
supply0 VAR5;
endmodule | apache-2.0 |
eleqian/WiDSO | CPLD/DSO_LA/src/dso_trig.v | 1,333 | module MODULE1(VAR9, clk, VAR8, VAR7, VAR10, VAR1, VAR3,
VAR2, VAR5, VAR6);
input VAR9;
input clk;
input VAR8;
input VAR7;
input VAR10;
input VAR1;
input VAR3;
input VAR2;
output VAR5;
output VAR6;
reg VAR5;
reg VAR4;
wire VAR11;
assign VAR11 = (VAR8 | VAR7) & (VAR1 | VAR3) & VAR10;
assign VAR6 = VAR5 & ~VAR4;
always @... | mit |
Jafet95/proy_3_grupo_2_sem_1_2016 | clock_screen_top_v2.v | 9,038 | module MODULE1
(
input wire VAR18, reset,
input wire [7:0] VAR63, VAR14,
input wire VAR29, VAR4,
output wire [7:0]VAR41,VAR66,VAR68,
output wire [7:0]VAR90,VAR6,VAR113,
output wire [7:0]VAR98,VAR5,VAR80,
output reg VAR52,output wire VAR64, VAR109,
output wire [7:0] VAR12
);
wire [9:0] VAR81,VAR37;
wire VAR87;
wire VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfsbp/sky130_fd_sc_hd__sdfsbp.behavioral.pp.v | 2,949 | module MODULE1 (
VAR5 ,
VAR19 ,
VAR25 ,
VAR26 ,
VAR17 ,
VAR16 ,
VAR20,
VAR29 ,
VAR23 ,
VAR28 ,
VAR7
);
output VAR5 ;
output VAR19 ;
input VAR25 ;
input VAR26 ;
input VAR17 ;
input VAR16 ;
input VAR20;
input VAR29 ;
input VAR23 ;
input VAR28 ;
input VAR7 ;
wire VAR18 ;
wire VAR32 ;
wire VAR1 ;
reg VAR30 ;
wire VAR3 ;
wi... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4bb/sky130_fd_sc_hs__and4bb.behavioral.pp.v | 1,895 | module MODULE1 (
VAR3,
VAR13,
VAR9 ,
VAR4 ,
VAR2 ,
VAR14 ,
VAR1
);
input VAR3;
input VAR13;
output VAR9 ;
input VAR4 ;
input VAR2 ;
input VAR14 ;
input VAR1 ;
wire VAR1 VAR12 ;
wire VAR11 ;
wire VAR10;
nor VAR8 (VAR12 , VAR4, VAR2 );
and VAR6 (VAR11 , VAR12, VAR14, VAR1 );
VAR15 VAR7 (VAR10, VAR11, VAR3, VAR13);
buf VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2/sky130_fd_sc_lp__and2.pp.blackbox.v | 1,260 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR7 ,
VAR2,
VAR1,
VAR6 ,
VAR4
);
output VAR5 ;
input VAR3 ;
input VAR7 ;
input VAR2;
input VAR1;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21a/sky130_fd_sc_hdll__o21a.functional.v | 1,420 | module MODULE1 (
VAR5 ,
VAR1,
VAR7,
VAR6
);
output VAR5 ;
input VAR1;
input VAR7;
input VAR6;
wire VAR2 ;
wire VAR4;
or VAR9 (VAR2 , VAR7, VAR1 );
and VAR3 (VAR4, VAR2, VAR6 );
buf VAR8 (VAR5 , VAR4 );
endmodule | apache-2.0 |
masc-ucsc/cmpe220fall16 | rtl/async_ram_1port.v | 4,447 | module MODULE1
( input [VAR6(VAR7)-1:0] VAR9
,input VAR5
,input [VAR8-1:0] VAR10
,output reg [VAR8-1:0] VAR1
);
reg [VAR8-1:0] VAR4 [VAR7-1:0]; reg [VAR8-1:0] VAR3;
VAR2 begin
if (VAR5) begin
VAR3 = 'b0;
end else begin
VAR3 = VAR4[VAR9];
end
end
always @(VAR9 or VAR10 or VAR5) begin
if (VAR5) begin
VAR4[VAR9] = VAR10;
... | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_get_0_val_r_0/synth/zc702_get_0_val_r_0.v | 3,255 | module MODULE1 (
VAR4,
VAR8,
VAR7,
clk,
VAR3,
VAR6
);
input wire [31 : 0] VAR4;
input wire VAR8;
input wire VAR7;
input wire clk;
output wire [31 : 0] VAR3;
output wire VAR6;
VAR2 #(
.VAR5(32)
) VAR1 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7),
.clk(clk),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_common/rtl/bw_io_jp_bs_baseblk.v | 1,951 | module MODULE1(VAR20 ,VAR22 ,VAR23 ,VAR13 ,VAR26
,VAR2 ,in );
output VAR20 ;
output VAR2 ;
input VAR22 ;
input VAR23 ;
input VAR13 ;
input VAR26 ;
input in ;
supply1 VAR28 ;
wire VAR3 ;
wire VAR7 ;
wire VAR12 ;
wire VAR24 ;
VAR11 VAR25 (
.VAR9 (VAR7 ),
.VAR8 (VAR3 ),
.VAR19 (VAR13 ),
.VAR5 (in ),
.VAR6 (VAR26 ),
.VAR17... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21boi/sky130_fd_sc_hd__a21boi.symbol.v | 1,397 | module MODULE1 (
input VAR4 ,
input VAR3 ,
input VAR8,
output VAR7
);
supply1 VAR2;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
myriadrf/A2300 | hdl/wca/WcaPhaseGen.v | 1,433 | module MODULE1 ( VAR3, reset, VAR8, enable, VAR2, VAR5, VAR11, VAR9);
parameter VAR4 = 0;
parameter VAR7 = 32;
input VAR3, reset, VAR8, enable, VAR2;
input wire [11:0] VAR11; inout wire [7:0] VAR9; output reg [VAR7-1:0] VAR5;
wire [VAR7-1:0] VAR10;
VAR6 #(VAR4) VAR1(.reset(reset), .out( VAR10), .VAR11(VAR11), .VAR9(VAR... | gpl-2.0 |
secworks/sha512 | src/rtl/sha512_h_constants.v | 5,100 | module MODULE1(
input wire [1 : 0] VAR17,
output wire [63 : 0] VAR13,
output wire [63 : 0] VAR8,
output wire [63 : 0] VAR5,
output wire [63 : 0] VAR11,
output wire [63 : 0] VAR4,
output wire [63 : 0] VAR18,
output wire [63 : 0] VAR2,
output wire [63 : 0] VAR1
);
reg [63 : 0] VAR7;
reg [63 : 0] VAR3;
reg [63 : 0] VAR14;... | bsd-2-clause |
wgml/sysrek | arithm/ipcore_dir/EpF.v | 28,086 | module MODULE2 (
clk, VAR226, VAR156, VAR239, VAR237
);
input clk;
input VAR226;
output [19 : 0] VAR156;
input [18 : 0] VAR239;
input [18 : 0] VAR237;
wire \VAR270/VAR140 ;
wire \VAR270/VAR154 ;
wire \VAR270/VAR187 ;
wire \VAR270/VAR7 ;
wire \VAR270/VAR90 ;
wire \VAR270/VAR284 ;
wire \VAR270/VAR258 ;
wire \VAR270/VAR15... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41ai/sky130_fd_sc_lp__o41ai_0.v | 2,424 | module MODULE2 (
VAR4 ,
VAR2 ,
VAR10 ,
VAR1 ,
VAR7 ,
VAR11 ,
VAR9,
VAR12,
VAR3 ,
VAR6
);
output VAR4 ;
input VAR2 ;
input VAR10 ;
input VAR1 ;
input VAR7 ;
input VAR11 ;
input VAR9;
input VAR12;
input VAR3 ;
input VAR6 ;
VAR8 VAR5 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR9... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_queues/sram_rr_output_queues/src/oq_regs_ctrl.v | 34,251 | module MODULE1
parameter VAR6 = 13,
parameter VAR10 = 8,
parameter VAR126 = 8,
parameter VAR29 = VAR51(VAR126),
parameter VAR81 = 17,
parameter VAR116 = VAR51(VAR81),
parameter VAR12 = 2048/VAR10, parameter VAR13 = 60/VAR10 + 1,
parameter VAR101 = VAR51((2**VAR6)/VAR13),
parameter VAR35 = 11,
parameter VAR121 = VAR35-V... | mit |
intelligenttoasters/CPC2.0 | FPGA/rtl/template.v | 1,517 | module MODULE1 (
);
endmodule | gpl-3.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/db/ip/SOC/submodules/fpoint_hw_qsys.v | 282,773 | module MODULE1
(
VAR66,
VAR7,
VAR77,
VAR88,
VAR80,
VAR83) ;
input VAR66;
input VAR7;
input VAR77;
input [31:0] VAR88;
input [31:0] VAR80;
output [31:0] VAR83;
tri0 VAR66;
tri1 VAR7;
reg VAR55;
reg VAR33;
reg VAR29;
reg VAR79;
reg VAR22;
reg VAR28;
reg VAR25;
reg VAR37;
reg [9:0] VAR76;
reg [9:0] VAR26;
reg [9:0] VAR5;
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111ai/sky130_fd_sc_hd__o2111ai.functional.v | 1,514 | module MODULE1 (
VAR6 ,
VAR1,
VAR3,
VAR5,
VAR9,
VAR4
);
output VAR6 ;
input VAR1;
input VAR3;
input VAR5;
input VAR9;
input VAR4;
wire VAR8 ;
wire VAR2;
or VAR11 (VAR8 , VAR3, VAR1 );
nand VAR10 (VAR2, VAR9, VAR5, VAR4, VAR8);
buf VAR7 (VAR6 , VAR2 );
endmodule | apache-2.0 |
joaocarlos/udlx-verilog | rtl/fetch/top_fetch.v | 4,396 | module MODULE1
parameter VAR13 = 20,
parameter VAR6 = 32,
parameter VAR9 = 20'h0
)(
input clk, input VAR4, input en,
input VAR8,
input VAR10, input [VAR13-1:0] VAR11,
output [VAR13-1:0] VAR7, output [VAR13-1:0] VAR12, input VAR2
);
reg [VAR13-1:0] VAR5;
reg [VAR13-1:0] VAR1;
reg [VAR13-1:0] VAR3;
always@
begin
VAR3 = V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2.functional.pp.v | 1,867 | module MODULE1 (
VAR8 ,
VAR12 ,
VAR6,
VAR10,
VAR4 ,
VAR5
);
output VAR8 ;
input VAR12 ;
input VAR6;
input VAR10;
input VAR4 ;
input VAR5 ;
wire VAR7 ;
wire VAR1;
not VAR9 (VAR7 , VAR12 );
VAR2 VAR3 (VAR1, VAR7, VAR6, VAR10);
buf VAR11 (VAR8 , VAR1 );
endmodule | apache-2.0 |
lvd2/zxevo | fpga/base_trdemu/trunk/z80/zmem.v | 9,807 | module MODULE1(
input wire VAR32,
input wire VAR14,
input wire VAR68, input wire VAR20,
input wire VAR13, input wire VAR7, input wire VAR31, input wire VAR60,
input wire [15:0] VAR9,
input wire [ 7:0] VAR47, output wire [ 7:0] VAR6,
output wire VAR74,
input wire VAR17,
input wire VAR70,
input wire VAR64,
input wire VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311o/sky130_fd_sc_ms__a311o.functional.v | 1,471 | module MODULE1 (
VAR6 ,
VAR10,
VAR2,
VAR5,
VAR1,
VAR3
);
output VAR6 ;
input VAR10;
input VAR2;
input VAR5;
input VAR1;
input VAR3;
wire VAR4 ;
wire VAR11;
and VAR8 (VAR4 , VAR5, VAR10, VAR2 );
or VAR7 (VAR11, VAR4, VAR3, VAR1);
buf VAR9 (VAR6 , VAR11 );
endmodule | apache-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/Audio_PLL.v | 14,893 | module MODULE1 (
VAR45,
VAR20,
VAR10);
input VAR45;
input VAR20;
output VAR10;
tri0 VAR45;
wire [5:0] VAR23;
wire [0:0] VAR72 = 1'h0;
wire [0:0] VAR64 = VAR23[0:0];
wire VAR10 = VAR64;
wire VAR22 = VAR20;
wire [1:0] VAR95 = {VAR72, VAR22};
VAR11 VAR26 (
.VAR45 (VAR45),
.VAR24 (VAR95),
.clk (VAR23),
.VAR12 (),
.VAR35 ()... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_port_monitor_128.v | 8,208 | module MODULE1 #(
parameter VAR7 = 9'd128,
parameter VAR13 = 512,
parameter VAR26 = (VAR13 - 4),
parameter VAR38 = VAR33((2**VAR33(VAR13))+1),
parameter VAR43 = 1
)
(
input VAR3,
input VAR42,
input [VAR7:0] VAR10, input VAR12, output VAR40,
output [VAR7-1:0] VAR39, output VAR11, input [VAR38-1:0] VAR22,
output VAR1, in... | gpl-3.0 |
DreamSourceLab/DSLogic-hdl | src/uart/uart_top.v | 2,229 | module MODULE1
(
VAR15, reset,
VAR2, VAR9,
VAR1, VAR6,
VAR17, VAR14, VAR10,
VAR11, VAR13,
VAR18
);
input VAR15; input reset; input VAR2; output VAR9; input [7:0] VAR17; input VAR14; output VAR10; output [7:0] VAR1; output VAR6; input [11:0] VAR11; input [15:0] VAR13;
output VAR18;
wire VAR4;
assign VAR18 = VAR4;
VAR5 V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/maj3/sky130_fd_sc_hs__maj3.behavioral.v | 2,130 | module MODULE1 (
VAR16 ,
VAR4 ,
VAR2 ,
VAR8 ,
VAR9,
VAR6
);
output VAR16 ;
input VAR4 ;
input VAR2 ;
input VAR8 ;
input VAR9;
input VAR6;
wire VAR12, VAR1 ;
wire VAR12, VAR5 ;
wire VAR7 ;
wire VAR14 ;
wire VAR19;
or VAR18 (VAR7 , VAR2, VAR4 );
and VAR11 (VAR1 , VAR7, VAR8 );
and VAR15 (VAR5 , VAR4, VAR2 );
or VAR10 (VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxtn/sky130_fd_sc_hs__dlxtn.functional.v | 1,713 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR7 ,
VAR1 ,
VAR13
);
input VAR3 ;
input VAR11 ;
output VAR7 ;
input VAR1 ;
input VAR13;
wire VAR2 VAR5 ;
wire VAR2 VAR4;
wire VAR2 VAR9 ;
wire VAR6 ;
not VAR12 (VAR6 , VAR13 );
VAR10 VAR8 (VAR5 , VAR1, VAR6, VAR3, VAR11);
buf VAR14 (VAR7 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_2.v | 2,398 | module MODULE2 (
VAR7 ,
VAR6,
VAR1,
VAR11 ,
VAR8 ,
VAR9,
VAR10,
VAR2 ,
VAR4
);
output VAR7 ;
input VAR6;
input VAR1;
input VAR11 ;
input VAR8 ;
input VAR9;
input VAR10;
input VAR2 ;
input VAR4 ;
VAR5 VAR3 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR4... | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_pc_1/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_axilite_conv.v | 9,137 | module MODULE1 #
(
parameter VAR60 = "VAR59",
parameter integer VAR63 = 1,
parameter integer VAR2 = 32,
parameter integer VAR4 = 32,
parameter integer VAR8 = 1,
parameter integer VAR47 = 1,
parameter integer VAR46 = 1,
parameter integer VAR36 = 1
)
(
input wire VAR18,
input wire VAR43,
input wire [VAR63-1:0] VAR66,
inp... | mit |
plindstroem/oh | memory/hdl/memory_writemask.v | 1,878 | module MODULE1(
VAR2,
write, VAR1, addr
);
input write;
input [1:0] VAR1;
input [2:0] addr;
output [7:0] VAR2;
reg [7:0] VAR2;
always@*
casez({write, VAR1[1:0],addr[2:0]})
6'b100000 : VAR2[7:0] = 8'b00000001;
6'b100001 : VAR2[7:0] = 8'b00000010;
6'b100010 : VAR2[7:0] = 8'b00000100;
6'b100011 : VAR2[7:0] = 8'b00001000;
... | gpl-3.0 |
HarmonInstruments/hififo | hdl/sync.v | 1,950 | module MODULE2
(
input VAR2,
input in,
output out
);
reg [2:0] VAR7 = 0;
always @(posedge VAR2)
VAR7 <= {VAR7[1:0], in};
assign out = VAR7[2];
endmodule
module MODULE1
(
input VAR2,
input in,
output reg out = 0
);
reg VAR6 = 0;
always @(posedge VAR2)
begin
VAR6 <= in;
out <= in & ~VAR6;
end
endmodule
module MODULE4
(
i... | gpl-3.0 |
sirchuckalot/zet | cores/vga/rtl/fml/vga_text_mode_fml.v | 6,480 | module MODULE1 (
input clk,
input rst,
input enable,
output reg [16:1] VAR8,
input [15:0] VAR23,
output VAR6,
input [9:0] VAR30,
input [9:0] VAR7,
input VAR34,
input VAR32,
output VAR1,
input [5:0] VAR19,
input [5:0] VAR3,
input [4:0] VAR40,
input [6:0] VAR22,
output reg [3:0] VAR11,
output VAR35
);
reg [ 6:0] VAR42;
r... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4bb/sky130_fd_sc_ls__or4bb.behavioral.pp.v | 1,988 | module MODULE1 (
VAR13 ,
VAR4 ,
VAR17 ,
VAR8 ,
VAR9 ,
VAR1,
VAR2,
VAR7 ,
VAR10
);
output VAR13 ;
input VAR4 ;
input VAR17 ;
input VAR8 ;
input VAR9 ;
input VAR1;
input VAR2;
input VAR7 ;
input VAR10 ;
wire VAR15 ;
wire VAR12 ;
wire VAR6;
nand VAR16 (VAR15 , VAR9, VAR8 );
or VAR14 (VAR12 , VAR17, VAR4, VAR15 );
VAR5 VAR... | apache-2.0 |
freecores/eco32 | fpga/src/tmr/tmr.v | 1,753 | module MODULE1(clk, reset,
en, wr, addr,
VAR4, VAR5,
VAR3, irq);
input clk;
input reset;
input en;
input wr;
input [3:2] addr;
input [31:0] VAR4;
output reg [31:0] VAR5;
output VAR3;
output irq;
reg [31:0] counter;
reg [31:0] VAR8;
reg VAR1;
reg VAR7;
reg VAR6;
reg VAR2;
always @(posedge clk) begin
if (VAR1 == 1) begin... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_4.behavioral.v | 8,908 | module MODULE1( VAR56, VAR14, VAR40, VAR12, VAR34 );
input VAR12, VAR40, VAR56, VAR14;
output VAR34;
reg VAR48;
VAR68 VAR4(.VAR56(VAR56),.VAR14(VAR14),.VAR40(VAR40),.VAR12(VAR12),.VAR34(VAR34),.VAR48(VAR48));
VAR68 VAR84(.VAR56(VAR56),.VAR14(VAR14),.VAR40(VAR40),.VAR12(VAR12),.VAR34(VAR34),.VAR48(VAR48));
not VAR2(VAR6... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/altpllpll.v | 15,902 | module MODULE1 (
VAR73,
VAR4,
VAR8);
input VAR73;
output VAR4;
output VAR8;
wire [9:0] VAR99;
wire [0:0] VAR70 = 1'h0;
wire [1:1] VAR66 = VAR99[1:1];
wire [0:0] VAR63 = VAR99[0:0];
wire VAR4 = VAR63;
wire VAR8 = VAR66;
wire VAR51 = VAR73;
wire [1:0] VAR26 = {VAR70, VAR51};
VAR2 VAR37 (
.VAR29 (VAR26),
.clk (VAR99),
.VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4b/sky130_fd_sc_hs__or4b.functional.pp.v | 1,880 | module MODULE1 (
VAR12,
VAR3,
VAR9 ,
VAR11 ,
VAR14 ,
VAR10 ,
VAR8
);
input VAR12;
input VAR3;
output VAR9 ;
input VAR11 ;
input VAR14 ;
input VAR10 ;
input VAR8 ;
wire VAR8 VAR15 ;
wire VAR5 ;
wire VAR7;
not VAR1 (VAR15 , VAR8 );
or VAR6 (VAR5 , VAR15, VAR10, VAR14, VAR11 );
VAR2 VAR4 (VAR7, VAR5, VAR12, VAR3);
buf VAR... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_synth.v | 1,503 | module MODULE1 #(parameter VAR22(VAR20)
, parameter VAR22(VAR7)
, parameter VAR9=0
, parameter VAR8=VAR12(VAR7)
)
(input VAR6
, input VAR3
, input VAR23
, input [VAR8-1:0] VAR15
, input [VAR5(VAR20, 1):0] VAR14
, input VAR4
, input [VAR8-1:0] VAR1
, output logic [VAR5(VAR20, 1):0] VAR2
, input VAR19
, input [VAR8-1:0] ... | bsd-3-clause |
yugr/primogen | src/prio_enc.v | 1,666 | module MODULE1 #(
parameter VAR2 = 4
) (VAR11, VAR9);
localparam VAR7 = 1 << VAR2;
localparam VAR5 = VAR7 - 1;
input [VAR5:0] VAR11;
output reg [VAR2 - 1:0] VAR9;
integer VAR8, VAR6;
reg [VAR5:0] VAR4;
always @* begin
VAR9 = 0;
VAR4 = VAR11;
for (VAR8 = VAR2 - 1; VAR8 >= 0; VAR8 = VAR8 - 1) begin
VAR6 = 1 << VAR8;
if (... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2b/sky130_fd_sc_lp__nor2b.blackbox.v | 1,307 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR2
);
output VAR4 ;
input VAR3 ;
input VAR2;
supply1 VAR6;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
ipcoregarfield/GEM_Project | Verilog_Code_Frame.v | 3,337 | module MODULE1 #(parameter VAR1 = 3, VAR9 = 2)
(
input VAR14, VAR23,
output VAR4
);
localparam VAR15 = VAR1 / VAR9;
localparam VAR24 = VAR1 - VAR9 * VAR15;
localparam VAR17 = VAR9;
localparam VAR18 = VAR17 - VAR24;
localparam VAR10 = VAR24;
localparam VAR13 = VAR18 * VAR15;
localparam VAR12 = VAR10 * (VAR15 + 1);
local... | gpl-3.0 |
finnball/igloo | infra/hdl/uart_tx.v | 1,530 | module MODULE1(
input VAR3,
input [VAR2 - 1 : 0] VAR8,
input VAR11,
output VAR5,
output VAR9
);
localparam VAR7 = 3'd0;
localparam VAR10 = 3'd1;
localparam VAR1 = 3'd2;
localparam VAR6 = 3'd3;
reg [2:0] state = VAR7;
reg [2:0] VAR13 = 0;
reg [VAR2 - 1 : 0] VAR4 = 0;
reg VAR12 = 1;
always @ (posedge VAR3)
begin
case (st... | gpl-3.0 |
mshr-h/fibonacci_verilog | fpga/mu500rx/fpga_top.v | 2,409 | module MODULE1
(
input wire VAR2,
input wire VAR32,
input wire clk,
input wire VAR5,
input wire VAR14,
output wire [7:0] VAR15,
output wire [7:0] VAR27,
output wire [7:0] VAR21,
output wire [7:0] VAR4,
output wire [7:0] VAR23,
output wire [7:0] VAR41,
output wire [7:0] VAR24,
output wire [7:0] VAR1,
output wire [8:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ebufn/sky130_fd_sc_lp__ebufn.behavioral.v | 1,312 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR8
);
output VAR7 ;
input VAR3 ;
input VAR8;
supply1 VAR2;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR5 ;
bufif0 VAR6 (VAR7 , VAR3, VAR8 );
endmodule | apache-2.0 |
ptracton/wb_soc_template | rtl/system_controller/system_controller_xilinx.v | 6,519 | module MODULE1 (
VAR9, VAR26, VAR33,
VAR13, VAR48
) ;
input wire VAR13;
input wire VAR48;
output wire VAR9;
output reg VAR26;
output wire VAR33;
wire VAR28;
VAR61 VAR22(.VAR59(VAR13), .VAR53(VAR28));
wire VAR10;
VAR64 VAR52 (
.VAR14(1'b1),
.VAR53(VAR9), .VAR59(VAR10) );
VAR30 #(
.VAR17("VAR27"),
.VAR56(6.0),
.VAR11(0.0... | mit |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkMem_Model.v | 5,585 | module MODULE1(VAR21,
VAR26,
VAR57,
VAR15,
VAR38,
VAR65,
VAR55,
VAR23);
input VAR21;
input VAR26;
input [352 : 0] VAR57;
input VAR15;
output VAR38;
input VAR65;
output [255 : 0] VAR55;
output VAR23;
wire [255 : 0] VAR55;
wire VAR38, VAR23;
wire [255 : 0] VAR29, VAR33;
wire VAR1,
VAR14,
VAR31,
VAR4,
VAR63;
wire [255 : 0... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufinv/sky130_fd_sc_hdll__bufinv.functional.pp.v | 1,800 | module MODULE1 (
VAR11 ,
VAR7 ,
VAR10,
VAR9,
VAR6 ,
VAR1
);
output VAR11 ;
input VAR7 ;
input VAR10;
input VAR9;
input VAR6 ;
input VAR1 ;
wire VAR4 ;
wire VAR3;
not VAR12 (VAR4 , VAR7 );
VAR8 VAR2 (VAR3, VAR4, VAR10, VAR9);
buf VAR5 (VAR11 , VAR3 );
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_ddrx_encoder_40.v | 8,560 | module MODULE1
(
VAR8,
VAR15,
VAR10) ;
input VAR8;
input [31:0] VAR15;
output [38:0] VAR10;
tri0 VAR8;
reg [38:0] VAR7;
wire VAR2;
wire VAR14;
wire [31:0] VAR13;
wire [17:0] VAR5;
wire [9:0] VAR9;
wire [4:0] VAR12;
wire [1:0] VAR11;
wire [0:0] VAR3;
wire [5:0] VAR6;
wire [37:0] VAR1;
wire [38:0] VAR4; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlclkp/sky130_fd_sc_ls__dlclkp.functional.pp.v | 1,730 | module MODULE1 (
VAR7,
VAR3,
VAR5 ,
VAR8,
VAR11,
VAR2 ,
VAR4
);
output VAR7;
input VAR3;
input VAR5 ;
input VAR8;
input VAR11;
input VAR2 ;
input VAR4 ;
wire VAR10 ;
wire VAR12;
not VAR9 (VAR12 , VAR5 );
VAR1 VAR13 (VAR10 , VAR3, VAR12, , VAR8, VAR11);
and VAR6 (VAR7 , VAR10, VAR5 );
endmodule | apache-2.0 |
sam-falvo/remex | example/rtl/PolarisCPU.v | 7,935 | module MODULE1(
output VAR134,
output VAR72,
output [3:0] VAR19,
output [63:0] VAR15,
output VAR172,
output VAR106,
input VAR13,
input VAR43,
input [31:0] VAR16,
output [63:0] VAR58,
output VAR136,
input VAR112,
input [63:0] VAR56,
output [63:0] VAR74,
output [63:0] VAR20,
output VAR117,
output VAR100,
output VAR29,
ou... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxbp/sky130_fd_sc_hd__dlxbp.blackbox.v | 1,327 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR6 ,
VAR8
);
output VAR7 ;
output VAR3 ;
input VAR6 ;
input VAR8;
supply1 VAR1;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_mult2_virtex4.v | 2,883 | module MODULE1(
input VAR30,
input VAR32,
input [12:0] VAR46,
input [12:0] VAR9,
output [25:0] VAR4
);
VAR37 #(
.VAR12(1), .VAR6(1), .VAR3("VAR15"), .VAR23(0), .VAR27(0), .VAR38(0), .VAR44("VAR43"), .VAR1(0), .VAR48(0), .VAR34(1), .VAR41(0) ) VAR42 (
.VAR45(), .VAR16(VAR4), .VAR36(), .VAR24(VAR46), .VAR31(VAR9), .VAR28... | lgpl-3.0 |
gbraad/minimig-de1 | rtl/soc/minimig_de2_top.v | 25,024 | module MODULE1 (
input wire VAR118, input wire VAR314, input wire VAR58, input wire VAR150, input wire VAR238, input wire VAR199, output wire VAR49, input wire [ 4-1:0] VAR243, input wire [ 10-1:0] VAR380, output wire [ 7-1:0] VAR354, output wire [ 7-1:0] VAR20, output wire [ 7-1:0] VAR43, output wire [ 7-1:0] VAR177, ... | gpl-3.0 |
HarmonInstruments/verilog | sincos/sincos.v | 1,635 | module MODULE1 (input VAR18,
input [25:0] VAR12,
output signed [VAR1-1:0] VAR14, VAR11);
parameter VAR1 = 25;
parameter VAR10 = 1'b1;
reg [23:0] VAR9 = 0;
reg [23:0] VAR13 = 0;
reg VAR15 = 0;
reg VAR19 = 0;
wire [25:0] VAR4 = (VAR10 << (24)) + ~VAR12;
always @ (posedge VAR18) begin
VAR9 <= VAR12[24] ? ~ VAR12[23:0] : V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3.functional.v | 1,759 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR7,
VAR5
);
output VAR9 ;
input VAR2 ;
input VAR7;
input VAR5;
wire VAR8 ;
wire VAR3;
not VAR4 (VAR8 , VAR2 );
VAR6 VAR1 (VAR3, VAR8, VAR7, VAR5);
buf VAR10 (VAR9 , VAR3 );
endmodule | apache-2.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/soc_system/synthesis/submodules/altera_jtag_sld_node.v | 6,698 | module MODULE1 (
VAR73,
VAR40,
VAR78,
VAR54,
VAR61,
VAR77,
VAR6,
VAR25,
VAR27,
VAR45,
VAR4,
VAR37,
VAR55
);
parameter VAR52 = 20;
localparam VAR66 = (1000/VAR52)/2;
localparam VAR29 = 3;
input [VAR29 - 1:0] VAR73;
input VAR40;
output reg [VAR29 - 1:0] VAR78;
output VAR54;
output reg VAR61 = 1'b0;
output VAR77;
output V... | mit |
kernelpanics/Grad | CORDIC-Exponential-Function/Verilog/Exponential/LUT_Z.v | 3,019 | module MODULE1#(parameter VAR6 = 32, parameter VAR4 = 5) (
input wire VAR2,
input wire VAR5,
input wire [VAR4-1:0] VAR3,
output reg [VAR6-1:0] VAR1
);
always @(posedge VAR2)
if (VAR5)
case (VAR3)
5'b00000: VAR1 <= 32'b10111111101011010101000010110010;
5'b00001: VAR1 <= 32'b10111111011110010001001110010101;
5'b00010: VA... | gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/impl/verilog/FIFO_image_filter_img_0_rows_V_channel.v | 3,019 | module MODULE1 (
clk,
VAR22,
VAR19,
VAR18,
VAR24);
parameter VAR9 = 32'd12;
parameter VAR13 = 32'd2;
parameter VAR23 = 32'd3;
input clk;
input [VAR9-1:0] VAR22;
input VAR19;
input [VAR13-1:0] VAR18;
output [VAR9-1:0] VAR24;
reg[VAR9-1:0] VAR10 [0:VAR23-1];
integer VAR25;
always @ (posedge clk)
begin
if (VAR19)
begin
fo... | gpl-3.0 |
Elphel/x393_sata | ahci/ahci_dma_rd_fifo.v | 12,103 | module MODULE1#(
parameter VAR31 = 21,
parameter VAR40 = 3
)(
input VAR58,
input VAR46,
input VAR24,
input VAR47,
input [VAR31-1:0] VAR42, input [1:0] VAR65, input VAR21, input [63:0] din,
input VAR50,
input VAR19,
input VAR26, output VAR27,
output reg VAR66, output VAR49, output [31:0] dout,
output VAR25,
input VAR69,... | gpl-3.0 |
HFoxtail/Mu80 | trunk/ram.v | 2,745 | module MODULE1 (VAR53, VAR26, VAR12, VAR27, VAR13, VAR39, VAR54);
input VAR12;
input [13:0] VAR26;
input [7:0] VAR27;
input VAR13;
input [13:0] VAR53;
output [7:0] VAR39;
output [7:0] VAR54;
tri1 VAR12;
tri0 VAR24;
tri0 VAR68;
wire [7:0] VAR42;
wire [7:0] VAR35;
wire [7:0] VAR39 = VAR42[7:0];
wire [7:0] VAR54 = VAR35[7... | gpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_sgb/msu.v | 5,556 | module MODULE1(
input VAR35,
input enable,
input [13:0] VAR28,
input [7:0] VAR7,
input VAR5,
input [2:0] VAR15,
input [7:0] VAR16,
output [7:0] VAR8,
input VAR41,
input VAR43,
input VAR23,
output [7:0] VAR11,
output [7:0] VAR45,
output VAR37,
output [31:0] VAR17,
output [15:0] VAR10,
input [5:0] VAR22,
input [5:0] VAR4... | gpl-2.0 |
DreamIP/GPStudio | support/process/gradient/hdl/matrix_prod.v | 3,861 | module MODULE1(
VAR15,
VAR7,
VAR14,
VAR16,
VAR21,
VAR13,
VAR6,
VAR9,
VAR19,
VAR10,
VAR11,
VAR5,
VAR3
);
parameter VAR8 = 8;
parameter VAR2 = 9;
input VAR15;
input VAR7;
input VAR10;
input VAR11;
input VAR5;
input VAR14;
input [VAR8-1:0] VAR16, VAR21, VAR13, VAR6;
input [VAR2-1:0] VAR9;
input [VAR2-1:0] VAR19;
output [(... | gpl-3.0 |
julioamerico/OpenCRC | src/SoC/component/Actel/DirectCore/CoreAHBLite/5.0.100/rtl/vlog/amba_bfm/bfm_ahbslaveext.v | 40,413 | module
MODULE1
(
VAR101
,
VAR133
,
VAR182
,
VAR83
,
VAR93
,
VAR185
,
VAR173
,
VAR267
,
VAR188
,
VAR177
,
VAR255
,
VAR160
,
VAR152
,
VAR59
,
VAR74
,
VAR54
,
VAR159
,
VAR86
,
VAR171
,
VAR11
,
VAR14
,
VAR96
)
;
parameter
VAR79
=
10
;
parameter
VAR229
=
256
;
parameter
VAR113
=
2
;
parameter
VAR281
=
" "
;
parameter
VAR163... | gpl-3.0 |
jakubfi/mera400f | src/px.v | 9,567 | module MODULE1(
input VAR76, input VAR106,
input VAR164, input VAR171, output VAR85, output VAR175, output VAR100, output VAR56, output VAR16, output VAR112,
input VAR66, input VAR181, input VAR156, input VAR48, input VAR154, input VAR69, input VAR142, input VAR93, input VAR116, input VAR138, input VAR77, input VAR32, ... | gpl-2.0 |
spike556/HuffmanCode | rtl model/HuffmanCode.v | 16,007 | module MODULE1 (
input clk,
input VAR28,
input [18:0] VAR17,
input [18:0] VAR35,
input [18:0] VAR26,
input [18:0] VAR44,
input [18:0] VAR40,
input [18:0] VAR42,
input [18:0] VAR50,
input [18:0] VAR1,
input [18:0] VAR39,
input [18:0] VAR11,
input VAR65,
output reg VAR37,
output reg [8:0] VAR45,
output reg [3:0] VAR55,
o... | gpl-3.0 |
anderson1008/PAB-NOC | RTL/fsmPG.v | 1,967 | module MODULE1 (clk, reset, VAR8, VAR21, VAR7, VAR2, VAR15, VAR16, VAR9, VAR11);
input clk, reset, VAR8, VAR7, VAR2, VAR15;
input [VAR19-1:0] VAR21;
output reg [VAR18-1:0] VAR16;
output reg VAR9;
output reg VAR11;
wire [5:0] VAR12;
reg [4:0] delay;
assign VAR12 [0] = (VAR8 == VAR13) ? 1 : 0; assign VAR12 [1] = (VAR21 <... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_tag/bsg_tag_client.v | 4,571 | module MODULE1
import VAR26::VAR3;
(
input VAR3 VAR5
, input VAR55
, output VAR44 , output [VAR30-1:0] VAR56
);
localparam VAR58 = 1;
logic VAR2, VAR59, VAR31;
VAR25 @(posedge VAR5.clk)
begin
VAR2 <= VAR5.VAR6;
VAR31 <= VAR5.VAR52;
VAR59 <= VAR2;
end
wire VAR48 = ~VAR2 & VAR31;
wire VAR45 = VAR2;
wire VAR36 = ~VAR2 & ~... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o22a/sky130_fd_sc_hvl__o22a.blackbox.v | 1,360 | module MODULE1 (
VAR8 ,
VAR7,
VAR9,
VAR2,
VAR1
);
output VAR8 ;
input VAR7;
input VAR9;
input VAR2;
input VAR1;
supply1 VAR6;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/intra/ram_frame_row_32x480.v | 4,130 | module MODULE1 (
VAR4 ,
VAR20 ,
VAR9 ,
VAR19 ,
VAR16 ,
VAR5 ,
VAR17 ,
VAR1 ,
VAR10 ,
VAR6 ,
VAR12 ,
VAR18 ,
VAR3 ,
VAR15
);
parameter VAR8=32;
parameter VAR2=9;
input VAR4; input VAR20; input VAR9; input VAR19; input [VAR2-1:0] VAR16; input [VAR8-1:0] VAR17; output [VAR8-1:0] VAR5;
input VAR1; input VAR10; input VAR6; ... | gpl-3.0 |
iafnan/es2-hardwaresecurity | or1200/bench/verilog/or1200_monitor2.v | 3,586 | module MODULE1;
wire [31:0] VAR34;
wire [31:0] VAR17;
wire [31:0] VAR4;
wire [31:0] VAR29;
wire [31:0] VAR23;
wire [31:0] VAR26;
wire [31:0] VAR30;
wire [31:0] VAR25;
wire [31:0] VAR27;
wire [31:0] VAR3;
wire [31:0] VAR9;
wire [31:0] VAR18;
wire [31:0] VAR8;
wire [31:0] VAR16;
wire [31:0] VAR11;
wire [31:0] VAR5;
wire ... | gpl-3.0 |
manu3193/TextEditor | SVN/hvsync_generator.v | 2,181 | module MODULE1(
input wire clk,
input wire reset,
output reg VAR4,
output reg VAR7,
output reg [10:0] VAR2,
output reg [10:0] VAR8,
output reg VAR13
);
parameter VAR1 = 11'd800;
parameter VAR16 = 11'd96;
parameter VAR15 = 11'd2;
parameter VAR12 = 11'd525;
parameter VAR3 = 11'd144 ;
parameter VAR14 = 11'd784 ;
parameter... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdlclkp/sky130_fd_sc_hs__sdlclkp_4.v | 2,135 | module MODULE1 (
VAR6,
VAR3,
VAR7 ,
VAR5 ,
VAR8,
VAR2
);
output VAR6;
input VAR3;
input VAR7 ;
input VAR5 ;
input VAR8;
input VAR2;
VAR1 VAR4 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR6,
VAR3,
VAR7 ,
VAR5
);
output VAR6;
input VAR3;
input VAR7 ;
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrbp/sky130_fd_sc_ms__dfrbp.blackbox.v | 1,378 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR3 ,
VAR1 ,
VAR5
);
output VAR4 ;
output VAR7 ;
input VAR3 ;
input VAR1 ;
input VAR5;
supply1 VAR2;
supply0 VAR8;
supply1 VAR9 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
ThomasLee969/verilog-homework | big_homework/cpu/CPU.v | 2,691 | module MODULE1(reset, clk);
input reset, clk;
reg [31:0] VAR36;
wire [31:0] VAR48;
always @(posedge reset or posedge clk)
if (reset)
VAR36 <= 32'h00000000;
else
VAR36 <= VAR48;
wire [31:0] VAR54;
assign VAR54 = VAR36 + 32'd4;
wire [31:0] VAR20;
VAR40 VAR18(.VAR23(VAR36), .VAR20(VAR20));
wire [1:0] VAR12;
wire [1:0] VAR... | mit |
trevortheblack/NewLondo16 | Verilog/RFT/asl.v | 2,087 | module MODULE1(VAR4, VAR2, VAR6, VAR3, VAR8);
input [31:0] VAR4, VAR2;
input [3:0] VAR6;
output [31:0] VAR3;
input VAR8;
wire VAR7 = |VAR2[31:5];
wire VAR5 = VAR2[4:0];
wire [4:0] VAR1 = (VAR5== 32'b0) ?
( {1'b0, VAR6} + 5'b1) : (VAR5 + {1'b0, VAR6});
assign VAR3 = (VAR7==1'b1) ? 32'b0 : (
(VAR1 == 5'b00000) ? VAR4[31:... | mit |
davidkoltak/tawas-core | ip/enet/rtl/sgmii_fifo.v | 2,795 | module MODULE1
(
input VAR9,
input VAR13,
input VAR4,
input [8:0] VAR22,
input VAR7,
output VAR15,
output [8:0] VAR23,
input VAR20,
output VAR25
);
parameter VAR2 = 32; parameter VAR11 = 12;
reg [5:0] VAR19;
wire VAR26 = (!VAR7 || (VAR19 == VAR11));
always @ (posedge VAR13 or posedge VAR9)
if (VAR9)
VAR19 <= 6'd0;
else... | mit |
MegaShow/college-programming | Homework/Computer Organization and Interfacing/Single Cycle CPU/Single Cycle CPU.srcs/sources_1/new/ControlUnit.v | 7,883 | module MODULE1(
input [5:0] VAR8,
input VAR4,
output reg VAR10,
output reg [1:0] VAR7,
output reg VAR13,
output reg VAR5,
output reg VAR14,
output reg [2:0] VAR11,
output reg VAR2,
output reg VAR6,
output reg VAR9,
output reg VAR12,
output reg VAR3,
output reg VAR1
); | mit |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_tx_pipeline.v | 22,519 | module MODULE1 #(
parameter VAR43 = 128, parameter VAR48 = "VAR50", parameter VAR14 = 1,
parameter VAR15 = (VAR43 == 128) ? 2 : 1, parameter VAR22 = VAR43 / 8 ) (
input [VAR43-1:0] VAR4, input VAR21, output VAR7, input [VAR22-1:0] VAR58, input VAR28, input [3:0] VAR18,
output [VAR43-1:0] VAR2, output VAR24, output VAR2... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfstp/sky130_fd_sc_hdll__dfstp.functional.pp.v | 1,843 | module MODULE1 (
VAR13 ,
VAR4 ,
VAR15 ,
VAR7,
VAR6 ,
VAR5 ,
VAR14 ,
VAR10
);
output VAR13 ;
input VAR4 ;
input VAR15 ;
input VAR7;
input VAR6 ;
input VAR5 ;
input VAR14 ;
input VAR10 ;
wire VAR8;
wire VAR2 ;
not VAR9 (VAR2 , VAR7 );
VAR3 VAR1 VAR11 (VAR8 , VAR15, VAR4, VAR2, , VAR6, VAR5);
buf VAR12 (VAR13 , VAR8 );
en... | apache-2.0 |
gbraad/minimig-de1 | rtl/or1200/or1200_spram_1024x8.v | 8,581 | module MODULE1(
VAR9, VAR21, VAR15,
clk, rst, VAR13, VAR7, VAR24, addr, VAR3, VAR32
);
parameter VAR16 = 10;
parameter VAR19 = 8;
input VAR9;
input [VAR28 - 1:0] VAR15;
output VAR21;
input clk; input rst; input VAR13; input VAR7; input VAR24; input [VAR16-1:0] addr; input [VAR19-1:0] VAR3; output [VAR19-1:0] VAR32;
ass... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decap/sky130_fd_sc_ls__decap.pp.symbol.v | 1,200 | module MODULE1 (
input VAR1 ,
input VAR4,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
SeanZarzycki/openSPARC-FPU | project/src/fpu_cnt_lead0_lvl1.v | 1,755 | module MODULE1 (
din,
VAR1,
VAR2,
VAR3
);
input [3:0] din;
output VAR1; output VAR2; output VAR3;
wire VAR1;
wire VAR2;
wire VAR3;
assign VAR1= (!(|din[3:0]));
assign VAR2= (!(|din[3:2]));
assign VAR3= ((!VAR2) && (!din[3]))
|| (VAR2 && (!din[1]));
endmodule | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/add_routing_header.v | 1,579 | module MODULE1
parameter VAR12 = 1)
(input clk, input reset, input VAR9,
input [35:0] VAR7, input VAR5, output VAR8,
output [35:0] VAR6, output VAR4, input VAR10);
reg [1:0] VAR2;
wire [1:0] VAR1 = VAR11;
wire [15:0] VAR3 = VAR7[15:0];
always @(posedge clk)
if(reset)
VAR2 <= VAR12 ? 0 : 1;
else
if(VAR4 & VAR10)
if(VAR6... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_axis_fifo/address_gray_pipelined.v | 5,149 | module MODULE1 (
input VAR2,
input VAR11,
input VAR27,
output reg VAR14,
output [VAR12-1:0] VAR10,
output [VAR12-1:0] VAR19,
output reg [VAR12:0] VAR4,
input VAR24,
input VAR1,
output reg VAR21,
input VAR17,
output reg VAR3,
output [VAR12-1:0] VAR23,
output reg [VAR12:0] VAR15
);
parameter VAR12 = 4;
reg [VAR12:0] VAR2... | gpl-3.0 |
CMCammarano/EE-454-Portable-Ultrasound | Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra.v | 10,498 | module MODULE1 (
input clk,
input [1:0] VAR20,
input VAR10,
input ack,
input VAR19,
input VAR4,
output [4095:0] VAR17,
output [7:0] VAR16
);
reg [3:0] VAR9;
reg VAR14;
wire [8191:0] VAR1;
wire [4095:0] VAR6;
wire [4095:0] VAR12;
wire [7:0] VAR15;
wire [7:0] VAR2;
VAR3 VAR5 (
.clk (clk),
.VAR10 (VAR10),
.VAR14 (VAR14),
... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_2.behavioral.pp.v | 1,407 | module MODULE1( VAR9, VAR10, VAR6, VAR5, VAR7, VAR3, VAR4 );
input VAR6, VAR7, VAR10, VAR5;
inout VAR3, VAR4;
output VAR9;
VAR2 VAR8(.VAR9(VAR9),.VAR10(VAR10),.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7),.VAR3(VAR3),.VAR4(VAR4));
VAR2 VAR1(.VAR9(VAR9),.VAR10(VAR10),.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7),.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ha/sky130_fd_sc_ls__ha_4.v | 2,184 | module MODULE2 (
VAR10,
VAR9 ,
VAR2 ,
VAR3 ,
VAR7,
VAR8,
VAR1 ,
VAR4
);
output VAR10;
output VAR9 ;
input VAR2 ;
input VAR3 ;
input VAR7;
input VAR8;
input VAR1 ;
input VAR4 ;
VAR6 VAR5 (
.VAR10(VAR10),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE2... | apache-2.0 |
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