repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
YoelRP/PROYECTO | bin/enpoint/transaction/CRC16_D72.v | 4,904 | module MODULE1(
VAR6,
VAR2,
VAR1
);
output reg [15:0] VAR6;
input wire [71:0] VAR2;
input wire [15:0] VAR1;
reg [71:0] VAR4;
reg [15:0] VAR3;
reg [15:0] VAR5;
always @ (*)
begin
VAR4 = VAR2;
VAR3 = VAR1;
VAR5[0] = VAR4[71] ^ VAR4[69] ^ VAR4[68] ^ VAR4[67] ^ VAR4[66] ^ VAR4[65] ^ VAR4[64] ^ VAR4[63] ^ VAR4[62] ^ VAR4[61... | gpl-3.0 |
devinacker/sd2snes | verilog/sd2snes/mcu_cmd.v | 16,286 | module MODULE1(
input clk,
input VAR22,
input VAR50,
input [7:0] VAR52,
input [7:0] VAR7,
output [2:0] VAR66,
output VAR10,
output VAR4,
output VAR6,
input VAR62,
output [7:0] VAR29,
input [7:0] VAR36,
output [7:0] VAR48,
input [31:0] VAR37,
input [2:0] VAR5,
output [23:0] VAR1,
output [23:0] VAR56,
output [23:0] VAR23... | gpl-2.0 |
lokisz/openzcore | pippo-0.9/rtl/verilog/pippo_pipectrl.v | 5,854 | module MODULE1(
VAR10, VAR6, VAR5,
VAR9, VAR3, VAR4, VAR1,
VAR13, VAR2, VAR11, VAR8, VAR12
);
input VAR9;
input VAR3;
input VAR1;
input [1:0] VAR4;
output VAR13;
output VAR2;
output VAR11;
output VAR8;
output VAR12;
input VAR10;
input VAR6;
output VAR5;
wire VAR7;
assign VAR5 = VAR10 | VAR6;
assign VAR13 = VAR5;
assign... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_sio_macro/sky130_fd_io__top_sio_macro.functional.pp.v | 10,516 | module MODULE1 (
VAR24,
VAR51,
VAR15,
VAR20,
VAR62,
VAR11,
VAR41,
VAR40,
VAR14,
VAR63,
VAR1,
VAR46,
VAR27,
VAR18,
VAR77,
VAR13,
VAR5,
VAR53,
VAR64,
VAR55,
VAR48,
VAR35,
VAR7,
VAR29,
VAR75,
VAR74,
VAR69,
VAR25,
VAR23,
VAR59,
VAR57,
VAR36,
VAR80,
VAR79,
VAR32,
VAR58,
VAR37,
VAR19,
VAR17,
VAR34,
VAR72,
VAR31
);
wire VAR38... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregrbp/sky130_fd_sc_lp__sregrbp.behavioral.v | 2,858 | module MODULE1 (
VAR3 ,
VAR28 ,
VAR4 ,
VAR29 ,
VAR18 ,
VAR9 ,
VAR14
);
output VAR3 ;
output VAR28 ;
input VAR4 ;
input VAR29 ;
input VAR18 ;
input VAR9 ;
input VAR14;
supply1 VAR13;
supply0 VAR10;
supply1 VAR26 ;
supply0 VAR15 ;
wire VAR24 ;
wire reset ;
wire VAR1 ;
reg VAR12 ;
wire VAR2 ;
wire VAR30 ;
wire VAR21 ;
wir... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_p0_afi_mux.v | 6,100 | module MODULE1(
VAR35,
VAR30,
VAR41,
VAR21,
VAR54,
VAR33,
VAR40,
VAR19,
VAR16,
VAR7,
VAR45,
VAR25,
VAR43,
VAR63,
VAR51,
VAR5,
VAR3,
VAR57,
VAR9,
VAR37,
VAR14,
VAR62,
VAR55,
VAR60,
VAR53,
VAR32,
VAR23,
VAR50,
VAR10,
VAR28,
VAR27,
VAR42,
VAR24,
VAR11,
VAR58,
VAR17,
VAR44,
VAR1,
VAR49,
VAR36,
VAR47,
VAR38,
VAR31,
VAR8,
VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4bb/sky130_fd_sc_hs__nor4bb.behavioral.v | 1,892 | module MODULE1 (
VAR13 ,
VAR2 ,
VAR7 ,
VAR11 ,
VAR12 ,
VAR15,
VAR4
);
output VAR13 ;
input VAR2 ;
input VAR7 ;
input VAR11 ;
input VAR12 ;
input VAR15;
input VAR4;
wire VAR12 VAR14 ;
wire VAR9 ;
wire VAR6;
nor VAR1 (VAR14 , VAR2, VAR7 );
and VAR5 (VAR9 , VAR14, VAR11, VAR12 );
VAR8 VAR10 (VAR6, VAR9, VAR15, VAR4);
buf ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3b/sky130_fd_sc_hd__nor3b.behavioral.v | 1,513 | module MODULE1 (
VAR10 ,
VAR12 ,
VAR6 ,
VAR2
);
output VAR10 ;
input VAR12 ;
input VAR6 ;
input VAR2;
supply1 VAR7;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR8 ;
wire VAR3 ;
wire VAR11;
nor VAR13 (VAR3 , VAR12, VAR6 );
and VAR4 (VAR11, VAR2, VAR3 );
buf VAR5 (VAR10 , VAR11 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21o/sky130_fd_sc_lp__a21o.symbol.v | 1,341 | module MODULE1 (
input VAR4,
input VAR8,
input VAR6,
output VAR7
);
supply1 VAR3;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/ppu/ppu_ri.v | 14,173 | module MODULE1
(
input wire VAR40, input wire VAR7, input wire [ 2:0] VAR24, input wire VAR46, input wire VAR57, input wire [ 7:0] VAR45, input wire [13:0] VAR55, input wire [ 7:0] VAR79, input wire [ 7:0] VAR54, input wire VAR37, input wire [ 7:0] VAR15, input wire VAR64, input wire VAR36, output wire [ 7:0] VAR44, ou... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvp/sky130_fd_sc_hs__einvp.functional.pp.v | 1,764 | module MODULE1 (
VAR2,
VAR6,
VAR4 ,
VAR11 ,
VAR9
);
input VAR2;
input VAR6;
output VAR4 ;
input VAR11 ;
input VAR9 ;
wire VAR5 ;
wire VAR1;
VAR3 VAR10 (VAR5 , VAR11, VAR2, VAR6 );
VAR3 VAR7 (VAR1, VAR9, VAR2, VAR6 );
notif1 VAR8 (VAR4 , VAR5, VAR1);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3b/sky130_fd_sc_lp__or3b.behavioral.v | 1,467 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR7 ,
VAR8
);
output VAR4 ;
input VAR3 ;
input VAR7 ;
input VAR8;
supply1 VAR6;
supply0 VAR10;
supply1 VAR2 ;
supply0 VAR9 ;
wire VAR5 ;
wire VAR13;
not VAR12 (VAR5 , VAR8 );
or VAR1 (VAR13, VAR7, VAR3, VAR5 );
buf VAR11 (VAR4 , VAR13 );
endmodule | apache-2.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_rdlvl.v | 147,465 | module MODULE1 #
(
parameter VAR96 = 100, parameter VAR123 = 2, parameter VAR89 = 3333, parameter VAR289 = 64, parameter VAR23 = 3, parameter VAR175 = 8, parameter VAR260 = 8, parameter VAR180 = 1, parameter VAR320 = "VAR88", parameter VAR93 = "VAR329", parameter VAR218 = "VAR343", parameter VAR256 = "VAR361", paramete... | mit |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ipshared/xilinx.com/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_wdata_mux.v | 6,888 | module MODULE1 #
(
parameter VAR6 = "none", parameter integer VAR25 = 1, parameter integer VAR29 = 1, parameter integer VAR44 = 1, parameter integer VAR19 = 0 )
(
input wire VAR11,
input wire VAR31,
input wire [VAR29*VAR25-1:0] VAR22,
input wire [VAR29-1:0] VAR37,
input wire [VAR29-1:0] VAR20,
output wire [VAR29-1:0] V... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_out.v | 4,775 | module MODULE1
,parameter VAR10(VAR13)
,parameter VAR10(VAR5)
,parameter VAR10(VAR58)
,parameter VAR29 = 1
,parameter VAR4 = 0
)
(input VAR24
,input VAR71
,input [VAR29-1:0][VAR35(VAR41)-1:0] VAR31
,output [VAR29-1:0][VAR35(VAR41)-1:0] VAR46
,input [VAR35(VAR41)-1:0] VAR60
,output [VAR35(VAR41)-1:0] VAR19
);
VAR59 [VAR... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfsbp/sky130_fd_sc_ls__dfsbp.symbol.v | 1,413 | module MODULE1 (
input VAR5 ,
output VAR7 ,
output VAR3 ,
input VAR9,
input VAR6
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/Altera/bidirbuf_bb.v | 3,486 | module MODULE1 (
VAR3,
VAR2,
VAR4,
VAR1);
input [15:0] VAR3;
input [15:0] VAR2;
inout [15:0] VAR4;
output [15:0] VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/diode/sky130_fd_sc_hdll__diode_4.v | 1,994 | module MODULE1 (
VAR7,
VAR6 ,
VAR2 ,
VAR3 ,
VAR4
);
input VAR7;
input VAR6 ;
input VAR2 ;
input VAR3 ;
input VAR4 ;
VAR5 VAR1 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR7
);
input VAR7;
supply1 VAR6;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR4 ;
VAR5 VAR1 (
.VAR7(VA... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/controller/arb_mux.v | 17,640 | module MODULE1 #
(
parameter VAR15 = 100,
parameter VAR8 = "VAR89",
parameter VAR93 = 11,
parameter VAR58 = 3,
parameter VAR92 = "8",
parameter VAR71 = 4,
parameter VAR40 = 31,
parameter VAR14 = 8,
parameter VAR20 = "VAR37",
parameter VAR42 = "VAR69",
parameter VAR76 = "VAR69",
parameter VAR4 = 4,
parameter VAR73 = 2, ... | lgpl-3.0 |
alexforencich/verilog-ethernet | example/S10MX_DK/fpga_10g/rtl/fpga.v | 11,105 | module MODULE1 (
input wire VAR185,
input wire VAR212,
output wire [3:0] VAR94,
output wire [3:0] VAR69,
input wire [3:0] VAR150,
input wire VAR72,
output wire VAR96,
output wire VAR57,
input wire VAR148,
output wire VAR61,
input wire VAR103,
output wire [3:0] VAR129,
input wire [3:0] VAR32,
input wire VAR26,
output wi... | mit |
racerxdl/SuperINT | Slave Codes/FPGA/SerialRX.v | 3,321 | module MODULE1(clk, VAR11, VAR6, VAR2, VAR13, VAR1);
input clk, VAR11;
output VAR6; output [7:0] VAR2;
parameter VAR16 = 16000000; parameter VAR3 = 115200;
output VAR13; output VAR1;
parameter VAR18 = VAR3*8;
parameter VAR7 = 16;
wire [VAR7:0] VAR14 = ((VAR18<<(VAR7-7))+(VAR16>>8))/(VAR16>>7);
reg [VAR7:0] VAR10;
alway... | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_pipe_rate.v | 46,139 | module MODULE1 #
(
parameter VAR126 = "VAR116", parameter VAR49 = "VAR98", parameter VAR88 = "3.0", parameter VAR102 = "VAR91", parameter VAR78 = "VAR51", parameter VAR69 = "VAR116", parameter VAR92 = "VAR116", parameter VAR32 = "VAR51", parameter VAR39 = 4'd15
)
(
input VAR19,
input VAR128,
input VAR2,
input VAR54,
in... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_rf32x80.v | 15,313 | module MODULE2 (
dout, VAR32,
VAR14, VAR19, VAR10, VAR8, VAR45, din,
VAR3, VAR38, VAR31, VAR11, VAR37, VAR28);
parameter VAR35 = 6 ; parameter VAR1 = 32 ;
input [4:0] VAR19; input VAR14; input VAR10; input [19:0] VAR8; input [4:0] VAR45; input [79:0] din; input VAR11; input VAR28; input VAR37; input VAR31; input VAR3; ... | gpl-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_010bits.v | 1,917 | module MODULE1 (
clk,
VAR17, VAR16, VAR6, VAR7, VAR33, VAR19, VAR14, VAR4,
sum,
);
input clk;
input [VAR13+0-1:0] VAR17, VAR16, VAR6, VAR7, VAR33, VAR19, VAR14, VAR4;
output [VAR13 :0] sum;
reg [VAR13 :0] sum;
wire [VAR13+3-1:0] VAR9;
wire [VAR13+2-1:0] VAR12, VAR22;
wire [VAR13+1-1:0] VAR11, VAR3, VAR21, VAR29;
reg [V... | mit |
mamijaz/RISC-V | src/riscv_pipeline/execute/ALU.v | 7,785 | module MODULE1 #(
parameter VAR31 = 32 ,
parameter VAR12 = 1'b1 ,
parameter VAR1 = 1'b0 ,
parameter VAR22 = 5'b00000 ,
parameter VAR16 = 5'b00001 ,
parameter VAR32 = 5'b00010 ,
parameter VAR9 = 5'b00011 ,
parameter VAR15 = 5'b00100 ,
parameter VAR19 = 5'b00101 ,
parameter VAR23 = 5'b00110 ,
parameter VAR27 = 5'b00111 ,... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2/sky130_fd_sc_hs__or2_4.v | 1,948 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR4 ,
VAR1,
VAR5
);
output VAR7 ;
input VAR2 ;
input VAR4 ;
input VAR1;
input VAR5;
VAR6 VAR3 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR7,
VAR2,
VAR4
);
output VAR7;
input VAR2;
input VAR4;
supply1 VAR1;
supply0 VAR5;
VAR6 VAR3 (
.... | apache-2.0 |
CospanDesign/nysa | nysa/data/template/wishbone/rtl/USER_SLAVE.v | 5,535 | module MODULE1(
module {VAR11} (
input clk,
input rst,
input VAR4,
input VAR3,
input [3:0] VAR2,
input [31:0] VAR10,
input VAR5,
output reg VAR12,
output reg [31:0] VAR13,
input [31:0] VAR1,
output reg VAR7
);
localparam VAR8 = 32'h00000000;
localparam VAR9 = 32'h00000001;
localparam VAR6 = 32'h00000002;
always @ (pose... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111o/sky130_fd_sc_hd__a2111o.functional.v | 1,489 | module MODULE1 (
VAR8 ,
VAR11,
VAR1,
VAR10,
VAR6,
VAR5
);
output VAR8 ;
input VAR11;
input VAR1;
input VAR10;
input VAR6;
input VAR5;
wire VAR2 ;
wire VAR3;
and VAR4 (VAR2 , VAR11, VAR1 );
or VAR9 (VAR3, VAR6, VAR10, VAR2, VAR5);
buf VAR7 (VAR8 , VAR3 );
endmodule | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/impl/ip/hdl/verilog/doHistStretch_sitofp_32s_32_6.v | 1,572 | module MODULE1
VAR4 = 3,
VAR6 = 6,
VAR3 = 32,
VAR8 = 32
)(
input wire clk,
input wire reset,
input wire VAR2,
input wire [VAR3-1:0] VAR19,
output wire [VAR8-1:0] dout
);
wire VAR17;
wire VAR5;
wire VAR11;
wire [31:0] VAR13;
wire VAR7;
wire [31:0] VAR15;
reg [VAR3-1:0] VAR12;
VAR1 VAR9 (
.VAR17 ( VAR17 ),
.VAR5 ( VAR5 )... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_20.v | 16,458 | module MODULE4 (
clk,
reset,
VAR5,
VAR110,
VAR96,
VAR95,
VAR65
);
parameter VAR94 = 18;
parameter VAR84 = 20;
parameter VAR26 = 10;
localparam VAR35 = 26;
input clk;
input reset;
input VAR5;
input VAR110;
input [VAR94-1:0] VAR96; output VAR95;
output [VAR94-1:0] VAR65;
localparam VAR33 = 18; localparam VAR22 = 36; loca... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxbn/sky130_fd_sc_hd__dlxbn.behavioral.v | 2,107 | module MODULE1 (
VAR13 ,
VAR8 ,
VAR4 ,
VAR15
);
output VAR13 ;
output VAR8 ;
input VAR4 ;
input VAR15;
supply1 VAR19;
supply0 VAR16;
supply1 VAR5 ;
supply0 VAR12 ;
wire VAR18 ;
wire VAR10 ;
wire VAR1;
wire VAR3 ;
reg VAR9 ;
wire VAR7 ;
wire 1 ;
not VAR17 (VAR18 , VAR1 );
VAR6 VAR11 (VAR10 , VAR3, VAR18, VAR9, VAR19, VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.v | 2,511 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR11 ,
VAR3 ,
VAR6 ,
VAR5,
VAR12 ,
VAR10 ,
VAR7 ,
VAR2
);
output VAR9 ;
input VAR1 ;
input VAR11 ;
input VAR3 ;
input VAR6 ;
input VAR5;
input VAR12 ;
input VAR10 ;
input VAR7 ;
input VAR2 ;
VAR8 VAR4 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/enet_if/tx_client_fifo_8.v | 54,914 | module MODULE1 #
(
parameter VAR181 = 0
)
(
input VAR115,
input VAR60,
input [7:0] VAR27,
input VAR96,
input VAR152,
output VAR4,
input VAR132,
input VAR12,
output [7:0] VAR9,
output reg VAR155,
output reg VAR107,
input VAR78,
output reg VAR135,
output VAR57,
output [3:0] VAR112,
input VAR51,
input VAR157
);
wire VAR84... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_mux_2to1_n/sky130_fd_sc_hdll__udp_mux_2to1_n.symbol.v | 1,297 | module MODULE1 (
input VAR4,
input VAR1,
output VAR3 ,
input VAR2
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_16.behavioral.v | 1,106 | module MODULE1( VAR5, VAR4 );
input VAR5;
output VAR4;
VAR3 VAR1(.VAR5(VAR5),.VAR4(VAR4));
VAR3 VAR2(.VAR5(VAR5),.VAR4(VAR4)); | apache-2.0 |
ejk43/rfnoc-neuralnet | rfnoc/fpga-src/noc_block_exmodrec.v | 8,935 | module MODULE1 #(
parameter VAR82 = 64'hABCD080D2EC00000,
parameter VAR45 = 11)
(
input VAR35, input VAR89,
input VAR85, input VAR90,
input [63:0] VAR93, input VAR59, input VAR37, output VAR41,
output [63:0] VAR24, output VAR12, output VAR11, input VAR6,
output [63:0] VAR44
);
wire [31:0] VAR50;
wire [7:0] VAR10;
wire ... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/minimig/minimig_syscontrol.v | 1,523 | module MODULE1
(
input clk, input VAR6,
input VAR5, input VAR4, output reset );
reg VAR1, VAR2; reg [2:0] VAR3 = 0; wire rst;
always @(posedge clk) begin
if (VAR6) begin
VAR1 <= VAR4;
VAR2 <= VAR1;
end
end
always @(posedge clk) begin
if (VAR6) begin
if (VAR2)
VAR3 <= 3'd0;
end
else if (!rst && VAR5)
VAR3 <= VAR3 + 3'd1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/decap/sky130_fd_sc_hd__decap.behavioral.pp.v | 1,172 | module MODULE1 (
VAR3,
VAR4,
VAR2 ,
VAR1
);
input VAR3;
input VAR4;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
Elphel/x353 | general/macros353.v | 3,702 | module MODULE2 (VAR12, VAR10, VAR18, VAR7);
output VAR12;
input [3:0] VAR10;
input VAR18, VAR7;
MODULE5 #(.VAR1(1'b0)) VAR4 (.VAR12(VAR12), .VAR21(VAR10[0]), .VAR17(VAR10[1]), .VAR15(VAR10[2]), .VAR22(VAR10[3]), .VAR18(VAR18), .VAR7(VAR7));
VAR11 VAR4 (.VAR12(VAR12), .VAR21(VAR10[0]), .VAR17(VAR10[1]), .VAR15(VAR10[2])... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221oi/sky130_fd_sc_hd__a221oi.symbol.v | 1,402 | module MODULE1 (
input VAR6,
input VAR7,
input VAR2,
input VAR3,
input VAR8,
output VAR9
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR10 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ip/image_processing_2d_design_not_1bit_0_0/synth/image_processing_2d_design_not_1bit_0_0.v | 2,901 | module MODULE1 (
VAR1,
VAR3
);
input wire VAR1;
output wire VAR3;
VAR2 VAR4 (
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_cam_1r1w_replacement.v | 4,693 | module MODULE1
, parameter VAR34 = "VAR13"
, parameter VAR59 = VAR2(VAR24,1)
)
(input VAR27
, input VAR35
, input [VAR59-1:0] VAR37
, input VAR11
, input [VAR59-1:0] VAR49
, output [VAR59-1:0] VAR60
);
if (VAR24 == 0)
begin : VAR8
assign VAR60 = 1'b0;
end
else if (VAR24 == 1)
begin : VAR14
assign VAR60 = 1'b1;
end
else... | bsd-3-clause |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_auto_pc_1/synth/tutorial_auto_pc_1.v | 13,148 | module MODULE1 (
VAR62,
VAR3,
VAR26,
VAR95,
VAR65,
VAR18,
VAR67,
VAR79,
VAR1,
VAR9,
VAR83,
VAR75,
VAR104,
VAR24,
VAR81,
VAR114,
VAR47,
VAR69,
VAR2,
VAR6,
VAR74,
VAR84,
VAR53,
VAR46,
VAR85,
VAR90,
VAR56,
VAR105,
VAR64,
VAR51,
VAR11,
VAR8,
VAR109,
VAR13,
VAR98,
VAR55,
VAR50,
VAR63,
VAR10,
VAR110,
VAR82,
VAR61,
VAR107,
VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2/sky130_fd_sc_ls__mux2_1.v | 2,187 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR1 ,
VAR9 ,
VAR4,
VAR10,
VAR3 ,
VAR2
);
output VAR6 ;
input VAR5 ;
input VAR1 ;
input VAR9 ;
input VAR4;
input VAR10;
input VAR3 ;
input VAR2 ;
VAR7 VAR8 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
P3Stor/P3Stor | pcie/core/trn_tx_128.v | 18,825 | module MODULE1 #(
parameter VAR68 = 100
) (
input VAR23, input VAR78, input VAR25,
input VAR28,
input [1:0] VAR42,
output [5:0] VAR67,
output VAR86,
output VAR74,
input VAR77,
input [127:0] VAR66,
input VAR47,
input [1:0] VAR96,
input VAR31,
input VAR13,
input VAR12,
input VAR34,
input VAR6,
input [5:0] VAR49,
input VA... | gpl-2.0 |
sergev/vak-opensource | hardware/verilator/t_clk.v | 3,009 | module MODULE1 (
VAR2,
VAR14, clk, VAR23
);
input VAR14;
input clk;
input VAR23;
output VAR2; reg VAR2; VAR8 VAR2 = 0;
reg VAR1; VAR8 VAR1=0;
reg [7:0] VAR24; VAR8 VAR24 = 0; wire [7:0] VAR26;
wire [7:0] VAR6;
wire [7:0] VAR19;
wire [7:0] VAR27;
reg [7:0] VAR17; VAR8 VAR17 = 0;
reg [7:0] VAR3;
reg VAR11; VAR8 VAR11 = 0... | apache-2.0 |
jmacneal/Design-Project | Display/Audio_Controller/Altera_UP_Audio_In_Deserializer.v | 6,336 | module MODULE1 (
clk,
reset,
VAR29,
VAR24,
VAR28,
VAR3,
VAR19,
VAR18,
VAR22,
VAR26,
VAR37,
VAR5,
VAR27,
VAR6
);
parameter VAR1 = 32;
parameter VAR13 = 5'd31;
input clk;
input reset;
input VAR29;
input VAR24;
input VAR28;
input VAR3;
input VAR19;
input VAR18;
input VAR22;
input VAR26;
output reg [7:0] VAR37;
output reg ... | gpl-3.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_pc_1/synth/system_auto_pc_1.v | 16,126 | module MODULE1 (
VAR105,
VAR112,
VAR38,
VAR29,
VAR32,
VAR35,
VAR30,
VAR45,
VAR72,
VAR89,
VAR81,
VAR74,
VAR62,
VAR109,
VAR69,
VAR98,
VAR83,
VAR59,
VAR36,
VAR101,
VAR56,
VAR43,
VAR87,
VAR9,
VAR67,
VAR94,
VAR3,
VAR41,
VAR63,
VAR49,
VAR53,
VAR24,
VAR21,
VAR34,
VAR61,
VAR44,
VAR50,
VAR15,
VAR97,
VAR19,
VAR13,
VAR2,
VAR25,
V... | mit |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.srcs/sources_1/bd/design_1/ip/design_1_rst_ps7_0_100M_0/design_1_rst_ps7_0_100M_0_stub.v | 1,795 | module MODULE1(VAR10, VAR6, VAR9,
VAR4, VAR8, VAR7, VAR5, VAR3,
VAR1, VAR2)
;
input VAR10;
input VAR6;
input VAR9;
input VAR4;
input VAR8;
output VAR7;
output [0:0]VAR5;
output [0:0]VAR3;
output [0:0]VAR1;
output [0:0]VAR2;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221ai/sky130_fd_sc_lp__o221ai_1.v | 2,457 | module MODULE2 (
VAR9 ,
VAR1 ,
VAR6 ,
VAR7 ,
VAR12 ,
VAR2 ,
VAR4,
VAR10,
VAR8 ,
VAR3
);
output VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR7 ;
input VAR12 ;
input VAR2 ;
input VAR4;
input VAR10;
input VAR8 ;
input VAR3 ;
VAR5 VAR11 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR12(VAR12),
.VAR2(VAR2),
.VAR4(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkinvlp/sky130_fd_sc_hd__clkinvlp.symbol.v | 1,286 | module MODULE1 (
input VAR6,
output VAR5
);
supply1 VAR3;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2/sky130_fd_sc_ls__nor2.functional.pp.v | 1,783 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR4 ,
VAR11,
VAR13,
VAR7 ,
VAR9
);
output VAR5 ;
input VAR10 ;
input VAR4 ;
input VAR11;
input VAR13;
input VAR7 ;
input VAR9 ;
wire VAR2 ;
wire VAR8;
nor VAR6 (VAR2 , VAR10, VAR4 );
VAR1 VAR12 (VAR8, VAR2, VAR11, VAR13);
buf VAR3 (VAR5 , VAR8 );
endmodule | apache-2.0 |
hhuang25/uwaterloo_ece224 | Lab1Good/timer_1.v | 6,610 | module MODULE1 (
address,
VAR28,
clk,
VAR15,
VAR3,
VAR5,
irq,
VAR9
)
;
output irq;
output [ 15: 0] VAR9;
input [ 2: 0] address;
input VAR28;
input clk;
input VAR15;
input VAR3;
input [ 15: 0] VAR5;
wire VAR26;
wire VAR31;
wire VAR19;
reg [ 3: 0] VAR25;
wire VAR6;
reg VAR20;
wire VAR22;
wire [ 31: 0] VAR16;
reg [ 31: 0]... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Control_Current1.v | 5,513 | module MODULE1
(
VAR1,
reset,
VAR12,
VAR44,
VAR7,
VAR49,
VAR35,
VAR33
);
input VAR1;
input reset;
input VAR12;
input VAR44;
input signed [17:0] VAR7; input signed [17:0] VAR49; input signed [17:0] VAR35; output signed [17:0] VAR33;
wire signed [35:0] VAR40; wire signed [35:0] VAR3; wire signed [17:0] VAR9; wire signed ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxtp/sky130_fd_sc_ls__dfxtp.pp.blackbox.v | 1,279 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR1 ,
VAR4,
VAR5,
VAR7 ,
VAR2
);
output VAR6 ;
input VAR3 ;
input VAR1 ;
input VAR4;
input VAR5;
input VAR7 ;
input VAR2 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffq/gf180mcu_fd_sc_mcu9t5v0__dffq_2.behavioral.pp.v | 2,179 | module MODULE1( VAR2, VAR10, VAR3, VAR7, VAR13 );
input VAR2, VAR10;
inout VAR7, VAR13;
output VAR3;
reg VAR4;
VAR9 VAR6(.VAR2(VAR2),.VAR10(VAR10),.VAR3(VAR3),.VAR7(VAR7),.VAR13(VAR13),.VAR4(VAR4));
VAR9 VAR8(.VAR2(VAR2),.VAR10(VAR10),.VAR3(VAR3),.VAR7(VAR7),.VAR13(VAR13),.VAR4(VAR4));
not VAR1(VAR12,VAR10);
buf VAR5(V... | apache-2.0 |
SeanZarzycki/openSPARC-FPU | project/src/fpu_out_ctl.v | 5,614 | module MODULE1 (
VAR31,
VAR29,
VAR11,
VAR32,
VAR7,
VAR8,
VAR24,
VAR12,
VAR17,
VAR28,
VAR10,
VAR16,
VAR9,
VAR26,
VAR38,
VAR21,
VAR19,
VAR35
);
input VAR31; input VAR29; input VAR11; input [9:0] VAR32; input [9:0] VAR7; input [9:0] VAR8; input VAR24; input VAR12; input VAR17;
output [7:0] VAR28; output [1:0] VAR10; outpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvn/sky130_fd_sc_hd__einvn_4.v | 2,150 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR5,
VAR2,
VAR7,
VAR6 ,
VAR9
);
output VAR4 ;
input VAR8 ;
input VAR5;
input VAR2;
input VAR7;
input VAR6 ;
input VAR9 ;
VAR1 VAR3 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR4 ,
VAR8 ,
VAR5
);
output VAR4 ;... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_dataid_manager.v | 36,806 | module MODULE1
parameter
VAR90 = 8,
VAR38 = 1,
VAR101 = 1,
VAR12 = 6,
VAR87 = 1,
VAR54 = 4,
VAR7 = 7,
VAR21 = 5,
VAR53 = 2
)
(
VAR42,
VAR107,
VAR61,
VAR15,
VAR37,
VAR88,
VAR8,
VAR80,
VAR71,
VAR69,
VAR23,
VAR55,
VAR35,
VAR83,
VAR22,
VAR45,
VAR75,
VAR109,
VAR108,
VAR24,
VAR49,
VAR40,
VAR26,
VAR86,
VAR98,
VAR29,
VAR67,
VA... | lgpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/cnet_reprogram.v | 9,917 | module MODULE1(
input [VAR5-1:0] VAR25, input VAR39, input VAR38,
output VAR3,
output VAR35, output reg VAR23, output reg VAR12,
output reg VAR34, output reg VAR37,
output reg VAR29,
input VAR21,
output VAR45,
output VAR14,
output VAR42,
output reg [7:0] VAR33,
input VAR11,
input reset,
input clk
);
reg [4:0] VAR15, VA... | mit |
archlabo/Frix | common/to_sdram.v | 5,380 | module MODULE1
(
input wire VAR9,
input wire rst,
input wire VAR20,
input wire [31:0] VAR3,
input wire [3:0] VAR42,
input wire VAR7,
output wire [31:0] VAR14,
input wire VAR4,
input wire [31:0] VAR25,
output wire VAR11,
output wire VAR13,
input wire [2:0] VAR10,
input wire [31:0] VAR39,
input wire VAR28,
output wire [3... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2/sky130_fd_sc_hd__nand2.pp.symbol.v | 1,269 | module MODULE1 (
input VAR4 ,
input VAR7 ,
output VAR1 ,
input VAR5 ,
input VAR6,
input VAR2,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2/sky130_fd_sc_ms__mux2_4.v | 2,187 | module MODULE2 (
VAR3 ,
VAR5 ,
VAR4 ,
VAR9 ,
VAR7,
VAR8,
VAR6 ,
VAR1
);
output VAR3 ;
input VAR5 ;
input VAR4 ;
input VAR9 ;
input VAR7;
input VAR8;
input VAR6 ;
input VAR1 ;
VAR2 VAR10 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE2 (... | apache-2.0 |
aj-michael/Digital-Systems | Pong/Phase4/PongWithSound.v | 1,137 | module MODULE1(
input VAR18, VAR4, VAR14, VAR20, VAR5, VAR7, VAR6, VAR8,
output [2:0] VAR16,
output [2:0] VAR11,
output [1:0] VAR22,
output VAR24, VAR23,
output VAR21
);
wire [9:0] VAR12;
wire [9:0] VAR19;
parameter [9:0] VAR17=10'd640, VAR9=10'd480;
parameter [9:0] VAR2=10'd100, VAR15=10'd25;
VAR10 VAR1(VAR17, VAR9, V... | mit |
borti4938/sd2snes | verilog/sd2snes_obc1/obc_upper.v | 10,650 | module MODULE1 (
VAR32,
VAR65,
VAR53,
VAR17,
VAR3,
VAR29,
VAR54,
VAR50,
VAR24);
input [7:0] VAR32;
input [5:0] VAR65;
input VAR53;
input [1:0] VAR17;
input [7:0] VAR3;
input VAR29;
input VAR54;
output [1:0] VAR50;
output [7:0] VAR24;
tri1 VAR53;
tri0 VAR29;
tri0 VAR54;
wire [1:0] VAR23;
wire [7:0] VAR44;
wire [1:0] VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a41oi/sky130_fd_sc_ms__a41oi_1.v | 2,439 | module MODULE1 (
VAR12 ,
VAR6 ,
VAR2 ,
VAR11 ,
VAR1 ,
VAR7 ,
VAR9,
VAR3,
VAR10 ,
VAR4
);
output VAR12 ;
input VAR6 ;
input VAR2 ;
input VAR11 ;
input VAR1 ;
input VAR7 ;
input VAR9;
input VAR3;
input VAR10 ;
input VAR4 ;
VAR5 VAR8 (
.VAR12(VAR12),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9... | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Video_In/synthesis/submodules/altera_up_video_clipper_counters.v | 6,438 | module MODULE1 (
clk,
reset,
VAR5,
VAR7,
VAR8,
VAR15,
VAR12,
VAR2
);
parameter VAR6 = 640; parameter VAR17 = 480; parameter VAR4 = 9; parameter VAR16 = 8;
parameter VAR18 = 0;
parameter VAR13 = 0;
parameter VAR3 = 0;
parameter VAR10 = 0;
input clk;
input reset;
input VAR5;
output VAR7;
output VAR8;
output VAR15;
output... | gpl-3.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/acl_staging_reg.v | 1,972 | module MODULE1
(
clk, reset, VAR10, VAR2, VAR8, VAR5, VAR9, VAR1
);
parameter VAR7=32;
input clk;
input reset;
input [VAR7-1:0] VAR10;
input VAR2;
output VAR8;
output [VAR7-1:0] VAR5;
output VAR9;
input VAR1;
reg [VAR7-1:0] VAR4;
reg VAR3;
assign VAR8 = VAR3;
assign VAR5 = (VAR3) ? VAR4 : VAR10;
assign VAR9 = (VAR3) ? ... | mit |
sh-chris110/chris | FPGA/atlas_linux_ghrd/soc_system/synthesis/submodules/soc_system_hps_0.v | 30,511 | module MODULE1 #(
parameter VAR66 = 3,
parameter VAR149 = 2
) (
output wire VAR87, input wire VAR185, input wire VAR80, input wire VAR169, input wire [27:0] VAR19, input wire VAR69, input wire [7:0] VAR72, input wire [31:0] VAR98, input wire [3:0] VAR124, input wire [2:0] VAR103, input wire [1:0] VAR150, input wire [1:... | gpl-2.0 |
markusC64/1541ultimate2 | fpga/altera/megafunctions/update/synthesis/submodules/update_remote_update_0.v | 1,369 | module MODULE1 (
output wire VAR2, output wire [28:0] VAR4, input wire [2:0] VAR6, input wire VAR3, input wire VAR7, input wire VAR8, input wire [1:0] VAR10, input wire VAR11, input wire reset );
VAR9 VAR1 (
.VAR3 (VAR3), .VAR6 (VAR6), .VAR7 (VAR7), .VAR8 (VAR8), .VAR11 (VAR11), .reset (reset), .VAR2 (VAR2), .VAR4 (VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso0n/sky130_fd_sc_hdll__inputiso0n_1.v | 2,321 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR5,
VAR8 ,
VAR1 ,
VAR7 ,
VAR3
);
output VAR6 ;
input VAR4 ;
input VAR5;
input VAR8 ;
input VAR1 ;
input VAR7 ;
input VAR3 ;
VAR2 VAR9 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR6 ,
VAR4 ,
VAR5
);
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai.blackbox.v | 1,405 | module MODULE1 (
VAR5 ,
VAR1,
VAR2,
VAR8 ,
VAR4
);
output VAR5 ;
input VAR1;
input VAR2;
input VAR8 ;
input VAR4 ;
supply1 VAR3;
supply0 VAR9;
supply1 VAR6 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_fsb/bsg_fsb_node_async_buffer.v | 6,575 | module MODULE2
,parameter VAR6 = 2
)
(
input VAR11
, input VAR17
, output VAR38
, output VAR23
, output [VAR14-1:0] VAR29
, input VAR39
, input VAR32
, input [VAR14-1:0] VAR28
, output VAR8
, input VAR10
, input VAR27
, input VAR7
, input VAR41
, input [VAR14-1:0] VAR34
, output VAR22
, output VAR19
, output [VAR14-1:0... | bsd-3-clause |
Elphel/x353 | compressor/focus_sharp.v | 15,465 | module MODULE1(clk, en, VAR116, VAR6, VAR141, VAR103, VAR32, VAR84, VAR61, VAR59, VAR57, VAR73, VAR135, VAR17, VAR55, VAR94, do, VAR80, VAR139 );
input clk;
input en;
input VAR116;
input VAR6;
input [ 9:0] VAR141;
input [15:0] VAR103;
input [ 1:0] VAR32;
input VAR84; input VAR61; input [ 2:0] VAR59; input VAR57; input ... | gpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/modules/dbe_wishbone/wb_ethmac/eth_random.v | 5,718 | module MODULE1 (VAR4, VAR1, VAR10, VAR7, VAR2, VAR3, VAR14,
VAR9, VAR11);
parameter VAR12 = 1;
input VAR4;
input VAR1;
input VAR10;
input VAR7;
input [3:0] VAR2;
input [15:0] VAR3;
input [9:0] VAR14;
output VAR9;
output VAR11;
wire VAR13;
reg [9:0] VAR6;
wire [9:0] VAR5;
reg [9:0] VAR8;
always @ (posedge VAR4 or posedg... | lgpl-3.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_ln1px_s5.v | 1,313 | module MODULE1 (
enable, VAR9,
VAR6,
VAR2,
VAR7);
input enable, VAR9;
input VAR6;
input [31:0] VAR2;
output [31:0] VAR7;
wire [31:0] VAR3;
wire [31:0] VAR7 = VAR3[31:0];
VAR10 VAR4 ( .clk(VAR6),
.VAR5(1'b0),
.en(enable),
.VAR8(VAR2),
.VAR1(VAR3));
endmodule | mit |
1995parham/AlteraDE2-RS232 | src/async-reciever.v | 3,990 | module MODULE1(
input clk,
input VAR12,
output reg VAR10 = 0,
output reg [7:0] VAR21 = 0,
output VAR22, output reg VAR27 = 0 );
parameter VAR5 = 25000000; parameter VAR19 = 115200;
parameter VAR30 = 8;
generate
if(VAR5<VAR19*VAR30) VAR33 VAR2("VAR14 VAR6 VAR11 for VAR29 VAR19 VAR13 and VAR31");
if(VAR30<8 || ((VAR30 & ... | gpl-2.0 |
patrick-samy/ace | data/register-file/register-file.v | 1,502 | module MODULE1(input[1:0] VAR11,
input[1:0] VAR13,
input[1:0] VAR3,
input[31:0] VAR7,
input VAR2,
output[31:0] VAR19,
output[31:0] VAR1);
wire[31:0] VAR9;
wire[31:0] VAR8;
wire[31:0] VAR15;
wire[31:0] VAR5;
wire[3:0] VAR17;
wire[3:0] VAR21;
VAR4 VAR22(VAR3, VAR17);
and (VAR21[0], VAR2, VAR17[0]);
and (VAR21[1], VAR2, V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211a/sky130_fd_sc_ls__o211a.symbol.v | 1,367 | module MODULE1 (
input VAR8,
input VAR2,
input VAR4,
input VAR5,
output VAR1
);
supply1 VAR9;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/lpddr2_cntrlr/lpddr2_cntrlr/lpddr2_cntrlr_s0.v | 41,592 | module MODULE1 (
input wire VAR277, input wire VAR59, output wire [15:0] VAR258, output wire VAR222, input wire [31:0] VAR4, output wire VAR250, output wire [31:0] VAR90, input wire VAR243, output wire [0:0] VAR238, output wire [3:0] VAR154, output wire [3:0] VAR193, output wire [31:0] VAR56, output wire [3:0] VAR190, ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211o/sky130_fd_sc_ls__a211o.symbol.v | 1,367 | module MODULE1 (
input VAR4,
input VAR3,
input VAR5,
input VAR1,
output VAR2
);
supply1 VAR9;
supply0 VAR6;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
eda-globetrotter/PicenoDecoders | zhiyang_and_andrew/commschannel.v | 11,759 | module MODULE1();
wire VAR4; wire [1:0] VAR36; wire [1:0] VAR21; wire VAR28; wire [1:0] VAR17;
reg VAR8[0:255];
reg VAR19;
reg [7:0] VAR3;
reg VAR18;
reg VAR24;
reg [7:0] VAR20;
reg [1:0] VAR16;
reg [7:0] VAR29;
wire [1:0] VAR1;
wire [1:0] VAR25;
reg VAR10;
reg [7:0] VAR34;
reg [1:0] VAR6;
reg [1:0] VAR23;
reg VAR30;
r... | mit |
Franderg/CE-4301-Arqui1 | Processor/unsaved/synthesis/unsaved.v | 1,398 | module MODULE1 (
input wire VAR17, input wire [4:0] VAR9, input wire VAR2, input wire VAR11, input wire VAR1, input wire VAR7, output wire [31:0] VAR18, input wire [31:0] VAR20, input wire [3:0] VAR16, input wire VAR3, input wire VAR6 );
VAR14 VAR10 (
.clk (VAR17), .address (VAR9), .VAR15 (VAR2), .VAR21 (VAR11), .VAR4 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221ai/sky130_fd_sc_hdll__o221ai_2.v | 2,473 | module MODULE2 (
VAR8 ,
VAR4 ,
VAR2 ,
VAR12 ,
VAR6 ,
VAR9 ,
VAR10,
VAR7,
VAR3 ,
VAR11
);
output VAR8 ;
input VAR4 ;
input VAR2 ;
input VAR12 ;
input VAR6 ;
input VAR9 ;
input VAR10;
input VAR7;
input VAR3 ;
input VAR11 ;
VAR5 VAR1 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR10(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/inv/sky130_fd_sc_hvl__inv.behavioral.pp.v | 1,757 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR10,
VAR1,
VAR9 ,
VAR6
);
output VAR5 ;
input VAR4 ;
input VAR10;
input VAR1;
input VAR9 ;
input VAR6 ;
wire VAR11 ;
wire VAR12;
not VAR8 (VAR11 , VAR4 );
VAR3 VAR7 (VAR12, VAR11, VAR10, VAR1);
buf VAR2 (VAR5 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s4s/sky130_fd_sc_hd__dlymetal6s4s.behavioral.pp.v | 1,868 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR12,
VAR1,
VAR5 ,
VAR8
);
output VAR4 ;
input VAR3 ;
input VAR12;
input VAR1;
input VAR5 ;
input VAR8 ;
wire VAR6 ;
wire VAR10;
buf VAR7 (VAR6 , VAR3 );
VAR11 VAR2 (VAR10, VAR6, VAR12, VAR1);
buf VAR9 (VAR4 , VAR10 );
endmodule | apache-2.0 |
yht1995/Digital-WeighingScale | FPGA/Uart.v | 1,172 | module MODULE1(
output wire VAR13, output reg VAR5, input VAR6, input [7:0]VAR8, input VAR3, input VAR10 );
reg [3:0] VAR9;
reg [8:0] VAR1;
assign VAR13 = |VAR9[3:1];
assign VAR11 = |VAR9;
reg [28:0] VAR7;
wire [28:0] VAR4 = VAR7[28] ? (115200) : (115200 - 50000000);
wire [28:0] VAR2 = VAR7 + VAR4;
always @(posedge VAR... | gpl-3.0 |
golfit/QcmMasterController | counter_n.v | 7,820 | module MODULE1 (clk,VAR1,VAR2);
input clk,VAR1;
output reg [13:0] VAR2;
reg [13:0] VAR3; reg [13:0] VAR6; reg [6:0] VAR9; reg VAR5; reg reset;
parameter VAR8=40000;
parameter VAR7=50;
parameter VAR10=VAR4'b10; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xor3/sky130_fd_sc_hd__xor3_4.v | 2,199 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR8 ,
VAR10 ,
VAR3,
VAR2,
VAR6 ,
VAR9
);
output VAR4 ;
input VAR1 ;
input VAR8 ;
input VAR10 ;
input VAR3;
input VAR2;
input VAR6 ;
input VAR9 ;
VAR7 VAR5 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxtp/sky130_fd_sc_hs__sdfxtp.behavioral.pp.v | 2,258 | module MODULE1 (
VAR8,
VAR1,
VAR21 ,
VAR7 ,
VAR5 ,
VAR4 ,
VAR15
);
input VAR8;
input VAR1;
output VAR21 ;
input VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR15 ;
wire VAR23 ;
wire VAR14 ;
reg VAR9 ;
wire VAR17 ;
wire VAR13;
wire VAR3;
wire VAR19;
wire VAR6 ;
wire VAR11 ;
wire VAR20 ;
wire VAR2 ;
VAR10 VAR22 (VAR14, VAR17,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor2/sky130_fd_sc_ls__xnor2_1.v | 2,132 | module MODULE2 (
VAR5 ,
VAR1 ,
VAR7 ,
VAR4,
VAR8,
VAR3 ,
VAR6
);
output VAR5 ;
input VAR1 ;
input VAR7 ;
input VAR4;
input VAR8;
input VAR3 ;
input VAR6 ;
VAR9 VAR2 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR5,
VAR1,
VAR7
);
output VAR5;
... | apache-2.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/triple_speed_ethernet-library/altera_tse_gxb_aligned_rxsync.v | 11,745 | module MODULE1 (
input clk,
input reset,
input [7:0] VAR8,
input VAR29,
input VAR23,
input VAR33,
input VAR4,
input VAR9,
input VAR30,
input VAR26,
input VAR27,
input VAR32,
output reg [7:0] VAR2,
output VAR12,
output reg VAR5,
output reg VAR3,
output reg VAR34,
output reg VAR10,
output reg VAR16,
output reg VAR19) ;
p... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor2/sky130_fd_sc_hs__xnor2.functional.v | 1,716 | module MODULE1 (
VAR1,
VAR7,
VAR4 ,
VAR2 ,
VAR8
);
input VAR1;
input VAR7;
output VAR4 ;
input VAR2 ;
input VAR8 ;
wire VAR3 ;
wire VAR9;
xnor VAR6 (VAR3 , VAR2, VAR8 );
VAR5 VAR11 (VAR9, VAR3, VAR1, VAR7);
buf VAR10 (VAR4 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3/sky130_fd_sc_ls__nand3.symbol.v | 1,280 | module MODULE1 (
input VAR4,
input VAR6,
input VAR7,
output VAR3
);
supply1 VAR2;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
LSaldyt/qnp | output/vs/opt_var15_multi.v | 19,671 | module MODULE1(VAR14, VAR4, VAR6, VAR8, VAR5, VAR9, VAR1, VAR3, VAR11, VAR2, VAR10, VAR16, VAR7, VAR12, VAR13, valid);
wire 000;
wire 001;
wire 002;
wire 003;
wire 004;
wire 005;
wire 006;
wire 007;
wire 008;
wire 009;
wire 010;
wire 011;
wire 012;
wire 013;
wire 014;
wire 015;
wire 016;
wire 017;
wire 018;
wire 019;
w... | mit |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkNear_Mem.v | 50,919 | module MODULE1(VAR311,
VAR59,
VAR26,
VAR156,
VAR101,
VAR90,
VAR153,
VAR375,
VAR269,
VAR125,
VAR12,
VAR6,
VAR367,
VAR120,
VAR310,
VAR245,
VAR278,
VAR335,
VAR136,
VAR113,
VAR117,
VAR328,
VAR33,
VAR192,
VAR417,
VAR172,
VAR61,
VAR358,
VAR362,
VAR410,
VAR326,
VAR189,
VAR376,
VAR183,
VAR100,
VAR169,
VAR41,
VAR255,
VAR368,
VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfbbn/sky130_fd_sc_ms__dfbbn.behavioral.pp.v | 2,820 | module MODULE1 (
VAR13 ,
VAR2 ,
VAR8 ,
VAR26 ,
VAR5 ,
VAR14,
VAR10 ,
VAR6 ,
VAR7 ,
VAR22
);
output VAR13 ;
output VAR2 ;
input VAR8 ;
input VAR26 ;
input VAR5 ;
input VAR14;
input VAR10 ;
input VAR6 ;
input VAR7 ;
input VAR22 ;
wire VAR29 ;
wire VAR27 ;
wire VAR21 ;
wire VAR25 ;
wire VAR19 ;
wire VAR30;
wire VAR1 ;
reg... | apache-2.0 |
elegabriel/myzju | junior1/CA/mips_pipeline2/code/top.v | 8,403 | module MODULE1(VAR52, VAR92, VAR73, VAR141, VAR122, VAR119,VAR19,
VAR76, VAR44, VAR137, VAR95
);
input wire VAR52;
input wire [3:0] VAR92;
input wire VAR73,VAR141,VAR119,VAR122;
output wire VAR76, VAR44, VAR137;
output wire [3:0] VAR95;
output wire [7:0] VAR19;
wire VAR59;
wire rst;
reg VAR64,VAR42;
wire VAR47,VAR100;
... | gpl-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/altera_avalon_dc_fifo.v | 25,360 | module MODULE1(
VAR41,
VAR91,
VAR42,
VAR53,
VAR2,
VAR57,
VAR45,
VAR73,
VAR65,
VAR71,
VAR10,
VAR22,
VAR12,
VAR26,
VAR104,
VAR44,
VAR105,
VAR62,
VAR31,
VAR56,
VAR109,
VAR38,
VAR100,
VAR54,
VAR47,
VAR40,
VAR24,
VAR72,
VAR88,
VAR14,
VAR63,
VAR8,
VAR5,
VAR69,
VAR110
);
parameter VAR94 = 1;
parameter VAR86 = 8;
parameter VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_12.behavioral.v | 1,106 | module MODULE1( VAR5, VAR1 );
input VAR5;
output VAR1;
VAR4 VAR2(.VAR5(VAR5),.VAR1(VAR1));
VAR4 VAR3(.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
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