repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3/sky130_fd_sc_ms__nand3_4.v | 2,175 | module MODULE2 (
VAR5 ,
VAR8 ,
VAR7 ,
VAR2 ,
VAR6,
VAR9,
VAR10 ,
VAR1
);
output VAR5 ;
input VAR8 ;
input VAR7 ;
input VAR2 ;
input VAR6;
input VAR9;
input VAR10 ;
input VAR1 ;
VAR4 VAR3 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4b/sky130_fd_sc_hdll__nor4b.pp.blackbox.v | 1,349 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR7 ,
VAR2 ,
VAR5 ,
VAR3,
VAR9,
VAR1 ,
VAR6
);
output VAR4 ;
input VAR8 ;
input VAR7 ;
input VAR2 ;
input VAR5 ;
input VAR3;
input VAR9;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/master_0/altera_jtag_dc_streaming/altera_jtag_streaming.v | 23,657 | module MODULE1 (
output VAR41,
input VAR88,
output [7:0] VAR75,
output VAR82,
input [7:0] VAR50,
input VAR14,
output VAR115,
input VAR6,
input VAR37,
output reg VAR61 = 1'b0
);
function integer VAR71;
input [31:0] VAR5;
integer VAR43;
begin
VAR43 = VAR5;
if ( VAR43 <= 0 ) VAR71 = 0;
end
else begin
for(VAR71 = -1; VAR43... | mit |
pwwu/FPGA | VGAbased/vga_game_graph.v | 13,405 | module MODULE1
(
input wire clk, reset,
input wire VAR37,
input wire [1:0] VAR65,
input wire [1:0] VAR11,
input wire VAR29,
input wire [9:0] VAR23, VAR52,
output reg VAR49, VAR26, VAR7,
output wire VAR10,
output reg [2:0] VAR51
);
localparam VAR44 = 640;
localparam VAR67 = 480;
wire VAR34;
localparam VAR6 = 20;
localpa... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi.pp.blackbox.v | 1,482 | module MODULE1 (
VAR5 ,
VAR2,
VAR6,
VAR4 ,
VAR8 ,
VAR1,
VAR7,
VAR3 ,
VAR9
);
output VAR5 ;
input VAR2;
input VAR6;
input VAR4 ;
input VAR8 ;
input VAR1;
input VAR7;
input VAR3 ;
input VAR9 ;
endmodule | apache-2.0 |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/bee3Top/src/c3dClkGen2.v | 5,924 | module MODULE1 (
input VAR2,
output VAR10,
output VAR53,
output VAR59,
output VAR27,
output VAR52
);
VAR61 #(.VAR32("VAR18"), .VAR46(2), .VAR19(0.0), .VAR55(3.2),
.VAR47(4), .VAR50(0.5), .VAR60(0.0),
.VAR5(2), .VAR13(0.5), .VAR63(0.0),
.VAR12(16), .VAR62(0.375), .VAR21(0.0),
.VAR11(4), .VAR8(0.5), .VAR33(180.0),
.VAR15... | gpl-3.0 |
ychaim/FPGA-Litecoin-Miner | source/altera_ram.v | 7,266 | module MODULE1 # ( parameter VAR42=10 ) (
address,
VAR4,
VAR38,
VAR11,
VAR53);
input [VAR42-1:0] address;
input VAR4;
input [255:0] VAR38;
input VAR11;
output [255:0] VAR53;
tri1 VAR4;
wire [255:0] VAR45;
wire [255:0] VAR53 = VAR45[255:0];
VAR15 VAR20 (
.VAR28 (address),
.VAR26 (VAR4),
.VAR7 (VAR38),
.VAR10 (VAR11),
.V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor2/sky130_fd_sc_ms__xnor2.pp.blackbox.v | 1,301 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR1 ,
VAR6,
VAR4,
VAR5 ,
VAR3
);
output VAR2 ;
input VAR7 ;
input VAR1 ;
input VAR6;
input VAR4;
input VAR5 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2b/sky130_fd_sc_hd__nor2b.symbol.v | 1,326 | module MODULE1 (
input VAR2 ,
input VAR1,
output VAR3
);
supply1 VAR4;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_of_pre_fifo.v | 8,024 | module MODULE1 #
(
parameter VAR20 = 100, parameter VAR12 = 4, parameter VAR16 = 32 )
(
input clk, input rst, input VAR18, input VAR8, input [VAR16-1:0] din, output VAR22, output [VAR16-1:0] dout, output VAR6 );
localparam VAR15
= (VAR12 == 2) ? 1 :
((VAR12 == 3) || (VAR12 == 4)) ? 2 :
(((VAR12 == 5) || (VAR12 == 6) ||... | bsd-2-clause |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/1_unroll_kernel_traversal/syn/verilog/convolve_kernel.v | 67,957 | module MODULE1 (
VAR241,
VAR143,
VAR442,
VAR207,
VAR189,
VAR175,
VAR88,
VAR36,
VAR384,
VAR490,
VAR254,
VAR136,
VAR351,
VAR42,
VAR115,
VAR89,
VAR79,
VAR157,
VAR74,
VAR406,
VAR299,
VAR165,
VAR96,
VAR285,
VAR83,
VAR271,
VAR473
);
parameter VAR318 = 137'd1;
parameter VAR201 = 137'd2;
parameter VAR482 = 137'd4;
parameter VA... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_047.v | 1,538 | module MODULE2 (
VAR6,
VAR7
);
input [31:0] VAR6;
output [31:0]
VAR7;
wire [31:0]
VAR4,
VAR3,
VAR14,
VAR11,
VAR13,
VAR9,
VAR12,
VAR1,
VAR8;
assign VAR4 = VAR6;
assign VAR3 = VAR4 << 7;
assign VAR14 = VAR4 + VAR3;
assign VAR11 = VAR4 << 14;
assign VAR13 = VAR14 + VAR11;
assign VAR12 = VAR13 + VAR9;
assign VAR8 = VAR12 +... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfbbn/sky130_fd_sc_hd__dfbbn.blackbox.v | 1,451 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR7 ,
VAR10 ,
VAR9 ,
VAR2
);
output VAR8 ;
output VAR3 ;
input VAR7 ;
input VAR10 ;
input VAR9 ;
input VAR2;
supply1 VAR1;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0p/sky130_fd_sc_lp__iso0p.behavioral.v | 1,360 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR7
);
output VAR1 ;
input VAR9 ;
input VAR7;
supply1 VAR3;
supply0 VAR4 ;
supply1 VAR6 ;
supply0 VAR5 ;
wire VAR8;
not VAR2 (VAR8, VAR7 );
and VAR10 (VAR1 , VAR9, VAR8 );
endmodule | apache-2.0 |
CospanDesign/sdio-device | rtl/sdio_device_stack.v | 25,637 | module MODULE1 (
input VAR147,
input VAR28,
input rst,
output VAR45,
output [7:0] VAR195, input [7:0] VAR227, output [2:0] VAR268,
input [7:0] VAR200,
input [7:0] VAR95,
output VAR89,
output [3:0] VAR275,
output [15:0] VAR153,
output VAR246,
output [3:0] VAR126,
output [15:0] VAR60,
output VAR107,
output [3:0] VAR291,
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decap/sky130_fd_sc_ls__decap.behavioral.v | 1,135 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
Obijuan/FPGA-peripherals | servos/osc/genrom.v | 1,538 | module MODULE1 #( parameter VAR4 = 6, parameter VAR8 = 8)
( input clk, input wire [VAR4-1: 0] addr, output reg [VAR8-1: 0] VAR3);
parameter VAR6 = "VAR1.VAR5";
localparam VAR2 = 2 ** VAR4;
reg [VAR8-1: 0] VAR7 [0: VAR2-1];
always @(posedge clk) begin
VAR3 <= VAR7[addr];
end | gpl-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_phy_wrcal.v | 54,326 | module MODULE1 #
(
parameter VAR210 = 100, parameter VAR189 = 2, parameter VAR156 = 2500,
parameter VAR13 = 64, parameter VAR158 = 3, parameter VAR58 = 8, parameter VAR9 = 8, parameter VAR130 = "VAR214", parameter VAR115 = "VAR192" )
(
input clk,
input rst,
input VAR237,
input VAR40,
input VAR60,
input VAR193,
input VA... | bsd-2-clause |
fallen/milkymist-mmu | cores/fmlarb/rtl/fmlarb.v | 5,824 | module MODULE1 #(
parameter VAR62 = 26
) (
input VAR56,
input VAR68,
input [VAR62-1:0] VAR41,
input VAR29,
input VAR34,
output VAR42,
input [7:0] VAR6,
input [63:0] VAR49,
output [63:0] VAR38,
input [VAR62-1:0] VAR27,
input VAR20,
input VAR43,
output VAR3,
input [7:0] VAR65,
input [63:0] VAR33,
output [63:0] VAR37,
inp... | lgpl-3.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_spram_1024x32_bw.v | 12,727 | module MODULE1(
VAR66, VAR73, VAR43,
clk, rst, VAR49, VAR72, VAR20, addr, VAR17, VAR8
);
input VAR66;
input [VAR29 - 1:0] VAR43; output VAR73;
input clk; input rst; input VAR49; input [3:0] VAR72; input VAR20; input [9:0] addr; input [31:0] VAR17; output [31:0] VAR8;
assign VAR73 = VAR66;
VAR13 VAR30(
VAR42 VAR30(
VAR1... | gpl-2.0 |
Kipsora/MIPS-CPU | source/machine/memory/ram.v | 1,900 | module MODULE1(
input wire VAR9,
input wire VAR15,
input wire VAR7,
input wire[VAR11] addr,
input wire[VAR20] VAR6,
input wire[VAR8] VAR13,
output reg[VAR8] VAR3
);
reg[VAR17] VAR18[0 : VAR4 - 1];
reg[VAR17] VAR5[0 : VAR4 - 1];
reg[VAR17] VAR19[0 : VAR4 - 1];
reg[VAR17] VAR14[0 : VAR4 - 1];
always @ (posedge VAR9) begi... | mit |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/gpio/gpio.v | 5,576 | module MODULE1 (
input wire clk,
input wire reset,
input wire VAR23,
input wire VAR12,
input wire VAR21,
input wire [VAR29] addr,
input wire [VAR2] VAR3,
output reg [VAR2] VAR27,
output reg VAR26
, input wire [VAR8-1:0] VAR20
, output reg [VAR22-1:0] VAR28
, inout wire [VAR11-1:0] VAR4
);
wire [VAR11-1:0] VAR1;
reg [VA... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/rd_bitslip.v | 5,424 | module MODULE1 #
(
parameter VAR2 = 100
)
(
input clk,
input [1:0] VAR8,
input [1:0] VAR9,
input [5:0] din,
output reg [3:0] VAR3
);
reg VAR6;
reg [3:0] VAR1;
reg [3:0] VAR7;
reg [3:0] VAR5;
reg [3:0] VAR4;
always @(posedge clk)
always @(VAR8 or din or VAR6)
case (VAR8)
2'b00: VAR1 = {din[3], din[2], din[1], din[0]};
2... | mit |
CospanDesign/sdio-device | rtl/phy/sdio_data_phy.v | 13,960 | module MODULE1 (
input clk,
input rst,
input VAR19,
input VAR8,
input VAR20,
input VAR35,
input VAR6,
input VAR51,
input VAR57,
output reg VAR56,
input VAR18,
input [12:0] VAR53,
output reg VAR41,
output [7:0] VAR25,
input VAR58,
input [7:0] VAR59,
output reg VAR22, input VAR2,
output reg VAR36,
output reg VAR50,
input... | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_gcd_0_1/gcd_block_design_gcd_0_1_stub.v | 2,706 | module MODULE1(VAR12,
VAR6, VAR10, VAR19, VAR9,
VAR13, VAR3, VAR1, VAR5,
VAR17, VAR8, VAR18,
VAR15, VAR16, VAR11, VAR4,
VAR2, VAR7, VAR14, interrupt)
;
input [5:0]VAR12;
input VAR6;
output VAR10;
input [31:0]VAR19;
input [3:0]VAR9;
input VAR13;
output VAR3;
output [1:0]VAR1;
output VAR5;
input VAR17;
input [5:0]VAR8;
i... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2.functional.v | 1,177 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
olgirard/opengfx430 | core/bench/verilog/ram.v | 3,097 | module MODULE1 (
VAR10,
VAR6, VAR5, VAR3, VAR9, VAR4 );
parameter VAR8 = 6; parameter VAR1 = 256;
output [15:0] VAR10;
input [VAR8:0] VAR6; input VAR5; input VAR3; input [15:0] VAR9; input [1:0] VAR4;
reg [15:0] VAR7 [0:(VAR1/2)-1];
reg [VAR8:0] VAR11;
wire [15:0] VAR2 = VAR7[VAR6];
always @(posedge VAR3)
if (~VAR5 & V... | bsd-3-clause |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_02/02 verilog/PorPruebas/ModulosBasicos/PruebasFPGA/contadorprueba/conmutacion.v | 1,097 | module MODULE1 (
input [3:0] VAR1,
input [3:0] VAR7,
input [3:0] VAR3,
input VAR9,
input VAR11,
input VAR10,
input VAR5,
output reg [1:0] VAR6,
output reg [3:0] VAR2
);
reg VAR4;
reg [1:0] VAR8;
begin
begin
begin
end
begin
begin
end
begin
begin
end
begin
begin
begin
begin
begin
begin | gpl-3.0 |
jmahler/mips-cpu | regm.v | 2,004 | module MODULE1(
input wire clk,
input wire [4:0] VAR4, VAR5,
output wire [31:0] VAR3, VAR1,
input wire VAR7,
input wire [4:0] VAR8,
input wire [31:0] VAR6);
reg [31:0] VAR2 [0:31];
reg [31:0] VAR3, VAR1; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32ai/sky130_fd_sc_ls__o32ai.behavioral.pp.v | 2,191 | module MODULE1 (
VAR15 ,
VAR2 ,
VAR8 ,
VAR11 ,
VAR19 ,
VAR16 ,
VAR6,
VAR13,
VAR5 ,
VAR14
);
output VAR15 ;
input VAR2 ;
input VAR8 ;
input VAR11 ;
input VAR19 ;
input VAR16 ;
input VAR6;
input VAR13;
input VAR5 ;
input VAR14 ;
wire VAR12 ;
wire VAR4 ;
wire VAR1 ;
wire VAR20;
nor VAR10 (VAR12 , VAR11, VAR2, VAR8 );
nor ... | apache-2.0 |
Kumikomi/openreroc_posturesensor | hardware/src/MPU_gyro_controller.v | 12,842 | module MODULE1(
input clk,
input reset,
output reg [15:0] VAR29, output reg [15:0] VAR35, output reg [15:0] VAR27, output VAR20, output VAR23, output VAR34, input VAR7, output reg VAR42
);
parameter VAR16 = 18,
VAR36 = 19,
VAR30 = 20,
VAR21 = 21,
VAR41 = 22,
VAR3 = 23,
VAR14 = 24,
VAR46 = 25,
VAR49 = 26,
VAR9 = 27,
VAR... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22o/sky130_fd_sc_ls__a22o.behavioral.pp.v | 2,151 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR12 ,
VAR14 ,
VAR16 ,
VAR7,
VAR4,
VAR2 ,
VAR5
);
output VAR6 ;
input VAR9 ;
input VAR12 ;
input VAR14 ;
input VAR16 ;
input VAR7;
input VAR4;
input VAR2 ;
input VAR5 ;
wire VAR8 ;
wire VAR19 ;
wire VAR13 ;
wire VAR18;
and VAR11 (VAR8 , VAR14, VAR16 );
and VAR1 (VAR19 , VAR9, VAR12 );
or... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd3/sky130_fd_sc_ms__clkdlyinv5sd3.behavioral.v | 1,440 | module MODULE1 (
VAR6,
VAR1
);
output VAR6;
input VAR1;
supply1 VAR7;
supply0 VAR2;
supply1 VAR9 ;
supply0 VAR4 ;
wire VAR8;
not VAR3 (VAR8, VAR1 );
buf VAR5 (VAR6 , VAR8 );
endmodule | apache-2.0 |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CoreAPB3/4.0.100/rtl/vlog/amba_bfm/bfm_ahbtoapb.v | 3,820 | module
MODULE1
(
VAR21
,
VAR1
,
VAR31
,
VAR6
,
VAR18
,
VAR11
,
VAR19
,
VAR37
,
VAR28
,
VAR7
,
VAR23
,
VAR12
,
VAR34
,
VAR40
,
VAR33
,
VAR29
,
VAR4
,
VAR20
,
VAR30
,
VAR2
,
VAR25
,
VAR16
,
VAR3
)
;
parameter
VAR13
=
1
;
input
VAR21
;
input
VAR1
;
input
VAR31
;
input
VAR6
;
input
[
31
:
0
]
VAR18
;
input
[
31
:
0
]
VAR11... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkbuf/sky130_fd_sc_hdll__clkbuf_6.v | 2,050 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR3,
VAR7,
VAR2 ,
VAR1
);
output VAR4 ;
input VAR6 ;
input VAR3;
input VAR7;
input VAR2 ;
input VAR1 ;
VAR8 VAR5 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR4,
VAR6
);
output VAR4;
input VAR6;
supply1 VAR3;
supply0 VAR7;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fa/sky130_fd_sc_ms__fa_1.v | 2,278 | module MODULE1 (
VAR9,
VAR10 ,
VAR4 ,
VAR11 ,
VAR8 ,
VAR2,
VAR6,
VAR5 ,
VAR3
);
output VAR9;
output VAR10 ;
input VAR4 ;
input VAR11 ;
input VAR8 ;
input VAR2;
input VAR6;
input VAR5 ;
input VAR3 ;
VAR7 VAR1 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5),
.V... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_gmultp2_32x32.v | 5,153 | module MODULE1 ( VAR3, VAR7, VAR4, VAR8, VAR6 );
input [VAR11-1:0] VAR3;
input [VAR11-1:0] VAR7;
input VAR4;
input VAR8;
output [VAR9-1:0] VAR6;
reg [VAR9-1:0] VAR2;
reg [VAR9-1:0] VAR1;
integer VAR5;
integer VAR10;
always @(VAR3)
VAR5 <= VAR3;
always @(VAR7)
VAR10 <= VAR7;
always @(posedge VAR4 or posedge VAR8)
if (VA... | apache-2.0 |
GSejas/Karatsuba_FPU | Resultados/CORDIC/CORDIC_Arch3_Vivado/CORDIC_Arch3_Vivado.srcs/sources_1/imports/Floating-Point-Unit-master/Coprocesador_CORDIC_RTL/sine_cosine_CORDIC/CORDIC_FSM_v2.v | 8,519 | module MODULE1
(
input wire clk, input wire reset, input wire VAR3, input wire VAR26, input wire VAR24, input wire VAR9,
input wire [1:0] VAR8, input wire [1:0] VAR31, input wire VAR40, input wire VAR20, VAR32, input wire VAR33, VAR47,
output reg VAR37,
output reg VAR38, output reg VAR29, output reg VAR35, output reg V... | gpl-3.0 |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/memAttack/lib/micron/ddr/ddr2.v | 130,488 | module MODULE1 (
VAR73,
VAR164,
VAR116,
VAR142,
VAR7,
VAR107,
VAR137,
VAR40,
VAR125,
addr,
VAR130,
VAR132,
VAR55,
VAR34,
VAR99
);
parameter VAR71 = 2500; parameter VAR14 = 100; parameter VAR44 = 100; parameter VAR42 = 200; parameter VAR151 = 150; parameter VAR97 = 175; parameter VAR59 = 200; parameter VAR52 = 200; para... | mit |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/tc_router_wrap.v | 16,029 | module MODULE1
(clk, reset, VAR42, VAR99, VAR90, VAR23, VAR72,
VAR93, VAR84, VAR61);
localparam VAR144 = VAR122 * VAR76;
localparam VAR97 = VAR144 * VAR69;
localparam VAR57 = VAR110(VAR97);
localparam VAR41
= (VAR100 + VAR27 - 1) / VAR27;
localparam VAR68 = VAR50(VAR41, VAR35);
localparam VAR107 = VAR110(VAR68);
localp... | mit |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/MIPS32/IDEX_Stage.v | 9,120 | module MODULE1(
input VAR39,
input reset,
input VAR96,
input VAR72,
input VAR1,
input VAR45,
input VAR59,
input VAR76,
input [4:0] VAR100,
input VAR77,
input VAR9,
input VAR18,
input VAR95,
input VAR40,
input VAR35,
input VAR10,
input VAR32,
input VAR73,
input VAR29,
input VAR11,
input VAR46,
input VAR63,
input [4:0] V... | lgpl-3.0 |
cafe-alpha/wascafe | v12/fpga_firmware/wasca/synthesis/submodules/wasca_mm_interconnect_0_avalon_st_adapter_001.v | 6,161 | module MODULE1 #(
parameter VAR5 = 34,
parameter VAR22 = 0,
parameter VAR14 = 34,
parameter VAR16 = 0,
parameter VAR25 = 0,
parameter VAR20 = 0,
parameter VAR13 = 1,
parameter VAR3 = 1,
parameter VAR21 = 0,
parameter VAR23 = 34,
parameter VAR10 = 0,
parameter VAR1 = 1,
parameter VAR9 = 0,
parameter VAR2 = 1,
parameter ... | gpl-2.0 |
iafnan/es2-hardwaresecurity | or1200/bench/verilog/xess_top.v | 10,094 | module MODULE1 (
);
VAR46 VAR30();
VAR10 VAR10();
VAR60 VAR60();
reg VAR20;
reg VAR33;
wire VAR38;
wire clk;
wire [31:0] VAR31;
wire [31:0] VAR27;
wire VAR76;
wire VAR59;
wire VAR52;
wire VAR45;
wire VAR1;
wire VAR5;
wire [7:0] VAR73;
wire [20:0] VAR56;
wire [31:0] VAR68; wire [31:0] VAR36; wire [1:0] VAR40; wire VAR77... | gpl-3.0 |
samyk/proxmark3 | fpga/fpga_lf.v | 8,629 | module MODULE1(
input VAR17, output VAR62, input VAR56, input VAR64,
input VAR93, input VAR91, input VAR74,
output VAR90, output VAR89,
output VAR28, output VAR26, output VAR23, output VAR61,
input [7:0] VAR1, output VAR40, output VAR55,
output VAR45, output VAR20, input VAR78, output VAR63,
input VAR32, input VAR92,
o... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_gmii_to_rgmii/mdc_mdio.v | 4,037 | module MODULE1 (
VAR10,
VAR7,
VAR5,
VAR8,
VAR13);
parameter VAR11 = 5'b10000;
input VAR10;
input VAR7;
input VAR5;
output [ 1:0] VAR8;
output VAR13;
localparam VAR12 = 2'b01;
localparam VAR6 = 2'b10;
wire VAR3;
reg [ 1:0] VAR4 = VAR12;
reg [ 1:0] VAR14 = VAR12;
reg [31:0] VAR1 = 32'h0;
reg [31:0] VAR9 = 32'h0;
reg [ 5:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtn/sky130_fd_sc_hdll__dlrtn.pp.symbol.v | 1,428 | module MODULE1 (
input VAR3 ,
output VAR6 ,
input VAR2,
input VAR4 ,
input VAR8 ,
input VAR5 ,
input VAR1 ,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtp/sky130_fd_sc_hs__dlrtp.behavioral.pp.v | 2,235 | module MODULE1 (
VAR14 ,
VAR7 ,
VAR13 ,
VAR5,
VAR8 ,
VAR19
);
input VAR14 ;
input VAR7 ;
output VAR13 ;
input VAR5;
input VAR8 ;
input VAR19 ;
wire VAR16 ;
reg VAR15 ;
wire VAR18 ;
wire VAR4 ;
wire VAR3 ;
wire VAR6;
wire VAR1 ;
wire VAR12 ;
wire VAR11 ;
wire VAR9 ;
not VAR17 (VAR16 , VAR6 );
VAR2 VAR10 (VAR1 , VAR18, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/diode/sky130_fd_sc_hs__diode.behavioral.v | 1,177 | module MODULE1 (
VAR5
);
input VAR5;
supply1 VAR4;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
tanelikaivola/blinkenlichten | fpga/sr_timer.v | 1,412 | module MODULE1 #(VAR1 = 8)
(
input VAR2,
input VAR8,
input VAR7,
output reg VAR6 = 0
);
reg [VAR3(VAR1)-1:0] VAR5 = 0;
reg VAR9 = 0;
always @(posedge VAR7) begin
if(VAR8) begin
VAR6 <= 0;
VAR5 <= 0;
VAR9 <= 0;
end else if(VAR2 & !VAR9) begin
VAR6 <= 1;
VAR9 <= 1;
end else if(VAR9) begin
VAR5 <= VAR5 + 1;
if(VAR5+1 == V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o32ai/sky130_fd_sc_hdll__o32ai.pp.blackbox.v | 1,433 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR4 ,
VAR8 ,
VAR9 ,
VAR10 ,
VAR6,
VAR1,
VAR2 ,
VAR7
);
output VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR8 ;
input VAR9 ;
input VAR10 ;
input VAR6;
input VAR1;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s.functional.v | 1,342 | module MODULE1 (
VAR3,
VAR1
);
output VAR3;
input VAR1;
wire VAR2;
buf VAR4 (VAR2, VAR1 );
buf VAR5 (VAR3 , VAR2 );
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_41.v | 27,415 | module MODULE1 (
clk,
reset,
VAR87,
VAR154,
VAR215,
VAR104,
VAR3
);
parameter VAR74 = 18;
parameter VAR22 = 41;
parameter VAR28 = 21;
localparam VAR174 = 42;
input clk;
input reset;
input VAR87;
input VAR154;
input [VAR74-1:0] VAR215; output VAR104;
output [VAR74-1:0] VAR3;
localparam VAR138 = 18; localparam VAR110 = 3... | mit |
ultraembedded/altor32 | rtl/cpu/altor32_lfu.v | 4,597 | module MODULE1
(
input [7:0] VAR1 ,
input [31:0] VAR5 ,
input [1:0] VAR4 ,
output reg [31:0] VAR2 ,
output reg VAR3
);
always @ *
begin
VAR2 = 32'h00000000;
VAR3 = 1'b0;
case (VAR1)
case (VAR4)
2'b00 : VAR2[7:0] = VAR5[31:24];
2'b01 : VAR2[7:0] = VAR5[23:16];
2'b10 : VAR2[7:0] = VAR5[15:8];
2'b11 : VAR2[7:0] = VAR5[7:0... | lgpl-3.0 |
trun/fpgaboy | src/io/debug/cls_spi.v | 9,247 | module MODULE1(
input wire VAR16,
input wire reset,
input wire [15:0] VAR32,
input wire [7:0] VAR51,
input wire [7:0] VAR2,
input wire [15:0] VAR48,
input wire [15:0] VAR20,
input wire [15:0] VAR57,
input wire [15:0] VAR33,
input wire [15:0] VAR21,
input wire [15:0] VAR46,
input wire [15:0] VAR35,
input wire [1:0] VAR5... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xor3/sky130_fd_sc_ms__xor3_1.v | 2,199 | module MODULE2 (
VAR3 ,
VAR4 ,
VAR2 ,
VAR6 ,
VAR7,
VAR8,
VAR10 ,
VAR1
);
output VAR3 ;
input VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR7;
input VAR8;
input VAR10 ;
input VAR1 ;
VAR5 VAR9 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v | 1,158 | module MODULE1
VAR4 = 32,
VAR3 = 32,
VAR2 = 32,
VAR5 = 16, VAR7 = 32,
VAR9 = 8,
VAR10 = 1,
VAR8 = 8,
VAR1 = 1,
VAR6 = 1
) (
);
endmodule | gpl-3.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/acl_fp_convert_to_internal.v | 3,383 | module MODULE1(VAR15, VAR1, VAR19, VAR21, VAR20, VAR22, VAR14, VAR13, VAR17, VAR18, enable);
parameter VAR4 = 1;
parameter VAR10 = 1;
parameter VAR16 = 0;
parameter VAR6 = 1;
input VAR15, VAR1;
input [31:0] VAR19;
output [26:0] VAR21;
output [8:0] VAR20;
output VAR22;
input enable, VAR14, VAR17;
output VAR13, VAR18;
re... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai.behavioral.v | 1,674 | module MODULE1 (
VAR3 ,
VAR12,
VAR10,
VAR11 ,
VAR8
);
output VAR3 ;
input VAR12;
input VAR10;
input VAR11 ;
input VAR8 ;
supply1 VAR6;
supply0 VAR15;
supply1 VAR2 ;
supply0 VAR5 ;
wire VAR9 ;
wire VAR16 ;
wire VAR7;
nand VAR1 (VAR9 , VAR10, VAR12 );
or VAR14 (VAR16 , VAR8, VAR11 );
nand VAR4 (VAR7, VAR9, VAR16);
buf VA... | apache-2.0 |
prernaa/CPUVerilog | id_ex.v | 4,056 | module MODULE1(
clk, VAR12, VAR53, VAR7,
VAR62, VAR47, VAR64,
VAR51, VAR4, VAR14, VAR26, VAR43, VAR1,
VAR38, VAR11, VAR55, VAR24,VAR18, VAR5, VAR22, VAR16,
VAR52, VAR23, VAR40, VAR41, VAR8,
VAR48, VAR20, VAR21, VAR6,
VAR65, VAR54 , VAR17, VAR59, VAR31,
VAR3, VAR67,
VAR56, VAR39,
VAR29,VAR37,
VAR34, VAR19,
VAR32, VAR46,... | mit |
alexforencich/verilog-axis | rtl/axis_cobs_decode.v | 11,865 | module MODULE1
(
input wire clk,
input wire rst,
input wire [7:0] VAR6,
input wire VAR34,
output wire VAR7,
input wire VAR17,
input wire VAR33,
output wire [7:0] VAR27,
output wire VAR39,
input wire VAR16,
output wire VAR20,
output wire VAR13
);
localparam [1:0]
VAR14 = 2'd0,
VAR2 = 2'd1,
VAR35 = 2'd2;
reg [1:0] VAR31 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso0n/sky130_fd_sc_hd__lpflow_inputiso0n.behavioral.pp.v | 1,803 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR1,
VAR4 ,
VAR9 ,
VAR11 ,
VAR3
);
output VAR2 ;
input VAR8 ;
input VAR1;
input VAR4 ;
input VAR9 ;
input VAR11 ;
input VAR3 ;
wire VAR7;
and VAR10 (VAR7, VAR8, VAR1 );
VAR5 VAR6 (VAR2 , VAR7, VAR4, VAR9);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.behavioral.pp.v | 18,950 | module MODULE1( VAR241, VAR282, VAR301, VAR212, VAR220, VAR142, VAR57, VAR108 );
input VAR212, VAR301, VAR241, VAR220, VAR282;
inout VAR57, VAR108;
output VAR142;
reg VAR166;
VAR112 VAR73(.VAR241(VAR241),.VAR282(VAR282),.VAR301(VAR301),.VAR212(VAR212),.VAR220(VAR220),.VAR142(VAR142),.VAR57(VAR57),.VAR108(VAR108),.VAR16... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/maj3/sky130_fd_sc_hs__maj3.functional.v | 2,127 | module MODULE1 (
VAR13,
VAR1,
VAR19 ,
VAR12 ,
VAR8 ,
VAR7
);
input VAR13;
input VAR1;
output VAR19 ;
input VAR12 ;
input VAR8 ;
input VAR7 ;
wire VAR16, VAR9 ;
wire VAR16, VAR18 ;
wire VAR6 ;
wire VAR15 ;
wire VAR14;
or VAR10 (VAR6 , VAR8, VAR12 );
and VAR4 (VAR9 , VAR6, VAR7 );
and VAR11 (VAR18 , VAR12, VAR8 );
or VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso1n/sky130_fd_sc_hd__lpflow_inputiso1n_1.v | 2,378 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR2,
VAR7 ,
VAR1 ,
VAR3 ,
VAR9
);
output VAR5 ;
input VAR4 ;
input VAR2;
input VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR9 ;
VAR6 VAR8 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR5 ,
VAR4 ,
VAR2
);
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbp/sky130_fd_sc_ms__dlxbp.functional.pp.v | 1,822 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR2 ,
VAR5,
VAR13,
VAR8,
VAR11 ,
VAR1
);
output VAR9 ;
output VAR6 ;
input VAR2 ;
input VAR5;
input VAR13;
input VAR8;
input VAR11 ;
input VAR1 ;
wire VAR10;
VAR4 VAR3 VAR7 (VAR10 , VAR2, VAR5, , VAR13, VAR8);
buf VAR12 (VAR9 , VAR10 );
not VAR14 (VAR6 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxbn/sky130_fd_sc_ls__dlxbn.pp.blackbox.v | 1,362 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR8 ,
VAR7,
VAR2 ,
VAR3 ,
VAR6 ,
VAR4
);
output VAR5 ;
output VAR1 ;
input VAR8 ;
input VAR7;
input VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
kielfriedt/ece472 | lab5/reg_file.v | 1,716 | module MODULE1(clk, VAR6, VAR4, VAR8, VAR7, VAR1, VAR3, VAR5);
input clk;
input VAR6;
input [4:0] VAR4, VAR8, VAR7;
input [31:0] VAR5;
output [31:0] VAR1, VAR3;
reg [31:0] VAR1, VAR3;
reg [31:0] VAR2 [31:1];
always @(VAR4 or VAR2[VAR4])
begin
if (VAR4 == 0) VAR1 = 32'd0;
end
else VAR1 = VAR2[VAR4];
", VAR4, VAR1);
end
... | gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/FIFO_image_filter_mask_rows_V.v | 2,983 | module MODULE2 (
clk,
VAR7,
VAR11,
VAR23,
VAR1);
parameter VAR22 = 32'd12;
parameter VAR18 = 32'd2;
parameter VAR2 = 32'd3;
input clk;
input [VAR22-1:0] VAR7;
input VAR11;
input [VAR18-1:0] VAR23;
output [VAR22-1:0] VAR1;
reg[VAR22-1:0] VAR27 [0:VAR2-1];
integer VAR13;
always @ (posedge clk)
begin
if (VAR11)
begin
for ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxbp/sky130_fd_sc_ls__dfxbp.behavioral.pp.v | 1,923 | module MODULE1 (
VAR2 ,
VAR14 ,
VAR1 ,
VAR11 ,
VAR9,
VAR7,
VAR3 ,
VAR13
);
output VAR2 ;
output VAR14 ;
input VAR1 ;
input VAR11 ;
input VAR9;
input VAR7;
input VAR3 ;
input VAR13 ;
wire VAR8 ;
reg VAR4 ;
wire VAR15 ;
wire VAR5;
wire VAR10 ;
VAR6 VAR16 (VAR8 , VAR15, VAR5, VAR4, VAR9, VAR7);
assign VAR10 = ( VAR9 === 1... | apache-2.0 |
chriz2600/DreamcastHDMI | Core/source/preproc/gamma.v | 1,469 | module MODULE1(
input VAR2,
input [4:0] VAR1,
input [7:0] in,
output reg [7:0] out
);
always @(posedge VAR2) begin
case (VAR1)
case (in)
endcase
end
case (in)
endcase
end
case (in)
endcase
end
case (in)
endcase
end
case (in)
endcase
end
case (in)
endcase
end
case (in)
endcase
end
case (in)
endcase
end
default: out <= i... | mit |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/verilog/axi_vdma_v6_2_axis_dwidth_converter_v1_0_axisc_downsizer.v | 14,214 | module MODULE1 #
(
parameter VAR75 = "VAR37",
parameter integer VAR21 = 96,
parameter integer VAR74 = 32,
parameter integer VAR25 = 1,
parameter integer VAR19 = 1,
parameter integer VAR11 = 3,
parameter integer VAR49 = 1,
parameter [31:0] VAR12 = 32'hFF ,
parameter integer VAR13 = 3 )
(
input wire VAR47,
input wire VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1.behavioral.v | 1,405 | module MODULE1 (
VAR8,
VAR2
);
output VAR8;
input VAR2;
supply1 VAR7;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR3 ;
wire VAR9;
buf VAR1 (VAR9, VAR2 );
buf VAR5 (VAR8 , VAR9 );
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/cart/cart.v | 4,454 | module MODULE1 (
input VAR28,
input [39:0] VAR12, input VAR27,
input VAR13, input [14:0] VAR26, input VAR17, input [ 7:0] VAR24, output [ 7:0] VAR25,
input [13:0] VAR18, input VAR4, input [ 7:0] VAR5, output [ 7:0] VAR20, output VAR8, output VAR11 );
wire VAR16;
wire [14:0] VAR7;
wire [7:0] VAR14;
VAR23 #(
.VAR21 (15 )... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfstp/sky130_fd_sc_ls__dfstp.blackbox.v | 1,319 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR6 ,
VAR3
);
output VAR2 ;
input VAR5 ;
input VAR6 ;
input VAR3;
supply1 VAR4;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.behavioral.pp.v | 1,089 | module MODULE1( VAR1, VAR5 );
inout VAR1, VAR5;
VAR3 VAR2(.VAR1(VAR1),.VAR5(VAR5));
VAR3 VAR4(.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1p/sky130_fd_sc_lp__iso1p.functional.pp.v | 1,872 | module MODULE1 (
VAR11 ,
VAR7 ,
VAR8,
VAR1,
VAR2 ,
VAR9 ,
VAR10
);
output VAR11 ;
input VAR7 ;
input VAR8;
input VAR1;
input VAR2 ;
input VAR9 ;
input VAR10 ;
wire VAR6 ;
wire VAR4;
VAR3 VAR12 (VAR6 , VAR7, VAR1, VAR2 );
VAR3 VAR13 (VAR4, VAR8, VAR1, VAR2 );
or VAR5 (VAR11 , VAR6, VAR4);
endmodule | apache-2.0 |
oblivioncth/DE0-Verilog-Processor | src/ID_01_Handler.v | 2,436 | module MODULE1 (VAR2, VAR1, VAR3);
input [13:0] VAR2;
output reg [15:0] VAR3;
output reg [18:0] VAR1;
always @(VAR2) begin
case (VAR2[13:9])
5'b10000: begin VAR1 = {6'b100001,VAR2[8:6],VAR2[5:3],7'b0000100}; VAR3 = 16'b1111111111111111; end
5'b10100: begin VAR1 = {6'b101001,VAR2[8:6],VAR2[5:3],VAR2[2:0],4'b1100}; VAR3 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/inv/sky130_fd_sc_ms__inv.functional.pp.v | 1,748 | module MODULE1 (
VAR2 ,
VAR12 ,
VAR7,
VAR11,
VAR1 ,
VAR5
);
output VAR2 ;
input VAR12 ;
input VAR7;
input VAR11;
input VAR1 ;
input VAR5 ;
wire VAR6 ;
wire VAR8;
not VAR3 (VAR6 , VAR12 );
VAR9 VAR10 (VAR8, VAR6, VAR7, VAR11);
buf VAR4 (VAR2 , VAR8 );
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/dest_fifo_inf.v | 4,564 | module MODULE1 (
input clk,
input VAR11,
input enable,
output VAR35,
input VAR38,
output VAR42,
input [VAR37-1:0] VAR6,
output [VAR37-1:0] VAR12,
output [VAR37-1:0] VAR21,
input VAR9,
input VAR23,
input en,
output [VAR25-1:0] dout,
output valid,
output VAR14,
output VAR24,
output VAR39,
input VAR2,
input [VAR25-1:0] VA... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_4.behavioral.v | 1,802 | module MODULE1( VAR4, VAR2, VAR7, VAR1, VAR8 );
input VAR7, VAR2, VAR1, VAR8;
output VAR4;
VAR6 VAR3(.VAR4(VAR4),.VAR2(VAR2),.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8));
VAR6 VAR5(.VAR4(VAR4),.VAR2(VAR2),.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8)); | apache-2.0 |
orbancedric/DeepGate | other/convPrototype/convLayerControl.v | 3,541 | module MODULE1 #(
parameter VAR18 = 16'd125, parameter VAR13 = 16'd100, parameter VAR1 = 16'd10, parameter VAR11 = 16'd10, parameter VAR14 = 16'd10,
parameter VAR4 = 16'd10,
parameter VAR3 = 16'd1
)(
input clk,
input VAR9,
input VAR12,
input VAR10,
output reg enable = 0,
output reg VAR16 = 0,
output reg VAR7 = 0,
outpu... | gpl-3.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | Registro_universal.v | 1,206 | module MODULE1
input wire VAR7,
input wire [VAR3-1:0]VAR1,
input wire [VAR3-1:0]VAR8,
input wire clk, input wire reset, input wire VAR4, output wire [VAR3-1:0]VAR5
);
reg [VAR3-1:0]VAR6;
reg [VAR3-1:0]VAR2;
always@(negedge clk, posedge reset)
begin
if(reset) VAR6 <= 0;
end
else VAR6 <= VAR2;
end
always@*
begin
if (~VAR... | mit |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_onchip_sram.v | 2,946 | module MODULE1 (
address,
VAR17,
VAR21,
clk,
VAR32,
reset,
VAR10,
write,
VAR31,
VAR13
)
;
parameter VAR20 = "MODULE1.VAR26";
output [ 31: 0] VAR13;
input [ 16: 0] address;
input [ 3: 0] VAR17;
input VAR21;
input clk;
input VAR32;
input reset;
input VAR10;
input write;
input [ 31: 0] VAR31;
wire VAR6;
wire [ 31: 0] VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21boi/sky130_fd_sc_hd__a21boi.pp.symbol.v | 1,394 | module MODULE1 (
input VAR1 ,
input VAR6 ,
input VAR8,
output VAR4 ,
input VAR3 ,
input VAR5,
input VAR2,
input VAR7
);
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/redundant/ovl_fifo_index.v | 1,887 | module MODULE1 (VAR16, reset, enable, VAR17, VAR25, VAR20);
parameter VAR12 = VAR1;
parameter VAR6 = 1;
parameter VAR2 = 1;
parameter VAR13 = 1;
parameter VAR7 = 1; parameter VAR22 = VAR14;
parameter VAR3 = VAR4;
parameter VAR24 = VAR5;
parameter VAR15 = VAR8;
parameter VAR9 = VAR18;
parameter VAR19 = VAR10;
input VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtp/sky130_fd_sc_ms__dlrtp.functional.pp.v | 1,928 | module MODULE1 (
VAR4 ,
VAR12,
VAR1 ,
VAR9 ,
VAR3 ,
VAR7 ,
VAR15 ,
VAR13
);
output VAR4 ;
input VAR12;
input VAR1 ;
input VAR9 ;
input VAR3 ;
input VAR7 ;
input VAR15 ;
input VAR13 ;
wire VAR5;
wire VAR6;
not VAR2 (VAR5 , VAR12 );
VAR8 VAR10 VAR14 (VAR6 , VAR1, VAR9, VAR5, , VAR3, VAR7);
buf VAR11 (VAR4 , VAR6 );
endmo... | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/fanout_merger.v | 2,548 | module MODULE1(VAR5, VAR17,
VAR14, VAR1, VAR3,
VAR12, VAR16, VAR13,
VAR4, VAR10);
parameter VAR6 = 32;
parameter VAR2 = 4;
parameter VAR8 = 3;
parameter VAR9 = 0;
input VAR5, VAR17;
input [VAR2*VAR6-1:0] VAR14;
input [VAR2-1:0] VAR1;
output [VAR2-1:0] VAR3;
output [VAR6-1:0] VAR12;
input VAR16;
output VAR13;
input [VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41a/sky130_fd_sc_hd__o41a_1.v | 2,411 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR4 ,
VAR10 ,
VAR2 ,
VAR12 ,
VAR3,
VAR8,
VAR5 ,
VAR6
);
output VAR7 ;
input VAR9 ;
input VAR4 ;
input VAR10 ;
input VAR2 ;
input VAR12 ;
input VAR3;
input VAR8;
input VAR5 ;
input VAR6 ;
VAR11 VAR1 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR3(... | apache-2.0 |
ShepardSiegel/ocpi | scripts/auguste/bram/mkDelay.v | 3,597 | module MODULE1(VAR25,
VAR14,
VAR20,
VAR8,
VAR11,
VAR17,
read,
VAR22);
input VAR25;
input VAR14;
input [31 : 0] VAR20;
input VAR8;
output VAR11;
input VAR17;
output [31 : 0] read;
output VAR22;
reg [31 : 0] read;
wire VAR22, VAR11;
reg [3 : 0] VAR2;
wire [3 : 0] VAR6;
wire VAR10;
reg [31 : 0] VAR24;
wire [31 : 0] VAR23;... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_2.behavioral.pp.v | 1,388 | module MODULE1( VAR4, VAR3, VAR5, VAR2, VAR10, VAR8, VAR1 );
input VAR4, VAR3, VAR5, VAR2;
inout VAR8, VAR1;
output VAR10;
VAR9 VAR7(.VAR4(VAR4),.VAR3(VAR3),.VAR5(VAR5),.VAR2(VAR2),.VAR10(VAR10),.VAR8(VAR8),.VAR1(VAR1));
VAR9 VAR6(.VAR4(VAR4),.VAR3(VAR3),.VAR5(VAR5),.VAR2(VAR2),.VAR10(VAR10),.VAR8(VAR8),.VAR1(VAR1)); | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_link/bsg_link_source_sync_upstream_sync.v | 6,345 | module MODULE1
,parameter VAR9 = 3
,parameter VAR1 = 0
,parameter VAR41 = 0
)
( input VAR33
,input VAR49
,input VAR27
,input VAR17
,input [VAR21-1:0] VAR14
,output VAR5
,output VAR43
,output [VAR21-1:0] VAR38
,input VAR3
);
logic VAR11, VAR12;
logic [VAR21-1:0] VAR18;
if (VAR41 == 0)
begin: VAR31
VAR24
) VAR48
(.VAR46 ... | bsd-3-clause |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/acl_fp_custom_mul_dbl_pumped.v | 3,497 | module MODULE1
(
input VAR2,
input VAR9,
input enable,
input VAR13,
input [VAR4-1:0] VAR7,
input [VAR4-1:0] b1,
input [VAR4-1:0] VAR16,
input [VAR4-1:0] VAR17,
output reg [VAR4-1:0] VAR5,
output reg [VAR4-1:0] VAR12
);
reg [VAR4-1:0] VAR8;
reg [VAR4-1:0] VAR14;
reg [VAR4-1:0] VAR11;
reg [VAR4-1:0] VAR10;
reg VAR15 ;
wi... | mit |
azonenberg/yosys | techlibs/intel/cyclone10/cells_arith.v | 2,584 | module MODULE1(
module 80alteraa10gxalu (VAR18, VAR17, VAR35, VAR9, VAR27, VAR20, VAR24);
parameter VAR3 = 0;
parameter VAR31 = 0;
parameter VAR11 = 1;
parameter VAR29 = 1;
parameter VAR22 = 1;
input [VAR11-1:0] VAR18;
input [VAR29-1:0] VAR17;
output [VAR22-1:0] VAR27, VAR20;
input VAR35, VAR9;
output VAR24;
wire VAR28... | isc |
trivoldus28/pulsarch-verilog | design/sys/iop/common/rtl/cluster_header_sync.v | 2,362 | module MODULE1 (
VAR10, VAR2, VAR14,
VAR7, VAR4,
VAR9, VAR16, VAR17,
VAR18, VAR1, VAR11, VAR12, VAR13
);
output VAR10;
output VAR2;
output VAR14;
output VAR7;
output VAR4;
input VAR9;
input VAR16;
input VAR17;
input VAR18;
input VAR1;
input VAR11;
input VAR12;
input VAR13;
wire VAR8;
wire VAR15;
wire VAR3;
VAR6 VAR5 (
... | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/up_dac_common.v | 19,450 | module MODULE1 (
VAR92,
VAR70,
VAR24,
VAR115,
VAR37,
VAR58,
VAR42,
VAR32,
VAR73,
VAR76,
VAR90,
VAR120,
VAR15,
VAR20,
VAR36,
VAR114,
VAR88,
VAR41,
VAR75,
VAR71,
VAR85,
VAR61,
VAR14,
VAR118,
VAR2,
VAR99,
VAR77,
VAR69,
VAR7,
VAR23,
VAR48,
VAR98,
VAR106,
VAR111,
VAR43,
VAR25);
parameter VAR30 = 32'h00040062;
parameter VAR9... | mit |
dcsun88/ntpserver-fpga | cpu/ip/cpu_processing_system7_0_0/hdl/processing_system7_bfm_v2_0_axi_master.v | 20,925 | module MODULE1 (
VAR6,
VAR40,
VAR5,
VAR22,
VAR43,
VAR31,
VAR57,
VAR23,
VAR21,
VAR49,
VAR18,
VAR42,
VAR16,
VAR50,
VAR46,
VAR61,
VAR17,
VAR14,
VAR12,
VAR38,
VAR30,
VAR33,
VAR47,
VAR19,
VAR56,
VAR1, VAR58, VAR25,
VAR59,
VAR10,
VAR9,
VAR15,
VAR52,
VAR4,
VAR24,
VAR28,
VAR34,
VAR44,
VAR3,
VAR27
);
parameter VAR41 = 0;
parame... | gpl-3.0 |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | Verilog_AES/AES/ClockGenerator.v | 1,391 | module MODULE1(
output reg VAR1,
output reg reset
);
always begin
VAR1 = ~VAR1;
end
begin | lgpl-2.1 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/example_design/PIO_TX_ENGINE.v | 14,012 | module MODULE1 #(
parameter VAR29 = 64,
parameter VAR5 = 1,
parameter VAR43 = VAR29 / 8
)(
input clk,
input VAR17,
input VAR3,
output reg [VAR29-1:0] VAR6,
output reg [VAR43-1:0] VAR52,
output reg VAR40,
output reg VAR18,
output VAR48,
input VAR8,
input VAR24,
output reg VAR12,
input [2:0] VAR51,
input VAR22,
input VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4b/sky130_fd_sc_lp__nand4b.behavioral.pp.v | 1,998 | module MODULE1 (
VAR3 ,
VAR16 ,
VAR12 ,
VAR2 ,
VAR10 ,
VAR7,
VAR6,
VAR5 ,
VAR9
);
output VAR3 ;
input VAR16 ;
input VAR12 ;
input VAR2 ;
input VAR10 ;
input VAR7;
input VAR6;
input VAR5 ;
input VAR9 ;
wire VAR8 ;
wire VAR13 ;
wire VAR11;
not VAR15 (VAR8 , VAR16 );
nand VAR14 (VAR13 , VAR10, VAR2, VAR12, VAR8 );
VAR1 VA... | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/02CAD-JOYSTICK/Version_02/02 verilog/adc/fifo.v | 2,232 | module MODULE1
parameter VAR10 = 10,
parameter VAR7 = 8
)
(
input VAR5, reset,
input wr,rd,
input [VAR7-1:0] VAR8,
output [VAR7-1:0] VAR14,
output VAR15,
output VAR16
);
parameter VAR6 = (1 << VAR10);
reg [VAR7-1:0] VAR11 [VAR6-1:0];
reg [VAR10-1:0] VAR17, VAR4;
reg [VAR10-1:0] VAR1, VAR12;
reg VAR9, VAR18, VAR13, VAR2... | gpl-3.0 |
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