repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
jotego/jt12 | hdl/jt03_acc.v | 2,033 | module MODULE1
(
input rst,
input clk,
input VAR7 ,
input signed [13:0] VAR4,
input VAR15,
input VAR3,
input VAR9,
input VAR6,
input VAR16,
input [2:0] VAR14,
output signed [15:0] VAR12
);
reg VAR5;
always @(*) begin
case ( VAR14 )
default: VAR5 = VAR6;
3'd4: VAR5 = VAR3 | VAR6;
3'd5,3'd6: VAR5 = ~VAR15;
3'd7: VAR5 = 1... | gpl-3.0 |
ShepardSiegel/ocpi | rtl/mkTimeClient.v | 4,245 | module MODULE1(VAR32,
VAR37,
VAR15,
VAR29,
VAR21,
VAR11,
VAR16,
VAR8,
VAR33,
VAR6,
VAR30,
VAR9);
input VAR32;
input VAR37;
input VAR15;
input VAR29;
input VAR21;
input VAR11;
input [63 : 0] VAR16;
input VAR8;
output VAR33;
output [66 : 0] VAR6;
input VAR30;
input VAR9;
wire [66 : 0] VAR6;
wire VAR33;
wire VAR31,
VAR17,... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrtp/sky130_fd_sc_ls__dfrtp.behavioral.pp.v | 2,243 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR18 ,
VAR1,
VAR15 ,
VAR9 ,
VAR20 ,
VAR6
);
output VAR8 ;
input VAR2 ;
input VAR18 ;
input VAR1;
input VAR15 ;
input VAR9 ;
input VAR20 ;
input VAR6 ;
wire VAR5 ;
wire VAR12 ;
reg VAR13 ;
wire VAR14 ;
wire VAR3;
wire VAR11 ;
wire VAR7 ;
wire VAR16 ;
wire VAR21 ;
not VAR4 (VAR12 , VAR3 );... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_p_pp_pg_n.symbol.v | 1,438 | module MODULE1 (
input VAR3 ,
output VAR1 ,
input VAR5 ,
input VAR2,
input VAR4 ,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311oi/sky130_fd_sc_hd__a311oi_4.v | 2,450 | module MODULE2 (
VAR9 ,
VAR7 ,
VAR10 ,
VAR1 ,
VAR12 ,
VAR3 ,
VAR6,
VAR4,
VAR5 ,
VAR2
);
output VAR9 ;
input VAR7 ;
input VAR10 ;
input VAR1 ;
input VAR12 ;
input VAR3 ;
input VAR6;
input VAR4;
input VAR5 ;
input VAR2 ;
VAR11 VAR8 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR12(VAR12),
.VAR3(VAR3),
.VAR6(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4b/sky130_fd_sc_ms__nor4b.pp.blackbox.v | 1,341 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR9 ,
VAR4 ,
VAR2 ,
VAR8,
VAR5,
VAR6 ,
VAR3
);
output VAR1 ;
input VAR7 ;
input VAR9 ;
input VAR4 ;
input VAR2 ;
input VAR8;
input VAR5;
input VAR6 ;
input VAR3 ;
endmodule | apache-2.0 |
rhalstea/cidr_15_fpga_join | probe_engine/verilog/engine.v | 4,976 | module MODULE1 (
input clk,
input rst,
output VAR46,
input [63:0] VAR19,
input [63:0] VAR49,
input [63:0] VAR35,
input [63:0] VAR4, input [63:0] VAR45,
input VAR42,
output VAR53,
output [47:0] VAR5,
output VAR31,
input VAR1,
input [63:0] VAR47,
input VAR58,
output VAR21,
output [47:0] VAR52,
output VAR41,
input VAR27,
... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ai/sky130_fd_sc_hs__o21ai.pp.symbol.v | 1,319 | module MODULE1 (
input VAR4 ,
input VAR6 ,
input VAR3 ,
output VAR1 ,
input VAR5,
input VAR2
);
endmodule | apache-2.0 |
rhalstea/cidr_15_fpga_join | probe_engine/verilog/probe_phase.v | 5,150 | module MODULE1 (
input clk,
input rst,
output VAR42,
output VAR59,
input VAR20,
input [63:0] VAR51,
input [63:0] VAR16,
input VAR55,
output VAR40,
output [47:0] VAR43,
output VAR52,
input VAR15,
input [63:0] VAR31,
input VAR6,
output VAR25,
output [47:0] VAR44,
output VAR57,
input VAR29,
input [63:0] VAR37,
input VAR35... | bsd-3-clause |
monotone-RK/FACE | IEICE-Trans/data_compression/8-way_2-tree/src/riffa/tx_engine_ultrascale.v | 12,315 | module MODULE1
parameter VAR84 = 1,
parameter VAR82 = 0,
parameter VAR50 = 64)
( input VAR7,
input VAR42, input VAR33, output VAR1,
output VAR73,
input [VAR65-1:0] VAR64,
input VAR83,
output VAR61,
output VAR67,
output [VAR34-1:0] VAR28,
output [(VAR34/32)-1:0] VAR24,
output [VAR66-1:0] VAR35,
input VAR41,
input [VAR34... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2/sky130_fd_sc_hd__mux2.symbol.v | 1,322 | module MODULE1 (
input VAR8,
input VAR6,
output VAR2 ,
input VAR7
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3/sky130_fd_sc_ms__nor3.blackbox.v | 1,288 | module MODULE1 (
VAR8,
VAR6,
VAR1,
VAR2
);
output VAR8;
input VAR6;
input VAR1;
input VAR2;
supply1 VAR5;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_srams.v | 3,948 | module MODULE1(
input VAR1,
input VAR21,
input VAR16,
input VAR18,
input [VAR5-1:0] VAR11,
input [VAR38-1:0] VAR3,
input [VAR6-1:0] VAR14,
output [VAR6-1:0] VAR19,
input VAR17,
input VAR37,
input VAR13,
input VAR42,
input VAR23,
input VAR12,
input [VAR30-1:0] VAR31,
input [VAR25-1:0] VAR34,
input [VAR33-1:0] VAR10,
out... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31oi/sky130_fd_sc_ls__a31oi.pp.blackbox.v | 1,391 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR8 ,
VAR9 ,
VAR7 ,
VAR1,
VAR4,
VAR3 ,
VAR5
);
output VAR2 ;
input VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR7 ;
input VAR1;
input VAR4;
input VAR3 ;
input VAR5 ;
endmodule | apache-2.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/cdp/rule_32_30_bb.v | 5,571 | module MODULE1 (
VAR3,
VAR5,
VAR6,
VAR4,
VAR1,
VAR7,
VAR2);
input VAR3;
input VAR5;
input [29:0] VAR6;
input VAR4;
input VAR1;
output [29:0] VAR7;
output [4:0] VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22o/sky130_fd_sc_ms__a22o_2.v | 2,339 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR2 ,
VAR4 ,
VAR9 ,
VAR7,
VAR6,
VAR8 ,
VAR1
);
output VAR3 ;
input VAR11 ;
input VAR2 ;
input VAR4 ;
input VAR9 ;
input VAR7;
input VAR6;
input VAR8 ;
input VAR1 ;
VAR10 VAR5 (
.VAR3(VAR3),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR... | apache-2.0 |
ak-fau/fpga-cyclone_iv | bemicro/sys_pll_bb.v | 11,209 | module MODULE1 (
VAR3,
VAR2,
VAR1,
VAR4);
input VAR3;
input VAR2;
output VAR1;
output VAR4;
tri0 VAR3;
endmodule | bsd-2-clause |
glennchid/font5-firmware | src/verilog/synthesis/Combiner.v | 2,379 | module MODULE1(
input clk,
input signed [15:0] din,
input VAR5,
input VAR12,
output signed [15:0] dout
);
parameter real VAR6 = 357e6; parameter real VAR2 = 280e-9;
localparam integer VAR11 = VAR3(VAR6 * VAR2);
localparam [VAR11-1:0] VAR10 = (VAR6 * VAR2);
reg signed [17:0] VAR9 [0:VAR10-1];
integer VAR1, VAR8;
VAR7 fo... | gpl-3.0 |
titorgalaxy/Titor | rtl/verilog/util/StripedDualMemory.v | 7,484 | module MODULE1(
VAR16,
VAR10,
VAR28,
VAR23,
VAR49,
VAR41,
VAR43,
VAR21,
VAR12,
VAR36,
VAR46,
VAR25,
clk,
reset
);
parameter VAR1 = VAR15;
output reg [VAR33-1:0] VAR16;
input [VAR33-1:0] VAR10;
input [VAR33-1:0] VAR28;
input [VAR27-1:0] VAR23; input VAR49;
input VAR41;
output reg [VAR33-1:0] VAR43;
input [VAR33-1:0] VAR... | gpl-3.0 |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/mi_nios/synthesis/submodules/mi_nios_SW.v | 1,861 | module MODULE1 (
address,
clk,
VAR3,
VAR2,
VAR5
)
;
output [ 31: 0] VAR5;
input [ 1: 0] address;
input clk;
input [ 3: 0] VAR3;
input VAR2;
wire VAR4;
wire [ 3: 0] VAR6;
wire [ 3: 0] VAR1;
reg [ 31: 0] VAR5;
assign VAR4 = 1;
assign VAR1 = {4 {(address == 0)}} & VAR6;
always @(posedge clk or negedge VAR2)
begin
if (VAR2... | mit |
zhangly/azpr_cpu | rtl/cpu/rtl/if_stage.v | 4,119 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR1] VAR8, output wire [VAR32] VAR24, output wire VAR15, output wire VAR17, output wire [VAR1] VAR28,
input wire [VAR1] VAR21, input wire VAR4, input wire VAR5, output wire VAR13, output wire [VAR32] VAR31, output wire VAR33, output wire VAR14, output wire... | mit |
osecpu/fpga | alu.v | 1,647 | module MODULE2(VAR1, VAR4, dout, VAR5, VAR3);
input signed [31:0] VAR1, VAR4;
output signed [31:0] dout;
input[3:0] VAR5;
input VAR3;
assign dout = VAR2(VAR5, VAR1, VAR4);
function signed [31:0] VAR2(input [3:0] VAR5, input signed [31:0] VAR1, input signed [31:0] VAR4);
if(VAR3 == 0) begin
case (VAR5)
default: VAR2 = 0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4/sky130_fd_sc_hdll__nor4.functional.v | 1,337 | module MODULE1 (
VAR4,
VAR1,
VAR5,
VAR3,
VAR8
);
output VAR4;
input VAR1;
input VAR5;
input VAR3;
input VAR8;
wire VAR6;
nor VAR2 (VAR6, VAR1, VAR5, VAR3, VAR8 );
buf VAR7 (VAR4 , VAR6 );
endmodule | apache-2.0 |
olofk/wb_intercon | rtl/verilog/wb_mux.v | 4,682 | module MODULE1
parameter [VAR22*VAR37-1:0] VAR30 = 0)
(input VAR40,
input VAR8,
input [VAR37-1:0] VAR28,
input [VAR18-1:0] VAR4,
input [3:0] VAR38,
input VAR5,
input VAR6,
input VAR27,
input [2:0] VAR13,
input [1:0] VAR21,
output [VAR18-1:0] VAR14,
output VAR23,
output VAR11,
output VAR35,
output [VAR22*VAR37-1:0] VAR1... | lgpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_fpu/bsg_fpu_f2i.v | 3,248 | module MODULE1
, parameter VAR2(VAR24)
, localparam VAR36=(VAR30+VAR24+1)
, localparam VAR31={1'b0, {(VAR30-1){1'b1}}}
)
(
input [VAR36-1:0] VAR8 , input VAR10
, output logic [VAR36-1:0] VAR6 , output logic VAR22
);
logic VAR28;
logic [VAR30-1:0] VAR27;
logic [VAR24-1:0] VAR26;
logic VAR18;
logic VAR19;
logic VAR3;
VAR... | bsd-3-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9680/axi_ad9680_channel.v | 5,893 | module MODULE1 (
VAR37,
VAR61,
VAR12,
VAR20,
VAR4,
VAR67,
VAR19,
VAR26,
VAR9,
VAR34,
VAR21,
VAR2,
VAR7,
VAR16,
VAR66,
VAR27,
VAR44,
VAR60,
VAR58);
parameter VAR48 = 0;
parameter VAR38 = 0;
input VAR37;
input VAR61;
input [55:0] VAR12;
input VAR20;
output [63:0] VAR4;
output VAR67;
output VAR19;
output VAR26;
output VAR... | gpl-3.0 |
dvanmali/Superscalar_Pipeline_Processor | branchhistorytable.v | 2,338 | module MODULE1(clk,VAR8,VAR4,VAR3,VAR7,VAR6,VAR5);
input clk;
input [1:0] VAR8;
input [31:0] VAR7, VAR3, VAR4;
output reg [31:0] VAR6;
output reg VAR5;
reg [65:0] VAR1[127:0];
reg [31:0] VAR10;
integer VAR2;
reg VAR9; | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufbuf/sky130_fd_sc_hdll__bufbuf.behavioral.pp.v | 1,786 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR1,
VAR3,
VAR5 ,
VAR2
);
output VAR9 ;
input VAR4 ;
input VAR1;
input VAR3;
input VAR5 ;
input VAR2 ;
wire VAR11 ;
wire VAR7;
buf VAR12 (VAR11 , VAR4 );
VAR6 VAR10 (VAR7, VAR11, VAR1, VAR3);
buf VAR8 (VAR9 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2.behavioral.v | 1,440 | module MODULE1 (
VAR9,
VAR2
);
output VAR9;
input VAR2;
supply1 VAR3;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR8 ;
wire VAR7;
not VAR1 (VAR7, VAR2 );
buf VAR5 (VAR9 , VAR7 );
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build4/regfileww.v | 4,749 | module MODULE1(VAR1,VAR15,VAR10,VAR2,VAR6,VAR7,
VAR11,VAR8,VAR16,VAR5,clk);
output [127:0] VAR1,VAR15;
input [0:127] VAR10;
input clk;
input VAR16;
input VAR11, VAR8;
input [4:0] VAR7, VAR2, VAR6;
input [15:0] VAR5;
reg [127:0] VAR1,VAR15;
reg [127:0] VAR9 [31:0];
reg [127:0] VAR3; reg [127:0] VAR12; reg [7:0] VAR4;
al... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/dma_engine_rr_arb.v | 5,446 | module MODULE1 (
input [3:0] VAR3,
input [15:0] VAR17, input VAR13,
output reg [3:0] VAR5,
output [15:0] VAR6,
output reg VAR12,
input VAR4,
input VAR16,
input VAR15,
input VAR19,
input reset,
input clk
);
reg [3:0] VAR20;
reg [3:0] VAR14;
wire [15:0] VAR9;
always @(posedge clk)
begin
if (reset || VAR19)
VAR20 <= 4'h0;... | mit |
SergKolo/msudenver_eet_4020_verilog | proj2_elevator/elevator.v | 7,375 | module MODULE1(VAR19,VAR17,VAR1,VAR9);
input [9:0] VAR1;
output reg [9:0] VAR17;
wire [9:0] VAR6;
wire [9:0] VAR22;
input VAR9;
output wire [4:0] VAR19;
reg [4:0] VAR18;
reg VAR5;
MODULE2 MODULE1(VAR22,VAR19,VAR5,VAR18,VAR9);
VAR7 VAR16(VAR6[0],
VAR22[0],VAR1[0],VAR9);
VAR7 VAR2(VAR6[1],
VAR22[1],VAR1[1],VAR9);
VAR7 VA... | mit |
pwwu/FPGA | VGAbased/final/lcd_write_number.v | 2,689 | module MODULE1
(
input VAR33,
output VAR2,
output VAR7,
output VAR28,
output [3:0] VAR16,
input [31:0] VAR34,
input VAR13,
output VAR23
);
reg [7:0] VAR6;
reg VAR8;
reg [31:0] VAR15;
reg VAR20;
wire VAR26;
reg VAR30;
reg [7:0] VAR4;
reg [1:0] state;
reg [31:0] VAR21;
reg VAR11;
reg VAR3;
reg [4:0] VAR5;
reg VAR27;
assi... | mit |
siamumar/TinyGarbled | circuit_synthesis/mips/Data_Mem.v | 3,910 | module MODULE1
(
parameter VAR8 = 32,
parameter VAR9 = 6
)
(
clk,
rst,
VAR5,
VAR3,
VAR7,
addr,
VAR13,
VAR4
);
localparam VAR1 = 2**VAR9;
input clk;
input rst;
input [VAR8*VAR1-1:0] VAR5;
output [VAR8*VAR1-1:0] VAR3;
input [3:0] VAR7;
input [31:0] addr;
input [VAR8-1:0] VAR13;
output [VAR8-1:0] VAR4;
reg [VAR8-1:0] VAR4... | gpl-3.0 |
natsutan/NPU | fpga_implement/npu8/npu8.cache/ip/d74462b9dbd19694/mult_17x16_stub.v | 1,315 | module MODULE1(VAR2, VAR4, VAR1, VAR3)
;
input VAR2;
input [16:0]VAR4;
input [15:0]VAR1;
output [24:0]VAR3;
endmodule | bsd-3-clause |
bluespec/Flute | src_SSITH_P2/xilinx_ip/hdl/SyncHandshake.v | 4,082 | module MODULE1(
VAR3,
VAR5,
VAR7,
VAR9,
VAR11,
VAR15
);
parameter VAR4 = 1'b0;
parameter VAR13 = 1'b0;
input VAR3 ;
input VAR5 ;
input VAR9 ;
output VAR11 ;
input VAR7 ;
output VAR15 ;
reg VAR12, VAR18 ;
reg VAR1 ;
reg VAR10 ;
reg VAR19, VAR2 ;
assign VAR15 = VAR18 != VAR1 ;
assign VAR11 = VAR2 == VAR10;
wire VAR6 = VA... | apache-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_axi_basic_rx_null_gen.v | 15,544 | module MODULE1 # (
parameter VAR27 = 128, parameter VAR19 = 1,
parameter VAR30 = VAR27 / 8 ) (
input [VAR27-1:0] VAR12, input VAR23, input VAR18, input VAR15, input [21:0] VAR25,
output VAR21, output VAR5, output [VAR30-1:0] VAR26, output VAR28, output reg [4:0] VAR36,
input VAR11, input VAR8 );
localparam VAR1 = (VAR2... | mit |
kyzhai/NUNY | src/hardware/bg.v | 6,302 | module MODULE1 (
address,
VAR50,
VAR8);
input [9:0] address;
input VAR50;
output [23:0] VAR8;
tri1 VAR50;
wire [23:0] VAR19;
wire [23:0] VAR8 = VAR19[23:0];
VAR13 VAR21 (
.VAR37 (address),
.VAR22 (VAR50),
.VAR33 (VAR19),
.VAR20 (1'b0),
.VAR38 (1'b0),
.VAR4 (1'b1),
.VAR36 (1'b0),
.VAR16 (1'b0),
.VAR17 (1'b1),
.VAR30 (1'... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcomms1/vc707/system_top.v | 10,548 | module MODULE1 (
VAR12,
VAR103,
VAR81,
VAR66,
VAR67,
VAR5,
VAR130,
VAR43,
VAR39,
VAR131,
VAR99,
VAR79,
VAR86,
VAR100,
VAR107,
VAR101,
VAR113,
VAR122,
VAR84,
VAR61,
VAR42,
VAR77,
VAR133,
VAR114,
VAR115,
VAR75,
VAR65,
VAR78,
VAR27,
VAR87,
VAR69,
VAR59,
VAR9,
VAR118,
VAR45,
VAR136,
VAR102,
VAR104,
VAR44,
VAR28,
VAR38,
VAR... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/db_ram_1p.v | 3,203 | module MODULE1 (
clk ,
VAR2 ,
VAR6 ,
VAR4 ,
VAR10 ,
VAR5 ,
VAR11
);
parameter VAR12 = 128;
parameter VAR7 = 8 ;
input clk ; input VAR2; input VAR6; input VAR4; input [VAR7-1:0] VAR10; input [VAR12-1:0] VAR5; output [VAR12-1:0] VAR11;
reg [VAR12-1:0] VAR8[(1<<VAR7)-1:0];
reg [VAR12-1:0] VAR9;
always @(posedge clk) begin... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22a/sky130_fd_sc_hs__o22a.pp.symbol.v | 1,335 | module MODULE1 (
input VAR7 ,
input VAR4 ,
input VAR6 ,
input VAR5 ,
output VAR2 ,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
CospanDesign/nysa-sata | rtl/phy/sata_phy_layer.v | 5,123 | module MODULE1 (
input rst, input clk,
input VAR4, output VAR13,
output VAR14,
output [31:0] VAR3,
output VAR7,
output VAR1,
output VAR24,
output VAR16,
input VAR9,
input [31:0] VAR28,
input [3:0] VAR30,
input VAR6,
input VAR17,
input VAR12,
input VAR25,
output VAR18,
input VAR2,
output [3:0] VAR10
);
parameter VAR32 =... | mit |
fabianmcg/usbc_tcpc | src/debug_module.v | 1,195 | module MODULE1(output reg [31:0] VAR1, input wire VAR3,input wire VAR2);
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin | mit |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/rtr_flow_ctrl_input.v | 5,024 | module MODULE1
(clk, reset, VAR4, VAR14, VAR8,
VAR23);
parameter VAR22 = 4;
parameter VAR15 = VAR13;
parameter VAR9 = VAR3;
localparam VAR19 = VAR7(VAR22);
localparam VAR21
= (VAR15 == VAR13) ? (1 + VAR19) :
-1;
input clk;
input reset;
input VAR4;
input [0:VAR21-1] VAR14;
output VAR8;
wire VAR8;
output [0:VAR22-1] VAR2... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21ai/sky130_fd_sc_ms__o21ai.symbol.v | 1,349 | module MODULE1 (
input VAR6,
input VAR7,
input VAR3,
output VAR4
);
supply1 VAR2;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/edc/edc_module.v | 7,983 | module MODULE1 (
input VAR22,
input VAR2,
input [31:0] VAR40,
input [15:0] VAR47,
input VAR8,
output [127:0] VAR39, input [127:0] VAR3, input VAR53,
input VAR19,
output VAR30,
output VAR33
);
parameter VAR18 = 26;
wire VAR11; wire VAR6;
reg [31:0] VAR1[0:3]; wire [3:0]VAR31;
VAR42 #(
.VAR27 ( 128 ),
.VAR25 ( 16 )
)
VAR... | lgpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/z80/tv80_alu.v | 11,495 | module MODULE1 (
VAR27, VAR29,
VAR18, VAR9, VAR14, VAR19, VAR31, VAR33, VAR20, VAR10
);
parameter VAR24 = 0;
parameter VAR26 = 0;
parameter VAR30 = 1;
parameter VAR16 = 2;
parameter VAR1 = 3;
parameter VAR5 = 4;
parameter VAR34 = 5;
parameter VAR15 = 6;
parameter VAR17 = 7;
input VAR18;
input VAR9;
input [3:0] VAR14 ;
... | gpl-3.0 |
SymbiFlow/nextpnr | ice40/benchmark/picorv32.v | 92,423 | module MODULE1 #(
parameter [ 0:0] VAR1 = 1,
parameter [ 0:0] VAR69 = 1,
parameter [ 0:0] VAR16 = 1,
parameter [ 0:0] VAR74 = 1,
parameter [ 0:0] VAR20 = 0,
parameter [ 0:0] VAR90 = 1,
parameter [ 0:0] VAR38 = 0,
parameter [ 0:0] VAR60 = 0,
parameter [ 0:0] VAR18 = 0,
parameter [ 0:0] VAR79 = 0,
parameter [ 0:0] VAR57 ... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ai/sky130_fd_sc_hd__o21ai_2.v | 2,261 | module MODULE2 (
VAR1 ,
VAR9 ,
VAR8 ,
VAR3 ,
VAR5,
VAR4,
VAR7 ,
VAR6
);
output VAR1 ;
input VAR9 ;
input VAR8 ;
input VAR3 ;
input VAR5;
input VAR4;
input VAR7 ;
input VAR6 ;
VAR2 VAR10 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE2 (... | apache-2.0 |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/mi_nios/synthesis/submodules/mi_nios_pll.v | 11,149 | module MODULE1
(
VAR8,
VAR2,
VAR3,
VAR1) ;
input VAR8;
input VAR2;
input [0:0] VAR3;
output [0:0] VAR1;
tri0 VAR8;
tri1 VAR2;
reg [0:0] VAR7;
reg [0:0] VAR4;
reg [0:0] VAR10;
wire VAR5;
wire VAR6;
wire VAR9; | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/intra/intra_ctrl.v | 25,832 | module MODULE1(
clk ,
VAR6 ,
VAR39 ,
VAR32 ,
VAR31 ,
VAR21 ,
VAR17 ,
VAR43 ,
VAR5 ,
VAR7 ,
VAR8 ,
VAR15 ,
VAR13 ,
VAR35 ,
VAR42 ,
VAR22 ,
VAR25 ,
VAR24 ,
VAR29 ,
VAR30 ,
VAR2 ,
VAR4
);
localparam VAR9 = 'd00 ,
VAR33 = 'd01 ,
VAR10 = 'd02 ,
VAR41 = 'd03 ,
VAR34 = 'd04 ,
VAR16 = 'd05 ,
VAR26 = 'd06 ,
VAR28 = 'd07 ,
VAR23... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111a/sky130_fd_sc_ls__o2111a.behavioral.pp.v | 2,074 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR16 ,
VAR18 ,
VAR10 ,
VAR14 ,
VAR17,
VAR2,
VAR12 ,
VAR9
);
output VAR3 ;
input VAR11 ;
input VAR16 ;
input VAR18 ;
input VAR10 ;
input VAR14 ;
input VAR17;
input VAR2;
input VAR12 ;
input VAR9 ;
wire VAR5 ;
wire VAR1 ;
wire VAR8;
or VAR7 (VAR5 , VAR16, VAR11 );
and VAR15 (VAR1 , VAR18,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4bb/sky130_fd_sc_hd__nor4bb_4.v | 2,325 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR7 ,
VAR1 ,
VAR3 ,
VAR8,
VAR11,
VAR2 ,
VAR10
);
output VAR4 ;
input VAR9 ;
input VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR8;
input VAR11;
input VAR2 ;
input VAR10 ;
VAR6 VAR5 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR2(VAR2),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3b/sky130_fd_sc_hdll__nand3b_2.v | 2,245 | module MODULE2 (
VAR4 ,
VAR6 ,
VAR7 ,
VAR1 ,
VAR9,
VAR2,
VAR3 ,
VAR8
);
output VAR4 ;
input VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR9;
input VAR2;
input VAR3 ;
input VAR8 ;
VAR5 VAR10 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE2 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31oi/sky130_fd_sc_hdll__a31oi.behavioral.v | 1,552 | module MODULE1 (
VAR14 ,
VAR6,
VAR1,
VAR4,
VAR5
);
output VAR14 ;
input VAR6;
input VAR1;
input VAR4;
input VAR5;
supply1 VAR2;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR8 ;
wire VAR13 ;
wire VAR9;
and VAR12 (VAR13 , VAR4, VAR6, VAR1 );
nor VAR10 (VAR9, VAR5, VAR13 );
buf VAR11 (VAR14 , VAR9 );
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9434_v1_00_a/hdl/verilog/axi_ad9434_pnmon.v | 10,294 | module MODULE1 (
VAR10,
VAR14,
VAR15,
VAR6,
VAR7);
input VAR10;
input [47:0] VAR14;
output VAR15;
output VAR6;
input VAR7;
reg [47:0] VAR4 = 'd0;
reg [ 6:0] VAR5 = 'd0;
reg VAR15 = 'd0;
reg VAR6 = 'd0;
wire [47:0] VAR9;
wire VAR13;
wire VAR8;
wire VAR12;
wire [47:0] VAR3;
wire VAR2;
wire VAR16;
function [47:0] VAR11;
i... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ba/sky130_fd_sc_hs__o21ba.blackbox.v | 1,345 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR5 ,
VAR1
);
output VAR6 ;
input VAR2 ;
input VAR5 ;
input VAR1;
supply1 VAR3;
supply0 VAR4;
endmodule | apache-2.0 |
eleqian/WiDSO | CPLD/DSO_LA/src/reg_rw.v | 2,584 | module MODULE1(en, din, dout);
input en;
input [2:0] din;
output reg [7:0] dout;
always @ begin
case (addr)
3'h0: dout <= VAR4;
3'h1: dout <= VAR3;
3'h2: dout <= VAR2;
3'h3: dout <= VAR1;
3'h4: dout <= VAR6;
3'h5: dout <= VAR8;
3'h6: dout <= VAR5;
3'h7: dout <= VAR7;
default: dout <= 8'b0;
endcase
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor2/sky130_fd_sc_hd__xnor2.symbol.v | 1,301 | module MODULE1 (
input VAR3,
input VAR6,
output VAR7
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtp/sky130_fd_sc_hd__dfrtp.behavioral.v | 2,202 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR10 ,
VAR17
);
output VAR4 ;
input VAR8 ;
input VAR10 ;
input VAR17;
supply1 VAR6;
supply0 VAR12;
supply1 VAR14 ;
supply0 VAR9 ;
wire VAR5 ;
wire VAR18 ;
reg VAR11 ;
wire VAR21 ;
wire VAR15;
wire VAR20 ;
wire VAR13 ;
wire VAR16 ;
wire VAR1 ;
not VAR3 (VAR18 , VAR15 );
VAR2 VAR7 (VAR5 , ... | apache-2.0 |
mballance/oc_wb_ip | rtl/wb_uart/uart_wb.v | 11,880 | module MODULE1 #(
parameter reg VAR3=1,
parameter reg VAR26=0,
parameter reg VAR6=1) (
clk, VAR23, VAR24, VAR7, VAR19, VAR4, VAR21,
VAR29, VAR22, VAR27, VAR1, VAR5, VAR10, VAR12,
VAR25, VAR17 );
parameter int VAR13 = (VAR26==1)?8:32;
input clk;
input VAR23;
input VAR24;
input VAR7;
input VAR19;
input [3:0] VAR12;
input... | apache-2.0 |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/CPU/controlunit6.v | 7,280 | module MODULE1 (output reg VAR10, VAR16, VAR6, VAR14, VAR8, VAR21, VAR2, VAR5,VAR20,VAR1,VAR9,VAR15,VAR22,output reg[4:0] VAR19, output reg[3:0] VAR11, input VAR7, VAR13,VAR18, input [31:0] VAR3,input [3:0] VAR17);
reg [4:0] VAR4, VAR12;
always @ (negedge VAR18, posedge VAR13)
if (VAR13) begin
VAR4 <= 5'b00001;VAR21 = ... | apache-2.0 |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/verilog/start_for_Loop_lojbC.v | 3,003 | module MODULE2 (
clk,
VAR2,
VAR19,
VAR22,
VAR4);
parameter VAR13 = 32'd1;
parameter VAR18 = 32'd2;
parameter VAR7 = 32'd3;
input clk;
input [VAR13-1:0] VAR2;
input VAR19;
input [VAR18-1:0] VAR22;
output [VAR13-1:0] VAR4;
reg[VAR13-1:0] VAR10 [0:VAR7-1];
integer VAR14;
always @ (posedge clk)
begin
if (VAR19)
begin
for (... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxtp/sky130_fd_sc_ms__dfxtp.behavioral.pp.v | 1,788 | module MODULE1 (
VAR1 ,
VAR11 ,
VAR4 ,
VAR5,
VAR6,
VAR12 ,
VAR2
);
output VAR1 ;
input VAR11 ;
input VAR4 ;
input VAR5;
input VAR6;
input VAR12 ;
input VAR2 ;
wire VAR8 ;
reg VAR3 ;
wire VAR7 ;
wire VAR14;
wire VAR13 ;
VAR9 VAR10 (VAR8 , VAR7, VAR14, VAR3, VAR5, VAR6);
assign VAR13 = ( VAR5 === 1'b1 );
buf VAR15 (VAR1 ... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/example_design/rtl/traffic_gen/mcb_flow_control.v | 17,386 | module MODULE1 #
(
parameter VAR22 = 100,
parameter VAR21 = "VAR54"
)
(
input VAR37,
input [9:0] VAR52,
output reg VAR59,
input VAR62,
input [2:0] VAR31,
input [31:0] VAR33,
input [5:0] VAR39,
input VAR34,
output reg [2:0] VAR29,
output reg [31:0] VAR10,
output reg [5:0] VAR56,
output VAR15, input VAR9,
input VAR63,
ou... | lgpl-3.0 |
Elphel/x393_sata | x393/util_modules/resync_data.v | 4,081 | module MODULE1
parameter integer VAR4=16,
parameter integer VAR9=4, parameter VAR8 = 0
) (
input VAR5, input VAR13, input VAR1, input VAR10, input VAR11, input VAR6, input [VAR4-1:0] VAR14, output reg [VAR4-1:0] VAR12, output reg valid );
localparam integer VAR7=(1<<VAR9)-1;
reg [VAR4-1:0] VAR3 [0:VAR7];
reg [VAR9-1:0]... | gpl-3.0 |
efabless/openlane | designs/sha3/src/sha3.v | 25,477 | module MODULE2(
input wire clk,
input wire VAR51,
input wire VAR32,
input wire VAR33,
input wire [7 : 0] address,
input wire [31 : 0] VAR7,
output wire [31 : 0] VAR13
);
localparam VAR113 = 8'h00;
localparam VAR26 = 8'h01;
localparam VAR14 = 8'h02;
localparam VAR22 = 8'h08;
localparam VAR124 = 0;
localparam VAR62 = 1;
... | apache-2.0 |
chriswynnyk/american-put-verilog | american_put_cyclone/src/fp_sub.v | 132,950 | module MODULE1
(
VAR5,
VAR10,
VAR8,
VAR9,
VAR2,
VAR1) ;
input VAR5;
input VAR10;
input VAR8;
input [54:0] VAR9;
input [5:0] VAR2;
output [54:0] VAR1;
reg [54:0] VAR7;
wire VAR4;
wire [31:0] VAR6;
wire [384:0] VAR3;
wire [5:0] VAR11; | apache-2.0 |
hpcn-uam/hardware_packet_train | NetFPGA10G/Verilog/tx_queue.v | 6,981 | module MODULE1
parameter VAR4 = 64 )
(
input [VAR4-1:0] VAR46,
input [VAR4/8-1:0] VAR13,
input VAR70,
input VAR77,
output VAR33,
input clk,
input reset,
output [63:0] VAR72,
output reg [ 7:0] VAR9,
output reg VAR58,
input VAR26,
input VAR54,
input [63:0] VAR47
);
localparam VAR59 = 0;
localparam VAR79 = 1;
localparam V... | gpl-2.0 |
iExalt/HelloWorld | helloworld/helloworld.v | 1,679 | module MODULE1 (clk, VAR5, VAR1, VAR2, VAR3);
input clk;
input VAR2;
input VAR3;
input [3:0] VAR1;
output reg [7:0] VAR5;
reg [31:0] counter = 0;
integer VAR4 = 0;
reg [3:0] VAR6 = 0;
always @ (posedge clk)
begin
if (counter <= 25000000)
begin
counter <= counter + 1;
end
else
begin
counter <= 0;
if (~VAR2)
begin
VAR5[V... | gpl-3.0 |
cpulabs/mist1032isa | src/core/l1_instruction/l1_inst_cache_hit_counter.v | 3,280 | module MODULE1(
input wire VAR7,
input wire VAR5,
input wire VAR4,
input wire VAR8,
output wire [6:0] VAR9
);
reg [99:0] VAR3;
always@(posedge VAR7 or negedge VAR5)begin
if(!VAR5)begin
VAR3 <= 100'h0;
end
else begin
if(VAR4)begin
VAR3 <= {VAR3[98:0], VAR8};
end
end
end
reg [3:0] VAR6[0:9]; reg [5:0] VAR1[0:1]; reg [6:0... | bsd-2-clause |
dingzh/piplined-MIPS-CPU | src/LAB6/dataMemory.v | 1,963 | module MODULE1(
input VAR2,
input [31:0] address,
input [31:0] VAR1,
output wire [31:0] VAR7,
input VAR3,
input VAR5
);
wire [6:0] VAR6;
reg [31:0] VAR4 [127:0];
begin | gpl-3.0 |
merckhung/zet | cores/zet/rtl/zet_mux8_16.v | 1,281 | module MODULE1(sel, VAR5, VAR3, VAR4, VAR7, VAR1, VAR6, VAR8, VAR2, out);
input [2:0] sel;
input [15:0] VAR5, VAR3, VAR4, VAR7, VAR1, VAR6, VAR8, VAR2;
output [15:0] out;
reg [15:0] out;
always @(sel or VAR5 or VAR3 or VAR4 or VAR7 or VAR1 or VAR6 or VAR8 or VAR2)
case(sel)
3'd0: out = VAR5;
3'd1: out = VAR3;
3'd2: out... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/alt_mem_ddrx_ecc_decoder.v | 13,339 | module MODULE1 #
( parameter
VAR43 = 40,
VAR10 = 8,
VAR32 = 1,
VAR46 = 0,
VAR6 = 7,
VAR2 = 7,
VAR37 = 1
)
(
VAR3,
VAR7,
VAR4,
VAR38,
VAR13,
VAR40,
VAR21,
VAR17,
VAR36,
VAR8,
VAR41,
VAR24,
VAR5
);
localparam VAR33 = (VAR43 > 8) ? (VAR43 - VAR10) : (VAR43);
input VAR3;
input VAR7;
input [VAR6 - 1 : 0] VAR4;
input [VAR2 -... | lgpl-3.0 |
CospanDesign/sdio-device | rtl/generic/crc16_2bit.v | 2,805 | module MODULE1 #(
parameter VAR6 = 16'h1021,
parameter VAR2 = 16'h0000
)(
input clk,
input rst,
input en,
input VAR1,
input VAR7,
output reg [15:0] VAR4
);
wire VAR5;
wire VAR3;
assign VAR3 = VAR7 ^ VAR4[15];
assign VAR5 = (VAR1 ^ VAR4[14]);
always @ (posedge clk) begin
if (rst) begin
VAR4 <= 0;
end
else begin
if (en) ... | mit |
wyvernSemi/lm32fpga | HDL/rtl/Sdram_Controller/command.v | 18,178 | module MODULE1(
VAR6,
VAR10,
VAR7,
VAR5,
VAR4,
VAR55,
VAR37,
VAR49,
VAR16,
VAR24,
VAR8,
VAR3,
VAR29,
VAR39,
VAR46,
VAR48,
VAR28,
VAR27,
VAR11,
VAR13,
VAR19,
VAR54,
VAR60
);
input VAR6; input VAR10; input [VAR59-1:0] VAR7; input VAR5; input VAR4; input VAR55; input VAR37; input VAR49; input VAR16; input VAR24; input VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3b/sky130_fd_sc_ms__and3b.behavioral.pp.v | 1,961 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR10 ,
VAR6 ,
VAR14,
VAR11,
VAR15 ,
VAR1
);
output VAR5 ;
input VAR9 ;
input VAR10 ;
input VAR6 ;
input VAR14;
input VAR11;
input VAR15 ;
input VAR1 ;
wire VAR8 ;
wire VAR16 ;
wire VAR2;
not VAR4 (VAR8 , VAR9 );
and VAR7 (VAR16 , VAR6, VAR8, VAR10 );
VAR12 VAR3 (VAR2, VAR16, VAR14, VAR11... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41ai/sky130_fd_sc_hs__o41ai_4.v | 2,297 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR6 ,
VAR7 ,
VAR3 ,
VAR9 ,
VAR1,
VAR10
);
output VAR4 ;
input VAR5 ;
input VAR6 ;
input VAR7 ;
input VAR3 ;
input VAR9 ;
input VAR1;
input VAR10;
VAR8 VAR2 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR10(VAR10)
);
endmodule
module MODUL... | apache-2.0 |
cpulabs/hdl_square_root | src/square_root32.v | 8,214 | module MODULE1(
input wire VAR36,
input wire VAR15,
input wire VAR64,
output wire VAR29,
input wire [31:0] VAR45,
output wire VAR54,
input wire VAR10,
output wire [15:0] VAR3
);
localparam VAR18 = 0;
localparam VAR34 = 1;
localparam VAR41 = 0;
localparam VAR52 = 1;
localparam VAR40 = 0;
localparam VAR6 = 1;
localparam ... | gpl-3.0 |
takeshineshiro/fpga_linear_128 | LOG_Table_bb.v | 5,110 | module MODULE1 (
address,
VAR2,
VAR1);
input [12:0] address;
input VAR2;
output [7:0] VAR1;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21bai/sky130_fd_sc_hd__o21bai.behavioral.pp.v | 2,174 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR1 ,
VAR16,
VAR8,
VAR5,
VAR11 ,
VAR9
);
output VAR10 ;
input VAR7 ;
input VAR1 ;
input VAR16;
input VAR8;
input VAR5;
input VAR11 ;
input VAR9 ;
wire VAR4 ;
wire VAR17 ;
wire VAR15 ;
wire VAR2;
not VAR3 (VAR4 , VAR16 );
or VAR6 (VAR17 , VAR1, VAR7 );
nand VAR18 (VAR15 , VAR4, VAR17 );
... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_4.behavioral.v | 1,116 | module MODULE1( VAR4, VAR3 );
input VAR4;
output VAR3;
VAR5 VAR1(.VAR4(VAR4),.VAR3(VAR3));
VAR5 VAR2(.VAR4(VAR4),.VAR3(VAR3)); | apache-2.0 |
esonghori/TinyGarbled | circuit_synthesis/knns_td/first_nns_comb_td.v | 1,960 | module MODULE1
(
parameter VAR21 = 15,
parameter VAR31 = 32
)
(
VAR13,
VAR25,
VAR10
);
function integer VAR16;
input [31:0] VAR8;
reg [31:0] VAR24;
begin
VAR24 = VAR8;
for (VAR16=0; VAR24>0; VAR16=VAR16+1)
VAR24 = VAR24>>1;
end
endfunction
localparam VAR15 = VAR16(VAR21);
input [2*VAR21-1:0] VAR13;
input [2*VAR21*VAR31... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/decap/sky130_fd_sc_hs__decap.behavioral.pp.v | 1,121 | module MODULE1 (
VAR1,
VAR2
);
input VAR1;
input VAR2;
endmodule | apache-2.0 |
MForever78/CPUFly | ipcore_dir/Instruction_Memory (shunjian1128@gmail.com 2015-09-19-15-43-09).v | 3,976 | module MODULE1(
VAR28,
VAR21
);
input [13 : 0] VAR28;
output [31 : 0] VAR21;
VAR22 #(
.VAR13(14),
.VAR23("0"),
.VAR45(16384),
.VAR29("VAR19"),
.VAR26(0),
.VAR33(0),
.VAR54(0),
.VAR42(0),
.VAR25(0),
.VAR12(0),
.VAR3(0),
.VAR20(0),
.VAR27(0),
.VAR47(0),
.VAR7(0),
.VAR15(0),
.VAR32(0),
.VAR35(0),
.VAR34(1),
.VAR37(0),
.VA... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Wrap_2pi_Once.v | 2,419 | module MODULE1
(
VAR8,
VAR6
);
input signed [31:0] VAR8; output signed [31:0] VAR6;
wire signed [31:0] VAR4; wire VAR2;
wire signed [31:0] VAR3; wire VAR14;
wire signed [31:0] VAR5; wire signed [31:0] VAR13; wire signed [31:0] VAR12; wire signed [31:0] VAR1; wire signed [31:0] VAR9; wire signed [31:0] VAR11;
assign VAR... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/cal_ctl.v | 17,932 | module MODULE1(VAR5,clk,reset,VAR2);
input clk;
input reset;
input [31:0] VAR5;
output [4:0] VAR2;
reg [5:0] VAR10;
reg [5:0] VAR8;
reg VAR13;
reg VAR9;
reg [4:0] VAR12;
reg [4:0] VAR2;
reg [31:0] VAR7;
reg VAR4;
always @(posedge clk)
begin
if(reset)
VAR4 <= 1'b0;
end
else if(VAR12 >= 5'd3)
VAR4 <= 1'b1;
else
VAR4 <= 1... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbp/sky130_fd_sc_ms__dlxbp.pp.symbol.v | 1,358 | module MODULE1 (
input VAR8 ,
output VAR6 ,
output VAR1 ,
input VAR3,
input VAR4 ,
input VAR7,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
tuura/fantasi | dependencies/Altera_DE4/niosII/synthesis/submodules/system1_nios2_gen2_0_cpu_debug_slave_tck.v | 8,473 | module MODULE1 (
VAR5,
VAR21,
VAR15,
VAR10,
VAR31,
VAR28,
VAR1,
VAR26,
VAR9,
VAR38,
VAR23,
VAR32,
VAR27,
VAR11,
VAR35,
VAR22,
VAR33,
VAR24,
VAR17,
VAR20,
VAR34,
VAR25,
VAR13,
VAR3,
VAR7,
VAR40,
VAR14,
VAR29,
VAR36,
VAR37,
VAR30
)
;
output [ 1: 0] VAR14;
output VAR29;
output [ 37: 0] VAR36;
output VAR37;
output VAR30;
i... | mit |
chriz2600/DreamcastHDMI | Core/source/pll_hdmi/pll_hdmi_reconfig.v | 1,561 | module MODULE1 (
input VAR13,
input [7:0] address,
input VAR5,
input [7:0] VAR2,
input VAR12,
output VAR7,
output VAR4,
output reg VAR10
);
reg VAR5 = 0;
reg VAR6;
reg VAR11;
reg VAR9;
reg VAR3;
reg VAR8;
reg [7:0] VAR1 = 0;
assign VAR7 = VAR11;
assign VAR4 = VAR8;
always @(posedge VAR13) begin
VAR5 <= VAR5;
if (VAR5 &... | mit |
ultraembedded/riscv | top_cache_axi/src_v/icache.v | 17,087 | module MODULE1
parameter VAR95 = 0
)
(
input VAR7
,input VAR45
,input VAR31
,input VAR57
,input VAR92
,input [ 31:0] VAR75
,input VAR27
,input VAR61
,input VAR60
,input [ 1:0] VAR5
,input [ 3:0] VAR13
,input VAR29
,input VAR2
,input [ 31:0] VAR71
,input [ 1:0] VAR3
,input [ 3:0] VAR17
,input VAR98
,output VAR103
,outpu... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor3/sky130_fd_sc_hdll__xnor3_2.v | 2,200 | module MODULE1 (
VAR10 ,
VAR4 ,
VAR1 ,
VAR2 ,
VAR6,
VAR9,
VAR7 ,
VAR5
);
output VAR10 ;
input VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR6;
input VAR9;
input VAR7 ;
input VAR5 ;
VAR3 VAR8 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_1.behavioral.v | 1,802 | module MODULE1( VAR1, VAR3, VAR5, VAR2, VAR7 );
input VAR5, VAR1, VAR2, VAR7;
output VAR3;
VAR6 VAR8(.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7));
VAR6 VAR4(.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7)); | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/video_sys/submodules/video_sys_Onchip_Memory.v | 3,923 | module MODULE1 (
address,
VAR3,
VAR18,
clk,
VAR30,
reset,
write,
VAR27,
VAR6
)
;
parameter VAR19 = "../MODULE1.VAR8";
output [ 31: 0] VAR6;
input [ 11: 0] address;
input [ 3: 0] VAR3;
input VAR18;
input clk;
input VAR30;
input reset;
input write;
input [ 31: 0] VAR27;
wire [ 31: 0] VAR6;
wire VAR22;
assign VAR22 = VAR1... | gpl-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/MAC_REG_ACC.v | 1,792 | module MODULE1(
input clk,
input reset,
input VAR2,
input [31:0] VAR7,
output reg [7:0] address,
output reg write,
output reg read,
output reg [31:0] VAR9);
reg [2:0] VAR1;
reg [3:0] VAR3;
reg [1:0] VAR8;
parameter VAR4 = 2'b00,
VAR5 = 2'b01,
VAR6 = 2'b10,
VAR10 = 2'b11;
always@(posedge clk or negedge reset)
if(!reset)... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/source/pcie_7x_v1_3_pipe_drp.v | 22,851 | module MODULE1 #
(
parameter VAR117 = "1.1", parameter VAR57 = "VAR90", parameter VAR87 = "VAR66", parameter VAR46 = "VAR115", parameter VAR28 = 0, parameter VAR78 = 0, parameter VAR59 = 4'd11
)
(
input VAR68,
input VAR12,
input VAR26,
input [ 1:0] VAR70,
input VAR71,
input [15:0] VAR109,
input VAR10,
output [ 8:0] VAR... | lgpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_mem_ddrx_csr.v | 51,663 | module MODULE1 #
( parameter
VAR186 = 2,
VAR62 = 1,
VAR61 = 1,
VAR104 = 0,
VAR33 = 0,
VAR137 = 8,
VAR75 = 32,
VAR47 = 1,
VAR51 = 72,
VAR5 = 1, VAR108 = 13, VAR85 = 10, VAR57 = 3,
VAR23 = 1,
VAR133 = 1,
VAR118 = 0,
VAR126 = 4, VAR159 = 3, VAR2 = 4, VAR120 = 5, VAR64 = 4, VAR24 = 6, VAR174 = 8, VAR125 = 13, VAR3 = 4, VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221ai/sky130_fd_sc_ms__o221ai.pp.symbol.v | 1,409 | module MODULE1 (
input VAR10 ,
input VAR3 ,
input VAR5 ,
input VAR9 ,
input VAR8 ,
output VAR6 ,
input VAR1 ,
input VAR2,
input VAR7,
input VAR4
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/spu/rtl/spu_mared.v | 21,068 | module MODULE1 (
VAR71,
VAR20,
VAR98,
VAR160,
VAR155,
VAR99,
VAR90,
VAR159,
VAR125,
VAR76,
VAR113,
VAR31,
VAR123,
VAR23,
VAR119,
VAR18,
VAR116,
VAR118,
VAR57,
VAR86,
VAR122,
VAR22,
VAR78,
VAR30,
VAR79,
VAR17,
VAR15,
VAR96,
VAR121,
VAR134,
VAR1,
VAR26,
VAR3,
VAR148,
VAR27,
VAR132,
VAR29,
VAR37,
VAR133,
VAR106,
VAR128,
r... | gpl-2.0 |
shahid313/MSCourseWork | Adv ASIC Design and FPGA/Assign4/qstn1_SequenceDetection/sqncdetct.v | 1,271 | module MODULE1(input in, clk,rst,output VAR5
);
localparam VAR1=5'b00001,
VAR8=5'b00010,
VAR4=5'b00100, VAR2=5'b01000,
VAR3=5'b10000;
reg [4:0] VAR7,VAR6;
always @(posedge clk,posedge rst)
if(rst)
VAR7<=VAR1;
else
VAR7<=VAR6;
always@(*)
case(VAR7)
VAR1: if(in) VAR6=VAR8;
else VAR6=VAR1;
VAR8: if(in) VAR6=VAR8;
else VAR... | gpl-2.0 |
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