repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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|---|---|---|---|---|
zhangly/azpr_cpu | rtl/top/rtl/chip_top.v | 2,481 | module MODULE1 (
input wire VAR1, input wire VAR2
);
wire clk; wire clk; wire VAR7;
VAR5 VAR5 (
.VAR1 (VAR1), .VAR2 (VAR2),
.clk (clk), .clk (clk),
.VAR7 (VAR7) );
VAR4 VAR4 (
.clk (clk), .clk (clk), .reset (VAR7)
, .VAR6 (VAR6) , .VAR3 (VAR3) VAR8
);
endmodule | mit |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/gc_command_fifo.v | 13,468 | module MODULE1(
clk,
rst,
din,
VAR136,
VAR146,
dout,
VAR24,
VAR123,
VAR243,
VAR411
);
input clk;
input rst;
input [28 : 0] din;
input VAR136;
input VAR146;
output [28 : 0] dout;
output VAR24;
output VAR123;
output [5 : 0] VAR243;
output VAR411;
VAR71 #(
.VAR182(0),
.VAR175(0),
.VAR293(0),
.VAR138(0),
.VAR336(0),
.VAR28... | gpl-2.0 |
parallella/oh | padring/hdl/oh_padring.v | 6,520 | module MODULE1
parameter VAR78 = 8,
parameter VAR82 = 8,
parameter VAR28 = 8,
parameter VAR39 = 8,
parameter VAR23 = 1,
parameter VAR71 = 8,
parameter VAR25 = 8,
parameter VAR37 = 8,
parameter VAR10 = 8,
parameter VAR21 = 8,
parameter VAR61 = 1,
parameter VAR38 = 8,
parameter VAR59 = 8,
parameter VAR86 = 8,
parameter V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxtn/sky130_fd_sc_hd__dlxtn.pp.blackbox.v | 1,323 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR2,
VAR5 ,
VAR1 ,
VAR4 ,
VAR7
);
output VAR3 ;
input VAR6 ;
input VAR2;
input VAR5 ;
input VAR1 ;
input VAR4 ;
input VAR7 ;
endmodule | apache-2.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/6-pipe_registers/latch_ID_EX.v | 5,515 | module MODULE1
parameter VAR39=32,VAR14=5
)
(
input wire clk,
input wire reset,
inout wire VAR27,
input wire VAR26,
input wire [VAR39-1:0] VAR21,
input wire [VAR39-1:0] VAR23,
input wire [VAR39-1:0] VAR16,
input wire [VAR39-1:0] VAR44,
input wire [VAR14-1:0] VAR9, input wire [VAR14-1:0] VAR30,
input wire [VAR14-1:0] VA... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/dct_transpose_32x16.v | 1,325 | module MODULE1(
clk ,
VAR6 ,
VAR3 ,
VAR1 ,
VAR5 ,
VAR7 ,
VAR9
);
input clk;
input VAR6;
input VAR3;
input VAR1;
input [4:0] VAR5;
input [15:0] VAR7;
output [15:0] VAR9;
VAR8 #(.VAR4(16),.VAR2(5))
MODULE1(
.clk(clk),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3.blackbox.v | 1,323 | module MODULE1 (
VAR2,
VAR3
);
output VAR2;
input VAR3;
supply1 VAR5;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/dma_read_fifo_4x32.v | 2,346 | module MODULE1(
input [31:0] din, input VAR13,
input VAR10, output [31:0] dout,
input VAR6, input VAR8,
output VAR11,
output VAR5,
input reset,
input clk
);
parameter VAR2 = 2;
parameter VAR3 = 2 ** VAR2;
reg [31:0] VAR4 [VAR3 - 1 : 0];
reg [VAR2 - 1 : 0] VAR1;
reg [VAR2 - 1 : 0] VAR9;
reg [VAR2 - 1 : 0] VAR7;
reg [VAR... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_MATLAB_Function.v | 1,082 | module MODULE1
(
VAR2,
VAR3
);
input [17:0] VAR2; output [8:0] VAR3;
wire [8:0] VAR1;
assign VAR1 = VAR2[17:9];
assign VAR3 = VAR1;
endmodule | gpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_controller_phy.v | 15,224 | module MODULE1 (
VAR150,
VAR42,
VAR63,
VAR79,
VAR17,
VAR59,
VAR103,
VAR147,
VAR61,
VAR114,
VAR161,
VAR27,
VAR31,
VAR165,
VAR67,
VAR43,
VAR51,
VAR30,
VAR28,
VAR11,
VAR6,
VAR96,
VAR99,
VAR66,
VAR34,
VAR152,
VAR93,
VAR53,
VAR149,
VAR94,
VAR45,
VAR132,
VAR69,
VAR100,
VAR26,
VAR144,
VAR44,
VAR18,
VAR163,
VAR148,
VAR169,
VAR... | gpl-3.0 |
JY-Kim/CA2016 | Sources/full_adder.v | 2,241 | module MODULE1
(
input VAR9, input VAR6, input VAR4,
output wire VAR8, output wire VAR2 );
wire VAR7;
wire VAR3;
wire VAR10;
VAR5 VAR11 (
.VAR9 ( VAR9 ),
.VAR6 ( VAR6 ),
.VAR8 ( VAR7 ),
.VAR2 ( VAR3 )
);
VAR5 VAR1 (
.VAR9 ( VAR7 ),
.VAR6 ( VAR4 ),
.VAR8 ( VAR8 ),
.VAR2 ( VAR10 )
);
assign VAR2 = ( VAR3 | VAR10 );
endmo... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_credit_to_token.v | 1,874 | module MODULE1 #( parameter VAR19(VAR9 )
, parameter VAR19(VAR8 )
)
( input VAR14
, input VAR12
, input VAR6
, input VAR3
, output VAR17
);
localparam VAR7 = VAR4(VAR8);
localparam VAR15 = VAR4(VAR9);
logic [VAR7-1:0] VAR5;
logic [VAR15-1:0] VAR22,VAR11;
logic VAR21, VAR2;
VAR10 #(.VAR8(VAR8)
,.VAR20(0)
,.VAR13(VAR9)
)... | bsd-3-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_min/rtl/jbi_min_rq_rhq_ctl.v | 15,932 | module MODULE1(
VAR5, VAR82, VAR53, VAR102,
VAR50, VAR38, VAR25, VAR34, VAR81,
clk, VAR96, VAR22, VAR16, VAR44, VAR76,
VAR58, VAR18,
VAR92, VAR79, VAR74, VAR56,
VAR36, VAR23, VAR28
);
input clk;
input VAR96;
input VAR22;
input VAR16;
input VAR44;
input VAR76;
input [31:0] VAR58;
input [1:0] VAR18;
input [3:0] VAR92;
ou... | gpl-2.0 |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_GeArN8R1P5_syn.v | 8,686 | module MODULE1 ( VAR136, VAR34, VAR191, VAR170 );
input [15:0] VAR34;
input [15:0] VAR191;
output [16:0] VAR170;
input VAR136;
wire VAR37, VAR135, VAR288, VAR270, VAR137, VAR81, VAR319, VAR275, VAR333, VAR117, VAR29, VAR113, VAR214, VAR328,
VAR24, VAR158, VAR315, VAR13, VAR232, VAR73, VAR95, VAR235, VAR74, VAR307, VAR2... | apache-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/v/uart_if.v | 5,326 | module MODULE1 (
VAR30, VAR5, VAR10, VAR18, VAR19, VAR24,
VAR26, VAR13, clk, VAR7, VAR2
);
output [23:0] VAR30;
output [13:0] VAR5;
output VAR10;
output VAR18;
output VAR19;
output VAR24;
input [23:0] VAR26;
input [23:0] VAR13;
input clk;
input VAR7;
input VAR2;
reg [15:0] VAR38;
reg [23:0] VAR30;
parameter VAR28 = 0;
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4b/sky130_fd_sc_ls__or4b.functional.v | 1,402 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR9 ,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR10 ;
input VAR9 ;
input VAR1 ;
input VAR3;
wire VAR6 ;
wire VAR8;
not VAR2 (VAR6 , VAR3 );
or VAR4 (VAR8, VAR6, VAR1, VAR9, VAR10);
buf VAR7 (VAR5 , VAR8 );
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/wishbone/rtl/wb_chunk.v | 3,478 | module MODULE1
parameter VAR22 = VAR12-1,
parameter VAR5 = 8,
parameter VAR3 = VAR5-1,
parameter VAR7 = (VAR12+VAR5-1) / VAR5 - 1,
parameter VAR9 = 3,
parameter VAR4 = VAR9-1,
parameter VAR11 = 3)
(
input VAR6,
input VAR19,
input VAR15,
input VAR23,
input VAR13, output reg VAR14 = 0,
input [VAR3:0] VAR10, output [VAR3:... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4bb/sky130_fd_sc_ms__and4bb.behavioral.v | 1,512 | module MODULE1 (
VAR7 ,
VAR11,
VAR2,
VAR3 ,
VAR14
);
output VAR7 ;
input VAR11;
input VAR2;
input VAR3 ;
input VAR14 ;
supply1 VAR8;
supply0 VAR9;
supply1 VAR1 ;
supply0 VAR12 ;
wire VAR6 ;
wire VAR5;
nor VAR10 (VAR6 , VAR11, VAR2 );
and VAR13 (VAR5, VAR6, VAR3, VAR14 );
buf VAR4 (VAR7 , VAR5 );
endmodule | apache-2.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_cop.v | 13,433 | module MODULE1
(
VAR39, VAR33,
VAR57, VAR4, VAR49, VAR27,
VAR43, VAR9, VAR23, VAR12,
VAR48,
VAR58, VAR26, VAR45, VAR38,
VAR52, VAR55, VAR50, VAR18,
VAR34,
VAR8, VAR20, VAR19, VAR44,
VAR53, VAR2, VAR3, VAR25,
VAR5,
VAR51, VAR31, VAR13, VAR30,
VAR21, VAR14, VAR24, VAR15,
VAR17
);
parameter VAR41=1;
input VAR39, VAR33;
in... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinv/sky130_fd_sc_lp__clkinv.functional.v | 1,251 | module MODULE1 (
VAR5,
VAR3
);
output VAR5;
input VAR3;
wire VAR1;
not VAR4 (VAR1, VAR3 );
buf VAR2 (VAR5 , VAR1 );
endmodule | apache-2.0 |
camacazio/icestick_JSTK2_ORGB | source/Main_Control.v | 4,028 | module MODULE1(
clk,
rst,
VAR27,
VAR15,
VAR1,
VAR26,
VAR21
);
input clk; input rst;
output [4:0] VAR27;
input VAR26; output VAR15; output VAR1; output VAR21;
wire VAR20;
wire [39:0] VAR10;
wire [9:0] VAR29;
wire [9:0] VAR13;
wire [39:0] VAR2;
wire [23:0] VAR8;
VAR23 VAR3(
.VAR9(clk),
.VAR19(rst),
.VAR20(VAR20),
.VAR5(V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4b/sky130_fd_sc_ms__and4b.symbol.v | 1,323 | module MODULE1 (
input VAR6,
input VAR5 ,
input VAR3 ,
input VAR2 ,
output VAR4
);
supply1 VAR8;
supply0 VAR7;
supply1 VAR9 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4b/sky130_fd_sc_ls__or4b.symbol.v | 1,317 | module MODULE1 (
input VAR4 ,
input VAR2 ,
input VAR9 ,
input VAR7,
output VAR3
);
supply1 VAR5;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_074.v | 1,421 | module MODULE1 (
VAR3,
VAR4
);
input [31:0] VAR3;
output [31:0]
VAR4;
wire [31:0]
VAR10,
VAR5,
VAR8,
VAR1,
VAR6,
VAR2,
VAR7;
assign VAR10 = VAR3;
assign VAR7 = VAR2 - VAR8;
assign VAR2 = VAR6 << 5;
assign VAR6 = VAR1 - VAR10;
assign VAR1 = VAR8 << 3;
assign VAR8 = VAR5 - VAR10;
assign VAR5 = VAR10 << 3;
assign VAR4 = V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxtp/sky130_fd_sc_lp__sdfxtp.pp.symbol.v | 1,409 | module MODULE1 (
input VAR1 ,
output VAR3 ,
input VAR2 ,
input VAR9 ,
input VAR4 ,
input VAR5 ,
input VAR8,
input VAR6,
input VAR7
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_250/source/pcie_7x_v1_3_qpll_wrapper.v | 17,393 | module MODULE1 #
(
parameter VAR82 = "VAR63", parameter VAR65 = "VAR10", parameter VAR18 = "1.1", parameter VAR49 = "VAR79", parameter VAR4 = 0
)
(
input VAR31,
input VAR57,
output VAR71,
output VAR51,
output VAR26,
input VAR70,
input VAR30,
input VAR39,
input [ 7:0] VAR27,
input VAR16,
input [15:0] VAR43,
input VAR2,
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4/sky130_fd_sc_hs__and4.behavioral.pp.v | 1,735 | module MODULE1 (
VAR11,
VAR13,
VAR8 ,
VAR9 ,
VAR5 ,
VAR3 ,
VAR10
);
input VAR11;
input VAR13;
output VAR8 ;
input VAR9 ;
input VAR5 ;
input VAR3 ;
input VAR10 ;
wire VAR12 ;
wire VAR7;
and VAR4 (VAR12 , VAR9, VAR5, VAR3, VAR10 );
VAR1 VAR2 (VAR7, VAR12, VAR11, VAR13);
buf VAR6 (VAR8 , VAR7 );
endmodule | apache-2.0 |
minosys-jp/FPGA | Zybo/vgagraph/vgagraph/HDL/syncgen.v | 1,112 | module MODULE1 (
input VAR18,
input VAR3,
output VAR11,
output reg VAR15,
output reg VAR2,
output [9:0] VAR9,
output [9:0] VAR6
);
reg VAR1 = 1'b0;
reg VAR5 = 1'b0;
assign VAR11 = VAR5;
always @(posedge VAR18) begin
if (VAR1 == 1'b1) begin
VAR5 <= ~VAR5;
end
VAR1 <= ~VAR1;
end
reg [9:0] VAR16 = 10'h0;
reg [9:0] VAR8 = ... | bsd-2-clause |
trevortheblack/NL16-BinaryCompression | hf_decompression.v | 6,611 | module MODULE1 (
input wire VAR20,
output reg [3:0] VAR32,
output reg VAR27,
input wire VAR38,
input wire VAR35
);
reg VAR13;
reg [15:0] VAR34;
always @ (posedge VAR38 or negedge VAR35) begin
if(~VAR35) begin
VAR13 <= 1'b1;
VAR32 <= 4'b0;
VAR27 <= 1'b0;
VAR34 <= 16'b0;
end
else if(~VAR13) begin
if (VAR14 == {VAR34[14:0... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/jbi_l2_buf2.v | 2,840 | module MODULE1(
VAR15, VAR16, VAR14,
VAR1, VAR3,
VAR6, VAR12,
VAR4, VAR13,
VAR18, VAR2, VAR7, VAR11,
VAR5, VAR17, VAR9,
VAR10, VAR8
);
output [31:0] VAR15;
output [31:0] VAR16;
output [6:0] VAR14;
output VAR1;
output VAR3;
output VAR6;
output VAR12;
output VAR4;
output VAR13;
input [31:0] VAR18;
input [31:0] VAR2;
inpu... | gpl-2.0 |
bluespec/Flute | src_SSITH_P2/xilinx_ip/hdl/mkJtagTap.v | 19,418 | module MODULE1(VAR74,
VAR113,
VAR116,
VAR55,
VAR88,
VAR47,
VAR139,
VAR81,
VAR162,
VAR76,
VAR28,
VAR117,
VAR160,
VAR108,
VAR25,
VAR27,
VAR32);
input VAR74;
input VAR113;
input VAR116;
input VAR55;
input VAR88;
output VAR47;
input VAR139;
output VAR81;
output [6 : 0] VAR162;
output [31 : 0] VAR76;
output [1 : 0] VAR28;
o... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4bb/sky130_fd_sc_lp__and4bb.pp.symbol.v | 1,334 | module MODULE1 (
input VAR9 ,
input VAR8 ,
input VAR5 ,
input VAR4 ,
output VAR2 ,
input VAR3 ,
input VAR7,
input VAR6,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbn/sky130_fd_sc_lp__sdfbbn.blackbox.v | 1,528 | module MODULE1 (
VAR10 ,
VAR5 ,
VAR3 ,
VAR12 ,
VAR1 ,
VAR8 ,
VAR9 ,
VAR6
);
output VAR10 ;
output VAR5 ;
input VAR3 ;
input VAR12 ;
input VAR1 ;
input VAR8 ;
input VAR9 ;
input VAR6;
supply1 VAR2;
supply0 VAR11;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnrsnq/gf180mcu_fd_sc_mcu7t5v0__dffnrsnq_1.functional.pp.v | 1,027 | module MODULE1( VAR17, VAR1, VAR15, VAR11, VAR3, VAR18, VAR4, VAR14 );
input VAR17, VAR1, VAR11, VAR15, VAR18, VAR4, VAR14;
output VAR3;
not VAR7( VAR5, VAR17 );
not VAR10( VAR2, VAR11 );
not VAR6( VAR8, VAR15 );
not VAR13( VAR19, VAR1 );
VAR12( VAR9, VAR8, VAR2, VAR5, VAR19, VAR14 );
not VAR16( VAR3, VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111a/sky130_fd_sc_lp__o2111a.functional.pp.v | 2,074 | module MODULE1 (
VAR4 ,
VAR13 ,
VAR5 ,
VAR17 ,
VAR9 ,
VAR7 ,
VAR14,
VAR18,
VAR16 ,
VAR3
);
output VAR4 ;
input VAR13 ;
input VAR5 ;
input VAR17 ;
input VAR9 ;
input VAR7 ;
input VAR14;
input VAR18;
input VAR16 ;
input VAR3 ;
wire VAR15 ;
wire VAR2 ;
wire VAR12;
or VAR8 (VAR15 , VAR5, VAR13 );
and VAR11 (VAR2 , VAR17, V... | apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_axi_quad_spi_shield_0/system_axi_quad_spi_shield_0_stub.v | 2,667 | module MODULE1(VAR11, VAR26, VAR18,
VAR8, VAR30, VAR31, VAR7, VAR29, VAR4,
VAR14, VAR24, VAR12, VAR15, VAR19, VAR6,
VAR25, VAR22, VAR20, VAR5, VAR3, VAR9, VAR32, VAR27, VAR16,
VAR23, VAR33, VAR17, VAR21, VAR2, VAR13, VAR10, VAR28, VAR1)
;
input VAR11;
input VAR26;
input VAR18;
input [6:0]VAR8;
input VAR30;
output VAR31... | apache-2.0 |
hcabrera-/lancetfish | RTL/router/rtl/routing_algorithm/west_first_minimal.v | 12,416 | module MODULE1 #(
parameter VAR6 = VAR22,
parameter VAR4 = 2,
parameter VAR32 = 2,
parameter VAR3 = 2,
parameter VAR24 = 2
)
(
input wire VAR15,
input wire [VAR39-1:0] VAR18,
input wire [VAR39-1:0] VAR10,
output reg [3:0] VAR19
);
reg [7:0] VAR26;
wire VAR34;
wire VAR33;
assign VAR34 = (VAR18 > VAR4) ? 1'b1 : 1'b0;
ass... | gpl-3.0 |
jmahler/mips-cpu | alu.v | 1,307 | module MODULE1(
input [3:0] VAR2,
input [31:0] VAR1, VAR4,
output reg [31:0] out,
output VAR10);
wire [31:0] VAR7;
wire [31:0] VAR3;
wire VAR9;
wire VAR8;
wire VAR6;
wire VAR5;
assign VAR10 = (0 == out);
assign VAR7 = VAR1 - VAR4;
assign VAR3 = VAR1 + VAR4;
assign VAR9 = (VAR1[31] == VAR4[31] && VAR3[31] != VAR1[31]) ?... | gpl-3.0 |
miamiasheep/nctu-dlab-99 | lab4/flashLED.v | 3,626 | module MODULE1(
output reg [7:0] VAR2,
input VAR7,
input [3:0] VAR1,
input in,
input reset
);
parameter VAR10 = 24;
reg [1:0] VAR11;
reg VAR4;
reg enable, VAR13;
reg [VAR10:0] VAR6, VAR12;
wire VAR3;
reg [1:0] VAR9;
VAR5 VAR14(VAR7, reset, VAR9[1], VAR3);
always @(posedge VAR7)
begin
if (reset) begin
VAR9 <= 2'b00;
end... | gpl-3.0 |
maijohnson/comp3601_blue_15s2 | AudioController/tone.v | 1,226 | module MODULE1(VAR15, VAR1, VAR4, VAR2, VAR12);
input VAR15; input [5:0] VAR1; input VAR4; input [3:0] VAR2; output VAR12; reg [5:0] VAR11; wire [13:0] period; wire [7:0] VAR10;
reg [13:0] counter;
parameter VAR3 = 6'd48;
VAR6 VAR8 (VAR15, VAR10, VAR2, VAR12);
VAR7 VAR9 (VAR1, period);
VAR13 VAR14 (VAR11, VAR10);
param... | mit |
loonquawl/fermiac | pcm/buspcm.v | 1,258 | module MODULE1
parameter VAR3=32,
parameter VAR4=16,
parameter VAR19=1,
parameter VAR9=1,
parameter VAR1=8
)
(
input clk,
inout [VAR3-1:0] VAR11,
inout [VAR4-1:0] VAR15,
inout [VAR4-1:0] VAR14,
inout [VAR4-1:0] VAR20,
input [VAR4-1:0] VAR7
output VAR10
);
wire [VAR3-1:0] VAR16,
wire [VAR4-1:0] VAR17,
wire VAR18,
wire V... | mit |
jefg89/proyecto_final_prototipado | ProyectoFinal/HDLNeuralNetwork/EscrituraRegistroToMemoria.v | 4,559 | module MODULE1#(parameter VAR16 = 4)
(VAR18,VAR5,VAR19,VAR9,VAR4,VAR20,VAR36,VAR39,VAR15,VAR8,VAR38,
VAR2,VAR14,VAR33,VAR27,VAR17,VAR10,VAR24,VAR32,VAR13,VAR22,VAR12,VAR7,VAR34,
VAR6,VAR26,VAR3,VAR28,VAR11,VAR37,VAR35,VAR21,VAR29,VAR1,VAR31,VAR23,VAR25,VAR30);
input VAR18,VAR5,VAR9;
input [8:0] VAR19;
input signed [VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphe/sky130_fd_sc_ls__decaphe_2.v | 1,899 | module MODULE2 (
VAR4,
VAR3,
VAR1 ,
VAR6
);
input VAR4;
input VAR3;
input VAR1 ;
input VAR6 ;
VAR2 VAR5 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE2 ();
supply1 VAR4;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR6 ;
VAR2 VAR5 ();
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie_recv_fifo/pcie_recv_fifo_stub.v | 1,369 | module MODULE1(clk, VAR2, din, VAR4, VAR1, dout, VAR5, VAR3)
;
input clk;
input VAR2;
input [255:0]din;
input VAR4;
input VAR1;
output [255:0]dout;
output VAR5;
output VAR3;
endmodule | gpl-3.0 |
praveendath92/securePUF | source/Runs.v | 4,254 | module MODULE2(
input wire clk,
input wire rst,
input wire rand,
output wire VAR10
);
parameter VAR6 = 20000;
reg [14:0] VAR2, VAR1, VAR8, VAR7;
reg VAR4;
wire en;
wire VAR5, VAR9;
assign en = (VAR1 == (VAR6-1));
assign VAR10 = VAR5 & VAR9;
MODULE1 MODULE1(
.clk(clk),
.rst(rst),
.en(en),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25.functional.pp.v | 1,866 | module MODULE1 (
VAR11 ,
VAR1 ,
VAR12,
VAR7,
VAR6 ,
VAR2
);
output VAR11 ;
input VAR1 ;
input VAR12;
input VAR7;
input VAR6 ;
input VAR2 ;
wire VAR9 ;
wire VAR4;
buf VAR8 (VAR9 , VAR1 );
VAR3 VAR5 (VAR4, VAR9, VAR12, VAR7);
buf VAR10 (VAR11 , VAR4 );
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/or1200/or1200_ctrl.v | 31,479 | module MODULE1
(
clk, rst,
VAR147, VAR135, VAR24, VAR60, VAR40,
VAR20,
VAR109, VAR8, VAR128, VAR74, VAR4, VAR42, VAR15,
VAR124, VAR111, VAR12, VAR99,
VAR34, VAR27, VAR100, VAR115, VAR86, VAR43, VAR146,
VAR63, VAR55, VAR136, VAR73,
VAR123, VAR67, VAR130, VAR65, VAR105, VAR10,
VAR29, VAR6,
VAR106, VAR126, VAR21, VAR46, V... | mit |
Siliciumer/DOS-Mario-FPGA | sources/change2negedge.v | 1,335 | module MODULE1
(
input wire VAR4,
input wire VAR1,
input wire VAR5,
input wire [23:0] VAR6,
input wire clk,
input wire rst,
output reg VAR3,
output reg VAR7,
output reg VAR2,
output reg [23:0] VAR8
);
always @(negedge clk or posedge rst) begin
if(rst) begin
VAR3 <= 0;
VAR7 <= 0;
VAR2 <= 0;
VAR8 <= 0;
end
else begin
VAR... | mit |
peteasa/parallella-fpga | AdaptevaLib/elink-gold/fifo_empty_block.v | 2,674 | module MODULE1 (
VAR9, VAR6, VAR10,
reset, VAR11, VAR4, VAR1
);
parameter VAR2 = 2;
input reset;
input VAR11;
input [VAR2:0] VAR4; input VAR1;
output VAR9;
output [VAR2-1:0] VAR6;
output [VAR2:0] VAR10;
reg [VAR2:0] VAR10;
reg [VAR2:0] VAR8;
reg VAR9;
wire VAR5;
wire [VAR2:0] VAR7;
wire [VAR2:0] VAR3;
always @(posedge ... | lgpl-3.0 |
parallella/oh | common/hdl/oh_mux.v | 1,030 | module MODULE1 #( parameter VAR2 = 1, parameter VAR1 = 1 )
(
input [VAR1-1:0] sel, input [VAR1*VAR2-1:0] in, output [VAR2-1:0] out );
reg [VAR2-1:0] mux;
integer VAR3;
always @*
begin
mux[VAR2-1:0] = 'b0;
for(VAR3=0;VAR3<VAR1;VAR3=VAR3+1)
mux[VAR2-1:0] = mux[VAR2-1:0] | {(VAR2){sel[VAR3]}} & in[((VAR3+1)*VAR2-1)-:VAR2]... | mit |
aquaxis/synverll | lib/llvm_memcpy/aq_axi_master32.v | 10,309 | module MODULE1(
input VAR27,
input VAR15,
output [0:0] VAR68,
output [31:0] VAR39,
output [7:0] VAR55, output [2:0] VAR11, output [1:0] VAR3, output VAR81, output [3:0] VAR41, output [2:0] VAR2, output [3:0] VAR24, output [0:0] VAR42, output VAR77,
input VAR40,
output [63:0] VAR91,
output [7:0] VAR16,
output VAR53,
out... | mit |
gigglesninja/digital-system-design | lab2_part2/ipcore_dir/add13bit.v | 9,508 | module MODULE1 (
VAR99, VAR108, VAR59
);
output [12 : 0] VAR99;
input [12 : 0] VAR108;
input [12 : 0] VAR59;
wire \VAR20/VAR31 ;
wire \VAR20/VAR34 ;
wire \VAR20/VAR2 ;
wire \VAR20/VAR84 ;
wire \VAR20/VAR21 ;
wire \VAR20/VAR109 ;
wire \VAR20/VAR89 ;
wire \VAR20/VAR61 ;
wire \VAR20/VAR39 ;
wire \VAR20/VAR19 ;
wire \VAR20... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrbp/sky130_fd_sc_hd__dfrbp.blackbox.v | 1,378 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR5 ,
VAR3 ,
VAR2
);
output VAR9 ;
output VAR1 ;
input VAR5 ;
input VAR3 ;
input VAR2;
supply1 VAR7;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfsbp/sky130_fd_sc_ms__sdfsbp.blackbox.v | 1,455 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR2 ,
VAR11 ,
VAR5 ,
VAR3 ,
VAR9
);
output VAR8 ;
output VAR1 ;
input VAR2 ;
input VAR11 ;
input VAR5 ;
input VAR3 ;
input VAR9;
supply1 VAR6;
supply0 VAR10;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
julioamerico/OpenCRC | src/SoC/component/work/crc_ahb_ip_MSS/MSS_CCC_0/crc_ahb_ip_MSS_tmp_MSS_CCC_0_MSS_CCC.v | 2,786 | module MODULE1(
VAR5,
VAR27,
VAR62,
VAR69,
VAR42,
VAR55,
VAR31,
VAR36,
VAR7,
VAR10,
VAR38,
VAR14,
VAR24,
VAR63,
VAR3,
VAR22,
VAR35,
VAR37,
VAR44,
VAR30,
VAR54,
VAR65,
VAR61,
VAR73,
VAR4,
VAR71,
VAR46,
VAR23,
VAR57
);
input VAR5;
input VAR27;
input VAR62;
input VAR69;
input VAR42;
input VAR55;
input VAR31;
input VAR36;
... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/spree/tmp/addersub_slt.v | 1,932 | module MODULE1 (
VAR11, VAR4,
VAR2,
VAR12,
VAR3 );
parameter VAR7=32;
input [VAR7-1:0] VAR11;
input [VAR7-1:0] VAR4;
input [3-1:0] VAR2;
output [VAR7-1:0] VAR12;
output VAR3;
wire VAR6;
reg [VAR7:0] sum;
wire VAR10;
wire VAR5;
wire VAR1;
assign VAR10=VAR2[2];
assign VAR5=VAR2[1];
assign VAR1=VAR2[0];
assign VAR12=sum[V... | mit |
jotego/jt12 | hdl/jt12_sumch.v | 1,352 | module MODULE1
(
input [4:0] VAR4,
output reg [4:0] VAR2
);
parameter VAR3=6;
reg [2:0] VAR1;
always @(*) begin
VAR1 = VAR4[2:0] + 3'd1;
if( VAR3==6 ) begin
VAR2[2:0] = VAR1[1:0]==2'b11 ? VAR1+3'd1 : VAR1;
VAR2[4:3] = VAR4[2:0]==3'd6 ? VAR4[4:3]+2'd1 : VAR4[4:3]; end else begin VAR2[2:0] = VAR1[1:0]==2'b11 ? 3'd0 : VAR... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/pfpu/rtl/pfpu_sincos.v | 2,437 | module MODULE1(
input VAR7,
input VAR10,
input [31:0] VAR6,
input VAR8,
input VAR2,
output [31:0] VAR11,
output VAR14
);
reg VAR13;
reg VAR17;
reg [12:0] VAR15;
wire [12:0] VAR4 = 13'd0 - VAR6[12:0];
always @(posedge VAR7) begin
if(VAR10)
VAR13 <= 1'b0;
end
else
VAR13 <= VAR2;
VAR17 <= VAR8;
if(VAR6[31]) begin
if(~VAR8... | lgpl-3.0 |
takeshineshiro/fpga_linear_128 | DAS_RF_bb.v | 7,787 | module MODULE1 (
VAR4,
VAR3,
VAR1,
VAR6,
VAR2,
VAR5);
input VAR4;
input [15:0] VAR3;
input [13:0] VAR1;
input [13:0] VAR6;
input VAR2;
output [15:0] VAR5;
tri1 VAR2;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/inv/sky130_fd_sc_ls__inv.symbol.v | 1,238 | module MODULE1 (
input VAR5,
output VAR6
);
supply1 VAR4;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o211ai/sky130_fd_sc_hdll__o211ai.behavioral.pp.v | 2,068 | module MODULE1 (
VAR10 ,
VAR15 ,
VAR9 ,
VAR11 ,
VAR1 ,
VAR13,
VAR7,
VAR4 ,
VAR8
);
output VAR10 ;
input VAR15 ;
input VAR9 ;
input VAR11 ;
input VAR1 ;
input VAR13;
input VAR7;
input VAR4 ;
input VAR8 ;
wire VAR5 ;
wire VAR6 ;
wire VAR17;
or VAR12 (VAR5 , VAR9, VAR15 );
nand VAR16 (VAR6 , VAR1, VAR5, VAR11 );
VAR3 VAR2... | apache-2.0 |
donnaware/AGC | rtl/de0/modules/ng_CLK.v | 1,490 | module MODULE1(
input VAR9, input VAR2, input VAR10, input VAR1, input VAR3, input VAR8, output VAR6, output VAR4 );
wire VAR12 = !(!(VAR1 & VAR3) & !(!VAR3 & VAR8)); wire VAR7 = !((VAR2 | VAR10) & !(VAR10 & VAR12));
reg VAR5, VAR11;
always@(negedge VAR7 or negedge VAR9)
if(!VAR9) VAR5 <= 1'b1;
else VAR5 <= (~VAR5 & ~V... | gpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/OUTPUT_CTL.v | 7,569 | module MODULE1(
clk,
reset,
VAR16,
VAR18,
VAR1,
VAR17,
VAR10,
VAR14,
VAR22,
VAR42,
VAR33,
VAR34,
VAR37,
VAR8,
VAR3,
VAR39,
VAR26,
VAR4,
VAR27,
VAR9,
VAR31
);
input clk;
input reset;
input VAR16;
input [133:0] VAR18;
input VAR1;
input VAR17;
output wire VAR10;
output reg [133:0] VAR14;
output reg VAR22;
output reg VAR42... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41ai/sky130_fd_sc_hd__o41ai.behavioral.v | 1,571 | module MODULE1 (
VAR1 ,
VAR14,
VAR13,
VAR4,
VAR9,
VAR8
);
output VAR1 ;
input VAR14;
input VAR13;
input VAR4;
input VAR9;
input VAR8;
supply1 VAR15;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR12 ;
wire VAR6 ;
wire VAR10;
or VAR3 (VAR6 , VAR9, VAR4, VAR13, VAR14 );
nand VAR11 (VAR10, VAR8, VAR6 );
buf VAR7 (VAR1 , VAR10 );... | apache-2.0 |
AngelTerrones/ADA | rtl/ada_hazard.v | 6,171 | module MODULE1(
input [4:0] VAR3, input [4:0] VAR27, input [4:0] VAR37, input [4:0] VAR39, input [4:0] VAR17, input VAR16, input VAR10, input VAR15, input VAR2, input VAR22, input VAR20, input VAR30, input VAR31, input VAR32, input VAR12, input VAR18, output [1:0] VAR26, output [1:0] VAR5, output VAR38, output VAR33, o... | mit |
mbuesch/pyprofibus | phy_fpga/led_blink_mod.v | 1,747 | module MODULE1 #(
parameter VAR4 = 1024,
parameter VAR3 = 1024,
) (
input clk,
input VAR6,
input enable,
output reg VAR5,
);
reg [31:0] VAR2;
reg [31:0] VAR1; | gpl-2.0 |
alexforencich/xfcp | lib/eth/rtl/ptp_perout.v | 10,445 | module MODULE1 #
(
parameter VAR67 = 1,
parameter VAR66 = 48'h0,
parameter VAR52 = 30'h0,
parameter VAR58 = 16'h0000,
parameter VAR4 = 48'd1,
parameter VAR46 = 30'd0,
parameter VAR30 = 16'h0000,
parameter VAR25 = 48'h0,
parameter VAR61 = 30'd1000,
parameter VAR19 = 16'h0000
)
(
input wire clk,
input wire rst,
input wir... | mit |
anderson1008/NOCulator | hring/hw/bless/priority_comp.v | 4,872 | module MODULE2(
input VAR46 VAR12,
input VAR46 VAR5,
input VAR46 VAR17,
input VAR46 VAR45,
input [1:0] VAR39,
output [1:0] VAR41,
output [1:0] VAR35,
output [1:0] VAR23,
output [1:0] VAR10);
wire VAR46 hc00, hc01, hc10, hc11, hc20, VAR25, VAR34, VAR28, VAR30, VAR37; wire [1:0] VAR38, VAR42, VAR29, VAR3, VAR32, VAR9, VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111ai/sky130_fd_sc_ms__o2111ai.functional.pp.v | 2,086 | module MODULE1 (
VAR14 ,
VAR9 ,
VAR6 ,
VAR11 ,
VAR1 ,
VAR5 ,
VAR3,
VAR2,
VAR7 ,
VAR12
);
output VAR14 ;
input VAR9 ;
input VAR6 ;
input VAR11 ;
input VAR1 ;
input VAR5 ;
input VAR3;
input VAR2;
input VAR7 ;
input VAR12 ;
wire VAR15 ;
wire VAR10 ;
wire VAR13;
or VAR18 (VAR15 , VAR6, VAR9 );
nand VAR4 (VAR10 , VAR1, VAR1... | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/synthesis/submodules/altera_up_slow_clock_generator.v | 7,439 | module MODULE1 (
clk,
reset,
VAR1,
VAR4,
VAR8,
VAR5,
VAR3,
VAR2
);
parameter VAR7 = 10;
input clk;
input reset;
input VAR1;
output reg VAR4;
output reg VAR8;
output reg VAR5;
output reg VAR3;
output reg VAR2;
reg [VAR7:1] VAR6;
always @(posedge clk)
begin
if (reset)
VAR6 <= 'h0;
end
else if (VAR1)
VAR6 <= VAR6 + 1;
end... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a311oi/sky130_fd_sc_lp__a311oi.functional.pp.v | 2,076 | module MODULE1 (
VAR11 ,
VAR2 ,
VAR1 ,
VAR12 ,
VAR16 ,
VAR10 ,
VAR6,
VAR15,
VAR9 ,
VAR13
);
output VAR11 ;
input VAR2 ;
input VAR1 ;
input VAR12 ;
input VAR16 ;
input VAR10 ;
input VAR6;
input VAR15;
input VAR9 ;
input VAR13 ;
wire VAR3 ;
wire VAR14 ;
wire VAR7;
and VAR17 (VAR3 , VAR12, VAR2, VAR1 );
nor VAR18 (VAR14 ,... | apache-2.0 |
cybero/Verilog | src/UART + checker module/rtl/uart.v | 1,035 | module MODULE1
parameter VAR1 = 8, VAR18 = 16, VAR7 = 326 )
(
input wire clk,
input wire reset,
input wire VAR8,
input wire VAR19,
input wire [7:0] VAR15,
output wire VAR14,
output wire VAR11,
output wire VAR12,
output wire VAR9,
output wire [7:0] VAR13
);
VAR3 VAR10 (
.clk(clk),
.reset(reset),
.VAR4(VAR4)
);
VAR16 VAR... | mit |
alan4186/16bit-Processor | control_fsm.v | 15,454 | module MODULE1
(
input clk, reset, VAR40,
input [15:0] VAR33, VAR29, VAR7, VAR30, VAR12,
output reg VAR17, VAR50,
output reg [2:0] VAR39,
output reg [3:0] VAR6, VAR58, VAR49,
output [15:0] VAR48, VAR18,
output reg [15:0] VAR44, VAR5
);
parameter VAR11 = 5'd0;
parameter VAR16 = 5'd1;
parameter VAR47 = 5'd2;
parameter VA... | mit |
marmolejo/zet | cores/hpdmc_sdr16/rtl/hpdmc.v | 6,211 | module MODULE1 #(
parameter VAR47 = 1'b0,
parameter VAR65 = 23,
parameter VAR3 = 8,
parameter VAR64 = VAR65-1-1-(VAR3+2)+1
)(
input VAR55,
input VAR38,
input [2:0] VAR40,
input VAR30,
input [15:0] VAR57,
output [15:0] VAR19,
input [VAR65-1:0] VAR4,
input VAR54,
input VAR13,
output VAR14,
input [1:0] VAR10,
input [15:0]... | gpl-3.0 |
ckdur/mriscv_vivado_arty | mriscv_vivado.srcs/sources_1/new/SEGMENT_interface_AXI.v | 14,633 | module MODULE1 #
(
parameter VAR22 = 15625
)
(
input VAR20,
input VAR31,
input VAR46,
output VAR26,
input [32-1:0] VAR13,
input [3-1:0] VAR5,
input VAR47,
output VAR8,
input [32-1:0] VAR15,
input [4-1:0] VAR9,
output reg VAR1,
input VAR27,
input VAR28,
output VAR36,
input [32-1:0] VAR10,
input [3-1:0] VAR37,
output reg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311ai/sky130_fd_sc_ls__o311ai_2.v | 2,435 | module MODULE2 (
VAR11 ,
VAR12 ,
VAR7 ,
VAR1 ,
VAR5 ,
VAR10 ,
VAR3,
VAR9,
VAR8 ,
VAR4
);
output VAR11 ;
input VAR12 ;
input VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR10 ;
input VAR3;
input VAR9;
input VAR8 ;
input VAR4 ;
VAR6 VAR2 (
.VAR11(VAR11),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR10(VAR10),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211oi/sky130_fd_sc_ms__a211oi.functional.pp.v | 2,044 | module MODULE1 (
VAR14 ,
VAR10 ,
VAR13 ,
VAR11 ,
VAR2 ,
VAR7,
VAR4,
VAR12 ,
VAR5
);
output VAR14 ;
input VAR10 ;
input VAR13 ;
input VAR11 ;
input VAR2 ;
input VAR7;
input VAR4;
input VAR12 ;
input VAR5 ;
wire VAR3 ;
wire VAR15 ;
wire VAR1;
and VAR16 (VAR3 , VAR10, VAR13 );
nor VAR6 (VAR15 , VAR3, VAR11, VAR2 );
VAR8 V... | apache-2.0 |
eda-globetrotter/PicenoDecoders | final/src/prog_counter2.v | 1,339 | module MODULE1 (VAR1,rst,clk);
output [0:31] VAR1;
input clk;
input rst;
reg [0:31] VAR1;
always @(posedge clk)
begin
if(rst==1)
begin
VAR1<=32'd0;
end
else
begin
VAR1<=VAR1+32'd4;
end
end
endmodule | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/altera/ad_lvds_in.v | 3,949 | module MODULE1 (
VAR6,
VAR23,
VAR31,
VAR3,
VAR33,
VAR27,
VAR8,
VAR13,
VAR34,
VAR18,
VAR1);
parameter VAR11 = 0;
parameter VAR29 = 0;
parameter VAR5 = "VAR2";
localparam VAR19 = 0;
localparam VAR28 = 1;
input VAR6;
input VAR23;
input VAR31;
output VAR3;
output VAR33;
input VAR27;
input VAR8;
input VAR13;
input [ 4:0] VA... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_4.behavioral.pp.v | 1,311 | module MODULE1( VAR6, VAR7, VAR1, VAR8, VAR5, VAR9 );
input VAR1, VAR7, VAR6;
inout VAR5, VAR9;
output VAR8;
VAR3 VAR4(.VAR6(VAR6),.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8),.VAR5(VAR5),.VAR9(VAR9));
VAR3 VAR2(.VAR6(VAR6),.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8),.VAR5(VAR5),.VAR9(VAR9)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211a/sky130_fd_sc_lp__o211a.behavioral.pp.v | 2,036 | module MODULE1 (
VAR11 ,
VAR17 ,
VAR8 ,
VAR1 ,
VAR7 ,
VAR15,
VAR13,
VAR4 ,
VAR9
);
output VAR11 ;
input VAR17 ;
input VAR8 ;
input VAR1 ;
input VAR7 ;
input VAR15;
input VAR13;
input VAR4 ;
input VAR9 ;
wire VAR2 ;
wire VAR6 ;
wire VAR14;
or VAR16 (VAR2 , VAR8, VAR17 );
and VAR3 (VAR6 , VAR2, VAR1, VAR7 );
VAR5 VAR12 (... | apache-2.0 |
sehugg/8bitworkshop | src/worker/lib/verilog/8bitworkshop.v | 1,122 | VAR23 = 1
VAR14 = 0
VAR13 = 1
VAR9 = 8
VAR22 = 255
module MODULE1(
output reg [31:0] VAR24,
output VAR15,
output VAR3,
input clk,
input reset
);
wire [7:0] VAR6;
wire [7:0] VAR7;
wire [7:0] VAR19;
wire VAR20;
wire VAR8;
wire VAR12;
assign VAR12 = 1'b1;
wire VAR1;
VAR5 VAR17(
.VAR25(clk),
.reset(reset),
.VAR21(VAR6),
.V... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_aluadder64.v | 2,219 | module MODULE1
(
VAR3,
VAR1,
VAR6,
VAR4,
VAR2,
VAR5
);
input [63:0] VAR3; input [63:0] VAR1; input VAR6;
output [63:0] VAR4; output VAR2; output VAR5;
assign {VAR2, VAR4[31:0]} = VAR3[31:0]+VAR1[31:0]+
VAR6;
assign {VAR5, VAR4[63:32]} = VAR3[63:32]
+ VAR1[63:32] + VAR2;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18.behavioral.v | 1,405 | module MODULE1 (
VAR5,
VAR8
);
output VAR5;
input VAR8;
supply1 VAR9;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR7 ;
wire VAR1;
buf VAR3 (VAR1, VAR8 );
buf VAR6 (VAR5 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg.pp.blackbox.v | 1,608 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR2,
VAR1 ,
VAR7 ,
VAR4 ,
VAR5 ,
VAR6
);
output VAR8 ;
input VAR3 ;
input VAR2;
input VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR5 ;
input VAR6 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_jesd_align.v | 3,711 | module MODULE1 (
VAR3,
VAR4,
VAR6,
VAR8,
VAR5);
input VAR3;
input [ 3:0] VAR4;
input [31:0] VAR6;
output VAR8;
output [31:0] VAR5;
reg [31:0] VAR1 = 'd0;
reg [ 3:0] VAR7 = 'd0;
reg VAR8 = 'd0;
reg VAR2 = 'd0;
reg [31:0] VAR5 = 'd0;
always @(posedge VAR3) begin
VAR1 <= VAR6;
VAR2 <= VAR4;
if (VAR4 != 4'h0) begin
VAR7 <=... | gpl-3.0 |
Nrpickle/ECE272 | Lab3_7SegDisplayDriver/section3/section3_schematic.v | 2,785 | module MODULE1( VAR44, VAR38, VAR26, VAR74, VAR77, VAR76, VAR22, VAR36, VAR51, VAR11, VAR20,
VAR28 );
input VAR44;
input VAR38;
input VAR26;
input VAR74;
output VAR77;
output VAR76;
output VAR22;
output VAR36;
output VAR51;
output VAR11;
output VAR20;
output VAR28;
wire VAR65;
wire VAR39;
wire VAR24;
wire VAR75;
wire V... | mit |
shaform/ArkanoidOnVerilog | block_memory.v | 2,734 | module MODULE1(
input VAR15, reset, enable,
input [4:0] VAR6, VAR25, input [4:0] VAR26, VAR28, input [1:0] VAR4,
input [1:0] VAR11,
output [2:0] VAR12, VAR10,
output ready
);
localparam VAR30 = 30;
localparam VAR18 = 2'b00;
reg write;
reg [4:0] VAR7, VAR2;
wire [4:0] VAR3;
reg [1:0] state, VAR20;
reg [1:0] VAR21;
wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211oi/sky130_fd_sc_ls__a211oi.functional.v | 1,457 | module MODULE1 (
VAR4 ,
VAR5,
VAR8,
VAR3,
VAR9
);
output VAR4 ;
input VAR5;
input VAR8;
input VAR3;
input VAR9;
wire VAR1 ;
wire VAR10;
and VAR7 (VAR1 , VAR5, VAR8 );
nor VAR6 (VAR10, VAR1, VAR3, VAR9);
buf VAR2 (VAR4 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221oi/sky130_fd_sc_ls__a221oi.functional.pp.v | 2,207 | module MODULE1 (
VAR17 ,
VAR6 ,
VAR16 ,
VAR8 ,
VAR14 ,
VAR4 ,
VAR3,
VAR10,
VAR12 ,
VAR1
);
output VAR17 ;
input VAR6 ;
input VAR16 ;
input VAR8 ;
input VAR14 ;
input VAR4 ;
input VAR3;
input VAR10;
input VAR12 ;
input VAR1 ;
wire VAR15 ;
wire VAR20 ;
wire VAR2 ;
wire VAR19;
and VAR11 (VAR15 , VAR8, VAR14 );
and VAR5 (V... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4_patch20110331.v | 23,770 | module MODULE1 #
(
parameter VAR9 = 200,
parameter VAR22 = "VAR163",
parameter VAR108 = 6, parameter VAR31 = 1,
parameter VAR109 = 3,
parameter VAR29 = 2,
parameter VAR69 = 2500,
parameter VAR118 = "VAR66",
parameter VAR190 = "VAR96",
parameter VAR83 = "VAR96",
parameter VAR172 = 1,
parameter VAR142 = 3,
parameter VAR1... | lgpl-3.0 |
dingzh/piplined-MIPS-CPU | src/LAB6/Register.v | 1,210 | module MODULE1(
input VAR5,
input VAR2,
input [4:0] VAR1, input [4:0] VAR10,
input [4:0] VAR6, input [31:0] VAR11,
input reset,
output [31:0] VAR4,
output [31:0] VAR8,
output [31:0] VAR9,
output [31:0] VAR7
);
reg [31:0] VAR3[31:0];
begin
end | gpl-3.0 |
efabless/openlane | designs/aes_cipher/src/aes_key_expand_128.v | 3,913 | module MODULE1(clk, VAR7, VAR3, VAR5, VAR1, VAR8, VAR9);
input clk;
input VAR7;
input [127:0] VAR3;
output [31:0] VAR5, VAR1, VAR8, VAR9;
reg [31:0] VAR6[3:0];
wire [31:0] VAR2;
wire [31:0] VAR18;
wire [31:0] VAR16;
assign VAR5 = VAR6[0];
assign VAR1 = VAR6[1];
assign VAR8 = VAR6[2];
assign VAR9 = VAR6[3];
always @(pos... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0p/sky130_fd_sc_lp__iso0p.symbol.v | 1,299 | module MODULE1 (
input VAR6 ,
output VAR5 ,
input VAR1
);
supply1 VAR2;
supply0 VAR4 ;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrbp/sky130_fd_sc_hd__dlrbp.pp.symbol.v | 1,462 | module MODULE1 (
input VAR6 ,
output VAR1 ,
output VAR7 ,
input VAR4,
input VAR8 ,
input VAR5 ,
input VAR9 ,
input VAR2 ,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4b/sky130_fd_sc_hd__nand4b.blackbox.v | 1,326 | module MODULE1 (
VAR7 ,
VAR6,
VAR4 ,
VAR2 ,
VAR1
);
output VAR7 ;
input VAR6;
input VAR4 ;
input VAR2 ;
input VAR1 ;
supply1 VAR8;
supply0 VAR9;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dmac_v1_00_a/hdl/verilog/response_generator.v | 3,332 | module MODULE1 (
input clk,
input VAR7,
input enable,
output reg VAR5,
input [VAR2-1:0] VAR6,
output reg [VAR2-1:0] VAR3,
input VAR4,
input VAR13,
output VAR1,
input VAR12,
output VAR9,
output [1:0] VAR11
);
parameter VAR2 = 3;
assign VAR11 = VAR10;
assign VAR9 = VAR13;
assign VAR1 = VAR6 != VAR3;
always @(posedge clk)... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfsbp/sky130_fd_sc_hd__sdfsbp.symbol.v | 1,524 | module MODULE1 (
input VAR2 ,
output VAR4 ,
output VAR1 ,
input VAR11,
input VAR3 ,
input VAR8 ,
input VAR5
);
supply1 VAR10;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
freecores/zet86 | rtl-model/util/div_uu.v | 5,864 | module MODULE1(clk, VAR13, VAR2, VAR9, VAR3, VAR10, VAR12, VAR17);
parameter VAR14 = 16;
parameter VAR19 = VAR14 /2;
input clk; input VAR13;
input [VAR14 -1:0] VAR2; input [VAR19 -1:0] VAR9; output [VAR19 -1:0] VAR3; output [VAR19 -1:0] VAR10; output VAR12;
output VAR17;
reg [VAR19-1:0] VAR3;
reg [VAR19-1:0] VAR10;
reg... | gpl-3.0 |
monotone-RK/FACE | IEICE-Trans/16-way_2-tree/src/riffa/recv_credit_flow_ctrl.v | 4,918 | module MODULE1
(
input VAR4,
input VAR19,
input [2:0] VAR12, input [11:0] VAR1, input [7:0] VAR11, input VAR3, input VAR6, input VAR13, output VAR8 );
reg VAR10=0;
reg VAR16=0;
reg VAR7=0;
reg [12:0] VAR17=0;
reg [11:0] VAR9=0;
reg [7:0] VAR15=0;
reg [11:0] VAR2=0;
reg [7:0] VAR18=0;
reg VAR14; reg VAR5;
assign VAR8 = ... | mit |
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