repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_dbg/rtl/jbi_dbg_ctl_qctl.v | 6,343 | module MODULE1(
VAR15, VAR22, VAR32, VAR30, VAR26, VAR20,
clk, VAR18, VAR6, VAR9, VAR19
); input clk;
input VAR18;
input VAR6;
input VAR9;
input VAR19;
output VAR15;
output VAR22;
output VAR32;
output [VAR17:0] VAR30;
output [VAR17-1:0] VAR26;
output [VAR17-1:0] VAR20;
wire VAR15;
wire VAR22;
wire VAR32;
wire [VAR17:0]... | gpl-2.0 |
zhaishaomin/ring_network-based-multicore- | regfile_LUT_RAM.v | 2,303 | module MODULE2 (
clk,
VAR20,
VAR22,
VAR19,
VAR2,
VAR12,
VAR7,
VAR8);
parameter VAR16=31;
parameter VAR10=31;
parameter VAR5=5;
input clk;
input VAR20;
input [VAR5-1:0] VAR22;
input [VAR5-1:0] VAR19;
input [VAR5-1:0] VAR2;
input [VAR10-1:0] VAR12;
output [VAR10-1:0] VAR7;
output [VAR10-1:0] VAR8;
reg [VAR10-1:0] VAR11 [... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31a/sky130_fd_sc_ls__o31a.blackbox.v | 1,339 | module MODULE1 (
VAR8 ,
VAR9,
VAR5,
VAR2,
VAR3
);
output VAR8 ;
input VAR9;
input VAR5;
input VAR2;
input VAR3;
supply1 VAR6;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
kyzhai/NUNY | src/hardware/seven_new2.v | 6,411 | module MODULE1 (
address,
VAR28,
VAR30);
input [9:0] address;
input VAR28;
output [11:0] VAR30;
tri1 VAR28;
wire [11:0] VAR19;
wire [11:0] VAR30 = VAR19[11:0];
VAR47 VAR18 (
.VAR39 (address),
.VAR48 (VAR28),
.VAR1 (VAR19),
.VAR34 (1'b0),
.VAR5 (1'b0),
.VAR7 (1'b1),
.VAR4 (1'b0),
.VAR31 (1'b0),
.VAR8 (1'b1),
.VAR12 (1'b... | gpl-2.0 |
peteasa/parallella-fpga | AdaptevaLib/src/gpio/hdl/parallella_gpio_emio.v | 4,752 | module MODULE1
(
VAR28,
VAR31, VAR27,
VAR25, VAR29
);
parameter VAR8 = 24; parameter VAR9 = 0; parameter VAR10 = 64;
inout [VAR8-1:0] VAR31;
inout [VAR8-1:0] VAR27;
output [VAR10-1:0] VAR28;
input [VAR10-1:0] VAR25;
input [VAR10-1:0] VAR29;
genvar VAR13;
generate
if( VAR9 == 1 ) begin: VAR22
VAR30
.VAR33("VAR26"),
.VAR... | lgpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab12/lab12/Code/CPU/MCtrl.v | 5,751 | module MODULE1(input clk,
input reset,
input [31:0] VAR28,
input VAR3,
input VAR46,
input VAR42,
output reg VAR4,
output reg VAR44,
output reg[2:0]VAR39,
output [4:0]VAR34,
output reg VAR12,
output reg VAR31,
output reg VAR37,
output reg [1:0]VAR5,
output reg VAR45,
output reg [1:0]VAR23,
output reg VAR25,
output reg [... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/serialInterfaceEngine/usbTxWireArbiter.v | 7,301 | module MODULE1 (VAR17, VAR11, VAR1, VAR26, VAR29, VAR25, VAR33, VAR30, VAR24, VAR3, VAR16, VAR34, clk, VAR19, VAR12, VAR6, VAR5, VAR21, VAR8, rst);
input VAR17;
input [1:0] VAR11;
input VAR1;
input VAR29;
input VAR25;
input VAR3;
input clk;
input VAR19;
input [1:0] VAR12;
input VAR6;
input VAR21;
input VAR8;
input rst;... | gpl-3.0 |
davidkoltak/tawas-core | ip/debug_ip/rtl/debug_lsa.v | 4,242 | module MODULE1
(
input VAR29,
input VAR3,
input [9:0] VAR2,
input VAR11,
input VAR36,
input [31:0] VAR12,
output reg [31:0] VAR9,
output reg VAR33,
output reg [7:0] VAR1,
input VAR35,
input VAR13,
input [31:0] VAR32
);
parameter VAR20 = 1;
parameter VAR7 = 0;
parameter VAR16 = 8'd0;
reg [1:0] VAR28;
reg [1:0] VAR24;
re... | mit |
lvd2/ngs | fpga/dmachans/channels/chan_ctrl.v | 5,799 | module MODULE1
(
input wire clk, input wire VAR32,
output reg [ 6:0] VAR18,
input wire [31:0] VAR8,
output reg [ 6:0] VAR28,
output wire [31:0] VAR31,
output reg VAR7,
input wire VAR27,
input wire [31:0] VAR26,
output reg [ 7:0] VAR20,
output reg VAR17, output reg VAR23 );
reg [ 5:0] VAR11; wire VAR24 = VAR11[5];
reg [... | gpl-3.0 |
monotone-RK/FACE | MCSoC-15/8-way_4-parallel/ise/ipcore_dir/dram/user_design/rtl/controller/mig_7series_v1_9_bank_compare.v | 10,847 | module MODULE1 #
(parameter VAR68 = 3,
parameter VAR50 = 100,
parameter VAR9 = "8",
parameter VAR32 = 12,
parameter VAR22 = 8,
parameter VAR71 = "VAR49",
parameter VAR65 = 2,
parameter VAR44 = 4,
parameter VAR29 = 16)
(
VAR47, VAR31, VAR66, VAR14,
VAR4, VAR57, VAR17, VAR82, VAR37,
VAR5, VAR27, VAR36, VAR28, VAR77,
VAR5... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/tiel/gf180mcu_fd_sc_mcu9t5v0__tiel.behavioral.v | 1,024 | module MODULE1( VAR4 );
output VAR4;
VAR3 VAR1(.VAR4(VAR4));
VAR3 VAR2(.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21bai/sky130_fd_sc_hd__o21bai_4.v | 2,329 | module MODULE2 (
VAR5 ,
VAR8 ,
VAR10 ,
VAR4,
VAR3,
VAR9,
VAR7 ,
VAR6
);
output VAR5 ;
input VAR8 ;
input VAR10 ;
input VAR4;
input VAR3;
input VAR9;
input VAR7 ;
input VAR6 ;
VAR1 VAR2 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE2 ... | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/ad_csc_CrYCb2RGB.v | 3,509 | module MODULE1 #(
parameter VAR2 = 16) (
input clk,
input [VAR8:0] VAR17,
input [23:0] VAR1,
output [VAR8:0] VAR15,
output [23:0] VAR6);
localparam VAR8 = VAR2 - 1;
VAR12 #(.VAR2(VAR2)) VAR5 (
.clk (clk),
.sync (VAR17),
.VAR10 (VAR1),
.VAR9 (17'h01989),
.VAR11 (17'h012a1),
.VAR7 (17'h00000),
.VAR4 (25'h10deebc),
.VAR14... | mit |
Jawanga/ece385final | usb_system/synthesis/submodules/usb_system_cpu_jtag_debug_module_wrapper.v | 10,271 | module MODULE1 (
VAR21,
VAR52,
clk,
VAR38,
VAR49,
VAR34,
VAR33,
VAR60,
VAR57,
VAR20,
VAR51,
VAR45,
VAR11,
VAR4,
VAR6,
VAR14,
VAR35,
VAR7,
VAR15,
VAR12,
VAR54,
VAR8,
VAR16,
VAR9,
VAR46,
VAR22,
VAR31,
VAR32,
VAR55,
VAR48,
VAR10,
VAR40,
VAR44,
VAR24,
VAR3,
VAR36
)
;
output [ 37: 0] VAR54;
output VAR8;
output VAR16;
output... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2.functional.v | 1,344 | module MODULE1 (
VAR3,
VAR2
);
output VAR3;
input VAR2;
wire VAR4;
not VAR5 (VAR4, VAR2 );
buf VAR1 (VAR3 , VAR4 );
endmodule | apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/example_design/rtl/traffic_gen/mig_7series_v4_0_tg.v | 27,431 | module MODULE1 #(
parameter VAR60 = 32, parameter VAR3 = 32,
parameter VAR24 = 0, parameter VAR9 = 32'h0,
parameter VAR45 = 32'h000000FF,
parameter VAR52 = 0,
parameter VAR53 = 3,
parameter VAR25 = 16,
parameter VAR103 = 16,
parameter VAR33 = 40,
parameter VAR90 = 40,
parameter VAR75 = 0,
parameter VAR88 = 8'h11,
param... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221o/sky130_fd_sc_hs__a221o.functional.v | 2,091 | module MODULE1 (
VAR10,
VAR8,
VAR5 ,
VAR18 ,
VAR9 ,
VAR2 ,
VAR16 ,
VAR7
);
input VAR10;
input VAR8;
output VAR5 ;
input VAR18 ;
input VAR9 ;
input VAR2 ;
input VAR16 ;
input VAR7 ;
wire VAR16 VAR13 ;
wire VAR16 VAR11 ;
wire VAR3 ;
wire VAR14;
and VAR15 (VAR13 , VAR2, VAR16 );
and VAR17 (VAR11 , VAR18, VAR9 );
or VAR1 (... | apache-2.0 |
jobisoft/jTDC | modules/sampler/carrysampler_spartan6_20ps.v | 3,621 | module MODULE2 (VAR23, VAR35, VAR3, VAR33, VAR10);
output wire [3:0] VAR33;
output wire VAR3;
input wire VAR35;
input wire VAR10;
input wire VAR23;
wire [3:0] VAR2;
VAR5 VAR8 (
.VAR3(VAR2), .VAR27(), .VAR35(VAR35), .VAR14(VAR23), .VAR28(), .VAR12(4'b1111) );
assign VAR3 = VAR2[3];
VAR4 #(.VAR30(1'b0)) VAR24 (.VAR22(VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphetap/sky130_fd_sc_ls__decaphetap.functional.pp.v | 1,126 | module MODULE1 (
VAR1,
VAR3,
VAR2
);
input VAR1;
input VAR3;
input VAR2 ;
endmodule | apache-2.0 |
AloriumTechnology/XLR8Pong | extras/rtl/my_rand.v | 3,700 | module MODULE1(clk,
rst,
VAR1,
VAR4
);
input clk;
input rst;
input [31:0] VAR1;
output [31:0] VAR4;
reg [31:0] VAR4;
reg [31:0] VAR3;
reg [31:0] VAR7,VAR2;
reg [5:0] VAR5;
always @(posedge clk) begin
VAR5 <= {VAR5[4:0], rst};
end
wire VAR6 = | VAR5 ;
always @(posedge clk) begin
VAR3 <= VAR1;
end
always @(posedge clk) b... | lgpl-3.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/iface/ip/SGDMA_dispatcher/read_signal_breakout.v | 5,632 | module MODULE1 (
VAR10, VAR17,
VAR8,
VAR13,
VAR5,
VAR6,
VAR11,
VAR1,
VAR14,
VAR9, VAR15, VAR2, VAR16,
VAR7,
VAR3,
VAR12
);
parameter VAR4 = 256;
input [VAR4-1:0] VAR10;
output wire [255:0] VAR17;
output wire [63:0] VAR8;
output wire [31:0] VAR13;
output wire [7:0] VAR5;
output wire VAR6;
output wire VAR11;
output wire ... | mit |
MIPSfpga/schoolMIPS | board/de10_nano/de10_nano.v | 1,497 | module MODULE1
(
output VAR5,
output VAR23,
output VAR20,
input VAR33,
inout [15:0] VAR13,
inout VAR22,
input VAR24,
input VAR8,
input VAR25,
inout VAR15,
inout VAR29,
inout VAR19,
inout VAR11,
inout VAR1,
inout VAR3,
output VAR10,
output VAR16,
output [23:0] VAR28,
output VAR2,
input VAR17,
output VAR31,
input [ 1:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtn/sky130_fd_sc_lp__sdfrtn.pp.blackbox.v | 1,470 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR2 ,
VAR10 ,
VAR1 ,
VAR8,
VAR5 ,
VAR3 ,
VAR7 ,
VAR6
);
output VAR9 ;
input VAR4 ;
input VAR2 ;
input VAR10 ;
input VAR1 ;
input VAR8;
input VAR5 ;
input VAR3 ;
input VAR7 ;
input VAR6 ;
endmodule | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/SGMII_DMUX.v | 15,388 | module MODULE1(
clk,
reset,
VAR7,
VAR3,
VAR30,
VAR45,
VAR2,
VAR4,
VAR11,
VAR8,
VAR53,
VAR16,
VAR18,
VAR26,
VAR40,
VAR17,
VAR38,
VAR48,
VAR61,
VAR24,
VAR32,
VAR50,
VAR60,
VAR44,
VAR47,
VAR19,
VAR54,
VAR9,
VAR31,
VAR29,
VAR27,
VAR43,
VAR37,
VAR5,
VAR36,
VAR6,
VAR20,
VAR35,
VAR63);
input clk;
input reset;
output VAR7;
out... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_4.functional.v | 1,209 | module MODULE1( VAR3, VAR8, VAR5, VAR1 );
input VAR1, VAR3, VAR5;
output VAR8;
wire VAR10;
not VAR2( VAR10, VAR1 );
wire VAR6;
not VAR4( VAR6, VAR3 );
wire VAR9;
not VAR11( VAR9, VAR5 );
and VAR7( VAR8, VAR10, VAR6, VAR9 );
endmodule | apache-2.0 |
mithro/HDMI2USB | hdl/UART/Baud_generator.v | 2,148 | module MODULE1
parameter VAR6=1, VAR5=1 )
(
input wire clk, reset,
output wire VAR4,
output wire [VAR6-1:0] VAR1
);
reg [VAR6-1:0] VAR2;
wire [VAR6-1:0] VAR3;
always @(posedge clk)
if (reset)
VAR2 <= 0;
else
VAR2 <= VAR3;
assign VAR3 = (VAR2==(VAR5-1)) ? 0 : VAR2 + 1;
assign VAR1 = VAR2;
assign VAR4 = (VAR2==(VAR5-1)) ... | bsd-2-clause |
kammce/LPCXpresso-Nexys4-Servo-Commander | ServoCommander.srcs/sources_1/new/PWM_FPGA.v | 11,054 | module MODULE1(
input wire VAR50,
input wire rst,
input wire [1:0] VAR31,
input wire [2:0] VAR17,
input wire [9:0] VAR80,
input wire VAR92,
input wire VAR28,
input wire VAR23,
output wire [2:0] VAR36,
output wire [VAR13-1:0] VAR49,
output wire VAR34,
output wire VAR74,
output wire VAR20,
output wire [7:0] VAR104,
outpu... | bsd-3-clause |
wicker/SystemVerilog-FSM | ticket-machine/verilog/TicketMachine.v | 2,815 | module MODULE1(VAR7, VAR17, VAR6, VAR15, VAR1, VAR18, VAR10, VAR8);
input VAR7, VAR17, VAR6, VAR15;
output VAR1, VAR18, VAR10, VAR8;
reg VAR1, VAR18, VAR10, VAR8;
parameter VAR11 = 1'b1;
parameter VAR13 = 1'b0;
parameter VAR14 = 6'b000001,
VAR2 = 6'b000010,
VAR3 = 6'b000100,
VAR4 = 6'b001000,
VAR9 = 6'b010000,
VAR5 = 6... | bsd-3-clause |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/Verilog_Xilinx_Port/sources/hdl/serial.v | 3,040 | module MODULE2(clk, VAR1, VAR21, VAR10);
input clk;
input VAR1;
wire VAR18;
wire [7:0] VAR7;
VAR9 VAR6(.clk(clk), .VAR1(VAR1), .VAR18(VAR18), .VAR7(VAR7));
output [255:0] VAR21;
output [255:0] VAR10;
reg [511:0] VAR19;
reg [511:0] VAR15;
reg [6:0] VAR12 = 7'b0000000;
assign VAR21 = VAR15[511:256];
assign VAR10 = VAR15[... | gpl-3.0 |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1.v | 3,976 | module MODULE1
(
input VAR5,
output VAR3,
input reset,
output VAR4
);
VAR1 VAR2
(
.VAR5(VAR5),
.VAR3(VAR3),
.reset(reset),
.VAR4(VAR4)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4/sky130_fd_sc_ls__and4_4.v | 2,242 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR10 ,
VAR7 ,
VAR6 ,
VAR9,
VAR11,
VAR1 ,
VAR8
);
output VAR3 ;
input VAR4 ;
input VAR10 ;
input VAR7 ;
input VAR6 ;
input VAR9;
input VAR11;
input VAR1 ;
input VAR8 ;
VAR2 VAR5 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR1(VAR1),
.... | apache-2.0 |
fallen/milkymist-mmu | cores/fmlbrg/rtl/fmlbrg_datamem.v | 3,181 | module MODULE1 #(
parameter VAR31 = 11
) (
input VAR40,
input [VAR31-1:0] VAR15,
input [7:0] VAR19,
input [63:0] VAR21,
output [63:0] do,
input [VAR31-1:0] VAR32,
output [63:0] VAR9
);
reg [7:0] VAR14[0:(1 << VAR31)-1];
reg [7:0] VAR4[0:(1 << VAR31)-1];
reg [7:0] VAR23[0:(1 << VAR31)-1];
reg [7:0] VAR39[0:(1 << VAR31)-... | lgpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axi_register_slice.v | 18,652 | module MODULE1 #
(
parameter VAR118 = "VAR6",
parameter VAR1 = 0,
parameter integer VAR61 = 4,
parameter integer VAR30 = 32,
parameter integer VAR108 = 32,
parameter integer VAR150 = 0,
parameter integer VAR79 = 1,
parameter integer VAR112 = 1,
parameter integer VAR29 = 1,
parameter integer VAR25 = 1,
parameter integer... | gpl-3.0 |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodAD1_v1_0/src/PmodAD1.v | 10,158 | module MODULE1
(VAR78,
VAR168,
VAR67,
VAR159,
VAR69,
VAR76,
VAR58,
VAR157,
VAR30,
VAR141,
VAR66,
VAR80,
VAR85,
VAR8,
VAR22,
VAR64,
VAR68,
VAR1,
VAR90,
VAR126,
VAR43,
VAR35,
VAR74,
VAR158,
VAR133,
VAR31,
VAR59,
VAR120,
VAR29,
VAR113,
VAR28,
VAR38,
VAR20,
VAR48,
VAR150,
VAR125,
VAR16,
VAR169,
VAR55,
VAR86,
VAR100,
VAR9,
... | bsd-3-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/lsu/rtl/lsu_dcache_lfsr.v | 2,239 | module MODULE1 (
out,
VAR2, clk, VAR6, VAR3, VAR4, reset
);
input VAR2;
input clk, VAR6, VAR3, VAR4, reset;
output [1:0] out;
reg [4:0] VAR8;
wire [4:0] VAR7;
always @ (VAR2 or VAR7 or reset)
begin
if (reset)
VAR8 = 5'b11111;
end
else if (VAR2)
begin
VAR8[1] = VAR7[0];
VAR8[2] = VAR7[1];
VAR8[3] = VAR7[2];
VAR8[4] = VA... | gpl-2.0 |
xcthulhu/periphondemand | src/library/components/uart16550/hdl/uart_debug_if.v | 6,042 | module MODULE1 (
VAR1,
VAR5, VAR2, VAR8, VAR7, VAR14, VAR15, VAR13,
VAR12, VAR3, VAR6, VAR4, VAR9
) ;
input [VAR10-1:0] VAR5;
output [31:0] VAR1;
input [3:0] VAR2;
input [3:0] VAR8;
input [1:0] VAR7; input [4:0] VAR14;
input [7:0] VAR15;
input [7:0] VAR13;
input [7:0] VAR12;
input [VAR11-1:0] VAR3;
input [VAR11-1:0] VA... | lgpl-2.1 |
alr46664/lab4 | verilog_source/pipeline1.v | 1,117 | module MODULE1(
VAR6, VAR15, VAR16, VAR1, VAR13, VAR10 );
input VAR6, VAR15, VAR16;
input [VAR12-1:0] VAR1;
output [VAR5-1:0] VAR13;
output [VAR12-1:0] VAR10;
reg [VAR12-1:0] VAR2;
wire VAR9, VAR7;
wire [VAR5-1:0] VAR8;
VAR3 VAR11(.clk(VAR7), .VAR9(VAR9), .addr(VAR2), .VAR17(VAR8), .VAR4(VAR13));
assign VAR9 = 0;
assig... | gpl-3.0 |
HarmonInstruments/hififo | hdl/sequencer.v | 4,004 | module MODULE2
(
input VAR8,
input reset,
output VAR11,
input VAR6,
input [63:0] VAR19,
input VAR9,
output VAR2,
output [63:0] VAR18,
output reg VAR10 = 0,
output reg VAR4 = 0,
output reg [VAR22-1:0] address = 0,
output reg [VAR13-1:0] VAR5 = 0,
input [VAR13-1:0] VAR16,
input [VAR1-1:0] VAR7
);
parameter VAR12 = 2; par... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221oi/sky130_fd_sc_lp__a221oi.behavioral.v | 1,678 | module MODULE1 (
VAR11 ,
VAR6,
VAR17,
VAR13,
VAR5,
VAR2
);
output VAR11 ;
input VAR6;
input VAR17;
input VAR13;
input VAR5;
input VAR2;
supply1 VAR4;
supply0 VAR10;
supply1 VAR14 ;
supply0 VAR12 ;
wire VAR8 ;
wire VAR9 ;
wire VAR16;
and VAR3 (VAR8 , VAR13, VAR5 );
and VAR1 (VAR9 , VAR6, VAR17 );
nor VAR7 (VAR16, VAR8, ... | apache-2.0 |
sirchuckalot/zet | cores/timer/rtl/clk_gen.v | 1,348 | module MODULE1 #(
parameter VAR6 = 20, parameter VAR4 = 1 )(
input VAR1, input VAR5,
output VAR3 );
reg [VAR6-1:0] VAR2;
assign VAR3 = VAR2[VAR6-1];
always @(posedge VAR1)
VAR2 <= VAR5 ? {VAR6{1'b0}} : (VAR2 + VAR4);
endmodule | gpl-3.0 |
silverfoxy/MIPS-Verilog | Single-Cycle/reg_bank.v | 1,305 | module MODULE1(clk, VAR8, VAR5, VAR3, VAR1, wr, VAR9, din, VAR2, VAR4, VAR6); input clk;
input wr;
input [4:0] VAR8, VAR3, VAR9;
input [31:0] din;
output [31:0] VAR5, VAR1;
output [7:0] VAR4;
input [2:0] VAR2;
input VAR6;
reg [31:0] VAR7 [0:31];
always @(posedge clk or negedge VAR6)
begin
if(~VAR6)
begin
VAR7[5'b00001]... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_ddr3_odt_gen.v | 12,906 | module MODULE1
VAR36 = 2,
VAR8 = 1,
VAR44 = 4,
VAR35 = 4
)
(
VAR9,
VAR34,
VAR18,
VAR11,
VAR30,
VAR12,
VAR47,
VAR20,
VAR25,
VAR24,
VAR38
);
localparam integer VAR5 = 2**VAR44;
localparam integer VAR42 = 6; localparam integer VAR16 = 4; localparam integer VAR15 = VAR36/2;
input VAR9;
input VAR34;
input [VAR44-1:0] VAR18;... | lgpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_35.v | 26,097 | module MODULE2 (
clk,
reset,
VAR98,
VAR112,
VAR51,
VAR34,
VAR94
);
parameter VAR33 = 18;
parameter VAR66 = 35;
parameter VAR12 = 18;
localparam VAR210 = 42;
input clk;
input reset;
input VAR98;
input VAR112;
input [VAR33-1:0] VAR51; output VAR34;
output [VAR33-1:0] VAR94;
localparam VAR218 = 18; localparam VAR181 = 36;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/einvp/sky130_fd_sc_hvl__einvp_1.v | 2,138 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR4 ,
VAR6,
VAR1,
VAR9 ,
VAR2
);
output VAR8 ;
input VAR5 ;
input VAR4 ;
input VAR6;
input VAR1;
input VAR9 ;
input VAR2 ;
VAR7 VAR3 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR8 ,
VAR5 ,
VAR4
);
output VAR8... | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_fp_atan.v | 1,346 | module MODULE1(VAR5, VAR6, enable, VAR13, VAR11);
input VAR5, VAR6, enable;
input [31:0] VAR13;
output [31:0] VAR11;
VAR2 VAR9(
.VAR8(VAR5),
.reset(~VAR6),
.enable(enable),
.VAR12(VAR13[31]),
.VAR1(VAR13[30:23]),
.VAR4(VAR13[22:0]),
.VAR10(VAR11[31]),
.VAR7(VAR11[30:23]),
.VAR3(VAR11[22:0])
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111a/sky130_fd_sc_lp__o2111a.pp.blackbox.v | 1,427 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR10 ,
VAR6 ,
VAR9 ,
VAR1 ,
VAR5,
VAR4,
VAR2 ,
VAR7
);
output VAR8 ;
input VAR3 ;
input VAR10 ;
input VAR6 ;
input VAR9 ;
input VAR1 ;
input VAR5;
input VAR4;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
bigeagle/riffa | fpga/riffa_hdl/one_hot_mux.v | 4,779 | module MODULE1
parameter VAR2 = 2,
parameter VAR1 = VAR2*VAR10
)
(
input [VAR2-1:0] VAR9,
input [VAR1-1:0] VAR6,
output [VAR10-1:0] VAR8);
genvar VAR4;
wire [VAR10-1:0] VAR7[(1<<VAR2):1];
reg [VAR10-1:0] VAR5;
assign VAR8 = VAR5;
generate
for( VAR4 = 0 ; VAR4 < VAR2; VAR4 = VAR4 + 1 ) begin : VAR3
assign VAR7[(1<<VAR4)... | bsd-3-clause |
lab1-ufba/Genius | fsm.v | 27,926 | module MODULE1( VAR50, VAR49, VAR23, VAR15, VAR9, VAR73, VAR27, VAR25, VAR62, VAR76, VAR61, VAR67, VAR43, VAR16, VAR54, VAR75, VAR57, VAR17, VAR37, VAR42, VAR31, VAR34, VAR66 );
input VAR50; input VAR49; input VAR9; input VAR73; input VAR27; input VAR25; input VAR23; input [1:0] VAR57; input [6:0] VAR37; input [6:0] VA... | gpl-3.0 |
ptracton/Picoblaze | projects/timers/rtl/timers_top.v | 3,484 | module MODULE1 (
VAR17, VAR11,
VAR16, VAR18
) ;
input VAR16;
input VAR18;
output [3:0] VAR17;
output [7:0] VAR11;
wire VAR6; wire VAR14;
wire [7:0] VAR13;
wire [7:0] VAR3;
wire [7:0] VAR31;
wire [7:0] VAR7;
wire [7:0] VAR10;
wire [3:0] VAR17;
wire [7:0] VAR11;
VAR25 VAR20(
.VAR6 (VAR6),
.VAR14 (VAR14),
.VAR16 (VAR16),
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21oi/sky130_fd_sc_hs__a21oi.functional.pp.v | 1,934 | module MODULE1 (
VAR11,
VAR2,
VAR13 ,
VAR4 ,
VAR3 ,
VAR14
);
input VAR11;
input VAR2;
output VAR13 ;
input VAR4 ;
input VAR3 ;
input VAR14 ;
wire VAR10 ;
wire VAR7 ;
wire VAR6;
and VAR5 (VAR10 , VAR4, VAR3 );
nor VAR1 (VAR7 , VAR14, VAR10 );
VAR9 VAR12 (VAR6, VAR7, VAR11, VAR2);
buf VAR8 (VAR13 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311oi/sky130_fd_sc_ms__a311oi.blackbox.v | 1,396 | module MODULE1 (
VAR9 ,
VAR1,
VAR4,
VAR8,
VAR5,
VAR7
);
output VAR9 ;
input VAR1;
input VAR4;
input VAR8;
input VAR5;
input VAR7;
supply1 VAR3;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/csr_block.v | 13,500 | module MODULE1 (
clk,
reset,
VAR9,
VAR2,
VAR19,
VAR12,
VAR4,
VAR45,
VAR24,
VAR44,
VAR21,
VAR18,
VAR36,
VAR37,
VAR38,
VAR22,
VAR11,
VAR13,
VAR20,
VAR32,
VAR8,
VAR3,
VAR28,
VAR43,
VAR7,
VAR29,
VAR23,
VAR33,
VAR16,
VAR17,
VAR40,
VAR5
);
parameter VAR6 = 3;
localparam VAR27 = 3'b001;
input clk;
input reset;
input [31:0] VA... | gpl-3.0 |
olajep/oh | src/adi/hdl/library/axi_dmac/request_arb.v | 32,580 | module MODULE1 #(
parameter VAR172 = 64,
parameter VAR128 = 64,
parameter VAR220 = 24,
parameter VAR174 = VAR257(VAR128/8),
parameter VAR188 = VAR257(VAR172/8),
parameter VAR19 = 0,
parameter VAR297 = 2,
parameter VAR312 = 32,
parameter VAR63 = 1,
parameter VAR216 = 1,
parameter VAR215 = 1,
parameter VAR177 = 0,
parame... | mit |
twlostow/dsi-shield | hdl/rtl/fmlarb/fml_wb_bridge.v | 3,725 | module MODULE1
parameter VAR11 = 26
)
(
input VAR24,
input VAR21,
output reg [VAR11-1:0] VAR22,
output reg VAR3,
output reg VAR5,
input VAR23,
output reg [3:0] VAR18,
output reg [31:0] VAR26,
input [31:0] VAR12,
input [31:0] VAR4,
input [31:0] VAR20,
input [3:0] VAR9,
input VAR16,
input VAR14,
input VAR8,
output reg VA... | lgpl-3.0 |
theapi/de0-nano | pong/quadrature_decoder.v | 1,680 | module MODULE1(
VAR7,
VAR1,
VAR6,
VAR9,
VAR3,
VAR8,
VAR4
);
input VAR7, VAR1, VAR6, VAR9;
output VAR3;
output VAR8;
output [3:0] VAR4;
reg [2:0] VAR5;
reg [2:0] VAR2;
always @(posedge VAR7 or posedge VAR1) begin
if (VAR1) begin
VAR5 <= 0;
end else begin
VAR5 <= {VAR5[1:0], VAR6};
end
end
always @(posedge VAR7 or posedg... | mit |
egyp7/mor1kx | rtl/verilog/mor1kx_fetch_espresso.v | 10,050 | module MODULE1
(
VAR33, VAR15, VAR19, VAR8,
VAR2, VAR29, VAR49, VAR14,
VAR50, VAR48, VAR22,
clk, rst, VAR42, VAR28, VAR11, VAR37,
VAR26, VAR9, VAR5, VAR41,
VAR3, VAR7, VAR24,
VAR47
);
parameter VAR40 = 32;
parameter VAR13 = 5;
parameter VAR43 = {{(VAR40-13){1'b0}},
input clk, rst;
output [VAR40-1:0] VAR33;
output VAR15... | mpl-2.0 |
spacemonkeydelivers/mor1kx | rtl/verilog/mor1kx_branch_predictor_saturation_counter.v | 3,938 | module MODULE1
(
input clk,
input rst,
output VAR2,
input VAR11, input VAR10, input VAR6, input VAR13, input VAR1, input VAR9,
input VAR5, input VAR3 );
localparam [1:0]
VAR14 = 2'b00,
VAR7 = 2'b01,
VAR4 = 2'b10,
VAR12 = 2'b11;
reg [1:0] state = VAR4;
assign VAR2 = (state[1] && VAR6) || (!state[1] && VAR13);
wire VAR8 ... | mpl-2.0 |
sehugg/8bitworkshop | presets/verilog/sound_generator.v | 2,971 | module MODULE1(clk, reset, VAR12,
VAR22,VAR15, VAR6,
VAR3, VAR7, VAR9, VAR4);
input clk, reset;
output reg VAR12 = 0;
input [9:0] VAR22; input [11:0] VAR15; input [11:0] VAR6; input VAR3; input VAR7; input [2:0] VAR9; input [2:0] VAR4;
reg [3:0] VAR1; reg [17:0] VAR20; reg VAR23; reg [12:0] VAR17; reg VAR19; reg [12:0]... | gpl-3.0 |
duttondj/DigitalDesignI-P4 | project4.v | 3,142 | module MODULE1(VAR6, VAR14, VAR33, VAR17, VAR23, VAR19, VAR26, VAR21, VAR10, VAR25);
input VAR6;
input[1:0] VAR14;
input[2:0] VAR33;
output [0:6] VAR17, VAR23, VAR19, VAR26, VAR21, VAR10;
output [7:0] VAR25;
wire enable;
wire[7:0] VAR3, VAR35, VAR4;
VAR2 VAR12(.VAR34(VAR6),.reset(VAR14[0]),.VAR20(VAR14[1]),.VAR9(enable... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_p0_read_valid_selector.v | 2,287 | module MODULE1(
VAR11,
VAR19,
VAR9,
VAR22,
VAR5,
VAR18
);
parameter VAR6 = "";
localparam VAR21 = 2**VAR6;
input VAR11;
input VAR19;
input [VAR21-1:0] VAR9;
input [VAR6-1:0] VAR22;
output VAR5;
output VAR18;
wire [VAR21-1:0] VAR2;
reg [VAR21-1:0] VAR4;
reg VAR5;
reg VAR15;
reg VAR18;
wire [VAR21-1:0] VAR8;
VAR17 VAR12(... | lgpl-3.0 |
aj-michael/Digital-Systems | Lab6-Part2/ReadTempI2C.v | 1,190 | module MODULE1(VAR1,VAR8,VAR4,VAR20,VAR11,VAR13,VAR2,VAR10,VAR3,VAR9);
input [19:0] VAR1;
input [29:0] VAR8;
input [7:0] VAR4;
input VAR20;
input VAR11;
input VAR13;
output [7:0] VAR2;
output VAR10;
output VAR3;
output VAR9;
wire VAR18;
wire VAR5;
wire VAR16;
wire VAR6;
wire VAR14;
wire VAR7;
VAR19 VAR15(VAR20,VAR3,VAR... | mit |
trivoldus28/pulsarch-verilog | verif/env/cmp/multicycle_mon.v | 77,386 | module MODULE1(
clk, VAR1
);
input clk;
input VAR1;
reg enable;
VAR2 VAR4;
integer VAR3;
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
beg... | gpl-2.0 |
sergev/vak-opensource | hardware/pdp11/control.v | 58,449 | module MODULE1 (
input wire [15:0] VAR83, input wire [2:0] VAR110, output reg [2:0] VAR76, output reg [2:0] VAR111, output reg [2:0] VAR24, output reg [1:0] VAR7, output reg [9:0] VAR78, output reg [2:0] VAR146, output reg VAR184, output reg VAR203, output reg VAR80, output reg VAR22, output reg VAR137, output reg VAR9... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tap/sky130_fd_sc_lp__tap.behavioral.pp.v | 1,189 | module MODULE1 (
VAR2,
VAR4,
VAR1 ,
VAR3
);
input VAR2;
input VAR4;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_30.v | 20,605 | module MODULE1 (
clk,
reset,
VAR100,
VAR69,
VAR134,
VAR185,
VAR124
);
parameter VAR137 = 18;
parameter VAR104 = 30;
parameter VAR131 = 15;
localparam VAR142 = 31;
input clk;
input reset;
input VAR100;
input VAR69;
input [VAR137-1:0] VAR134; output VAR185;
output [VAR137-1:0] VAR124;
localparam VAR26 = 18; localparam VA... | mit |
ptracton/pmodacl2 | soc/display/display.v | 3,454 | module MODULE1 (
VAR15, VAR3,
clk, reset, VAR8, VAR9, VAR7, VAR13
) ;
input clk;
input reset;
input [3:0] VAR8;
input [3:0] VAR9;
input [3:0] VAR7;
input [3:0] VAR13;
output [3:0] VAR15;
output [7:0] VAR3;
reg [3:0] VAR15 = 4'hF;
reg [7:0] VAR3 = 8'h00;
wire VAR10;
VAR12 VAR14(
.VAR16(VAR10),
.VAR6(),
.clk(clk),
.reset... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrtp/sky130_fd_sc_ms__sdfrtp.pp.symbol.v | 1,517 | module MODULE1 (
input VAR8 ,
output VAR2 ,
input VAR5,
input VAR10 ,
input VAR4 ,
input VAR6 ,
input VAR9 ,
input VAR1 ,
input VAR7 ,
input VAR3
);
endmodule | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIFO_ADC/FIFO_ADC_bb.v | 5,432 | module MODULE1 (
VAR6,
VAR2,
VAR1,
VAR3,
VAR5,
VAR7,
VAR8,
VAR4);
input VAR6;
input [15:0] VAR2;
input VAR1;
input VAR3;
input VAR5;
output VAR7;
output VAR8;
output [15:0] VAR4;
endmodule | gpl-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_atomics.v | 10,840 | module MODULE1
(
VAR41, VAR67,
VAR40,
VAR22,
VAR66,
VAR36,
VAR26,
VAR32,
VAR48,
VAR20,
VAR19,
VAR74,
VAR62,
VAR82,
VAR14,
VAR75,
VAR5,
VAR23,
VAR39,
VAR15,
VAR1,
VAR70
);
parameter VAR29=27; parameter VAR11=256; parameter VAR34=6;
parameter VAR59=32;
parameter VAR31=32; parameter VAR16=5;
parameter VAR73=4096;
localpar... | mit |
svofski/mahponk | src/robohand.v | 1,587 | module MODULE1(reset, VAR5, VAR7, VAR8);
parameter VAR1 = 10'd0;
parameter VAR9 = 10'd0;
input reset;
input VAR5;
input [9:0] VAR7;
output reg[9:0] VAR8;
reg VAR2;
reg [9:0] VAR6;
reg [9:0] VAR11;
reg [2:0] VAR3;
always @(negedge VAR5 or posedge reset) begin
if (reset) begin
VAR8 <= VAR9/2;
end
else begin
if (VAR7 < VA... | bsd-2-clause |
lvd2/zxevo | fpga/baseconf/trunk/video/video_vga_double.v | 2,774 | module MODULE1(
input wire clk,
input wire VAR1,
input wire VAR5,
input wire [ 5:0] VAR3,
input wire VAR14,
output reg [ 5:0] VAR16
);
reg [9:0] VAR13; reg [9:0] VAR9;
reg VAR6;
reg VAR15;
wire [ 7:0] VAR4;
always @(posedge clk) if( VAR1 )
VAR6 <= ~VAR6;
always @(posedge clk)
begin
if( VAR5 )
begin
VAR13[9:8] <= 2'b00;... | gpl-3.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/PreProcessY.v | 4,082 | module MODULE1(
input [31:0] VAR11,
input [3:0] VAR48,
input [31:0] VAR20,
input [7:0] VAR36,
input VAR52,
output [31:0] VAR38,
output VAR14,
output [31:0] VAR39,
output [3:0] VAR49,
output [7:0] VAR30
);
reg [31:0] VAR28 = 32'hbf800000;
wire [31:0] VAR1;
assign VAR1 = VAR28;
wire VAR5,VAR26,VAR45,VAR50;
wire [3:0] VAR... | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd/gcd.cache/ip/2018.2/e50e3d2e678dd930/gcd_block_design_auto_pc_0_stub.v | 4,585 | module MODULE1(VAR49, VAR27, VAR44, VAR56,
VAR25, VAR38, VAR51, VAR50, VAR24, VAR17,
VAR9, VAR31, VAR13, VAR30, VAR45, VAR48, VAR52,
VAR11, VAR16, VAR32, VAR57, VAR14, VAR23, VAR29,
VAR21, VAR3, VAR58, VAR43, VAR35, VAR41,
VAR54, VAR37, VAR2, VAR53, VAR33, VAR22, VAR10,
VAR1, VAR47, VAR42, VAR7, VAR40, VAR12,
VAR59, VA... | mit |
drichmond/riffa | fpga/xilinx/zc706/riffa_wrapper_zc706.v | 38,582 | module MODULE1
parameter VAR215 = 128,
parameter VAR357 = 256,
parameter VAR59 = 5,
parameter VAR114 = "VAR139")
( input [VAR215-1:0] VAR27,
input [(VAR215/8)-1:0] VAR262,
input VAR107,
input VAR363,
output VAR130,
input [VAR287-1:0] VAR98,
output VAR54,
output VAR113,
output [VAR215-1:0] VAR19,
output [(VAR215/8)-1:0]... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_4.behavioral.pp.v | 1,561 | module MODULE1( VAR6, VAR2, VAR7, VAR3, VAR9, VAR8 );
input VAR6, VAR2, VAR3;
inout VAR9, VAR8;
output VAR7;
VAR1 VAR5(.VAR6(VAR6),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3),.VAR9(VAR9),.VAR8(VAR8));
VAR1 VAR4(.VAR6(VAR6),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3),.VAR9(VAR9),.VAR8(VAR8)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21boi/sky130_fd_sc_ms__a21boi.pp.blackbox.v | 1,401 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR8 ,
VAR7,
VAR2,
VAR1,
VAR6 ,
VAR4
);
output VAR5 ;
input VAR3 ;
input VAR8 ;
input VAR7;
input VAR2;
input VAR1;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
omicronns/studies-sys-rek | de1-soc/src/image_processor.v | 1,533 | module MODULE1 (
input [7:0] VAR13,
input [7:0] VAR23,
input [7:0] VAR4,
input VAR2,
input VAR6,
input VAR3,
input VAR12,
input VAR18,
input VAR10,
output [7:0] VAR14,
output [7:0] VAR1,
output [7:0] VAR24,
output VAR11,
output VAR21,
output VAR8,
output VAR15,
output [23:0] VAR7
);
VAR17 VAR20(
.VAR18(VAR18),
.VAR3(VA... | mit |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/soc_system_lcd_16207_0.v | 2,326 | module MODULE1 (
address,
VAR9,
clk,
read,
VAR6,
write,
VAR7,
VAR4,
VAR8,
VAR5,
VAR1,
VAR2
)
;
output VAR4;
output VAR8;
output VAR5;
inout [ 7: 0] VAR1;
output [ 7: 0] VAR2;
input [ 1: 0] address;
input VAR9;
input clk;
input read;
input VAR6;
input write;
input [ 7: 0] VAR7;
wire VAR4;
wire VAR8;
wire VAR5;
wire [ 7:... | gpl-3.0 |
aj-michael/Digital-Systems | Pong/Phase1/ipcore_dir/Clock50MHz/example_design/Clock50MHz_exdes.v | 4,762 | module MODULE1
parameter VAR12 = 100
)
( input VAR25,
input VAR21,
output [1:1] VAR15,
output VAR20
);
localparam VAR11 = 16;
wire VAR16 = VAR21;
reg VAR24;
reg VAR10;
reg VAR17;
reg VAR7;
wire VAR23;
wire VAR9;
wire clk;
reg [VAR11-1:0] counter;
VAR4 VAR3
( .VAR25 (VAR25),
.VAR26 (VAR23));
assign VAR9 = ~clk;
VAR5 VAR... | mit |
golfit/QcmMasterController | lut.v | 3,722 | module MODULE1(clk,VAR1, state);
input clk;
input [13:0] VAR1;
output reg [6:0] state;
always @(posedge clk) begin
end
if(VAR1<VAR2[0]) state=7'b1010000; else if(VAR1<VAR2[1]) state=7'b1001111;
else if(VAR1<VAR2[2]) state=7'b1001110;
else if(VAR1<VAR2[3]) state=7'b1001101;
else if(VAR1<VAR2[4]) state=7'b1001100;
else i... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrbp/sky130_fd_sc_ls__sdfrbp.pp.blackbox.v | 1,515 | module MODULE1 (
VAR2 ,
VAR10 ,
VAR4 ,
VAR5 ,
VAR3 ,
VAR9 ,
VAR7,
VAR8 ,
VAR6 ,
VAR1 ,
VAR11
);
output VAR2 ;
output VAR10 ;
input VAR4 ;
input VAR5 ;
input VAR3 ;
input VAR9 ;
input VAR7;
input VAR8 ;
input VAR6 ;
input VAR1 ;
input VAR11 ;
endmodule | apache-2.0 |
Siliciumer/DOS-Mario-FPGA | sources/board.v | 5,063 | module MODULE1 (
input wire [9:0] VAR47,
input wire VAR53,
input wire [9:0] VAR14,
input wire VAR10,
input wire VAR41,
input wire [23:0] VAR12,
input wire VAR8,
input wire clk,
input wire rst,
input wire [7:0] VAR46,
input wire [5:0] VAR51,
input wire [5:0] VAR20,
output reg [7:0] VAR15,
output reg [3:0] VAR38,
output ... | mit |
LukeBi/DotRunner | project.v | 7,990 | module MODULE4(
VAR52,
VAR33,
VAR27,
VAR4,
VAR40,
VAR5,
VAR26,
VAR11,
VAR29,
VAR2,
VAR23,
VAR50
);
input VAR52;
input [9:0] VAR27;
input [3:0] VAR33;
output VAR4;
output VAR40;
output VAR5;
output VAR26;
output VAR11;
output [9:0] VAR29;
output [9:0] VAR2;
output [9:0] VAR23;
output [9:0] VAR50;
wire [2:0] VAR56;
wire ... | gpl-3.0 |
comododragon/SHA256_FPGA | Full/Verilog/sha256_k_constants.v | 4,856 | module MODULE1(
input wire [5 : 0] addr,
output wire [31 : 0] VAR1
);
reg [31 : 0] VAR2;
assign VAR1 = VAR2;
always @*
begin : VAR3
case(addr)
00: VAR2 = 32'h428a2f98;
01: VAR2 = 32'h71374491;
02: VAR2 = 32'hb5c0fbcf;
03: VAR2 = 32'he9b5dba5;
04: VAR2 = 32'h3956c25b;
05: VAR2 = 32'h59f111f1;
06: VAR2 = 32'h923f82a4;
07... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtp/sky130_fd_sc_hs__dlrtp.behavioral.v | 2,226 | module MODULE1 (
VAR17,
VAR4 ,
VAR16 ,
VAR14 ,
VAR13 ,
VAR2
);
input VAR17;
input VAR4 ;
input VAR16 ;
output VAR14 ;
input VAR13 ;
input VAR2 ;
wire VAR18 ;
reg VAR5 ;
wire VAR19 ;
wire VAR20 ;
wire VAR11 ;
wire VAR10;
wire VAR12 ;
wire VAR8 ;
wire VAR9 ;
wire VAR7 ;
not VAR1 (VAR18 , VAR10 );
VAR15 VAR3 (VAR12 , VAR1... | apache-2.0 |
romovs/xula-lib-verilog | HostIo.v | 23,110 | module MODULE1 (VAR1, VAR55, VAR20, VAR9, VAR5, VAR29);
output VAR1;
output VAR55;
output VAR20;
output VAR9;
output VAR5;
input VAR29;
VAR54 VAR33
(
.VAR11(VAR1), .VAR38(VAR55), .VAR37(VAR20), .VAR7(VAR9), .VAR47(VAR5), .VAR26(VAR29), .VAR35(1'b0)
);
endmodule
module MODULE4 (VAR19, VAR8, VAR17, VAR46, VAR13, VAR42, V... | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_instruction_unit.v | 29,678 | module MODULE1 (
VAR142,
VAR104,
VAR33,
VAR118,
VAR1,
VAR114,
VAR130,
VAR12,
VAR87,
VAR21,
VAR45,
VAR7,
VAR38,
VAR55,
VAR63,
VAR73,
VAR97,
VAR3,
VAR46,
VAR151,
VAR153,
VAR52,
VAR8,
VAR83,
VAR123,
VAR82,
VAR127,
VAR107,
VAR131,
VAR79,
VAR64,
VAR133,
VAR39,
VAR67,
VAR75,
VAR25,
VAR16,
VAR102,
VAR14,
VAR135,
VAR11,
VAR150... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrbp/sky130_fd_sc_hs__dfrbp_2.v | 2,298 | module MODULE2 (
VAR4,
VAR3 ,
VAR2 ,
VAR9 ,
VAR8 ,
VAR6 ,
VAR7
);
input VAR4;
input VAR3 ;
input VAR2 ;
output VAR9 ;
output VAR8 ;
input VAR6 ;
input VAR7 ;
VAR5 VAR1 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR4,
VAR3 ,
VAR2 ,
VAR9 ,
VAR... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.behavioral.v | 1,116 | module MODULE1( VAR1, VAR5 );
input VAR1;
output VAR5;
VAR2 VAR4(.VAR1(VAR1),.VAR5(VAR5));
VAR2 VAR3(.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
combinatorylogic/soc | backends/small1/hw/rtl/core.v | 26,414 | module MODULE1(
input clk, input rst,
output reg [31:0] VAR19,
output reg VAR127,
input [31:0] VAR113,
input VAR162,
input [31:0] VAR111, input VAR27, input VAR4,
output VAR143, output VAR119, output [31:0] VAR107, output [31:0] VAR47,
input irq, input [3:0] VAR38, output VAR128, output VAR149,
output reg [31:0] VAR33,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_isolatchhv_pp_plg_s/sky130_fd_sc_hvl__udp_isolatchhv_pp_plg_s.blackbox.v | 1,511 | module MODULE1 (
VAR6,
VAR5 ,
VAR1 ,
VAR4 ,
VAR2 ,
VAR3
);
output VAR6;
input VAR5 ;
input VAR1 ;
input VAR4 ;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.v | 2,154 | module MODULE1 (
VAR9,
VAR4,
VAR7 ,
VAR2,
VAR8,
VAR3 ,
VAR1
);
output VAR9;
input VAR4;
input VAR7 ;
input VAR2;
input VAR8;
input VAR3 ;
input VAR1 ;
VAR6 VAR5 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR9,
VAR4,
VAR7
);
output VAR9;
inpu... | apache-2.0 |
ridecore/ridecore | src/fpga/ram_sync.v | 6,676 | module MODULE2 #(
parameter VAR6 = VAR23,
parameter VAR20 = VAR13,
parameter VAR26 = 32
)
(
input wire clk,
input wire [VAR6-1:0] VAR9,
output reg [VAR20-1:0] VAR16,
input wire [VAR6-1:0] VAR28,
input wire [VAR20-1:0] VAR18,
input wire VAR2
);
reg [VAR20-1:0] VAR15 [0:VAR26-1];
always @ (posedge clk) begin
VAR16 <= VAR... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_sideband.v | 55,641 | module MODULE1
VAR61 = 3,
VAR153 = 2, VAR124 = 1,
VAR143 = 4,
VAR114 = 1,
VAR95 = 1, VAR100 = 3,
VAR80 = 4,
VAR59 = 2,
VAR134 = 0,
VAR129 = 10,
VAR91 = 13,
VAR78 = 10,
VAR3 = 10,
VAR60 = 10,
VAR117 = 6,
VAR90 = 2, VAR156 = 16
)
(
VAR36,
VAR11,
VAR10,
VAR120,
VAR144,
VAR126,
VAR108,
VAR76,
VAR112,
VAR6,
VAR70,
VAR48,
VA... | lgpl-3.0 |
javierbrito29/papiGB | rtl/timers.v | 19,897 | module MODULE1
(
input wire VAR2,
input wire VAR71,
input wire [7:0] VAR20,
input wire VAR19,
input wire VAR52,
input wire VAR29,
input wire VAR16,
input wire [3:0] VAR91, input wire [7:0] VAR72,
output wire [7:0] VAR47, output wire [7:0] VAR25, output wire [7:0] VAR64, output wire [7:0] VAR76,
output wire VAR39
);
wir... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvp/sky130_fd_sc_hdll__einvp_4.v | 2,146 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR1 ,
VAR8,
VAR5,
VAR3 ,
VAR6
);
output VAR7 ;
input VAR4 ;
input VAR1 ;
input VAR8;
input VAR5;
input VAR3 ;
input VAR6 ;
VAR9 VAR2 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR7 ,
VAR4 ,
VAR1
);
output VAR7... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32a/sky130_fd_sc_lp__o32a_0.v | 2,428 | module MODULE2 (
VAR10 ,
VAR12 ,
VAR1 ,
VAR11 ,
VAR4 ,
VAR7 ,
VAR5,
VAR9,
VAR2 ,
VAR8
);
output VAR10 ;
input VAR12 ;
input VAR1 ;
input VAR11 ;
input VAR4 ;
input VAR7 ;
input VAR5;
input VAR9;
input VAR2 ;
input VAR8 ;
VAR3 VAR6 (
.VAR10(VAR10),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR7(VAR7),
.VA... | apache-2.0 |
gigglesninja/digital-system-design | Lab4/lab4dpath_part1.v | 1,214 | module MODULE1(VAR22,VAR16,VAR15,VAR13,clk);
input [9:0] VAR22,VAR16,VAR15;
input clk;
output [9:0] VAR13;
wire [11:0] VAR12, VAR8, VAR19, VAR9;
wire [23:0] VAR1, VAR2, VAR20;
reg [9:0] VAR3, VAR24, VAR7, VAR4, VAR5, VAR23;
always @(posedge clk) begin
VAR3 <= VAR22;
VAR24 <= VAR16;
VAR7 <= VAR15;
end
always @(posedge c... | gpl-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_AO_RVT_FF_210930.v | 231,279 | module MODULE1 (VAR9, VAR3, VAR1, VAR2, VAR10);
output VAR9;
input VAR3, VAR1, VAR2, VAR10;
wire VAR5, VAR7, VAR6;
wire VAR8, VAR4, VAR11;
not (VAR8, VAR10);
not (VAR6, VAR2);
not (VAR7, VAR1);
and (VAR4, VAR7, VAR6);
not (VAR5, VAR3);
and (VAR11, VAR5, VAR6);
or (VAR9, VAR11, VAR4, VAR8); | bsd-3-clause |
bunnie/novena-afe-hs-fpga | novena-afe-hs.srcs/sources_1/imports/imports/adc08d1020_serial.v | 1,848 | module MODULE1(
output wire VAR7, output reg VAR3,
output reg VAR19,
input wire [15:0] VAR21,
input wire [3:0] VAR26,
input wire VAR17,
output wire VAR12,
input wire VAR14
);
reg [15:0] VAR10;
reg [3:0] VAR8;
reg VAR23;
reg VAR5;
reg [5:0] VAR13;
reg [31:0] VAR20;
reg VAR18;
reg VAR2;
assign VAR12 = VAR5;
always @(pose... | apache-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.