repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
ckdur/mriscv_vivado_arty | mriscv_vivado.srcs/sources_1/new/AXI_SPI_ROM_EXT.v | 18,257 | module MODULE1 #
(
parameter VAR87 = 32,
parameter VAR94 = 3, parameter VAR14 = 15625
)
(
input VAR19, input VAR98,
input VAR70,
output VAR63,
input [32-1:0] VAR66,
input [3-1:0] VAR6,
input VAR45,
output VAR52,
input [32-1:0] VAR79,
input [4-1:0] VAR58,
output reg VAR13,
input VAR40,
input VAR74,
output VAR55,
input [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22oi/sky130_fd_sc_hvl__a22oi_1.v | 2,360 | module MODULE2 (
VAR9 ,
VAR11 ,
VAR1 ,
VAR7 ,
VAR10 ,
VAR2,
VAR4,
VAR6 ,
VAR3
);
output VAR9 ;
input VAR11 ;
input VAR1 ;
input VAR7 ;
input VAR10 ;
input VAR2;
input VAR4;
input VAR6 ;
input VAR3 ;
VAR8 VAR5 (
.VAR9(VAR9),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/edk/pcores/ccx2mb_v1_00_a/hdl/verilog/pcx2mb_link_ctr.v | 2,978 | module MODULE1 (
VAR9,
VAR10,
VAR3,
VAR5,
VAR6,
VAR4,
VAR7
);
output VAR9;
input VAR10;
input VAR3;
input VAR5;
input VAR6;
input VAR4;
input VAR7;
reg [1:0] VAR2;
wire VAR9;
wire VAR1;
wire VAR8;
assign VAR1 = VAR5 || (VAR6 && VAR4);
assign VAR8 = VAR7;
always @(posedge VAR10) begin
if (!VAR3) begin
VAR2 <= 2'b00;
end... | gpl-2.0 |
azonenberg/antikernel-ipcores | noc/rpcv3/RPCv3RouterReceiver.v | 7,142 | module MODULE1
parameter VAR4 = 32,
parameter VAR11 = 16
)
(
input wire clk,
input wire VAR1,
input wire[VAR11-1:0] VAR17,
output wire VAR6,
input wire VAR14,
output wire VAR8,
output wire VAR12,
output wire[VAR4-1:0] VAR5,
output wire VAR3
);
localparam VAR2 = (VAR11 < VAR4);
localparam VAR13 = (VAR11 > VAR4);
localpa... | bsd-3-clause |
peteasa/parallella-fpga | ohLocal/memory/dv/fifo_async_104x32.v | 1,502 | module MODULE1
(
VAR13, VAR12, dout, VAR1, valid,
rst, VAR8, VAR4, VAR3, din, VAR11
);
parameter VAR6 = 104; parameter VAR14 = 16;
input VAR5; input VAR10; input VAR8; input VAR4;
input VAR3;
input [VAR6-1:0] din;
output VAR13;
output VAR12;
output VAR7;
input VAR11;
output [VAR6-1:0] dout;
output VAR1;
output valid;
i... | lgpl-3.0 |
gbraad/minimig-de1 | rtl/audio/I2C_AV_Config.v | 4,490 | module MODULE1 ( VAR11,
VAR16,
VAR9,
VAR29
);
input VAR11;
input VAR16;
output VAR9;
inout VAR29;
reg [15:0] VAR6;
reg [23:0] VAR30;
reg VAR32;
reg VAR10;
wire VAR23;
wire VAR26;
reg [15:0] VAR22;
reg [3:0] VAR12;
reg [1:0] VAR36;
parameter VAR37 = 24000000; parameter VAR3 = 20000; parameter VAR25 = 11;
parameter VAR13... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.v | 2,358 | module MODULE2 (
VAR5 ,
VAR6,
VAR1 ,
VAR8 ,
VAR2 ,
VAR4 ,
VAR9 ,
VAR3
);
output VAR5 ;
input VAR6;
input VAR1 ;
input VAR8 ;
input VAR2 ;
input VAR4 ;
input VAR9 ;
input VAR3 ;
VAR10 VAR7 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
module MODULE2... | apache-2.0 |
fbalakirev/red-pitaya-notes | projects/red_pitaya_0_92/red_pitaya_ams.v | 12,356 | module MODULE1
(
input VAR61 , input VAR74 , input [ 5-1: 0] VAR46 , input [ 5-1: 0] VAR83 ,
output [ 24-1: 0] VAR89 , output [ 24-1: 0] VAR44 , output [ 24-1: 0] VAR109 , output [ 24-1: 0] VAR3 ,
input VAR81 , input VAR117 , input [ 32-1: 0] VAR68 , input [ 32-1: 0] VAR25 , input [ 4-1: 0] VAR95 , input VAR29 , input ... | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/V2NFC100DDR_v1_0_0/81152d2e/src/NPhy_Toggle_Physical_Output_DDR100.v | 19,052 | module MODULE1
(
parameter VAR3 = 4
)
(
VAR32 ,
VAR36 ,
VAR41 ,
VAR34 ,
VAR69 ,
VAR8 ,
VAR38 ,
VAR53 ,
VAR26 ,
VAR13 ,
VAR6 ,
VAR22 ,
VAR16 ,
VAR81 ,
VAR71 ,
VAR58 ,
VAR18 ,
VAR50 ,
VAR47 ,
VAR42 ,
VAR33
);
input VAR32 ;
input VAR36 ;
input VAR41 ;
input VAR34 ;
input VAR69 ;
input [7:0] VAR8 ; input [31:0] VAR38 ; inp... | gpl-3.0 |
sh-chris110/chris | FPGA/chris.convolution.ok/Qsys/chris_slave.v | 5,898 | module MODULE1 (
input wire [3:0] VAR25, input wire VAR33, output wire [31:0] VAR26, input wire VAR38, input wire [31:0] VAR6, output wire VAR13, input wire VAR23, input wire VAR11, output wire VAR22 );
reg [31:0] VAR42;
assign VAR26 = VAR42;
reg VAR1;
reg VAR20;
reg [31:0] VAR17[8:0];
reg VAR8;
reg [31:0] VAR5;
reg [3... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31a/sky130_fd_sc_lp__o31a.pp.symbol.v | 1,351 | module MODULE1 (
input VAR2 ,
input VAR4 ,
input VAR8 ,
input VAR7 ,
output VAR5 ,
input VAR3 ,
input VAR1,
input VAR9,
input VAR6
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_20.behavioral.v | 1,113 | module MODULE1( VAR3, VAR4 );
input VAR3;
output VAR4;
VAR1 VAR2(.VAR3(VAR3),.VAR4(VAR4));
VAR1 VAR5(.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3/sky130_fd_sc_hdll__nor3.pp.symbol.v | 1,322 | module MODULE1 (
input VAR4 ,
input VAR3 ,
input VAR6 ,
output VAR7 ,
input VAR5 ,
input VAR1,
input VAR8,
input VAR2
);
endmodule | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | core/core_id.v | 15,218 | module MODULE1( clk,
rst,
VAR43,
VAR42,
VAR78,
VAR24,
VAR30,
VAR48,
VAR99,
VAR16,
VAR96,
VAR90,
VAR32,
VAR25,
VAR71,
VAR89,
VAR15,
VAR61,
VAR94,
VAR6,
VAR5,
VAR76,
VAR8,
VAR73,
VAR70,
VAR87,
VAR82,
VAR28,
VAR64,
VAR55,
VAR31,
VAR33,
VAR91,
VAR104,
VAR98,
VAR14,
VAR32,
VAR84,
VAR29,
VAR38,
VAR105,
VAR3,
VAR52,
VAR47,
VA... | apache-2.0 |
catompiler/fpgalibs | uart/uart.v | 18,668 | module MODULE2 #(parameter VAR14=16)
(input wire clk, input wire rst, input wire VAR13,
input wire[VAR14-1:0] VAR25, output wire out);
VAR10 #(VAR14) VAR20(.clk(clk), .rst(rst), .VAR13(VAR13),
.VAR24(VAR25), .out(), .VAR23(out));
endmodule
module MODULE1 (input wire clk, input wire rst, input wire VAR13, input wire VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4bb/sky130_fd_sc_hdll__and4bb.pp.symbol.v | 1,342 | module MODULE1 (
input VAR9 ,
input VAR8 ,
input VAR4 ,
input VAR2 ,
output VAR7 ,
input VAR1 ,
input VAR5,
input VAR3,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinv/sky130_fd_sc_lp__clkinv_16.v | 2,042 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR7,
VAR8,
VAR4 ,
VAR3
);
output VAR1 ;
input VAR2 ;
input VAR7;
input VAR8;
input VAR4 ;
input VAR3 ;
VAR6 VAR5 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
supply1 VAR7;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4b/sky130_fd_sc_ls__nand4b.pp.blackbox.v | 1,347 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR9 ,
VAR6 ,
VAR7 ,
VAR4,
VAR3,
VAR2 ,
VAR8
);
output VAR1 ;
input VAR5 ;
input VAR9 ;
input VAR6 ;
input VAR7 ;
input VAR4;
input VAR3;
input VAR2 ;
input VAR8 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/Mibench/firmware/outputs/localram.v | 52,818 | module MODULE1(clk, addr, VAR40, VAR80, VAR32, en, reset);
input clk;
input [13:2] addr;
input [31:0] VAR40;
output [31:0] VAR80;
input [3:0] VAR32;
input en;
input reset;
VAR39 VAR42(
.VAR5 (VAR80[3:0]),
.VAR53 (addr[13:2]),
.VAR57 (clk),
.VAR25 (VAR40[3:0]),
.VAR22 (en),
.VAR11 (reset),
.VAR18 (VAR32[0])
);
... | mit |
javierbrito29/papiGB | rtl/sound_controller_modules/SoundControllerChannel1.v | 5,582 | module MODULE1 (
input wire VAR23, input wire VAR33,
input wire VAR18, input wire VAR5, input wire VAR12, input wire VAR20,
input wire [7:0] VAR27,
input wire [7:0] VAR24,
input wire [7:0] VAR3,
input wire [7:0] VAR21,
input wire [7:0] VAR11,
output reg [4:0] VAR4,
output wire VAR7
);
reg [2:0] VAR19;
reg VAR13;
reg [2... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3b/sky130_fd_sc_lp__nor3b.pp.symbol.v | 1,341 | module MODULE1 (
input VAR8 ,
input VAR1 ,
input VAR5 ,
output VAR4 ,
input VAR2 ,
input VAR3,
input VAR7,
input VAR6
);
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/ddc_chain.v | 6,872 | module MODULE1
parameter VAR90 = 0,
parameter VAR53 = 0,
parameter VAR116 = 24
)
(input clk, input rst, input VAR64,
input VAR17, input [7:0] VAR11, input [31:0] VAR85,
input VAR100, input [7:0] VAR124, input [31:0] VAR86,
input [VAR116-1:0] VAR43,
input [VAR116-1:0] VAR29,
output [31:0] VAR46,
input VAR72,
output VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111a/sky130_fd_sc_ls__o2111a.symbol.v | 1,393 | module MODULE1 (
input VAR5,
input VAR1,
input VAR3,
input VAR2,
input VAR9,
output VAR10
);
supply1 VAR6;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4.behavioral.pp.v | 9,064 | module MODULE1( VAR61, VAR37, VAR91, VAR6, VAR13, VAR42, VAR40 );
input VAR61, VAR37, VAR6, VAR91;
inout VAR42, VAR40;
output VAR13;
reg VAR44;
VAR86 VAR58(.VAR61(VAR61),.VAR37(VAR37),.VAR91(VAR91),.VAR6(VAR6),.VAR13(VAR13),.VAR42(VAR42),.VAR40(VAR40),.VAR44(VAR44));
VAR86 VAR49(.VAR61(VAR61),.VAR37(VAR37),.VAR91(VAR91... | apache-2.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | generador_figuras_v2.v | 2,713 | module MODULE1
(
input wire VAR12,input wire [9:0] VAR25, VAR22,output wire VAR20,
output reg [7:0] VAR3 );
localparam VAR7 = 640;
localparam VAR21 = 480;
localparam VAR17 = 160; localparam VAR9 = 479; localparam VAR24 = 64;localparam VAR18 = 255;
localparam VAR15 = 48;localparam VAR19 = 303;localparam VAR8 = 352;local... | mit |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_04_a/hdl/verilog/user_logic.v | 27,355 | /* VAR79 VAR106:
module MODULE1
(
VAR100,
VAR5,
VAR61,
VAR2,
VAR98,
VAR88,
VAR140,
VAR119,
VAR10,
VAR104,
VAR127,
VAR141,
VAR60,
VAR77,
VAR35,
VAR128,
VAR152,
VAR69,
VAR149,
VAR90,
VAR22,
VAR16,
VAR48,
VAR54,
VAR148,
VAR28,
VAR42,
VAR57,
VAR58,
VAR31,
VAR84,
VAR45,
VAR64,
VAR87,
VAR124,
VAR89,
VAR36,
VAR86,
VAR151,
VAR... | bsd-2-clause |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/phy/mig_7series_v4_0_poc_top.v | 16,253 | module MODULE1 #
(parameter VAR48 = 2,
parameter VAR15 = 10,
parameter VAR57 = 95,
parameter VAR35 = "VAR11",
parameter VAR29 = 100,
parameter VAR31 = 0,
parameter VAR63 = 0,
parameter VAR47 = 8,
parameter VAR12 = 128,
parameter VAR68 = 7,
parameter VAR6 =112)
(
VAR41, VAR33, VAR20, VAR56, VAR40,
VAR38, VAR53, VAR17,
V... | mit |
KorotkiyEugene/LAG_sv_syn_quartus | LAG_tree_arbiter.v | 2,841 | module MODULE1 (request, VAR1, VAR10, clk, VAR4);
parameter VAR17=0;
parameter VAR6=20;
parameter VAR14=4;
parameter VAR15=VAR6/VAR14;
input [VAR6-1:0] request;
output [VAR6-1:0] VAR1;
input VAR10;
input clk, VAR4;
logic [VAR6-1:0] VAR18;
logic [VAR15-1:0] VAR3, VAR16;
logic [VAR15-1:0] VAR5, VAR13;
logic [VAR15-1:0] V... | gpl-2.0 |
sittner/lcnc-mdsio | vhdl/source/can/can_top.v | 24,494 | module MODULE1
(
VAR87,
VAR24,
VAR21,
VAR94,
VAR10,
VAR60,
VAR41,
VAR112,
VAR76,
VAR50,
VAR98,
VAR88,
VAR52,
VAR12,
VAR46,
VAR47,
VAR100,
VAR27,
VAR49,
VAR51,
VAR83
,
VAR38, VAR33, VAR9 VAR79
);
parameter VAR78 = 1;
input VAR87;
input VAR24;
input [7:0] VAR21;
output [7:0] VAR94;
input VAR10;
input VAR60;
input VAR41;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32o/sky130_fd_sc_hdll__a32o_4.v | 2,485 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR1 ,
VAR3 ,
VAR10 ,
VAR11 ,
VAR8,
VAR12,
VAR5 ,
VAR6
);
output VAR2 ;
input VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR10 ;
input VAR11 ;
input VAR8;
input VAR12;
input VAR5 ;
input VAR6 ;
VAR9 VAR7 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR8... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decap/sky130_fd_sc_lp__decap_6.v | 1,870 | module MODULE2 (
VAR6,
VAR5,
VAR1 ,
VAR3
);
input VAR6;
input VAR5;
input VAR1 ;
input VAR3 ;
VAR4 VAR2 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE2 ();
supply1 VAR6;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR3 ;
VAR4 VAR2 ();
endmodule | apache-2.0 |
camacazio/icestick_JSTK2_ORGB | source/PmodOLED_Source/SpiCtrl_OLED.v | 4,805 | module MODULE1(
VAR10,
VAR6,
VAR1,
VAR11,
VAR8,
VAR21,
VAR9,
VAR18
);
input VAR10;
input VAR6;
input VAR1;
input [7:0] VAR11;
output VAR8;
output VAR21;
output VAR9;
output VAR18;
wire VAR8, VAR21, VAR9, VAR18;
reg [7:0] VAR14 = 8'h00; reg [3:0] VAR5 = 4'h0; wire VAR15; reg [1:0] counter = 2'b00; reg VAR13 = 1'b1;
reg ... | gpl-3.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/proyecto-final/clock_divider.v | 1,032 | module MODULE1(input VAR1, input reset, input[5:0] counter, output reg VAR3);
reg[5:0] VAR2;
begin
begin
begin
end
begin | mit |
kyzhai/NUNY | src/hardware/stage2.v | 6,366 | module MODULE1 (
address,
VAR53,
VAR39);
input [11:0] address;
input VAR53;
output [11:0] VAR39;
tri1 VAR53;
wire [11:0] VAR44;
wire [11:0] VAR39 = VAR44[11:0];
VAR41 VAR47 (
.VAR26 (address),
.VAR4 (VAR53),
.VAR16 (VAR44),
.VAR25 (1'b0),
.VAR9 (1'b0),
.VAR11 (1'b1),
.VAR5 (1'b0),
.VAR10 (1'b0),
.VAR15 (1'b1),
.VAR13 (... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21a/sky130_fd_sc_ms__o21a.pp.symbol.v | 1,344 | module MODULE1 (
input VAR8 ,
input VAR3 ,
input VAR2 ,
output VAR4 ,
input VAR7 ,
input VAR1,
input VAR6,
input VAR5
);
endmodule | apache-2.0 |
Marcoslz22/Tercer_Proyecto | Decodificador_2.v | 1,749 | module MODULE1(
input [3:0] VAR1,
output reg [7:0] VAR2
);
always @(*)
begin
case (VAR1)
4'h0: begin
VAR2 <= 8'b00000011;
end
4'h1: begin
VAR2 <= 8'b10011111;
end
4'h2: begin
VAR2 <= 8'b00100101;
end
4'h3: begin
VAR2 <= 8'b00001101;
end
4'h4: begin
VAR2 <= 8'b10011001;
end
4'h5: begin
VAR2 <= 8'b01001001;
end
4'h6: beg... | mit |
kevintownsend/R3 | verilog/spoonPacketDecoder.v | 4,833 | module MODULE1(
input reset,
input clk,
input [63:0] VAR1,
input VAR15,
input VAR6,
output [63:0] VAR8,
output [31:0] VAR27,
output [31:0] VAR3,
output VAR11,
output VAR21);
reg [255:0] buffer;
reg [5:0] VAR7, VAR14;
reg [5:0] VAR13;
reg [63:0] VAR24;
reg [31:0] VAR29, VAR16;
reg VAR26;
reg [4:0] VAR33;
reg [2:0] VAR9;... | mit |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/vcr_ovc_ctrl.v | 6,375 | module MODULE1
(clk, reset, VAR3, VAR30, VAR37, VAR20, VAR32, VAR5,
VAR26, VAR35, VAR33, VAR28, VAR12, VAR10, VAR19,
VAR1, VAR17);
parameter VAR38 = 4;
parameter VAR2 = 5;
parameter VAR13 = 1;
parameter VAR22 = VAR34;
parameter VAR11 = VAR24;
input clk;
input reset;
input VAR3;
input VAR30;
input [0:VAR2-1] VAR37;
inpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2/sky130_fd_sc_hd__mux2_1.v | 2,187 | module MODULE2 (
VAR4 ,
VAR8 ,
VAR3 ,
VAR9 ,
VAR6,
VAR5,
VAR1 ,
VAR2
);
output VAR4 ;
input VAR8 ;
input VAR3 ;
input VAR9 ;
input VAR6;
input VAR5;
input VAR1 ;
input VAR2 ;
VAR10 VAR7 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 (... | apache-2.0 |
eda-globetrotter/PicenoDecoders | extra_credit/spare/build1/encoder.v | 1,236 | module MODULE1 (VAR1,VAR3);
output reg [14:0] VAR3;
input [10:0] VAR1;
reg [3:0] VAR2;
always @(*)
begin
VAR2[0]=VAR1[0]^VAR1[1]^VAR1[3]^VAR1[4]^VAR1[6]^VAR1[8]^VAR1[10];
VAR2[1]=((VAR1[0]^VAR1[2])^(VAR1[3]^VAR1[5]))^((VAR1[6]^VAR1[9])^VAR1[10]);
VAR2[2]=((VAR1[1]^VAR1[2])^(VAR1[3]^VAR1[7]))^((VAR1[8]^VAR1[9])^VAR1[10]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fill/sky130_fd_sc_lp__fill.behavioral.pp.v | 1,147 | module MODULE1 (
VAR2,
VAR1,
VAR4 ,
VAR3
);
input VAR2;
input VAR1;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
Gifts/descrypt-ztex-bruteforcer | user_cores/io/src/comparer.v | 1,383 | module MODULE1 #(parameter VAR6=63)(
input [VAR6:0] VAR3,
input VAR7,
input reset,
output [VAR6:0] VAR2,
output VAR4
);
reg [VAR6:0] VAR5;
reg VAR1;
always @(posedge VAR7)
begin
if (reset == 1)
begin
VAR5 <= 64'b0;
VAR1 <= 1;
end
else
begin
VAR5 <= VAR3;
VAR1 <= 1;
end
else
VAR1 <= 0;
end
end
assign VAR2 = VAR5;
assi... | gpl-3.0 |
peteasa/oh | src/mio/hdl/mrx_io.v | 3,388 | module MODULE1 (
VAR24, VAR14,
VAR11, VAR20, VAR12, VAR3, VAR2, VAR9, VAR19
);
parameter VAR17 = 16;
input VAR11; input VAR20; input VAR12; input VAR3; input VAR2;
input [VAR17-1:0] VAR9; input VAR19;
output VAR24; output [2*VAR17-1:0] VAR14;
reg VAR24;
wire [2*VAR17-1:0] VAR16;
reg [2*VAR17-1:0] VAR13;
reg VAR23;
wire... | mit |
MeshSr/onetswitch45 | ons45-app52-ref_ofshw/vivado/onets_7045_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/output_port_lookup_reg_master.v | 21,948 | module MODULE1#
(
parameter VAR7=64,
parameter VAR15=16,
parameter VAR13=VAR16(VAR15),
parameter VAR55=2,
parameter VAR19=0
)
(
input [31:0] VAR11,
input [31:0] VAR48,
input VAR45,
input VAR46,
output reg VAR37,
output reg[31:0] VAR10,
output reg VAR43,
output reg VAR23,
output reg [VAR2-1:0]VAR18,
output reg [319:0]VA... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31ai/sky130_fd_sc_lp__o31ai.behavioral.pp.v | 2,027 | module MODULE1 (
VAR6 ,
VAR16 ,
VAR11 ,
VAR9 ,
VAR3 ,
VAR14,
VAR8,
VAR7 ,
VAR1
);
output VAR6 ;
input VAR16 ;
input VAR11 ;
input VAR9 ;
input VAR3 ;
input VAR14;
input VAR8;
input VAR7 ;
input VAR1 ;
wire VAR2 ;
wire VAR17 ;
wire VAR15;
or VAR10 (VAR2 , VAR11, VAR16, VAR9 );
nand VAR13 (VAR17 , VAR3, VAR2 );
VAR4 VAR5... | apache-2.0 |
jepler/linuxcnc | src/hal/drivers/pluto_servo_firmware/quad.v | 1,773 | module MODULE1(clk, VAR13, VAR16, VAR11, VAR10, out);
parameter VAR7=14;
input clk, VAR13, VAR16, VAR11, VAR10;
reg [(VAR7-1):0] VAR6, VAR15; reg VAR5;
output [2*VAR7:0] out = { VAR5, VAR15, VAR6 };
reg [2:0] VAR9, VAR4;
reg [2:0] VAR8;
always @(posedge clk) VAR9 <= {VAR9[1:0], VAR13};
always @(posedge clk) VAR4 <= {VA... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/ecc/ecc_gen.v | 7,892 | module MODULE1
parameter VAR5 = 72,
parameter VAR7 = 8,
parameter VAR19 = 64
)
(
VAR2
);
function integer VAR16 (input integer VAR11);
integer VAR20;
if (VAR11 == 1) VAR16 = 1;
else begin
VAR16 = 1;
for (VAR20=2; VAR20<=VAR11; VAR20=VAR20+1)
VAR16 = VAR16 * VAR20;
end
endfunction
function integer VAR3 (input integer VA... | lgpl-3.0 |
oblivioncth/DE0-Verilog-Processor | src/ID_10_Handler.v | 6,577 | module MODULE1 (VAR5, VAR4, VAR7, VAR17, VAR2, VAR9, VAR18, VAR3, VAR13, VAR15, VAR12, VAR8, VAR11, VAR14);
input [13:0] VAR5;
input VAR4, VAR7, VAR17;
input [2:0] VAR12;
output reg [15:0] VAR9;
output reg [18:0] VAR2;
output reg VAR18;
output reg [1:0] VAR3;
output reg VAR13;
output reg VAR15;
output reg [1:0] VAR8;
o... | mit |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkCSR_MIP.v | 9,941 | module MODULE1(VAR33,
VAR42,
VAR59,
VAR4,
VAR27,
VAR8,
VAR23,
VAR17,
VAR69,
VAR3,
VAR11,
VAR64,
VAR14,
VAR13,
VAR30,
VAR31,
VAR50);
input VAR33;
input VAR42;
input VAR59;
output [63 : 0] VAR4;
input [27 : 0] VAR27;
input [63 : 0] VAR8;
input VAR23;
output [63 : 0] VAR17;
output [63 : 0] VAR69;
input [27 : 0] VAR3;
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2i/sky130_fd_sc_ms__mux2i.behavioral.pp.v | 1,934 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR11 ,
VAR2 ,
VAR15,
VAR3,
VAR13 ,
VAR4
);
output VAR5 ;
input VAR9 ;
input VAR11 ;
input VAR2 ;
input VAR15;
input VAR3;
input VAR13 ;
input VAR4 ;
wire VAR7;
wire VAR1;
VAR8 VAR10 (VAR7, VAR9, VAR11, VAR2 );
VAR6 VAR14 (VAR1, VAR7, VAR15, VAR3);
buf VAR12 (VAR5 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a222oi/sky130_fd_sc_hdll__a222oi_1.v | 2,558 | module MODULE1 (
VAR12 ,
VAR2 ,
VAR3 ,
VAR8 ,
VAR6 ,
VAR4 ,
VAR1 ,
VAR13,
VAR9,
VAR11 ,
VAR5
);
output VAR12 ;
input VAR2 ;
input VAR3 ;
input VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR1 ;
input VAR13;
input VAR9;
input VAR11 ;
input VAR5 ;
VAR7 VAR10 (
.VAR12(VAR12),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6),... | apache-2.0 |
bargei/NoC264 | NoC264_2x2/mkinputvcqueues.v | 19,033 | module MODULE1(VAR72,
VAR36,
VAR27,
VAR67,
VAR42,
VAR30,
VAR45,
VAR57,
VAR47,
VAR51);
input VAR72;
input VAR36;
input VAR27;
input [69 : 0] VAR67;
input VAR42;
input VAR30;
input VAR45;
output [69 : 0] VAR57;
output [1 : 0] VAR47;
output [1 : 0] VAR51;
wire [69 : 0] VAR57;
wire [1 : 0] VAR47, VAR51;
wire [2 : 0] VAR69,... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/invz/gf180mcu_fd_sc_mcu9t5v0__invz_8.behavioral.v | 1,180 | module MODULE1( VAR2, VAR6, VAR4 );
input VAR2, VAR6;
output VAR4;
VAR1 VAR3(.VAR2(VAR2),.VAR6(VAR6),.VAR4(VAR4));
VAR1 VAR5(.VAR2(VAR2),.VAR6(VAR6),.VAR4(VAR4)); | apache-2.0 |
alexforencich/hdg2000 | fpga/rtl/soc_interface_wb_8.v | 10,947 | module MODULE1
(
input wire clk,
input wire rst,
input wire [7:0] VAR29,
input wire VAR15,
output wire VAR57,
input wire VAR47,
output wire [7:0] VAR35,
output wire VAR3,
input wire VAR23,
output wire VAR24,
output wire [35:0] VAR7, input wire [7:0] VAR59, output wire [7:0] VAR1, output wire VAR18, output wire VAR19, i... | mit |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_pipe_eq.v | 35,561 | module MODULE1 #
(
parameter VAR66 = "VAR91",
parameter VAR93 = "VAR132",
parameter VAR140 = 1
)
(
input VAR40,
input VAR33,
input VAR25,
input [ 1:0] VAR101,
input [ 3:0] VAR5,
input [ 3:0] VAR115,
input [ 5:0] VAR75,
input [ 1:0] VAR29,
input [ 2:0] VAR117,
input [ 5:0] VAR68,
input [ 3:0] VAR56,
input VAR119,
input ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311oi/sky130_fd_sc_hs__a311oi.behavioral.v | 1,970 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR4 ,
VAR7 ,
VAR8 ,
VAR6 ,
VAR11,
VAR14
);
output VAR2 ;
input VAR9 ;
input VAR4 ;
input VAR7 ;
input VAR8 ;
input VAR6 ;
input VAR11;
input VAR14;
wire VAR8 VAR13 ;
wire VAR3 ;
wire VAR16;
and VAR12 (VAR13 , VAR7, VAR9, VAR4 );
nor VAR5 (VAR3 , VAR13, VAR8, VAR6 );
VAR10 VAR15 (VAR16, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxbp/sky130_fd_sc_lp__sdfxbp.behavioral.v | 2,477 | module MODULE1 (
VAR10 ,
VAR22,
VAR24,
VAR21 ,
VAR2,
VAR6
);
output VAR10 ;
output VAR22;
input VAR24;
input VAR21 ;
input VAR2;
input VAR6;
supply1 VAR25;
supply0 VAR5;
supply1 VAR17 ;
supply0 VAR11 ;
wire VAR13 ;
wire VAR23 ;
reg VAR20 ;
wire VAR12 ;
wire VAR15;
wire VAR8;
wire VAR19;
wire VAR26 ;
wire VAR3 ;
wire VA... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_arb_mux.v | 19,702 | module MODULE1 #
(
parameter VAR92 = 100,
parameter VAR114 = "VAR118",
parameter VAR61 = "1T",
parameter VAR81 = 11,
parameter VAR32 = 3,
parameter VAR102 = "8",
parameter VAR45 = 4,
parameter VAR38 = 5,
parameter VAR116 = 5,
parameter VAR4 = 31,
parameter VAR33 = 8,
parameter VAR43 = "VAR96",
parameter VAR52 = "VAR85"... | mit |
skyfex/svo-raycaster | raycaster2/raycaster.v | 13,573 | module MODULE1(
VAR152,
VAR87,
VAR106, VAR61,
VAR219, VAR11, VAR75,
VAR27, VAR175,
VAR90, VAR186, VAR162, VAR98,
VAR34, VAR94, VAR62,
VAR60, VAR149, VAR212,
VAR170, VAR159, VAR120,
VAR205, VAR130,
VAR50
);
input VAR152;
input VAR87;
input [7:0] VAR106;
input [7:0] VAR61;
input VAR219;
input VAR11;
input VAR75;
input [2... | mit |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/shortfifo.v | 2,477 | module MODULE1
(input clk, input rst,
input [VAR2-1:0] VAR7,
output [VAR2-1:0] VAR1,
input read,
input write,
input VAR20,
output reg VAR14,
output reg VAR10,
output reg [4:0] VAR9,
output reg [4:0] VAR13);
reg [3:0] VAR11;
genvar VAR8;
generate
for (VAR8=0;VAR8<VAR2;VAR8=VAR8+1)
begin : VAR12
VAR17
VAR5(.VAR21(VAR1[VA... | gpl-2.0 |
monotone-RK/FACE | IEICE-Trans/16-way/src/ip_dram/ecc/mig_7series_v2_3_ecc_gen.v | 7,915 | module MODULE1
parameter VAR9 = 72,
parameter VAR14 = 8,
parameter VAR18 = 64
)
(
VAR15
);
function integer VAR12 (input integer VAR4);
integer VAR10;
if (VAR4 == 1) VAR12 = 1;
else begin
VAR12 = 1;
for (VAR10=2; VAR10<=VAR4; VAR10=VAR10+1)
VAR12 = VAR12 * VAR10;
end
endfunction
function integer VAR8 (input integer VAR... | mit |
c4puter/bridge-hdl | modules/wb_conmax/wb_conmax_msel.v | 7,442 | module MODULE1(
VAR24, VAR23,
VAR17, req, sel, VAR10
);
parameter [1:0] VAR21 = 2'd0;
input VAR24, VAR23;
input [15:0] VAR17;
input [7:0] req;
output [2:0] sel;
input VAR10;
wire [1:0] VAR26, VAR30, VAR6, VAR20;
wire [1:0] VAR14, VAR33, VAR2, VAR25;
wire [1:0] VAR31;
reg [1:0] VAR3;
wire [7:0] VAR29, VAR8, VAR7, VAR1;
... | gpl-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_ddr3/rtl/wb_tx1_ddr3.v | 5,430 | module MODULE1 (
input clk,
input rst,
input VAR6,
input VAR11,
input [3:0] VAR4,
input [31:0] VAR9,
input VAR8,
output reg VAR1,
output reg [31:0] VAR7,
input [31:0] VAR3,
output reg VAR12
);
localparam VAR2 = 32'h00000000;
localparam VAR10 = 32'h00000001;
localparam VAR5 = 32'h00000002;
always @ (posedge clk) begin
i... | mit |
fallen/milkymist-mmu | cores/vgafb/rtl/vgafb_pixelfeed.v | 5,082 | module MODULE1 #(
parameter VAR11 = 26
) (
input VAR4,
input VAR46,
input VAR2,
input [17:0] VAR10,
input [VAR11-1:0] VAR5,
output VAR20,
output reg [VAR11-1:0] VAR6,
output reg VAR31,
input VAR28,
input [63:0] VAR45,
output reg VAR26,
output [VAR11-1:0] VAR32,
input [63:0] VAR29,
input VAR24,
output VAR33,
output [15:... | lgpl-3.0 |
jairov4/puj-ca-de1-audio-pump | ip/i2c_opencores/i2c_master_top.v | 9,914 | module MODULE1(
VAR10, VAR4, VAR39, VAR7, VAR40, VAR31,
VAR36, VAR3, VAR55, VAR18, VAR48,
VAR8, VAR53, VAR35, VAR15, VAR25, VAR28 );
parameter VAR21 = 1'b0;
input VAR10; input VAR4; input VAR39; input [2:0] VAR7; input [7:0] VAR40; output [7:0] VAR31; input VAR36; input VAR3; input VAR55; output VAR18; output VAR48;
re... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4/sky130_fd_sc_hd__nor4_4.v | 2,275 | module MODULE2 (
VAR6 ,
VAR10 ,
VAR2 ,
VAR3 ,
VAR4 ,
VAR1,
VAR5,
VAR8 ,
VAR9
);
output VAR6 ;
input VAR10 ;
input VAR2 ;
input VAR3 ;
input VAR4 ;
input VAR1;
input VAR5;
input VAR8 ;
input VAR9 ;
VAR11 VAR7 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR... | apache-2.0 |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_m04_regslice_12/synth/system_m04_regslice_12.v | 10,970 | module MODULE1 (
VAR41,
VAR12,
VAR20,
VAR28,
VAR63,
VAR90,
VAR91,
VAR26,
VAR106,
VAR4,
VAR2,
VAR93,
VAR49,
VAR84,
VAR105,
VAR99,
VAR35,
VAR65,
VAR18,
VAR112,
VAR31,
VAR54,
VAR19,
VAR78,
VAR52,
VAR11,
VAR96,
VAR10,
VAR66,
VAR51,
VAR55,
VAR80,
VAR40,
VAR53,
VAR79,
VAR36,
VAR109,
VAR94,
VAR61,
VAR30
);
input wire VAR41;
i... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1.behavioral.pp.v | 1,867 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR10,
VAR12,
VAR2 ,
VAR11
);
output VAR8 ;
input VAR4 ;
input VAR10;
input VAR12;
input VAR2 ;
input VAR11 ;
wire VAR6 ;
wire VAR9;
not VAR1 (VAR6 , VAR4 );
VAR5 VAR3 (VAR9, VAR6, VAR10, VAR12);
buf VAR7 (VAR8 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfstp/sky130_fd_sc_ls__sdfstp.symbol.v | 1,498 | module MODULE1 (
input VAR3 ,
output VAR4 ,
input VAR5,
input VAR10 ,
input VAR7 ,
input VAR9
);
supply1 VAR1;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_cache/bsg_cache_sbuf.v | 5,248 | module MODULE1
import VAR16::*;
,parameter VAR46(VAR47)
,parameter VAR46(VAR36)
,localparam VAR8=(VAR42>>3)
,localparam VAR64=VAR71(VAR47,VAR42,VAR36)
)
(
input VAR11
,input VAR74
,input [VAR64-1:0] VAR58
,input VAR67
,output logic [VAR64-1:0] VAR25
,output logic VAR35
,input logic VAR1
,output logic VAR65
,output logi... | bsd-3-clause |
MarcoVogt/basil | firmware/modules/utils/generic_fifo.v | 2,140 | module MODULE1 (
clk, reset, write, read,
VAR7,
VAR13,
VAR6,
VAR14,
VAR12
);
parameter VAR8 = 32;
parameter VAR3 = 8;
input wire clk, reset, write, read;
input wire [VAR8-1:0] VAR7;
output wire VAR13;
output reg VAR6;
output reg [VAR8-1:0] VAR14;
reg [VAR8:0] VAR11 [VAR3-1:0];
parameter VAR10 = VAR4(VAR3);
reg [VAR10-1... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbp/sky130_fd_sc_hs__sdfbbp.behavioral.v | 3,371 | module MODULE1 (
VAR7 ,
VAR30 ,
VAR20 ,
VAR26 ,
VAR21 ,
VAR19 ,
VAR33 ,
VAR4,
VAR23 ,
VAR35
);
output VAR7 ;
output VAR30 ;
input VAR20 ;
input VAR26 ;
input VAR21 ;
input VAR19 ;
input VAR33 ;
input VAR4;
input VAR23 ;
input VAR35 ;
wire VAR18 ;
wire VAR1 ;
wire VAR28 ;
reg VAR5 ;
wire VAR34 ;
wire VAR22 ;
wire VAR11 ... | apache-2.0 |
Valakor/EE201-Text-Editor | text_editor_top.v | 18,256 | module MODULE1(
VAR16, VAR93, VAR122, VAR22, VAR17, VAR52, VAR103, VAR106, VAR82, VAR102, VAR62, VAR87, VAR13, VAR77, VAR125,
VAR55, VAR58, VAR64, VAR47, VAR124, VAR14, VAR101, VAR6, VAR27, VAR9, VAR66, VAR10, VAR100, VAR84, VAR119, VAR5, VAR117, VAR1, VAR28 );
input VAR52;
input VAR103;
inout VAR100, VAR84;
output VAR... | mit |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/ovld_reg_v1_0/hdl/Event_Pulse.v | 1,487 | module MODULE1(
input in, input clk, output VAR4, output VAR3, output VAR2 );
reg [1:0] VAR1 = 2'b0;
assign VAR4 = (~VAR1[1]) & VAR1[0]; assign VAR3 = VAR1[1] &(~VAR1[0]); assign VAR2 = ((~VAR1[1]) & VAR1[0]) | (VAR1[1] & (~VAR1[0]));
always @(posedge clk)
begin
VAR1[0] <= in;
VAR1[1] <= VAR1[0];
end
endmodule | mit |
ruishihan/R7-with-notes | src/rtl/ad9361_1t1r.v | 3,616 | module MODULE1
(
VAR2,
VAR11,
VAR37,
VAR29,
VAR9,
VAR12,
VAR36,
VAR26,
VAR25,
VAR19,
VAR41,
VAR28,
clk,
rst,
VAR7,
VAR1,
VAR34,
VAR38,
VAR31,
VAR15
);
input VAR2; input VAR11; input VAR37; input VAR29; input [5:0]VAR9; input [5:0]VAR12;
output VAR36; output VAR26; output VAR25; output VAR19; output [5:0]VAR41; output [... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.v | 2,583 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR10 ,
VAR11 ,
VAR12 ,
VAR5,
VAR9 ,
VAR1 ,
VAR7 ,
VAR4
);
output VAR2 ;
input VAR6 ;
input VAR10 ;
input VAR11 ;
input VAR12 ;
input VAR5;
input VAR9 ;
input VAR1 ;
input VAR7 ;
input VAR4 ;
VAR8 VAR3 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR12(VAR12),
.VAR5(VAR5),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp.behavioral.pp.v | 2,792 | module MODULE1 (
VAR8,
VAR17 ,
VAR15,
VAR12 ,
VAR5,
VAR13,
VAR6 ,
VAR1
);
output VAR8;
input VAR17 ;
input VAR15;
input VAR12 ;
input VAR5;
input VAR13;
input VAR6 ;
input VAR1 ;
wire VAR9 ;
wire VAR26 ;
wire VAR19 ;
wire VAR25 ;
wire VAR2 ;
wire VAR14 ;
wire VAR18;
wire VAR27 ;
reg VAR4 ;
wire VAR3 ;
wire VAR10 ;
wire... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41a/sky130_fd_sc_lp__o41a.behavioral.v | 1,549 | module MODULE1 (
VAR12 ,
VAR4,
VAR13,
VAR14,
VAR11,
VAR9
);
output VAR12 ;
input VAR4;
input VAR13;
input VAR14;
input VAR11;
input VAR9;
supply1 VAR7;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR10 ;
wire VAR5 ;
wire VAR1;
or VAR3 (VAR5 , VAR11, VAR14, VAR13, VAR4 );
and VAR6 (VAR1, VAR5, VAR9 );
buf VAR15 (VAR12 , VAR1 )... | apache-2.0 |
esonghori/TinyGarble | circuit_synthesis/aes/aes_1cc.v | 1,597 | module MODULE1
(
clk,
rst,
VAR32,
VAR14,
VAR25
);
localparam VAR1 = 10;
input clk;
input rst;
input [127:0] VAR32; input [127:0] VAR14; output [127:0] VAR25;
wire [127:0] VAR5;
wire [127:0] VAR9;
wire [127:0] out;
wire [128*(VAR1+1)-1:0] VAR19;
wire [127:0] VAR18[VAR1:0];
wire [127:0] VAR27[VAR1-1:0];
wire [127:0] VAR4... | gpl-3.0 |
chebykinn/university | circuitry/lab4/src/hdl/regfile.v | 1,069 | module MODULE1(
input wire clk, input wire rst, input wire [4:0] VAR5, VAR1, VAR9, input wire [31:0] VAR6, input wire VAR2, output wire [31:0] VAR4, VAR8 );
reg [31:0] VAR3 [31:0];
assign VAR4 = VAR3 [VAR5];
assign VAR8 = VAR3 [VAR1];
integer VAR7;
begin
begin
end | mit |
ElegantLin/My-CPU | Small Program/Small Program.srcs/sources_1/imports/imports/sources_1/imports/Chapter11/ex.v | 16,212 | module MODULE1(
input wire rst,
input wire[VAR13] VAR61,
input wire[VAR38] VAR82,
input wire[VAR17] VAR35,
input wire[VAR17] VAR10,
input wire[VAR28] VAR70,
input wire VAR23,
input wire[VAR17] VAR67,
input wire[31:0] VAR83,
input wire[VAR17] VAR54,
input wire[VAR17] VAR84,
input wire[VAR17] VAR15,
input wire[VAR17] VAR... | gpl-3.0 |
olgirard/openmsp430 | core/synthesis/actel/src/openMSP430_fpga.v | 7,397 | module MODULE1 (
VAR40, VAR4, VAR18, VAR16, VAR21, VAR34, VAR33, VAR32, VAR26,
VAR41, VAR8, irq, VAR10, VAR7, VAR38, VAR6 );
output VAR40; output VAR4; output VAR18; output [13:0] VAR16; output [7:0] VAR21; output [15:0] VAR34; output [1:0] VAR33; output VAR32; output VAR26;
input VAR41; input VAR8; input [13:0] irq; i... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_isowell/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.functional.pp.v | 2,052 | module MODULE1 (
VAR10 ,
VAR5 ,
VAR11,
VAR2 ,
VAR4 ,
VAR12 ,
VAR8
);
output VAR10 ;
input VAR5 ;
input VAR11;
input VAR2 ;
input VAR4 ;
input VAR12 ;
input VAR8 ;
wire VAR3;
wire VAR9 ;
VAR7 VAR1 (VAR3, VAR5, VAR11, VAR4 );
buf VAR6 (VAR9 , VAR3 );
VAR7 VAR13 (VAR10 , VAR9, VAR2, VAR4);
endmodule | apache-2.0 |
CospanDesign/sdio-device | rtl/sdio_data_control.v | 20,716 | module MODULE1 #(
parameter VAR13 = 400
)(
input clk,
input rst,
output VAR22,
output VAR7,
input VAR57,
input VAR74,
input [12:0] VAR9,
output reg [12:0] VAR117,
input VAR66,
input [17:0] VAR51,
output reg [17:0] VAR82,
input VAR67,
output reg VAR80,
input VAR92,
input VAR114,
input [3:0] VAR1,
input [7:0] VAR58,
outp... | mit |
JakeMercer/mac | MAC/rtl/mac/mac_loopback.v | 1,309 | module MODULE1(
input wire reset,
input wire VAR26,
input wire VAR3,
input wire VAR4,
input wire VAR2,
output wire VAR13,
output wire [7:0] VAR23,
input wire VAR6,
input wire [7:0] VAR15,
input wire VAR5
);
wire [7:0] VAR27;
wire VAR10;
wire VAR14;
reg VAR17;
wire VAR1;
wire VAR21;
VAR12 VAR24(
.reset(reset),
.VAR9(VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2b/sky130_fd_sc_ls__nor2b.blackbox.v | 1,307 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR5
);
output VAR7 ;
input VAR6 ;
input VAR5;
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_altmemddr_0_phy_alt_mem_phy_pll.v | 22,771 | module MODULE1 (
VAR83,
VAR4,
VAR90,
VAR84,
VAR29,
VAR59,
VAR125,
VAR103,
VAR2,
VAR41,
VAR134,
VAR55,
VAR46);
input VAR83;
input VAR4;
input [2:0] VAR90;
input VAR84;
input VAR29;
input VAR59;
output VAR125;
output VAR103;
output VAR2;
output VAR41;
output VAR134;
output VAR55;
output VAR46;
tri0 VAR83;
tri0 [2:0] VAR9... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4/sky130_fd_sc_lp__or4_4.v | 2,231 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR8 ,
VAR2 ,
VAR11 ,
VAR6,
VAR10,
VAR4 ,
VAR7
);
output VAR1 ;
input VAR5 ;
input VAR8 ;
input VAR2 ;
input VAR11 ;
input VAR6;
input VAR10;
input VAR4 ;
input VAR7 ;
VAR9 VAR3 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR4(VAR4),
.... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Mark_Extract_Bits.v | 1,204 | module MODULE1
(
VAR1,
VAR7
);
input [17:0] VAR1; output [8:0] VAR7;
wire [8:0] VAR2;
VAR4 VAR3 (.VAR5(VAR1), .VAR6(VAR2) );
assign VAR7 = VAR2;
endmodule | gpl-3.0 |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_reversor.v | 2,078 | module MODULE1
(VAR4, VAR2);
parameter VAR5 = 32;
input [0:VAR5-1] VAR4;
output [0:VAR5-1] VAR2;
wire [0:VAR5-1] VAR2;
generate
genvar VAR3;
for(VAR3 = 0; VAR3 < VAR5; VAR3 = VAR3 + 1)
begin:VAR1
assign VAR2[VAR3] = VAR4[(VAR5-1)-VAR3];
end
endgenerate
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21bai/sky130_fd_sc_ls__o21bai.symbol.v | 1,394 | module MODULE1 (
input VAR7 ,
input VAR5 ,
input VAR3,
output VAR6
);
supply1 VAR2;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/de3d/des_comp_gen_fx_z.v | 2,740 | module MODULE1
(
input clk,
input VAR18,
input [23:0] VAR2, input [23:0] VAR15, input [95:0] VAR3,
output reg signed [31:0] VAR7
);
wire [31:0] VAR14;
wire [31:0] VAR16;
wire [31:0] VAR4;
reg [63:0] VAR12;
reg [63:0] VAR11;
reg [25:0] VAR9;
VAR19 VAR6(VAR3[95:64], VAR14); VAR19 VAR17(VAR3[63:32], VAR16); VAR19 VAR5(VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31ai/sky130_fd_sc_hd__o31ai.behavioral.v | 1,543 | module MODULE1 (
VAR10 ,
VAR9,
VAR12,
VAR13,
VAR7
);
output VAR10 ;
input VAR9;
input VAR12;
input VAR13;
input VAR7;
supply1 VAR11;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR6 ;
wire VAR4 ;
wire VAR14;
or VAR5 (VAR4 , VAR12, VAR9, VAR13 );
nand VAR1 (VAR14, VAR7, VAR4 );
buf VAR3 (VAR10 , VAR14 );
endmodule | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | LCD/LCD_Peripheral.v | 3,564 | module MODULE1(clk , rst , din , VAR17 , addr , rd , wr, VAR6, VAR9, VAR12, VAR19, VAR11, VAR3, dout );
input [15:0]din;
input VAR17;
input [3:0]addr;
input rd;
input wr;
output reg [15:0] dout;
input clk;
input rst;
input VAR19;
output VAR11;
output [15:0] VAR3;
output VAR9;
output VAR6;
output [7:0] VAR12;
reg [10:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufinv/sky130_fd_sc_lp__bufinv.blackbox.v | 1,238 | module MODULE1 (
VAR3,
VAR4
);
output VAR3;
input VAR4;
supply1 VAR1;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtn/sky130_fd_sc_ms__dlrtn.symbol.v | 1,416 | module MODULE1 (
input VAR5 ,
output VAR8 ,
input VAR1,
input VAR6
);
supply1 VAR7;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0/bd_0/hdl/bd_350b_wrapper.v | 8,211 | module MODULE1
(VAR18,
VAR19,
VAR60,
VAR43,
VAR24,
VAR34,
VAR58,
VAR5,
VAR39,
VAR50,
VAR2,
VAR20,
VAR57,
VAR49,
VAR35,
VAR4,
VAR52,
VAR14,
VAR29,
VAR36,
VAR45,
VAR23,
VAR28,
VAR13,
VAR62,
VAR32,
VAR9,
VAR27,
VAR31,
VAR42,
VAR59,
VAR21,
VAR26,
VAR38,
VAR48,
VAR51,
VAR55,
VAR11,
VAR10,
VAR16,
VAR46,
VAR25,
VAR41,
VAR1,
V... | mit |
ffu/DSA-3.2.2 | usrp/fpga/inband_lib/channel_ram.v | 3,284 | module MODULE1
( input VAR18, input reset,
input [31:0] VAR25, input VAR21, input VAR17, output VAR9,
output [31:0] VAR11, input VAR24, input VAR20, output VAR23);
reg [6:0] VAR7, VAR14;
reg [1:0] VAR5, VAR3;
reg [2:0] VAR1;
reg [31:0] VAR2 [0:127];
reg [31:0] VAR19 [0:127];
reg [31:0] VAR12 [0:127];
reg [31:0] VAR6 [0... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/sync_flag.v | 5,752 | module MODULE1(
input VAR3,
input VAR1,
input VAR15,
input [VAR20-1:0] VAR14,
output VAR11,
input VAR2,
output VAR6,
output [VAR20-1:0] VAR10
);
parameter VAR12 = 1;
parameter VAR20 = 1;
parameter VAR4 = 0;
parameter VAR7 = 0;
reg [VAR20-1:0] VAR8 = 'h0;
wire [VAR20-1:0] VAR5;
reg VAR19 = 'h0;
wire VAR9;
generate if (V... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/alt_mem_ddrx_list.v | 8,506 | module MODULE1
parameter
VAR9 = 3, VAR17 = 8,
VAR23 = "VAR22", VAR11 = "VAR2" )
(
VAR7,
VAR18,
VAR20,
VAR15,
VAR6,
VAR5,
VAR14,
VAR10,
VAR16
);
input VAR7;
input VAR18;
input VAR15;
output VAR20;
output [VAR9-1:0] VAR6;
output [VAR17-1:0] VAR5;
output VAR10;
input VAR14;
input [VAR9-1:0] VAR16;
reg VAR20;
wire VAR15;
r... | lgpl-3.0 |
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