repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/NVMeHostController_v2_0_0/ba7abda2/src/dma_cmd_fifo.v | 11,395 | module MODULE1 # (
parameter VAR27 = 50,
parameter VAR35 = 9
)
(
input VAR60,
input VAR82,
input VAR12,
input [VAR27-1:0] VAR18,
input [VAR27-1:0] VAR61,
output VAR75,
input VAR57,
input VAR44,
input VAR54,
output [VAR27-1:0] VAR74,
output VAR26
);
localparam VAR24 = 1;
localparam VAR63 = 3'b001;
localparam VAR17 = 3'b... | gpl-3.0 |
theHawke/real-dcpu | RAM.v | 10,697 | module MODULE1 (
VAR42,
VAR18,
VAR14,
VAR44,
VAR53,
VAR26,
VAR21,
VAR48,
VAR1,
VAR39);
input [15:0] VAR42;
input [15:0] VAR18;
input VAR14;
input VAR44;
input [15:0] VAR53;
input [15:0] VAR26;
input VAR21;
input VAR48;
output [15:0] VAR1;
output [15:0] VAR39;
tri1 VAR14;
tri0 VAR21;
tri0 VAR48;
wire [15:0] VAR8;
wire [... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2.1/6f26cfffdb36de71/zqynq_lab_1_design_auto_pc_3_stub.v | 5,786 | module MODULE1(VAR15, VAR74, VAR29, VAR27,
VAR16, VAR51, VAR41, VAR8, VAR59, VAR10,
VAR18, VAR43, VAR2, VAR65, VAR6, VAR79, VAR62,
VAR44, VAR30, VAR70, VAR61, VAR63, VAR54, VAR69,
VAR3, VAR34, VAR73, VAR5, VAR11, VAR57,
VAR39, VAR25, VAR53, VAR75, VAR38, VAR42, VAR26,
VAR1, VAR14, VAR47, VAR72, VAR56, VAR12, VAR40,
VAR... | mit |
tmatsuya/milkymist-ml401 | cores/aceusb/rtl/aceusb_access.v | 2,615 | module MODULE1(
input VAR15,
input rst,
input [5:0] VAR17,
input [15:0] VAR13,
output reg [15:0] do,
input read,
input write,
output reg ack,
output [6:0] VAR6,
inout [15:0] VAR21,
output reg VAR22,
output reg VAR19,
output reg VAR20,
input VAR4,
output VAR3,
output VAR2,
input VAR9
);
assign VAR3 = 1'b1;
assign VAR2 =... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2a/sky130_fd_sc_ls__o2bb2a.pp.symbol.v | 1,383 | module MODULE1 (
input VAR8,
input VAR3,
input VAR6 ,
input VAR9 ,
output VAR4 ,
input VAR2 ,
input VAR5,
input VAR1,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/inv/sky130_fd_sc_hs__inv.pp.symbol.v | 1,205 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/practica4.v | 3,674 | module MODULE1( VAR4,
VAR12,
VAR43,
VAR24,
VAR11,
VAR23,
VAR1,
VAR3,
VAR34,
VAR32,
VAR25,
VAR17,
VAR5,
VAR19,
VAR26,
VAR16,
VAR18,
VAR22,
VAR9,
VAR29,
VAR40,
VAR39,
VAR42,
);
input VAR4;
input VAR12;
output [7:0]VAR43;
input [3:0]VAR24;
output VAR11;
output VAR23;
output VAR1;
input VAR3;
output [12:0]VAR34;
output [1:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/diode/sky130_fd_sc_hvl__diode_2.v | 1,986 | module MODULE2 (
VAR2,
VAR7 ,
VAR6 ,
VAR3 ,
VAR5
);
input VAR2;
input VAR7 ;
input VAR6 ;
input VAR3 ;
input VAR5 ;
VAR1 VAR4 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR2
);
input VAR2;
supply1 VAR7;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR5 ;
VAR1 VAR4 (
.VAR2(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4bb/sky130_fd_sc_hs__and4bb_4.v | 2,196 | module MODULE2 (
VAR6 ,
VAR9 ,
VAR8 ,
VAR2 ,
VAR5 ,
VAR4,
VAR7
);
output VAR6 ;
input VAR9 ;
input VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR4;
input VAR7;
VAR1 VAR3 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR6 ,
VAR9,
VAR8,
VAR2 ,
VAR5
)... | apache-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/vfabric_lsu_bursting.v | 14,489 | module MODULE2(VAR7, VAR28,
VAR26, VAR61, VAR42,
VAR103, VAR1, VAR63,
VAR71, VAR36, VAR52,
VAR64, VAR40, VAR47,
VAR41, VAR96, VAR82, VAR68,
VAR72, VAR92, VAR2,
VAR81, VAR48, VAR100,
VAR11, VAR54,
VAR65,
VAR86,
VAR87,
VAR8,
VAR99,
VAR101, VAR57,
VAR50,
VAR84,
VAR80
);
parameter VAR15 = "VAR32-VAR29-VAR107";
parameter VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd.functional.v | 1,140 | module MODULE1 (
VAR1,
VAR2
);
input VAR1;
input VAR2;
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/top.v | 4,828 | module MODULE2 (
VAR22,
VAR11,
VAR66,
VAR21,
VAR9,
VAR64,
VAR13,
VAR49,
VAR40,
VAR56,
VAR27,
VAR33,
VAR23,
VAR31,
VAR45,
VAR12,
VAR46,
VAR60,
VAR67,
VAR51,
VAR58,
VAR28,
VAR39,
VAR37,
VAR14,
VAR15,
VAR6,
VAR57,
VAR70,
VAR20,
VAR29,
VAR30,
VAR10,
VAR8,
VAR19
);
input wire VAR22;
input wire VAR11;
output wire [3:0] VAR66... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_029.v | 1,433 | module MODULE1 (
VAR2,
VAR4
);
input [31:0] VAR2;
output [31:0]
VAR4;
wire [31:0]
VAR12,
VAR8,
VAR5,
VAR1,
VAR6,
VAR9,
VAR11;
assign VAR12 = VAR2;
assign VAR8 = VAR12 << 4;
assign VAR5 = VAR12 + VAR8;
assign VAR6 = VAR5 + VAR1;
assign VAR11 = VAR9 - VAR5;
assign VAR9 = VAR6 << 10;
assign VAR1 = VAR12 << 1;
assign VAR4 ... | mit |
hly11/CollisionDetectionFPGA | hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/synth/design_1_auto_pc_0.v | 13,144 | module MODULE1 (
VAR110,
VAR96,
VAR99,
VAR79,
VAR73,
VAR24,
VAR30,
VAR63,
VAR15,
VAR59,
VAR47,
VAR80,
VAR57,
VAR31,
VAR83,
VAR38,
VAR25,
VAR77,
VAR9,
VAR91,
VAR19,
VAR103,
VAR89,
VAR88,
VAR36,
VAR87,
VAR41,
VAR3,
VAR106,
VAR5,
VAR62,
VAR67,
VAR102,
VAR39,
VAR100,
VAR81,
VAR4,
VAR69,
VAR75,
VAR18,
VAR45,
VAR70,
VAR60,
V... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/alt_mem_ddrx_rdata_path.v | 51,062 | module MODULE1
parameter
VAR44 = 8,
VAR30 = 2,
VAR229 = 3, VAR70 = 3,
VAR197 = 32,
VAR74 = 5,
VAR134 = 2,
VAR263 = 3,
VAR210 = 13,
VAR121 = 10,
VAR135 = 4, VAR160 = "VAR126", VAR262 = 2,
VAR247 = 3,
VAR24 = 2,
VAR209 = 1,
VAR228 = 8,
VAR31 = 3,
VAR158 = 1,
VAR238 = 1,
VAR258 = 1,
VAR142 = 5,
VAR27 = 2,
VAR83 = 9,
VAR16... | lgpl-3.0 |
kyzhai/NUNY | src/hardware/ninja1.v | 6,363 | module MODULE1 (
address,
VAR19,
VAR28);
input [11:0] address;
input VAR19;
output [11:0] VAR28;
tri1 VAR19;
wire [11:0] VAR29;
wire [11:0] VAR28 = VAR29[11:0];
VAR4 VAR15 (
.VAR1 (address),
.VAR52 (VAR19),
.VAR12 (VAR29),
.VAR11 (1'b0),
.VAR36 (1'b0),
.VAR8 (1'b1),
.VAR48 (1'b0),
.VAR49 (1'b0),
.VAR2 (1'b1),
.VAR10 (1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invkapwr/sky130_fd_sc_lp__invkapwr.behavioral.pp.v | 1,841 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR11 ,
VAR12 ,
VAR10,
VAR5 ,
VAR4
);
output VAR6 ;
input VAR8 ;
input VAR11 ;
input VAR12 ;
input VAR10;
input VAR5 ;
input VAR4 ;
wire VAR9 ;
wire VAR2;
not VAR7 (VAR9 , VAR8 );
VAR3 VAR1 (VAR2, VAR9, VAR10, VAR12);
buf VAR13 (VAR6 , VAR2 );
endmodule | apache-2.0 |
ultraembedded/riscv | core/riscv/riscv_fetch.v | 8,412 | module MODULE1
parameter VAR9 = 1
)
(
input VAR20
,input VAR1
,input VAR44
,input VAR12
,input VAR42
,input VAR46
,input [ 31:0] VAR11
,input VAR36
,input VAR27
,input VAR34
,input [ 31:0] VAR24
,input [ 1:0] VAR38
,output VAR31
,output [ 31:0] VAR41
,output [ 31:0] VAR19
,output VAR21
,output VAR17
,output VAR43
,outp... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/decap/sky130_fd_sc_ms__decap.pp.blackbox.v | 1,198 | module MODULE1 (
VAR2,
VAR3,
VAR4 ,
VAR1
);
input VAR2;
input VAR3;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
argonnexraydetector/RoachFirmPy | ANLYellowBlocks/mkid_dacadc_4x/ise/mkiddac/ipcore_dir/mmcm_mkid/example_design/mmcm_mkid_exdes.v | 6,279 | module MODULE1
parameter VAR36 = 100
)
( input VAR19,
input VAR4,
output [4:1] VAR2,
output [4:1] VAR7,
output VAR28
);
localparam VAR16 = 16;
localparam VAR38 = 4;
genvar VAR30;
wire VAR11 = !VAR28 || VAR4;
reg [VAR38:1] VAR12;
reg [VAR38:1] VAR17;
reg [VAR38:1] VAR39;
reg [VAR38:1] VAR8;
wire VAR33;
wire VAR26;
wire ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ai/sky130_fd_sc_hd__o21ai.behavioral.v | 1,530 | module MODULE1 (
VAR9 ,
VAR12,
VAR5,
VAR4
);
output VAR9 ;
input VAR12;
input VAR5;
input VAR4;
supply1 VAR2;
supply0 VAR1;
supply1 VAR10 ;
supply0 VAR3 ;
wire VAR13 ;
wire VAR8;
or VAR6 (VAR13 , VAR5, VAR12 );
nand VAR7 (VAR8, VAR4, VAR13 );
buf VAR11 (VAR9 , VAR8 );
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/nios_altmemddr_0_alt_mem_ddrx_controller_top.v | 41,341 | module MODULE1(
clk,
VAR247,
VAR364,
VAR30,
VAR360,
VAR31,
VAR204,
VAR35,
VAR348,
VAR371,
VAR236,
VAR317,
VAR47,
VAR313,
VAR350,
VAR244,
VAR267,
VAR225,
VAR207,
VAR227,
VAR20,
VAR118,
VAR80,
VAR402,
VAR134,
VAR399,
VAR293,
VAR104,
VAR400,
VAR239,
VAR8,
VAR214,
VAR192,
VAR71,
VAR29,
VAR401,
VAR357,
VAR334,
VAR337,
VAR29... | gpl-3.0 |
grindars/bfcore | ClockManager.v | 1,304 | module MODULE1(
input VAR4,
input VAR6,
output VAR1,
output reg VAR2
);
parameter VAR7 = 4;
reg [VAR7 - 1:0] VAR5;
reg VAR3;
always @ (posedge VAR4)
if(VAR6)
VAR5 <= 0;
else
VAR5 <= VAR5 + 1;
always @ (posedge VAR4)
if(VAR6)
begin
VAR2 <= 1'b1;
VAR3 <= 1'b0;
end
else if(VAR5 == (1 << VAR7) - 1)
begin
VAR2 <= 1'b0;
VAR3... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/controller/rank_mach.v | 11,023 | module MODULE1 #
(
parameter VAR21 = "8",
parameter VAR31 = 4,
parameter VAR36 = "VAR46",
parameter VAR11 = 40,
parameter VAR24 = 4,
parameter VAR23 = 2,
parameter VAR34 = 5,
parameter VAR7 = 30,
parameter VAR32 = 8,
parameter VAR53 = 4,
parameter VAR22 = 4,
parameter VAR6 = 20,
parameter VAR49 = 16,
parameter VAR51 = ... | lgpl-3.0 |
QuantumQuadrate/HamamatsuCameralink | serdes_1_to_n_data_s8_diff.v | 15,660 | module MODULE1 (VAR75, VAR45, VAR56, VAR32, reset, VAR10, VAR59, VAR70, VAR63, VAR1) ;
parameter integer VAR69 = 8 ; parameter integer VAR5 = 16 ; parameter VAR28 = "VAR102" ;
input VAR75 ; input [VAR5-1:0] VAR45 ; input VAR56 ; input VAR32 ; input reset ; input VAR10 ; input VAR59 ; input [1:0] VAR70 ; output [(VAR5*V... | bsd-3-clause |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/b2b/src/aur1_idle_and_ver_gen.v | 15,202 | module MODULE1
(
VAR19,
VAR18,
VAR3,
VAR6,
VAR24,
VAR9,
VAR38,
VAR23
);
input VAR19;
output VAR18;
output [0:3] VAR3;
output [0:7] VAR6;
output [0:7] VAR24;
output [0:7] VAR9;
input VAR38;
input VAR23;
reg [0:3] VAR13;
reg [0:3] VAR31;
reg VAR20;
reg VAR27;
wire VAR17;
wire VAR10;
wire VAR35;
wire [0:2] VAR28;
wire [0:... | gpl-3.0 |
xuefei1/ElectronicEngineControl | niosII_system/synthesis/submodules/niosII_system_generic_tristate_controller_0.v | 28,062 | module MODULE1 #(
parameter VAR50 = 22,
parameter VAR11 = 8,
parameter VAR67 = 1,
parameter VAR56 = 160,
parameter VAR46 = 160,
parameter VAR71 = 40,
parameter VAR54 = 40,
parameter VAR9 = 2,
parameter VAR32 = 0,
parameter VAR36 = 2,
parameter VAR58 = 1,
parameter VAR17 = 1,
parameter VAR3 = 1,
parameter VAR13 = 1,
par... | apache-2.0 |
CMU-SAFARI/NOCulator | hring/hw/HRnode/HRnode.v | 1,600 | module MODULE1
(
input VAR22 VAR20,
input VAR22 VAR6,
input VAR22 VAR16,
input VAR22 VAR18,
output VAR9,
output VAR13,
input clk,
input rst,
output VAR22 VAR2,
output VAR22 VAR1,
output VAR22 VAR15,
output VAR22 VAR4
);
wire VAR22 VAR21, VAR3, VAR11, VAR23;
assign VAR21 = (rst) ? VAR7'd0 : VAR20;
assign VAR3 = (rst) ? ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/buf/sky130_fd_sc_hs__buf.symbol.v | 1,200 | module MODULE1 (
input VAR3,
output VAR1
);
supply1 VAR4;
supply0 VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2i/sky130_fd_sc_ms__mux2i.symbol.v | 1,344 | module MODULE1 (
input VAR7,
input VAR3,
output VAR2 ,
input VAR5
);
supply1 VAR6;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/lucy_tc/de3d_tc_top.v | 27,140 | module MODULE1
(
input VAR63, input VAR122, input VAR103, input VAR281, input [31:0] VAR176, input VAR200, input [8:0] VAR124, input [8:0] VAR82, input [3:0] VAR242, input VAR232, input [10:0] VAR19, input [10:0] VAR126,
input [209:0] VAR135, input VAR78, input VAR111, input [11:0] VAR56, input [31:0] VAR289, output [7... | gpl-3.0 |
cr88192/bgbtech_bjx1core | bjx1c32b1/ExUnit.v | 12,818 | module MODULE1(
VAR103, reset,
VAR72, VAR66,
VAR120, VAR178,
VAR33,
VAR136, VAR104,
VAR155, VAR152,
VAR128
);
input VAR103; input reset;
output[31:0] VAR72; inout[127:0] VAR66; output VAR120; output VAR178; input VAR33;
output[31:0] VAR136; inout[31:0] VAR104; output VAR155; output VAR152; input[1:0] VAR128;
assign VAR... | mit |
adbrant/zuma-fpga | verilog/platforms/altera/onchip_memory2_0.v | 3,594 | module MODULE1 (
address,
VAR15,
clk,
VAR8,
reset,
write,
VAR2,
VAR18
)
;
parameter VAR21 = "../MODULE1.VAR9";
output [ 7: 0] VAR18;
input [ 16: 0] address;
input VAR15;
input clk;
input VAR8;
input reset;
input write;
input [ 7: 0] VAR2;
wire [ 7: 0] VAR18;
wire VAR3;
assign VAR3 = VAR15 & write;
VAR27 VAR12
(
.VAR30 ... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4bb/sky130_fd_sc_ls__or4bb.blackbox.v | 1,326 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR2 ,
VAR4,
VAR9
);
output VAR1 ;
input VAR6 ;
input VAR2 ;
input VAR4;
input VAR9;
supply1 VAR7;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
natsutan/nromgen | output/rtl/sinrom.v | 13,601 | module MODULE1
(
input VAR1,
input VAR3,
input [8:0] VAR4,
output reg [23:0] VAR2
);
always @(posedge VAR1 or negedge VAR3)begin
if(VAR3 == 1'b0)begin
VAR2 <= 24'd0;
end else begin
case(VAR4)
0:VAR2 <= 24'hffffcb;
1:VAR2 <= 24'hfffe39;
2:VAR2 <= 24'hfffca8;
3:VAR2 <= 24'hfffb16;
4:VAR2 <= 24'hfff984;
5:VAR2 <= 24'hfff7... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/sctag_scbuf_rptr1.v | 7,720 | module MODULE1 (
VAR6, VAR35,
VAR40, VAR49,
VAR15, VAR48,
VAR45, VAR44,
VAR25, VAR4,
VAR20, VAR39,
VAR5, VAR27,
VAR14, VAR12,
VAR38, VAR42,
VAR41, VAR3,
VAR31, VAR17,
VAR19, VAR29,
VAR23,
VAR33, VAR24,
VAR47, VAR10,
VAR30, VAR7,
VAR13, VAR37,
VAR1, VAR26,
VAR11, VAR28,
VAR34, VAR2,
VAR8, VAR18,
VAR36, VAR16,
VAR22, VAR... | gpl-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_dsp/mcu_cmd.v | 16,407 | module MODULE1(
input clk,
input VAR24,
input VAR66,
input [7:0] VAR27,
input [7:0] VAR2,
output [2:0] VAR13,
output reg VAR49 = 0,
output VAR68,
output reg VAR48 = 0,
input VAR67,
output [7:0] VAR52,
input [7:0] VAR17,
output [7:0] VAR21,
input [31:0] VAR14,
input [2:0] VAR64,
output [23:0] VAR40,
output [7:0] VAR9,
o... | gpl-2.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/decode/decode_core.v | 14,283 | module MODULE1(
VAR4,
VAR10,
VAR9,
VAR1,
VAR19,
VAR5,
VAR17,
VAR20,
VAR24,
VAR12,
VAR21,
VAR8,
VAR7
);
input [63:0] VAR4;
input VAR10;
output VAR9;
output [1:0] VAR1;
output [31:0] VAR19;
output [15:0] VAR5;
output [31:0] VAR17;
output [9:0] VAR20;
output [9:0] VAR24;
output [9:0] VAR12;
output [9:0] VAR21;
output [9:0... | bsd-3-clause |
kramble/FPGA-Litecoin-Miner | experimental/hashvariant-A.v | 29,908 | module MODULE1 (VAR78, VAR65, VAR26, VAR116, VAR57, VAR103, VAR87, VAR80, VAR29, VAR115);
input VAR78;
input [255:0] VAR65;
input [255:0] VAR26;
input [127:0] VAR116;
input [31:0] VAR57;
input [3:0] VAR103; output [31:0] VAR87;
output [31:0] VAR80;
output VAR29; input VAR115;
reg VAR74 = 1'b1;
reg reset = 1'b1;
always ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or3b/sky130_fd_sc_ms__or3b.pp.blackbox.v | 1,308 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR6 ,
VAR2 ,
VAR1,
VAR5,
VAR4 ,
VAR3
);
output VAR8 ;
input VAR7 ;
input VAR6 ;
input VAR2 ;
input VAR1;
input VAR5;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1.functional.pp.v | 1,733 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR9,
VAR1
);
output VAR8 ;
input VAR5 ;
input VAR9;
input VAR1;
wire VAR3 ;
wire VAR7;
buf VAR6 (VAR3 , VAR5 );
VAR10 VAR2 (VAR7, VAR3, VAR9, VAR1);
buf VAR4 (VAR8 , VAR7 );
endmodule | apache-2.0 |
jhennessy/parallella-hw-old | fpga/hdl/gpio/parallella_gpio_emio.v | 5,168 | module MODULE1
(
VAR35,
VAR15, VAR21,
VAR14, VAR24
);
inout [VAR4-1:0] VAR15;
inout [VAR4-1:0] VAR21;
output [47:0] VAR35;
input [47:0] VAR14;
input [47:0] VAR24;
wire [VAR18-1:0] VAR29;
assign VAR35[VAR18-1:0] = VAR29;
wire [VAR18-1:0] VAR20
= VAR14[VAR18-1:0];
wire [VAR18-1:0] VAR31
= VAR24[VAR18-1:0];
VAR36
.VAR25("... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/pfpu/rtl/pfpu_addrgen.v | 1,425 | module MODULE1(
input VAR7,
input VAR5,
input VAR2,
input [6:0] VAR10,
input [6:0] VAR6,
output [31:0] VAR3,
output [31:0] VAR8,
output reg VAR9
);
reg [6:0] VAR1;
assign VAR3 = {25'd0, VAR1};
reg [6:0] VAR4;
assign VAR8 = {25'd0, VAR4};
always @(posedge VAR7) begin
if(VAR5) begin
VAR1 <= 7'd0;
VAR4 <= 7'd0;
end else i... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111o/sky130_fd_sc_hd__a2111o.functional.pp.v | 2,070 | module MODULE1 (
VAR13 ,
VAR5 ,
VAR11 ,
VAR16 ,
VAR4 ,
VAR17 ,
VAR9,
VAR10,
VAR14 ,
VAR8
);
output VAR13 ;
input VAR5 ;
input VAR11 ;
input VAR16 ;
input VAR4 ;
input VAR17 ;
input VAR9;
input VAR10;
input VAR14 ;
input VAR8 ;
wire VAR18 ;
wire VAR3 ;
wire VAR12;
and VAR1 (VAR18 , VAR5, VAR11 );
or VAR2 (VAR3 , VAR4, V... | apache-2.0 |
olajep/oh | src/common/hdl/oh_csa42.v | 1,791 | module MODULE1 #( parameter VAR9 = 1 )
( input [VAR9-1:0] VAR6, input [VAR9-1:0] VAR4, input [VAR9-1:0] VAR13, input [VAR9-1:0] VAR5, input [VAR9-1:0] VAR10, output [VAR9-1:0] VAR11, output [VAR9-1:0] VAR7, output [VAR9-1:0] VAR3 );
localparam VAR8 = VAR2;
generate
if(VAR8)
begin
VAR12 VAR1[VAR9-1:0] (.VAR11(VAR11[VAR9... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtn/sky130_fd_sc_ms__dfrtn_1.v | 2,371 | module MODULE2 (
VAR7 ,
VAR9 ,
VAR1 ,
VAR8,
VAR2 ,
VAR5 ,
VAR3 ,
VAR6
);
output VAR7 ;
input VAR9 ;
input VAR1 ;
input VAR8;
input VAR2 ;
input VAR5 ;
input VAR3 ;
input VAR6 ;
VAR10 VAR4 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32o/sky130_fd_sc_lp__a32o.functional.v | 1,580 | module MODULE1 (
VAR2 ,
VAR10,
VAR11,
VAR12,
VAR9,
VAR4
);
output VAR2 ;
input VAR10;
input VAR11;
input VAR12;
input VAR9;
input VAR4;
wire VAR13 ;
wire VAR6 ;
wire VAR8;
and VAR7 (VAR13 , VAR12, VAR10, VAR11 );
and VAR5 (VAR6 , VAR9, VAR4 );
or VAR1 (VAR8, VAR6, VAR13);
buf VAR3 (VAR2 , VAR8 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_2.behavioral.v | 18,884 | module MODULE1( VAR68, VAR270, VAR184, VAR5, VAR194, VAR100 );
input VAR5, VAR184, VAR68, VAR194, VAR270;
output VAR100;
reg VAR189;
VAR242 VAR249(.VAR68(VAR68),.VAR270(VAR270),.VAR184(VAR184),.VAR5(VAR5),.VAR194(VAR194),.VAR100(VAR100),.VAR189(VAR189));
VAR242 VAR96(.VAR68(VAR68),.VAR270(VAR270),.VAR184(VAR184),.VAR5(... | apache-2.0 |
DSP-Crowd/software | apps/mobile_rgb-led/de0_nano/src/42s16160.v | 40,138 | module MODULE1 (VAR95, VAR4, VAR34, VAR8, VAR43, VAR58, VAR26, VAR89, VAR1, VAR72);
parameter VAR31 = 13;
parameter VAR45 = 16;
parameter VAR10 = 9;
parameter VAR75 = 4194304;
inout [VAR45 - 1 : 0] VAR95;
input [VAR31 - 1 : 0] VAR4;
input [1 : 0] VAR34;
input VAR8;
input VAR43;
input VAR58;
input VAR26;
input VAR89;
in... | gpl-2.0 |
marmolejo/zet | cores/vga/rtl/vga_lcd.v | 8,151 | module MODULE1 (
input clk, input rst,
input VAR6, input VAR36,
output [17:1] VAR46,
input [15:0] VAR22,
output VAR60,
input [3:0] VAR45,
input VAR39,
output [7:0] VAR71,
input [7:0] VAR2,
input VAR14,
input [1:0] VAR89,
input [7:0] VAR48,
output [3:0] VAR55,
input [1:0] VAR29,
input [7:0] VAR23,
input [3:0] VAR70,
out... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinv/sky130_fd_sc_hdll__clkinv.pp.symbol.v | 1,272 | module MODULE1 (
input VAR6 ,
output VAR5 ,
input VAR2 ,
input VAR4,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v | 4,106 | module MODULE1 (clk, VAR1, enable, VAR2, VAR7, rst, VAR6, VAR4);
input clk;
input VAR1;
input enable;
input VAR2;
input VAR7;
input rst;
output [31:0] VAR6;
output VAR4;
reg [31:0] VAR3;
wire [31:0] VAR5;
assign VAR5[0] = VAR3[1];
assign VAR5[1] = VAR3[2];
assign VAR5[2] = VAR3[3];
assign VAR5[3] = VAR3[4];
assign VAR5... | gpl-2.0 |
silent-observer/RCPU | CPU/source/HeapRAM.v | 7,335 | module MODULE1 (
address,
VAR1,
VAR13,
VAR57,
VAR44,
VAR52);
input [11:0] address;
input [1:0] VAR1;
input VAR13;
input [15:0] VAR57;
input VAR44;
output [15:0] VAR52;
tri1 [1:0] VAR1;
tri1 VAR13;
wire [15:0] VAR43;
wire [15:0] VAR52 = VAR43[15:0];
VAR10 VAR40 (
.VAR15 (address),
.VAR38 (VAR1),
.VAR51 (VAR13),
.VAR24 (... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2/sky130_fd_sc_lp__mux2.behavioral.v | 1,604 | module MODULE1 (
VAR11 ,
VAR9,
VAR10,
VAR3
);
output VAR11 ;
input VAR9;
input VAR10;
input VAR3 ;
supply1 VAR12;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR8 ;
wire VAR6;
VAR7 VAR1 (VAR6, VAR9, VAR10, VAR3 );
buf VAR2 (VAR11 , VAR6);
endmodule | apache-2.0 |
lucasrangit/Robertsons_Multiplier | toprobertsons.v | 1,876 | module MODULE1(
input clk, reset,
input [7:0] VAR2, input [7:0] VAR1, output [15:0] VAR4, output VAR5 );
VAR3 VAR6(clk, reset, VAR2, VAR1, VAR4, VAR5);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4bb/sky130_fd_sc_hs__or4bb_4.v | 2,187 | module MODULE2 (
VAR2 ,
VAR9 ,
VAR8 ,
VAR5 ,
VAR6 ,
VAR4,
VAR7
);
output VAR2 ;
input VAR9 ;
input VAR8 ;
input VAR5 ;
input VAR6 ;
input VAR4;
input VAR7;
VAR1 VAR3 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR2 ,
VAR9 ,
VAR8 ,
VAR5,
VAR6
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4b/sky130_fd_sc_ls__nor4b.behavioral.v | 1,510 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR8 ,
VAR14 ,
VAR10
);
output VAR5 ;
input VAR2 ;
input VAR8 ;
input VAR14 ;
input VAR10;
supply1 VAR9;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR7 ;
wire VAR13 ;
wire VAR12;
not VAR11 (VAR13 , VAR10 );
nor VAR3 (VAR12, VAR2, VAR8, VAR14, VAR13);
buf VAR1 (VAR5 , VAR12 );
endmodule | apache-2.0 |
secworks/trng | src/rtl/trng_mixer.v | 33,515 | module MODULE1(
input wire clk,
input wire VAR62,
input wire VAR117,
input wire VAR66,
input wire [7 : 0] address,
input wire [31 : 0] VAR101,
output wire [31 : 0] VAR59,
output wire VAR125,
input wire VAR16,
input wire VAR152,
output wire VAR154,
input wire VAR69,
input wire VAR112,
input wire VAR172,
input wire [31 :... | bsd-2-clause |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/ucore/pps_if.v | 7,130 | module MODULE1
(
VAR25,VAR3,
VAR2,
VAR14,VAR19,VAR15,
VAR6,VAR18,
VAR10,VAR23,VAR26,
VAR22,VAR13,
VAR20,VAR12, VAR21 );
parameter VAR4 = VAR17;
parameter VAR7 = 0;
input VAR25;
input VAR3;
input VAR14;
input VAR15;
input VAR19;
input VAR2;
input VAR6; input [31:0] VAR18; input VAR10; input VAR23; input [31:0] VAR26;
ou... | mit |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/KeyboardCtrl_0/synth/KeyboardCtrl_0.v | 3,285 | module MODULE1 (
VAR7,
VAR4,
VAR8,
valid,
VAR5,
VAR1,
VAR9,
rst,
clk
);
output wire [7 : 0] VAR7;
output wire VAR4;
output wire VAR8;
output wire valid;
output wire VAR5;
inout wire VAR1;
inout wire VAR9;
input wire rst;
input wire clk;
VAR6 #(
.VAR2(100000000)
) VAR3 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.valid(val... | gpl-3.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/verilog/axi_vdma_v6_2_axis_dwidth_converter_v1_0_axisc_upsizer.v | 14,849 | module MODULE1 #
(
parameter VAR19 = "VAR22",
parameter integer VAR35 = 32,
parameter integer VAR24 = 96,
parameter integer VAR31 = 1,
parameter integer VAR44 = 1,
parameter integer VAR61 = 1,
parameter integer VAR50 = 3,
parameter [31:0] VAR58 = 32'hFF ,
parameter integer VAR34 = 3 )
(
input wire VAR15,
input wire VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfbbp/sky130_fd_sc_ms__dfbbp.functional.pp.v | 2,202 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR7 ,
VAR15 ,
VAR6 ,
VAR17,
VAR3 ,
VAR14 ,
VAR20 ,
VAR16
);
output VAR8 ;
output VAR10 ;
input VAR7 ;
input VAR15 ;
input VAR6 ;
input VAR17;
input VAR3 ;
input VAR14 ;
input VAR20 ;
input VAR16 ;
wire VAR1;
wire VAR9 ;
wire VAR4;
not VAR11 (VAR1 , VAR17 );
not VAR2 (VAR9 , VAR6 );
VAR5... | apache-2.0 |
monotone-RK/FACE | MCSoC-15/16-way/ise/ipcore_dir/dram/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_top.v | 66,901 | module MODULE1 #
(
parameter VAR219 = 100, parameter VAR69 = "0", parameter VAR50 = 3, parameter VAR119 = "8", parameter VAR384 = "VAR344", parameter VAR111 = "VAR81", parameter VAR65 = 1, parameter VAR117 = 5,
parameter VAR287 = 12, parameter VAR251 = 1, parameter VAR151 = 1, parameter VAR83 = 5,
parameter VAR188 = 8,... | mit |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_stub.v | 1,270 | module MODULE1(VAR2, VAR5, VAR3, VAR4, VAR1)
;
output VAR2;
output VAR5;
input VAR3;
output VAR4;
input VAR1;
endmodule | gpl-3.0 |
zeruniverse/pipelined_CPU | ISE project/cpu_top.v | 2,536 | module MODULE1(
input wire VAR18,rst,clk,
input wire [1:0] VAR43,
input wire [4:0] VAR53,
output wire VAR3,
output wire [5:0] VAR20,
output wire [3:0] VAR2,
output wire [7:0] VAR72
);
wire VAR78;
wire VAR57;
wire VAR55;
wire [31:0] VAR36;
reg [15:0] VAR73,VAR74=0;
wire [7:0] VAR38;
wire [31:0] VAR46;
wire [31:0] VAR28;... | gpl-3.0 |
skyfex/svo-raycaster | orlink/hw/orlink_top.v | 6,936 | module MODULE1
(
input VAR4,
input VAR18,
input VAR125,
inout [7:0] VAR110,
input VAR121,
input VAR32,
output VAR11,
output VAR66,
output VAR82,
output [1:0] VAR94,
output VAR88,
output [7:0] VAR120,
input [4:0] VAR132
);
wire VAR108;
wire VAR61;
assign VAR108 = ~VAR4;
wire VAR33;
wire VAR49, VAR78;
wire VAR111, VAR99;... | mit |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/mig_v3_4/user_design/rtl/ddr2_phy_ctl_io.v | 9,968 | module MODULE1 #
(
parameter VAR23 = 2,
parameter VAR20 = 1,
parameter VAR47 = 10,
parameter VAR17 = 1,
parameter VAR2 = 0,
parameter VAR42 = 1,
parameter VAR65 = 1,
parameter VAR33 = 14,
parameter VAR12 = 1
)
(
input VAR37,
input VAR63,
input VAR31,
input VAR46,
input [VAR33-1:0] VAR22,
input [VAR23-1:0] VAR11,
input ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32oi/sky130_fd_sc_hdll__a32oi.behavioral.v | 1,719 | module MODULE1 (
VAR12 ,
VAR16,
VAR5,
VAR11,
VAR14,
VAR4
);
output VAR12 ;
input VAR16;
input VAR5;
input VAR11;
input VAR14;
input VAR4;
supply1 VAR3;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR15 ;
wire VAR9 ;
wire VAR13 ;
wire VAR2;
nand VAR10 (VAR9 , VAR5, VAR16, VAR11 );
nand VAR17 (VAR13 , VAR4, VAR14 );
and VAR7 (V... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/dbg_interface/dbg_registers.v | 11,006 | module MODULE1(VAR21, VAR85, VAR2, VAR66, VAR11, VAR51, VAR63, VAR30,
VAR25,
VAR55, VAR4, VAR72, VAR91,
VAR68, VAR53, VAR31, VAR7, VAR54, VAR92,
VAR45, VAR73, VAR32, VAR77,
VAR90, VAR71, VAR35, VAR52,
VAR15, VAR76, VAR48, VAR1,
VAR46, VAR17, VAR41, VAR87,
VAR19, VAR39, VAR83, VAR13, VAR88, VAR12, VAR67,
VAR26, VAR69,
V... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cpu/jp.v | 4,015 | module MODULE1(
input clk, input rst,
input VAR6, input [15:0] VAR5, input VAR1, output reg [7:0] VAR13,
input [7:0] VAR3, input [7:0] VAR7 );
localparam [15:0] VAR11 = 16'h4016;
localparam [15:0] VAR8 = 16'h4017;
reg [15:0] VAR10;
wire VAR9;
reg VAR2;
reg [8:0] VAR12;
reg [8:0] VAR4;
assign VAR9 = (VAR10 != VAR5);
alw... | mit |
esonghori/TinyGarbled | circuit_synthesis/encoder/encoder.v | 1,089 | module MODULE2
parameter VAR2=4
)
(
VAR3,
VAR4,
VAR7
);
localparam VAR6 = 2**VAR2;
input [VAR6/2-1:0] VAR3;
input [VAR6/2-1:0] VAR4;
output [VAR2-1:0] VAR7;
wire [VAR6-1:0] in;
assign in[VAR6/2-1:0] = VAR3;
assign in[VAR6-1:VAR6/2] = VAR4;
MODULE2
.VAR2(VAR2)
)
VAR5
(
.in(in),
.VAR7(VAR7)
);
endmodule
module MODULE2
pa... | gpl-3.0 |
julioamerico/OpenCRC | src/rtl/crc_unit.v | 2,531 | module MODULE1
(
output [31:0] VAR26,
output [31:0] VAR27,
output [31:0] VAR7,
output [7:0] VAR16,
output VAR9,
output VAR11,
output VAR28,
input [31:0] VAR35,
input [ 1:0] VAR13,
input [ 1:0] VAR15,
input [ 1:0] VAR34,
input VAR30,
input VAR33,
input VAR22,
input VAR19,
input VAR25,
input VAR5,
input clk,
input VAR32
... | gpl-3.0 |
SymbiFlow/fpga-tool-perf | src/picosoc-spimemio/picosoc_spimemio_wrap.v | 2,045 | module MODULE1(input wire clk, input wire VAR22, input wire VAR15, output wire do);
localparam integer VAR11 = 66;
localparam integer VAR19 = 75;
reg [VAR11-1:0] din;
wire [VAR19-1:0] dout;
reg [VAR11-1:0] VAR26;
reg [VAR19-1:0] VAR1;
always @(posedge clk) begin
VAR26 <= {VAR26, VAR15};
VAR1 <= {VAR1, VAR26[VAR11-1]};
... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/bufinv/sky130_fd_sc_hd__bufinv.behavioral.v | 1,355 | module MODULE1 (
VAR8,
VAR9
);
output VAR8;
input VAR9;
supply1 VAR7;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR6 ;
wire VAR3;
not VAR5 (VAR3, VAR9 );
buf VAR2 (VAR8 , VAR3 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_2.functional.pp.v | 1,404 | module MODULE1( VAR3, VAR1, VAR10, VAR8, VAR9, VAR14, VAR16 );
input VAR9, VAR8, VAR3, VAR10;
inout VAR14, VAR16;
output VAR1;
wire VAR11;
not VAR4( VAR11, VAR9 );
wire VAR2;
not VAR6( VAR2, VAR8 );
wire VAR13;
not VAR15( VAR13, VAR3 );
wire VAR5;
not VAR7( VAR5, VAR10 );
and VAR12( VAR1, VAR11, VAR2, VAR13, VAR5 );
en... | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/Timer_Counter/Peripheral_clk_interruptor.v | 1,926 | module MODULE1(
input clk,
input rst,
input [15:0] din,
input VAR7,
input [3:0] addr,
input rd,
input wr,
output reg [15:0] dout
);
reg [5:0] VAR4;
reg [31:0] VAR6;
reg [31:0] VAR3;
reg en=0;
wire VAR8;
wire VAR1;
always @(*) begin
case (addr)
4'h0:begin VAR4 = (VAR7 && wr) ? 6'b000001 : 6'b000000 ;end 4'h2:begin VAR4 ... | mit |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_iq_fgen_block.v | 65,446 | module MODULE1 #(
parameter VAR33 = 11,
parameter VAR1 = 17,
parameter VAR4 = 32
)
(
input VAR35,
input VAR53,
input VAR52,
input VAR6,
input VAR2,
input VAR36,
input VAR37,
input [VAR4-1:0] VAR16,
input [VAR4-1:0] VAR8,
output [VAR1-1:0] VAR38 ,
output [VAR1-1:0] VAR39 ,
output [VAR1-1:0] VAR54 ,
output [VAR1-1:0] VAR... | mit |
alexforencich/xfcp | lib/eth/rtl/axis_eth_fcs.v | 3,781 | module MODULE1 #
(
parameter VAR8 = 8,
parameter VAR11 = (VAR8>8),
parameter VAR4 = (VAR8/8)
)
(
input wire clk,
input wire rst,
input wire [VAR8-1:0] VAR5,
input wire [VAR4-1:0] VAR6,
input wire VAR1,
output wire VAR9,
input wire VAR7,
input wire VAR3,
output wire [31:0] VAR2,
output wire VAR10
); | mit |
igalanommatis/zdma | hw/oled/src/SpiCtrl.v | 4,249 | module MODULE1(
VAR1,
VAR8,
VAR5,
VAR14,
VAR15,
VAR4,
VAR16
);
input VAR1;
input VAR8;
input VAR5;
input [7:0] VAR14;
output VAR15;
output VAR4;
output VAR16;
wire VAR15, VAR4, VAR16;
reg [39:0] VAR7 = "VAR9";
reg [7:0] VAR12 = 8'h00; reg [3:0] VAR6 = 4'h0; wire VAR10; reg [4:0] counter = 5'b00000; reg VAR13 = 1'b1;
re... | gpl-3.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/hdl/verilog/lane_init_sm_4byte.v | 16,306 | module MODULE1
(
VAR38,
VAR29,
VAR1,
VAR33,
VAR16,
VAR28,
VAR21,
VAR24,
VAR45,
VAR14,
VAR18,
VAR7,
VAR36,
VAR50,
VAR12,
VAR51,
VAR37,
VAR5,
VAR53
);
input [3:0] VAR38; input [3:0] VAR29; input [3:0] VAR1; input VAR33;
output VAR16; output VAR28; output VAR21;
output VAR24;
output VAR45; output VAR14;
input VAR18; input... | bsd-2-clause |
lsnow/mips32 | rom.v | 3,282 | module MODULE1(
VAR1,
VAR2,
clk);
parameter VAR3= 32;
parameter VAR4= 16;
input [VAR3-1:0] VAR1;
input clk;
output [VAR3-1:0] VAR2;
reg [VAR3-1:0] VAR2;
always @(posedge clk)
begin
case(VAR1)
32'h00000000 : VAR2<= 32'b11100100000000001111111111111111;
32'h00000004: VAR2<= 32'b11101000000000001111111111111111;
32'h00000... | gpl-2.0 |
dnet/proxmark3 | fpga/fpga_lf.v | 4,442 | module MODULE1(
input VAR63, output VAR74, input VAR64, input VAR58,
input VAR6, input VAR49, input VAR36,
output VAR42, output VAR54,
output VAR34, output VAR69, output VAR32, output VAR35,
input [7:0] VAR51, output VAR77, output VAR75,
output VAR33, output VAR45, input VAR83, output VAR7,
input VAR8, input VAR30,
out... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkbuf/sky130_fd_sc_ms__clkbuf_4.v | 2,034 | module MODULE2 (
VAR7 ,
VAR3 ,
VAR1,
VAR8,
VAR4 ,
VAR6
);
output VAR7 ;
input VAR3 ;
input VAR1;
input VAR8;
input VAR4 ;
input VAR6 ;
VAR2 VAR5 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR7,
VAR3
);
output VAR7;
input VAR3;
supply1 VAR1;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.v | 2,443 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR11 ,
VAR6 ,
VAR7 ,
VAR2 ,
VAR3,
VAR10,
VAR5 ,
VAR1
);
output VAR9 ;
output VAR4 ;
input VAR11 ;
input VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR3;
input VAR10;
input VAR5 ;
input VAR1 ;
VAR12 VAR8 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(V... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/ip_pcie/PCIeGen2x8If128_stub.v | 7,217 | module MODULE1(VAR69, VAR32, VAR63, VAR23, VAR73, VAR71, VAR8, VAR13, VAR68, VAR72, VAR75, VAR16, VAR11, VAR12, VAR70, VAR36, VAR29, VAR4, VAR77, VAR42, VAR10, VAR74, VAR57, VAR87, VAR49, VAR7, VAR9, VAR30, VAR56, VAR64, VAR19, VAR34, VAR81, VAR85, VAR44, VAR37, VAR6, VAR14, VAR55, VAR78, VAR66, VAR39, VAR25, VAR26, VA... | mit |
tommythorn/yari | shared/rtl/target/Cycore-ep1c12/main.v | 4,682 | module MODULE1(
input wire clk,
output wire VAR24,
input wire VAR71,
input wire VAR35,
output wire VAR22,
output wire VAR5,
output wire [17:0] VAR70,
inout wire [15:0] VAR21,
output wire VAR26,
output wire VAR64,
output wire VAR32,
output wire VAR44,
output wire VAR11,
output wire [17:0] VAR63,
inout wire [15:0] VAR4,
... | gpl-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Cache/L1/Valid_Ram.v | 1,260 | module MODULE1(
input VAR4,
input VAR12,
input [3:0] VAR7,
input VAR5,
input VAR3,
output VAR1,
input [7:0] VAR13,
output reg VAR2
);
VAR8#(4,1,16) VAR9(
.VAR4 (VAR4),
.VAR10 ((VAR2) ? 1'b1 : VAR3),
.VAR6 ((VAR2) ? VAR13[3:0] : VAR7),
.VAR14 ((VAR2) ? 1'b0 : VAR5),
.VAR11 (VAR1)
);
always @ (posedge VAR4) begin
if (VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbp/sky130_fd_sc_ls__dfbbp.functional.v | 1,931 | module MODULE1 (
VAR9 ,
VAR12 ,
VAR1 ,
VAR14 ,
VAR8 ,
VAR7
);
output VAR9 ;
output VAR12 ;
input VAR1 ;
input VAR14 ;
input VAR8 ;
input VAR7;
wire VAR3;
wire VAR15 ;
wire VAR4;
not VAR13 (VAR3 , VAR7 );
not VAR11 (VAR15 , VAR8 );
VAR2 VAR6 VAR10 (VAR4 , VAR15, VAR3, VAR14, VAR1);
buf VAR5 (VAR9 , VAR4 );
not VAR16 (VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_2.behavioral.pp.v | 7,224 | module MODULE1( VAR9, VAR11, VAR1, VAR4, VAR7, VAR5, VAR10, VAR8, VAR6 );
input VAR5, VAR10, VAR4, VAR7, VAR11, VAR1;
inout VAR8, VAR6;
output VAR9;
VAR12 VAR3(.VAR9(VAR9),.VAR11(VAR11),.VAR1(VAR1),.VAR4(VAR4),.VAR7(VAR7),.VAR5(VAR5),.VAR10(VAR10),.VAR8(VAR8),.VAR6(VAR6));
VAR12 VAR2(.VAR9(VAR9),.VAR11(VAR11),.VAR1(VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3b/sky130_fd_sc_hd__nand3b.functional.pp.v | 1,971 | module MODULE1 (
VAR11 ,
VAR4 ,
VAR9 ,
VAR15 ,
VAR16,
VAR2,
VAR13 ,
VAR3
);
output VAR11 ;
input VAR4 ;
input VAR9 ;
input VAR15 ;
input VAR16;
input VAR2;
input VAR13 ;
input VAR3 ;
wire VAR14 ;
wire VAR1 ;
wire VAR6;
not VAR7 (VAR14 , VAR4 );
nand VAR12 (VAR1 , VAR9, VAR14, VAR15 );
VAR10 VAR8 (VAR6, VAR1, VAR16, VAR... | apache-2.0 |
efabless/openlane | designs/151/src/controller.v | 12,289 | module MODULE1(
input clk,
input reset,
input VAR33,
input VAR8,
input wire [6:0] VAR56,
input wire [6:0] VAR32,
input wire [6:0] VAR26,
input wire [4:0] VAR31,
input wire [4:0] VAR62,
input wire [4:0] VAR15,
input wire [4:0] VAR2,
input wire [4:0] VAR16,
input wire [4:0] VAR37,
input wire [4:0] VAR4,
input wire [4:0] ... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/bw_clk_cclk_inv_64x.v | 1,292 | module MODULE1 (
VAR1,
VAR2 );
output VAR1;
input VAR2;
assign VAR1 = ~( VAR2 );
endmodule | gpl-2.0 |
saiedhk/WhirlpoolHashEngine | whirlpool_wcipher_mu.v | 3,339 | module MODULE1 (
output [7:0] VAR17, VAR35, VAR23, VAR10, VAR58, VAR39, VAR14, VAR40,
VAR4, VAR57, VAR48, VAR25, VAR37, VAR46, VAR61, VAR36,
VAR49, VAR65, VAR32, VAR3, VAR2, VAR52, VAR33, VAR64,
VAR41, VAR56, VAR55, VAR59, VAR11, VAR42, VAR28, VAR47,
VAR62, VAR50, VAR54, VAR60, VAR30, VAR19, VAR20, VAR63,
VAR45, VAR26,... | mit |
fpgaminer/fpgaminer-vanitygen | cores/vanitygen-serial/address_hash.v | 1,425 | module MODULE1 (
input clk,
input VAR3,
input [255:0] VAR14,
input [255:0] VAR4,
output VAR13,
output [159:0] VAR10
);
reg VAR1 = 1'b1;
wire VAR7;
wire [255:0] VAR5;
VAR8 VAR9 (
.clk (clk),
.VAR3 (VAR3),
.VAR6 ({7'h1, VAR4[0], VAR14}),
.VAR13 (VAR7),
.VAR10 (VAR5)
);
VAR11 VAR12 (
.clk (clk),
.VAR3 (VAR3 | VAR1),
.VAR2... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/Video_System/submodules/Video_System_CPU_jtag_debug_module_tck.v | 8,220 | module MODULE1 (
VAR37,
VAR23,
VAR29,
VAR14,
VAR10,
VAR40,
VAR28,
VAR8,
VAR35,
VAR4,
VAR13,
VAR31,
VAR22,
VAR11,
VAR1,
VAR24,
VAR6,
VAR39,
VAR17,
VAR18,
VAR38,
VAR20,
VAR5,
VAR12,
VAR34,
VAR21,
VAR32,
VAR2,
VAR26,
VAR3,
VAR16
)
;
output [ 1: 0] VAR32;
output VAR2;
output [ 37: 0] VAR26;
output VAR3;
output VAR16;
input... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/models/SRLC16E.v | 1,568 | module MODULE1 (VAR20, VAR2, VAR11, VAR14, VAR12, VAR10, VAR9, VAR5, VAR21);
parameter VAR18 = 16'h0000;
output VAR20, VAR2;
input VAR11, VAR14, VAR12, VAR10, VAR9, VAR5, VAR21;
reg [15:0] VAR8;
wire [3:0] addr;
wire VAR7;
buf VAR6 (addr[3], VAR10);
buf VAR15 (addr[2], VAR12);
buf VAR1 (addr[1], VAR14);
buf VAR13 (addr... | gpl-2.0 |
ptracton/wb_soc_template | rtl/wb_ram/rtl/verilog/wb_ram.v | 2,532 | module MODULE1
parameter VAR22 = 256,
parameter VAR16 = VAR19(VAR22),
parameter VAR26 = "")
(input VAR12,
input VAR35,
input [VAR16-1:0] VAR10,
input [VAR1-1:0] VAR32,
input [3:0] VAR7,
input VAR21,
input [1:0] VAR6,
input [2:0] VAR33,
input VAR30,
input VAR11,
output reg VAR28,
output VAR39,
output [VAR1-1:0] VAR31);
... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_rf16x160.v | 27,115 | module MODULE2(
dout, VAR29, VAR65,
din, VAR46, VAR47, VAR26, VAR15, VAR37, VAR42,
VAR19, VAR13, VAR59, VAR11, VAR6, VAR71, VAR70, VAR2
);
input [159:0] din; input [3:0] VAR46; input [3:0] VAR47; input VAR26;
input VAR15; input VAR37 ; input [3:0] VAR42; input [19:0] VAR19; input VAR13;
input VAR59;
input VAR11, VAR6, ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22a/sky130_fd_sc_lp__o22a.blackbox.v | 1,356 | module MODULE1 (
VAR6 ,
VAR7,
VAR5,
VAR4,
VAR1
);
output VAR6 ;
input VAR7;
input VAR5;
input VAR4;
input VAR1;
supply1 VAR9;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
sehugg/8bitworkshop | presets/verilog/chardisplay.v | 1,858 | module MODULE1(clk, reset, VAR10, VAR14, VAR15);
input clk, reset;
output VAR10, VAR14;
output [2:0] VAR15;
wire VAR19;
wire [8:0] VAR21;
wire [8:0] VAR12;
wire [9:0] VAR2;
wire [7:0] VAR16;
reg [7:0] VAR25;
reg VAR20 = 0;
VAR8 VAR26(
.clk(clk),
.dout(VAR16),
.din(VAR25),
.addr(VAR2),
.VAR17(VAR20)
);
VAR4 VAR11(
.clk(... | gpl-3.0 |
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