repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai_1.v | 2,427 | module MODULE2 (
VAR6 ,
VAR7,
VAR11,
VAR8 ,
VAR4 ,
VAR2,
VAR3,
VAR5 ,
VAR1
);
output VAR6 ;
input VAR7;
input VAR11;
input VAR8 ;
input VAR4 ;
input VAR2;
input VAR3;
input VAR5 ;
input VAR1 ;
VAR10 VAR9 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VA... | apache-2.0 |
bigeagle/riffa | fpga/xilinx/vc707/riffa_wrapper_vc707.v | 37,829 | module MODULE1
parameter VAR326 = 128,
parameter VAR2 = 256,
parameter VAR207 = 5
)
(
input [VAR326-1:0] VAR176,
input [(VAR326/8)-1:0] VAR48,
input VAR152,
input VAR103,
output VAR44,
input [VAR334-1:0] VAR335,
output VAR149,
output VAR214,
output [VAR326-1:0] VAR225,
output [(VAR326/8)-1:0] VAR60,
output VAR16,
outpu... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/edfxbp/sky130_fd_sc_ls__edfxbp.blackbox.v | 1,378 | module MODULE1 (
VAR2 ,
VAR7,
VAR4,
VAR6 ,
VAR3
);
output VAR2 ;
output VAR7;
input VAR4;
input VAR6 ;
input VAR3 ;
supply1 VAR5;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311a/sky130_fd_sc_lp__o311a_2.v | 2,422 | module MODULE2 (
VAR10 ,
VAR12 ,
VAR4 ,
VAR3 ,
VAR8 ,
VAR11 ,
VAR9,
VAR7,
VAR1 ,
VAR2
);
output VAR10 ;
input VAR12 ;
input VAR4 ;
input VAR3 ;
input VAR8 ;
input VAR11 ;
input VAR9;
input VAR7;
input VAR1 ;
input VAR2 ;
VAR6 VAR5 (
.VAR10(VAR10),
.VAR12(VAR12),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR11(VAR11),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxbp/sky130_fd_sc_hdll__sdfxbp.pp.symbol.v | 1,442 | module MODULE1 (
input VAR8 ,
output VAR7 ,
output VAR1 ,
input VAR9 ,
input VAR6 ,
input VAR4 ,
input VAR3 ,
input VAR2,
input VAR10,
input VAR5
);
endmodule | apache-2.0 |
jon-whit/4-bit_comp | verilog modules/cpu_controller.v | 7,059 | module MODULE1(clk, VAR37, VAR25, VAR21, VAR20, VAR5, VAR2, VAR18, VAR4, VAR10,
VAR1, VAR17, VAR6, VAR19, VAR42, VAR38, VAR9, VAR40, VAR41);
input clk, VAR37, VAR5, VAR2;
input [7:0] VAR21; input [7:0] VAR20;
input [1:0] VAR25;
output reg VAR18, VAR1, VAR17, VAR6, VAR19, VAR42, VAR41;
output reg [3:0] VAR4, VAR10;
outp... | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/Tiger4NSC/src/CompletionDataChannel.v | 7,148 | module MODULE1
(
parameter VAR6 = 32 ,
parameter VAR26 = 16 ,
parameter VAR7 = 1
)
(
VAR10 ,
VAR1 ,
VAR14 ,
VAR30 ,
VAR16 ,
VAR21 ,
VAR34 ,
VAR23 ,
VAR24 ,
VAR17 ,
VAR22 ,
VAR9 ,
VAR29 ,
VAR3
);
input VAR10 ;
input VAR1 ;
input [4:0] VAR30 ;
input [VAR26 - 1:0] VAR14 ;
input VAR16 ;
output VAR21 ;
input [VAR6 - 1:0] VA... | gpl-3.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | contador_AD_HH_2dig.v | 2,936 | module MODULE1
(
input wire clk,
input wire reset,
input wire [3:0]VAR4,
input wire VAR3,
input wire VAR8,
output wire [7:0] VAR5);
localparam VAR2 = 5; reg [VAR2-1:0] VAR9, VAR1;
wire [VAR2-1:0] VAR10;
reg [3:0] VAR6, VAR7;
always@(posedge clk, posedge reset)
begin
if(reset)
begin
VAR9 <= 5'b0;
end
else
begin
VAR9 <= ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxtp/sky130_fd_sc_ms__dfxtp.pp.blackbox.v | 1,279 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR2 ,
VAR7,
VAR1,
VAR5 ,
VAR4
);
output VAR6 ;
input VAR3 ;
input VAR2 ;
input VAR7;
input VAR1;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_2.functional.v | 1,046 | module MODULE1( VAR6, VAR3, VAR7 );
input VAR7, VAR6;
output VAR3;
wire VAR1;
not VAR4( VAR1, VAR7 );
wire VAR8;
not VAR2( VAR8, VAR6 );
or VAR5( VAR3, VAR1, VAR8 );
endmodule | apache-2.0 |
tejchava1460/Evaluation-Project-for-ASIC-FPGA-Design-Engineer | Verilog_Noise_generator/log_impltn.v | 1,291 | module MODULE1(VAR11, VAR7, clk);
input [47:0]VAR11;
input clk;
output [30:0]VAR7;
reg [30:0]VAR7;
reg [7:0]VAR1;
reg [47:0]VAR10;
reg [113:0]VAR13, VAR6, VAR2, VAR5;
reg [65:0]VAR6;
reg [15:0]VAR4;
reg [18:0]VAR12;
reg [33:0]VAR12, VAR5;
reg [34:0]VAR14;
reg [16:0]VAR15;
reg [16:0]VAR3, VAR9;
reg [48:0]VAR10;
integer ... | gpl-3.0 |
mda-ut/SubZero | fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/DE0_Nano_SOPC_cpu_jtag_debug_module_sysclk.v | 6,946 | module MODULE1 (
clk,
VAR10,
VAR3,
VAR21,
VAR30,
VAR25,
VAR26,
VAR18,
VAR29,
VAR16,
VAR17,
VAR7,
VAR24,
VAR22,
VAR13,
VAR23,
VAR14,
VAR11,
VAR12
)
;
output [ 37: 0] VAR25;
output VAR26;
output VAR18;
output VAR29;
output VAR16;
output VAR17;
output VAR7;
output VAR24;
output VAR22;
output VAR13;
output VAR23;
output VA... | mit |
gajjanag/6111_Project | src/vga.v | 2,787 | module MODULE1(input VAR9,
output reg [9:0] VAR19, output reg [9:0] VAR8, output reg VAR13,VAR14,VAR4);
parameter VAR20 = 10'd639;
parameter VAR2 = 10'd655;
parameter VAR23 = 10'd751;
parameter VAR10 = 10'd799;
parameter VAR25 = 10'd479;
parameter VAR18 = 10'd490;
parameter VAR26 = 10'd492;
parameter VAR7 = 10'd523;
re... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_vref_logic.v | 2,747 | module MODULE1(VAR4 ,VAR17 ,VAR36 ,VAR23 ,VAR3 );
output [7:0] VAR17 ;
input VAR4 ;
input VAR36 ;
input VAR23 ;
input VAR3 ;
wire VAR9 ;
wire VAR24 ;
wire VAR22 ;
wire VAR2 ;
wire VAR33 ;
wire VAR30 ;
wire VAR25 ;
wire VAR7 ;
wire VAR20 ;
wire VAR34 ;
wire VAR35 ;
VAR19 VAR16 (
.VAR15 (VAR9 ),
.VAR4 (VAR4 ),
.VAR23 (VA... | gpl-2.0 |
Blunk-electronic/M-1 | HW/ise/trc_mini/src/i2c_slave.v | 2,498 | module MODULE1 (VAR4, VAR11, VAR12, VAR1, reset, VAR6);
inout VAR4; input VAR11;
input reset;
input [6:0] VAR1; output reg [7:0] VAR12;
output VAR6;
reg VAR13 = 1; reg VAR5 = 1; reg [4:0] VAR9 = -1; reg [6:0] address = -1;
reg [7:0] VAR2 = -1;
wire VAR8;
wire VAR3 ;
assign VAR3 = !VAR8;
wire VAR10 ;
assign VAR10 = !VAR... | gpl-2.0 |
binderclip/BCOpenMIPS | cpu-code/mem.v | 12,160 | module MODULE1 (
input wire rst,
input wire[VAR46] VAR51,
input wire VAR60,
input wire[VAR58] VAR56,
input wire VAR24,
input wire[VAR58] VAR15,
input wire[VAR58] VAR54,
input wire[VAR66] VAR14,
input wire[VAR58] VAR30,
input wire[VAR58] VAR2,
input wire[VAR58] VAR57,
input wire VAR47,
input wire VAR61,
input wire VAR55... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4/sky130_fd_sc_lp__and4_4.v | 2,242 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR3 ,
VAR2 ,
VAR11 ,
VAR5,
VAR9,
VAR6 ,
VAR8
);
output VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR2 ;
input VAR11 ;
input VAR5;
input VAR9;
input VAR6 ;
input VAR8 ;
VAR10 VAR7 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR... | apache-2.0 |
ncos/Xilinx-Verilog | INTERFACES/src/CAN/queue.v | 2,990 | module MODULE1 #
(
parameter integer VAR14 = 108,
parameter integer VAR12 = 4
)
(
input wire VAR16,
input wire VAR11,
input wire VAR4,
input wire VAR3,
output reg VAR5 = 1'b0,
output reg VAR1 = 1'b1,
input wire [VAR14-1:0] VAR15,
output reg [VAR14-1:0] VAR9
);
reg [VAR14-1:0] VAR7[0:VAR12-1];
reg [63:0] head = 64'd0;
r... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/decap/sky130_fd_sc_hd__decap.pp.blackbox.v | 1,198 | module MODULE1 (
VAR1,
VAR2,
VAR3 ,
VAR4
);
input VAR1;
input VAR2;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/phy/phy_init.v | 138,478 | module MODULE1 #
(
parameter VAR23 = 100,
parameter VAR127 = 4, parameter VAR72 = 3000, parameter VAR87 = 0, parameter VAR166 = 64, parameter VAR313 = 2,
parameter VAR121 = 10,
parameter VAR277 = 1, parameter VAR10 = 64,
parameter VAR160 = 8,
parameter VAR297 = 3, parameter VAR48 = 14,
parameter VAR7 = 1,
parameter VAR... | lgpl-3.0 |
joaocarlos/udlx-verilog | rtl/decode/control.v | 2,789 | module MODULE1
parameter VAR3 = 5
)
(
input VAR10,
input [VAR3-1:0] VAR8,
input VAR4,
input VAR1,
input [VAR3-1:0] VAR2,
input [VAR3-1:0] VAR13,
input VAR6,
output reg VAR11,
output reg VAR5,
output reg VAR7,
output reg VAR12
);
wire VAR9;
assign VAR9 = VAR10 &
(((VAR8==VAR2)&VAR4)|
((VAR8==VAR13)&VAR1));
always@(*)beg... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xor3/sky130_fd_sc_ms__xor3.pp.symbol.v | 1,315 | module MODULE1 (
input VAR8 ,
input VAR1 ,
input VAR4 ,
output VAR3 ,
input VAR6 ,
input VAR5,
input VAR7,
input VAR2
);
endmodule | apache-2.0 |
Ribeiro/sd2snes | verilog/sd2snes_cx4/mcu_cmd.v | 12,874 | module MODULE1(
input clk,
input VAR28,
input VAR51,
input [7:0] VAR23,
input [7:0] VAR9,
output [2:0] VAR40,
output VAR22,
output VAR34,
output VAR5,
input VAR2,
output [7:0] VAR25,
input [7:0] VAR3,
output [7:0] VAR38,
input [31:0] VAR18,
input [2:0] VAR26,
output [23:0] VAR37,
output [23:0] VAR44,
output [23:0] VAR1... | gpl-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/rw_manager_ac_ROM_no_ifdef_params.v | 3,035 | module MODULE1 (
VAR42,
VAR47,
VAR35,
VAR37,
VAR62,
VAR17);
parameter VAR56 = "VAR45.VAR1";
input VAR42;
input [31:0] VAR47;
input [5:0] VAR35;
input [5:0] VAR37;
input VAR62;
output [31:0] VAR17;
tri1 VAR42;
tri0 VAR62;
wire [31:0] VAR27;
wire [31:0] VAR17 = VAR27[31:0];
VAR28 VAR21 (
.VAR64 (VAR37),
.VAR60 (VAR42),
.... | gpl-3.0 |
kevintownsend/convey_spmv | rtl/pe/x_vector_cache.v | 4,514 | module MODULE1(clk, rst, VAR29, VAR51, VAR3, VAR6, VAR33, VAR4, VAR49, VAR8, VAR45, VAR31, VAR2);
parameter VAR12 = 8; parameter VAR5 = VAR14(VAR12 - 1);
parameter VAR42 = 16;
input clk;
input rst;
input [31:0] VAR29;
input VAR51;
input [47:0] VAR3;
output VAR6;
output [47:0] VAR33;
input VAR4;
input [63:0] VAR49;
outp... | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/bus/rtl/bus_master_mux.v | 2,878 | module MODULE1 (
input wire [VAR9] VAR21, input wire VAR17, input wire VAR8, input wire [VAR2] VAR30, input wire VAR18, input wire [VAR9] VAR13, input wire VAR23, input wire VAR27, input wire [VAR2] VAR10, input wire VAR16, input wire [VAR9] VAR6, input wire VAR29, input wire VAR26, input wire [VAR2] VAR20, input wire ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111oi/sky130_fd_sc_hs__a2111oi.behavioral.pp.v | 1,983 | module MODULE1 (
VAR14,
VAR4,
VAR1 ,
VAR3 ,
VAR5 ,
VAR16 ,
VAR9 ,
VAR13
);
input VAR14;
input VAR4;
output VAR1 ;
input VAR3 ;
input VAR5 ;
input VAR16 ;
input VAR9 ;
input VAR13 ;
wire VAR9 VAR2 ;
wire VAR12 ;
wire VAR6;
and VAR7 (VAR2 , VAR3, VAR5 );
nor VAR15 (VAR12 , VAR16, VAR9, VAR13, VAR2 );
VAR8 VAR10 (VAR6, VA... | apache-2.0 |
thinkoco/de1_soc_opencl | de10_standard_sharedonly_vga/ip/TERASIC_AUDIO/AUDIO_ADC.v | 3,989 | module MODULE1(
clk,
reset,
read,
VAR10,
VAR8,
VAR17,
VAR11,
VAR21,
VAR25
);
parameter VAR19 = 32;
input clk;
input reset;
input read;
output [(VAR19-1):0] VAR10;
output VAR8;
input VAR17;
input VAR11;
input VAR21;
input VAR25;
reg [4:0] VAR7; reg VAR2;
reg VAR4;
reg [(VAR19-1):0] VAR14;
reg [(VAR19-1):0] VAR23;
reg VA... | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/tec-drums/i2s_out.v | 1,786 | module MODULE1(input VAR6, input reset, input[15:0] VAR3,
input[15:0] VAR5, output VAR4, output VAR2, output VAR7, output reg VAR8);
reg [3:0] VAR1;
begin
begin
begin
begin
end
begin
begin
begin
end
begin | mit |
AmeerAbdelhadi/2D-Binary-Content-Addressable-Memory-BCAM | mwram_gen.v | 4,365 | module MODULE1
localparam VAR8 = VAR3*VAR9/VAR2 ; localparam VAR1 = VAR4(VAR8) ; localparam VAR5 = VAR4(VAR3) ; localparam VAR10 = VAR4(VAR9/VAR2);
reg [VAR9-1:0] VAR6 [0:VAR3-1]; integer VAR7; | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31oi/sky130_fd_sc_hd__a31oi_1.v | 2,350 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR1 ,
VAR11 ,
VAR6 ,
VAR8,
VAR9,
VAR4 ,
VAR7
);
output VAR3 ;
input VAR5 ;
input VAR1 ;
input VAR11 ;
input VAR6 ;
input VAR8;
input VAR9;
input VAR4 ;
input VAR7 ;
VAR10 VAR2 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfbbn/sky130_fd_sc_hd__dfbbn_2.v | 2,601 | module MODULE2 (
VAR8 ,
VAR4 ,
VAR6 ,
VAR5 ,
VAR1 ,
VAR10,
VAR2 ,
VAR3 ,
VAR9 ,
VAR11
);
output VAR8 ;
output VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR1 ;
input VAR10;
input VAR2 ;
input VAR3 ;
input VAR9 ;
input VAR11 ;
VAR7 VAR12 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlrtp/sky130_fd_sc_hvl__dlrtp.pp.blackbox.v | 1,403 | module MODULE1 (
VAR3 ,
VAR7,
VAR1 ,
VAR4 ,
VAR6 ,
VAR5 ,
VAR2 ,
VAR8
);
output VAR3 ;
input VAR7;
input VAR1 ;
input VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR8 ;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/FastMultiplier-master/BoothPPG_32R4.v | 2,256 | module MODULE1(VAR25 ,VAR44, VAR23,
VAR6, VAR34, VAR19, VAR24, VAR4,
VAR29, VAR41, VAR26, VAR2,
VAR16, VAR7, VAR1, VAR22,
VAR36, VAR28, VAR9, VAR40,
VAR38);
input wire[31:0] VAR25;
input wire[31:0] VAR44;
input wire VAR23;
output wire[15:0] VAR6;
output wire[33:0] VAR34;
output wire[33:0] VAR19;
output wire[33:0] VAR24... | gpl-3.0 |
Jawanga/ece385lab9 | lab9_soc/synthesis/submodules/lab9_soc_sysid_qsys_0.v | 1,454 | module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1428568153 : 0;
endmodule | apache-2.0 |
trun/fpgaboy | src/tv80/rtl/core/tv80s.v | 5,324 | module MODULE1 (
VAR23, VAR39, VAR9, VAR42, VAR15, VAR28, VAR18, VAR38, VAR16, do,
VAR27, VAR13, VAR19, VAR6, VAR25, VAR5, VAR26, VAR22, VAR29, VAR21,
VAR20, clk, VAR14, VAR1, VAR36, VAR4, VAR8
);
parameter VAR37 = 3; parameter VAR12 = 1; parameter VAR30 = 1;
input VAR20;
input clk;
input VAR14;
input VAR1;
input VAR36... | mit |
Proxmark/proxmark3 | fpga/hi_get_trace.v | 3,245 | module MODULE1(
VAR14,
VAR20, VAR13, VAR15,
VAR2, VAR7, VAR17
);
input VAR14;
input [7:0] VAR20;
input VAR13;
input [2:0] VAR15;
output VAR2, VAR7, VAR17;
reg [6:0] VAR10;
always @(negedge VAR14)
begin
VAR10 <= VAR10 + 1;
end
reg [2:0] VAR5;
always @(negedge VAR14)
begin
if (VAR5 == 3'd7)
VAR5 <= 3'd0;
end
else
VAR5 <=... | gpl-2.0 |
freecores/eco32 | fpga/src/kbd/keyboard.v | 3,114 | module MODULE1(VAR13, VAR25,
clk, reset,
VAR14, VAR22);
input VAR13;
input VAR25;
input clk;
input reset;
output [7:0] VAR14;
output VAR22;
reg VAR23;
reg VAR16;
reg VAR15;
reg VAR20;
wire [3:0] VAR11;
reg [3:0] VAR3;
reg VAR5;
reg VAR12;
wire VAR1;
wire VAR24;
wire VAR9;
wire [9:0] VAR21;
reg [9:0] VAR4;
wire [12:0] V... | bsd-2-clause |
shaform/ArkanoidOnVerilog | Arkanoid.v | 3,519 | module MODULE1(
input VAR65,
input VAR7, VAR80, VAR48, VAR27,
input [3:0] VAR92,
input VAR95, VAR104,
output VAR85, VAR112, VAR66, VAR121, VAR32,
output [7:0] VAR89
);
localparam VAR20 = 2;
localparam VAR86 = 2;
reg VAR39;
wire VAR87, VAR2;
wire [4:0] VAR4;
wire [9:0] VAR11, VAR107, VAR29, VAR113;
wire reset, VAR61, VA... | gpl-3.0 |
GSejas/Aproximate-Arithmetic-Operators | src_lib/multlib/KOA_1c_approx.v | 6,381 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR17,
input wire [VAR27-1:0] VAR31,
input wire [VAR27-1:0] VAR40,
output wire [2*VAR27-1:0] VAR4
);
wire [1:0] VAR3;
wire [3:0] VAR36;
assign VAR3 = 2'b00;
assign VAR36 = 4'b0000;
wire [VAR27/2-1:0] VAR28;
wire [VAR27/2:0] VAR21;
wire [VAR27/2-3:0] VAR25;
wir... | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/system_acl_iface_hps_hps_io.v | 6,754 | module MODULE1 (
output wire [14:0] VAR7, output wire [2:0] VAR33, output wire VAR4, output wire VAR10, output wire VAR40, output wire VAR26, output wire VAR25, output wire VAR13, output wire VAR16, output wire VAR31, inout wire [31:0] VAR22, inout wire [3:0] VAR42, inout wire [3:0] VAR9, output wire VAR14, output wire... | mit |
carstenbru/fpga-log | spartanmc/hardware/contrast_box/src/contrast_box_in_out.v | 6,177 | module MODULE1 #(parameter VAR16 = 16000000,
parameter VAR37 = 1000,
parameter VAR13 = 3, parameter VAR22 = 11,
parameter VAR9 = 100, parameter VAR6 = 11,
parameter VAR4 = 5, parameter VAR42 = 11,
parameter VAR35 = 10,
parameter VAR28 = 1023, parameter VAR32 = 17) (
input wire clk, input wire reset, input wire VAR30, i... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ffu/rtl/sparc_ffu.v | 30,781 | module MODULE1 (
VAR76, VAR127, VAR150, VAR121,
VAR13, VAR73, VAR86,
VAR2, VAR8, VAR91,
VAR55, VAR65, VAR30,
VAR113, VAR43, VAR162,
VAR66, VAR87, VAR167,
VAR101, VAR112, VAR108, VAR72,
VAR67, VAR145,
VAR141, VAR63, VAR110, VAR129, VAR17, VAR71,
VAR143, VAR128, VAR11,
VAR111, VAR78, VAR52,
VAR45, VAR105, VAR166,
VAR164,... | gpl-2.0 |
hakehuang/pycpld | ips/ip/i2c_master_two_ad/I2C_wr.v | 10,793 | module MODULE1(
VAR54,VAR52,ack,VAR9,clk,VAR35,VAR47,VAR41,VAR18
);
input VAR9,VAR35,VAR47,clk;
input VAR18;
output VAR52,ack;
inout [7:0] VAR41;
inout VAR54;
reg VAR22,VAR30;
reg[7:0] VAR20;
reg VAR52,ack,VAR53,VAR5,VAR2;
reg VAR6;
reg VAR12;
reg[8:0] VAR51;
reg[9:0] VAR43;
reg VAR27;
reg[6:0] VAR38;
reg[7:0] VAR17;
r... | mit |
trivoldus28/pulsarch-verilog | design/sys/edk_bee3/pcores/aurora_201_pcore_v1_00_a/hdl/verilog/aurora_201_idle_and_ver_gen.v | 11,627 | module MODULE1
(
VAR30,
VAR1,
VAR26,
VAR36,
VAR37,
VAR38,
VAR32,
VAR25
);
input VAR30;
output VAR1;
output VAR26;
output [0:1] VAR36;
output [0:1] VAR37;
output [0:1] VAR38;
input VAR32;
input VAR25;
reg [0:3] VAR2;
reg [0:3] VAR17;
reg VAR34;
reg VAR23;
wire VAR7;
wire VAR4;
wire VAR22;
wire [0:2] VAR5;
wire [0:1] VAR... | gpl-2.0 |
SergKolo/msudenver_eet_4020_verilog | LAB_4/eight_bit_counter.v | 3,139 | module MODULE1(VAR6,enable,VAR17,VAR16);
input enable,VAR17,VAR16;
output [7:0] VAR6;
wire [6:0] VAR5;
wire VAR13;
MODULE2 MODULE1(VAR13,VAR17);
VAR10 VAR1(VAR6[0],enable,VAR13,VAR16);
assign VAR5[0] = VAR6[0] & enable;
VAR10 VAR2(VAR6[1],VAR5[0],VAR13,VAR16);
assign VAR5[1] = VAR5[0] & VAR6[1];
VAR10 VAR8(VAR6[2],VAR5... | mit |
asicguy/gplgpu | hdl/altera_project/dpram_64_32x32/dpram_64_32x32_bb.v | 7,216 | module MODULE1 (
VAR1,
VAR4,
VAR7,
VAR5,
VAR3,
VAR6,
VAR2);
input [31:0] VAR1;
input VAR4;
input [4:0] VAR7;
input [3:0] VAR5;
input VAR3;
input VAR6;
output [63:0] VAR2;
endmodule | gpl-3.0 |
vvk/sysrek | hdmi_example/src/hdmi_main.v | 10,867 | module MODULE1
(
input wire VAR7, input wire VAR73,
input wire [3:0] VAR88,
input wire [3:0] VAR117,
output wire [3:0] VAR146,
output wire [3:0] VAR18,
output wire [7:0] VAR99
);
wire VAR1, VAR71;
VAR25 #(.VAR152("VAR44"), .VAR24(5))
VAR114 (.VAR116(VAR71), .VAR15(), .VAR128(), .VAR121(VAR73));
VAR110 VAR76 (.VAR121(VA... | gpl-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/synthesis/submodules/altera_up_video_scaler_multiply_width.v | 7,790 | module MODULE1 (
clk,
reset,
VAR6,
VAR12,
VAR15,
VAR3,
VAR14,
VAR8,
VAR11,
VAR4,
VAR16,
VAR1
);
parameter VAR9 = 15;
parameter VAR2 = 0;
input clk;
input reset;
input [VAR9: 0] VAR6;
input VAR12;
input VAR15;
input VAR3;
input VAR14;
output VAR8;
output reg [VAR9: 0] VAR11;
output reg VAR4;
output reg VAR16;
output reg... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pipe_eq.v | 35,592 | module MODULE1 #
(
parameter VAR104 = "VAR88",
parameter VAR54 = "VAR76",
parameter VAR109 = 1
)
(
input VAR30,
input VAR112,
input VAR3,
input [ 1:0] VAR40,
input [ 3:0] VAR41,
input [ 3:0] VAR20,
input [ 5:0] VAR128,
input [ 1:0] VAR7,
input [ 2:0] VAR107,
input [ 5:0] VAR22,
input [ 3:0] VAR98,
input VAR83,
input [1... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_116.v | 1,562 | module MODULE2 (
VAR6,
VAR12
);
input [31:0] VAR6;
output [31:0]
VAR12;
wire [31:0]
VAR4,
VAR15,
VAR5,
VAR8,
VAR13,
VAR10,
VAR14,
VAR9,
VAR1,
VAR3;
assign VAR4 = VAR6;
assign VAR5 = VAR15 - VAR4;
assign VAR15 = VAR4 << 10;
assign VAR9 = VAR14 << 2;
assign VAR8 = VAR4 << 11;
assign VAR3 = VAR1 << 3;
assign VAR1 = VAR13 ... | mit |
fallen/milkymist-mmu | cores/hpdmc_ddr32/rtl/hpdmc.v | 5,508 | module MODULE1 #(
parameter VAR48 = 4'h0,
parameter VAR39 = 26,
parameter VAR1 = 9
) (
input VAR15,
input VAR74,
input VAR22,
input [13:0] VAR20,
input VAR73,
input [31:0] VAR16,
output [31:0] VAR46,
input [VAR39-1:0] VAR27,
input VAR18,
input VAR68,
output VAR43,
input [7:0] VAR2,
input [63:0] VAR21,
output [63:0] VAR... | lgpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_hdmi_rx/axi_hdmi_rx.v | 7,574 | module MODULE1 (
VAR29,
VAR36,
VAR57,
VAR23,
VAR39,
VAR41,
VAR48,
VAR77,
VAR8,
VAR90,
VAR82,
VAR35,
VAR20,
VAR37,
VAR89,
VAR97,
VAR19,
VAR18,
VAR70,
VAR55,
VAR3,
VAR66,
VAR78,
VAR26,
VAR27,
VAR81,
VAR34);
parameter VAR83 = 0;
input VAR29;
input [15:0] VAR36;
output VAR57;
output VAR23;
output VAR39;
output [63:0] VAR41... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.blackbox.v | 1,311 | module MODULE1 (
VAR4,
VAR1 ,
VAR3 ,
VAR2
);
output VAR4;
input VAR1 ;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/axi/master/axi_lite_master.v | 12,807 | module MODULE1 #(
parameter VAR13 = 1,
parameter VAR70 = 32,
parameter VAR22 = 32,
parameter VAR11 = 32'd100000000 )(
output [31:0] VAR68,
output reg VAR46,
input VAR16,
output reg VAR63,
output reg VAR54,
input [VAR70 - 1:0] VAR37,
input VAR18, input [3:0] VAR62,
input [31:0] VAR19,
output reg [31:0] VAR41,
input clk,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41ai/sky130_fd_sc_ms__o41ai.symbol.v | 1,374 | module MODULE1 (
input VAR1,
input VAR2,
input VAR8,
input VAR3,
input VAR9,
output VAR4
);
supply1 VAR10;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_asin.v | 1,346 | module MODULE1(VAR7, VAR13, enable, VAR2, VAR1);
input VAR7, VAR13, enable;
input [31:0] VAR2;
output [31:0] VAR1;
VAR10 VAR8(
.VAR11(VAR7),
.reset(~VAR13),
.enable(enable),
.VAR3(VAR2[31]),
.VAR9(VAR2[30:23]),
.VAR12(VAR2[22:0]),
.VAR4(VAR1[31]),
.VAR6(VAR1[30:23]),
.VAR5(VAR1[22:0])
);
endmodule | mit |
jmassucco17/full_mips | processor/SingleCycleDatapath/Main.v | 1,495 | module MODULE1;
reg VAR4;
reg VAR1;
VAR2 VAR3(VAR4, VAR1); | mit |
eda-globetrotter/PicenoDecoders | coding_theory/syn/netlist/ham_decoder.syn.v | 4,463 | module MODULE1 ( VAR56, VAR65 );
input [14:0] VAR56;
output [10:0] VAR65;
wire VAR40, VAR167, VAR100, VAR44, VAR179, VAR149, VAR14, VAR84, VAR174, VAR79, VAR173, VAR74, VAR172, VAR63, VAR61, VAR143,
VAR73, VAR80, VAR156, VAR8, VAR128, VAR53, VAR134, VAR3, VAR71, VAR57, VAR60, VAR124, VAR135, VAR110,
VAR108, VAR45, VAR2... | mit |
sh-chris110/chris | FPGA/HPS.bak/Qsys/hps_design/synthesis/submodules/hps_sdram_p0_generic_ddio.v | 2,314 | module MODULE1(
VAR11,
VAR8,
VAR9,
VAR18,
VAR20
);
parameter VAR22 = 1;
localparam VAR5 = 4 * VAR22;
localparam VAR7 = VAR22;
input [VAR5-1:0] VAR11;
input VAR8;
input [VAR22-1:0] VAR18;
input [VAR22-1:0] VAR20;
output [VAR7-1:0] VAR9;
generate
genvar VAR16;
for (VAR16 = 0; VAR16 < VAR22; VAR16 = VAR16 + 1)
begin:VAR24... | gpl-2.0 |
DreamSourceLab/DSLogic-hdl | src/dso_ctl.v | 7,020 | module MODULE1(
input VAR29,
input VAR16,
input VAR1,
inout VAR48,
output reg VAR40,
output reg [23:0] VAR42,
output reg [23:0] VAR50,
output [7:0] VAR62,
output [7:0] VAR10,
output reg [15:0] VAR3,
input VAR18,
output VAR27
);
wire [11:0] VAR25; wire [15:0] VAR12;
wire VAR24;
wire [7:0] VAR55;
wire [7:0] VAR21;
wire [... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3b/sky130_fd_sc_hs__and3b_4.v | 2,091 | module MODULE2 (
VAR7 ,
VAR8 ,
VAR4 ,
VAR3 ,
VAR6,
VAR5
);
output VAR7 ;
input VAR8 ;
input VAR4 ;
input VAR3 ;
input VAR6;
input VAR5;
VAR2 VAR1 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR7 ,
VAR8,
VAR4 ,
VAR3
);
output VAR7 ;
input VAR8;
input VAR4 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbp/sky130_fd_sc_hs__sdfbbp.pp.symbol.v | 1,540 | module MODULE1 (
input VAR4 ,
output VAR3 ,
output VAR1 ,
input VAR2,
input VAR9 ,
input VAR10 ,
input VAR5 ,
input VAR7 ,
input VAR8 ,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.symbol.v | 1,457 | module MODULE1 (
input VAR6 ,
output VAR3 ,
input VAR2,
input VAR9 ,
input VAR8 ,
input VAR1
);
supply1 VAR10;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a21oi/sky130_fd_sc_hvl__a21oi.symbol.v | 1,353 | module MODULE1 (
input VAR6,
input VAR1,
input VAR4,
output VAR8
);
supply1 VAR5;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_4.behavioral.v | 1,098 | module MODULE1( VAR3, VAR5 );
input VAR3;
output VAR5;
VAR2 VAR4(.VAR3(VAR3),.VAR5(VAR5));
VAR2 VAR1(.VAR3(VAR3),.VAR5(VAR5)); | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_15.v | 12,347 | module MODULE3 (
clk,
reset,
VAR101,
VAR4,
VAR76,
VAR92,
VAR3
);
parameter VAR24 = 18;
parameter VAR15 = 15;
parameter VAR13 = 8;
localparam VAR61 = 16;
input clk;
input reset;
input VAR101;
input VAR4;
input [VAR24-1:0] VAR76; output VAR92;
output [VAR24-1:0] VAR3;
localparam VAR27 = 18; localparam VAR36 = 36; localpa... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfsbp/sky130_fd_sc_hd__dfsbp.behavioral.pp.v | 2,300 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR17 ,
VAR2 ,
VAR12,
VAR16 ,
VAR21 ,
VAR19 ,
VAR23
);
output VAR8 ;
output VAR4 ;
input VAR17 ;
input VAR2 ;
input VAR12;
input VAR16 ;
input VAR21 ;
input VAR19 ;
input VAR23 ;
wire VAR3 ;
wire VAR5 ;
reg VAR10 ;
wire VAR6 ;
wire VAR14;
wire VAR1 ;
wire VAR13 ;
wire VAR20 ;
wire VAR22 ;... | apache-2.0 |
olofk/oh | elink/hdl/ereset.v | 2,141 | module MODULE1 (
VAR4, VAR7, VAR1,
reset, VAR6, VAR3, VAR12
);
input reset;
input VAR6; input VAR3; input VAR12;
output VAR4; output VAR7; output VAR1;
wire VAR5;
wire VAR8;
wire VAR9;
VAR11 VAR10 (.out (VAR8),
.in (1'b1),
.clk (VAR3),
.reset (reset)
);
VAR11 VAR2 (.out (VAR9),
.in (1'b1),
.clk (VAR6),
.reset (reset)
)... | gpl-3.0 |
andres-erbsen/sha3-verilog-mirror | low_throughput_core/rtl/rconst.v | 1,542 | module MODULE1(VAR2, VAR1);
input [23:0] VAR2;
output reg [63:0] VAR1;
always @ (VAR2)
begin
VAR1 = 0;
VAR1[0] = VAR2[0] | VAR2[4] | VAR2[5] | VAR2[6] | VAR2[7] | VAR2[10] | VAR2[12] | VAR2[13] | VAR2[14] | VAR2[15] | VAR2[20] | VAR2[22];
VAR1[1] = VAR2[1] | VAR2[2] | VAR2[4] | VAR2[8] | VAR2[11] | VAR2[12] | VAR2[13] ... | apache-2.0 |
fredchen00/MDA-Software | fpga/fpga_hw/top_level/motor_controller/slave_controller.v | 1,831 | module MODULE1(input clk, input VAR8, input write, input [3:0]addr, input [31:0] VAR1, output [23:0] VAR4);
reg [11:0] in = 12'd0;
reg [6*VAR6-1:0] VAR3 = 0;
reg [15:0] period = 16'd0;
always @(posedge clk)
if (VAR8 & write)
casex (addr)
4'b0000:
in[1:0] <= VAR1[1:0];
4'b0001:
in[3:2] <= VAR1[1:0];
4'b0010:
in[5:4] <= ... | apache-2.0 |
antmicro/yosys | techlibs/nexus/lrams_map.v | 1,161 | module \VAR24 (VAR11, VAR15, VAR1, VAR14, VAR23, VAR30, VAR22);
parameter VAR8 = 14;
parameter VAR10 = 32;
parameter VAR3 = 4;
parameter VAR20 = 1;
parameter [524287:0] VAR9 = 524287'b0;
input VAR11;
input [VAR8-1:0] VAR15;
input [VAR10-1:0] VAR1;
input [VAR3-1:0] VAR14;
input [VAR8-1:0] VAR23;
output [VAR10-1:0] VAR30... | isc |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_1.behavioral.v | 1,262 | module MODULE1( VAR6, VAR4, VAR1, VAR5 );
input VAR5, VAR1, VAR6;
output VAR4;
VAR7 VAR3(.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1),.VAR5(VAR5));
VAR7 VAR2(.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/clk_wiz_v3_3.v | 6,923 | module MODULE1
( input VAR24,
output VAR28,
input VAR38,
output VAR8
);
VAR53 VAR73
(.VAR33 (VAR15),
.VAR19 (VAR24));
wire [15:0] VAR16;
wire VAR78;
wire VAR1;
wire VAR21;
wire VAR59;
wire VAR49;
wire VAR61;
wire VAR40;
wire VAR37;
wire VAR50;
wire VAR5;
wire VAR55;
wire VAR10;
wire VAR22;
wire VAR45;
wire VAR42;
wire ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4bb/sky130_fd_sc_ms__or4bb.blackbox.v | 1,326 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR1 ,
VAR5,
VAR6
);
output VAR7 ;
input VAR3 ;
input VAR1 ;
input VAR5;
input VAR6;
supply1 VAR2;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
Elphel/x353 | sensor/sensor_phase353.v | 24,337 | module MODULE1 #(
parameter VAR170 = "VAR100",
parameter VAR184 = "0",
parameter VAR147 = "0"
)(
VAR84, VAR129, VAR8, VAR189, VAR10, VAR107, VAR104, VAR36, VAR13, VAR81, VAR167, VAR123, VAR73, VAR96, VAR64, VAR162, VAR2, VAR191, VAR101, VAR199, VAR26, VAR83);
parameter VAR3=130; VAR139 VAR21
parameter VAR120=1;
paramet... | gpl-3.0 |
SiLab-Bonn/basil | basil/firmware/modules/utils/rgmii_io.v | 11,611 | module MODULE1 (
output wire [3:0] VAR37 ,
output wire VAR19 ,
output wire VAR20 ,
input wire [3:0] VAR11 ,
input wire VAR41 ,
input wire [7:0] VAR32 , input wire VAR23 ,
input wire VAR18 ,
output wire VAR56 ,
output wire VAR51 ,
output reg [7:0] VAR48 , output reg VAR34 , output reg VAR67 , output reg VAR10 ,
output r... | bsd-3-clause |
CospanDesign/vivado-ip-cores | ip/axi_pmod_tft/verilog/axi/slave/axi_pmod_tft/rtl/nh_lcd.v | 5,135 | module MODULE1 #(
parameter VAR4 = 24,
parameter VAR20 = 12
)(
input rst,
input clk,
output [31:0] VAR5,
input VAR32,
input VAR12,
input VAR3,
input VAR18,
input VAR24,
input VAR23,
input VAR48,
input [7:0] VAR21,
output [7:0] VAR8,
output VAR56,
input VAR33,
input VAR53,
input [31:0] VAR17,
input [31:0] VAR6,
input VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/bufinv/sky130_fd_sc_ls__bufinv.symbol.v | 1,272 | module MODULE1 (
input VAR4,
output VAR6
);
supply1 VAR1;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_SLAVE/source_code/PHYctrl_Slave.v | 6,711 | module MODULE1 (
input VAR50,
input [0: 0] VAR118,
input [17: 0] VAR124,
output [17: 0] VAR75,
output [10: 0] VAR20,
output [8: 0] VAR3,
output [6:0]VAR8,VAR66,VAR65,VAR54,VAR18,VAR60,VAR74,VAR99,
output VAR73,
inout VAR25,
output VAR52,
output VAR96,
input VAR126,
input VAR10,
input [3: 0] VAR88,
input VAR31,
output [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3/sky130_fd_sc_ls__or3.functional.pp.v | 1,801 | module MODULE1 (
VAR12 ,
VAR4 ,
VAR1 ,
VAR9 ,
VAR7,
VAR3,
VAR2 ,
VAR6
);
output VAR12 ;
input VAR4 ;
input VAR1 ;
input VAR9 ;
input VAR7;
input VAR3;
input VAR2 ;
input VAR6 ;
wire VAR13 ;
wire VAR10;
or VAR8 (VAR13 , VAR1, VAR4, VAR9 );
VAR5 VAR14 (VAR10, VAR13, VAR7, VAR3);
buf VAR11 (VAR12 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregsbp/sky130_fd_sc_lp__sregsbp.symbol.v | 1,413 | module MODULE1 (
input VAR3 ,
output VAR4 ,
output VAR8 ,
input VAR10,
input VAR7 ,
input VAR1 ,
input VAR5
);
supply1 VAR11;
supply0 VAR2;
supply1 VAR9 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor2/sky130_fd_sc_hdll__xor2_1.v | 2,133 | module MODULE2 (
VAR1 ,
VAR3 ,
VAR7 ,
VAR4,
VAR2,
VAR5 ,
VAR6
);
output VAR1 ;
input VAR3 ;
input VAR7 ;
input VAR4;
input VAR2;
input VAR5 ;
input VAR6 ;
VAR8 VAR9 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR1,
VAR3,
VAR7
);
output VAR1;
... | apache-2.0 |
svenstaro/uni-projekt | verilog/rom.v | 6,509 | module MODULE1 (
address,
VAR14,
VAR24,
VAR30);
input [7:0] address;
input VAR14;
input VAR24;
output [31:0] VAR30;
tri1 VAR14;
tri1 VAR24;
wire [31:0] VAR34;
wire [31:0] VAR30 = VAR34[31:0];
VAR52 VAR33 (
.VAR48 (address),
.VAR19 (VAR14),
.VAR16 (VAR24),
.VAR42 (VAR34),
.VAR37 (1'b0),
.VAR26 (1'b0),
.VAR11 (1'b1),
.VA... | gpl-3.0 |
chriswynnyk/american-put-verilog | american_put_stratix/src/value_buffer.v | 6,929 | module MODULE1(
clk,
VAR101,
VAR17,
VAR30,
VAR83,
VAR102,
VAR21,
VAR74,
VAR100,
VAR127,
VAR60,
VAR56,
VAR99,
VAR114,
VAR105,
VAR69,
VAR61,
VAR108,
VAR115,
VAR89,
VAR75,
VAR29,
VAR121,
VAR52,
VAR67,
VAR71,
VAR16,
VAR42,
VAR126,
VAR109,
VAR12,
VAR94,
VAR65,
VAR2,
VAR68,
VAR22,
VAR27,
VAR26,
VAR90,
VAR4,
VAR97,
VAR5,
VAR7... | apache-2.0 |
P3Stor/P3Stor | pcie/app/BAR1.v | 21,940 | module MODULE1# (
parameter VAR28 = 4'b0010,
parameter VAR21 = 8'h14
)
(
clk, VAR53, en,
VAR42, VAR9,
VAR84,
VAR34,
VAR88, VAR56, VAR8,
VAR30, VAR35, VAR86, VAR76,
VAR38,
VAR63, VAR45, VAR47, VAR81, VAR20, VAR22, VAR83, VAR26, VAR82, VAR10, VAR52, VAR55, VAR43,
VAR72, VAR73, VAR87, VAR57, VAR79, VAR31, VAR18, VAR5, VAR... | gpl-2.0 |
fpgasystems/caribou | hw/src/nukv/nukv_fifogen_aclk.v | 14,348 | module MODULE1 #(
parameter VAR47=5, parameter VAR61=16 )
(
input wire VAR20,
input wire VAR14,
input wire rst,
input wire [VAR61-1:0] VAR37,
input wire VAR19,
output wire VAR49,
output wire VAR33,
output wire [VAR61-1:0] VAR46,
output wire VAR3,
input wire VAR38
);
wire[(VAR61+72):0] VAR55;
assign VAR55[VAR61-1:0] = {... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlxtn/sky130_fd_sc_hdll__dlxtn_2.v | 2,220 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR1,
VAR3 ,
VAR2 ,
VAR7 ,
VAR8
);
output VAR9 ;
input VAR4 ;
input VAR1;
input VAR3 ;
input VAR2 ;
input VAR7 ;
input VAR8 ;
VAR6 VAR5 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR9 ,
VAR4 ,
VAR1
);
output VA... | apache-2.0 |
olgirard/openmsp430 | core/bench/verilog/ram.v | 3,027 | module MODULE1 (
VAR4,
VAR10, VAR11, VAR5, VAR3, VAR7 );
parameter VAR6 = 6; parameter VAR1 = 256;
output [15:0] VAR4;
input [VAR6:0] VAR10; input VAR11; input VAR5; input [15:0] VAR3; input [1:0] VAR7;
reg [15:0] VAR9 [0:(VAR1/2)-1];
reg [VAR6:0] VAR2;
wire [15:0] VAR8 = VAR9[VAR10];
always @(posedge VAR5)
if (~VAR11 ... | bsd-3-clause |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/aux_io.v | 6,234 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR40,
input wire VAR14,
input wire [31:0] VAR24,
output reg [31:0] VAR38,
input wire [25:0] address,
output wire VAR48,
input wire VAR35,
input wire [112:0] VAR56,
output wire [64:0] VAR20
);
localparam VAR45 = 3'd0,
VAR23 = 3'd1,
VAR37 = 3'd2,
VAR30 = 3'd3;... | gpl-2.0 |
hydai/Verilog-Practice | DigitalDesign/hw2/hw2_101062124/hw2_A/hw2_A.v | 1,397 | module MODULE1 (
input in,
input clk,
input VAR5,
output reg out
);
parameter VAR3 = 0;
parameter VAR2 = 1;
reg state, VAR1;
reg VAR4;
always @(posedge clk or negedge VAR5) begin
if (~VAR5) begin
state <= VAR3;
end else begin
state <= VAR1;
end end
always @ begin
case (state)
VAR3: begin if (in == 0) begin VAR4 <= 0;
e... | mit |
DougFirErickson/parallella-hw | fpga/old/esaxi/hdl/esaxi_v1_0_S00_AXI.v | 20,520 | module MODULE1 #
(
parameter [11:0] VAR87 = 12'h810,
parameter integer VAR67 = 1,
parameter integer VAR42 = 32,
parameter integer VAR59 = 30,
parameter integer VAR62 = 0,
parameter integer VAR10 = 0,
parameter integer VAR96 = 0,
parameter integer VAR85 = 0,
parameter integer VAR15 = 0
)
(
output reg [102:0] VAR3,
outpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111o/sky130_fd_sc_lp__a2111o.pp.blackbox.v | 1,427 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR3 ,
VAR9 ,
VAR6 ,
VAR2 ,
VAR10,
VAR8,
VAR4 ,
VAR7
);
output VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR9 ;
input VAR6 ;
input VAR2 ;
input VAR10;
input VAR8;
input VAR4 ;
input VAR7 ;
endmodule | apache-2.0 |
AngelTerrones/Antares | Hardware/verilog/antares_control_unit.v | 19,296 | module MODULE1 #(parameter VAR60 = 1, parameter VAR63 = 1, parameter VAR29 = 1 )(
input [5:0] VAR24, input [5:0] VAR30, input [4:0] VAR51, input [4:0] VAR40, output [7:0] VAR67,
output VAR35, output VAR14, output VAR11, output VAR47, output VAR68, output VAR28, output VAR22, output VAR10, output VAR17, output VAR56, ou... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2o/sky130_fd_sc_ls__a2bb2o.blackbox.v | 1,454 | module MODULE1 (
VAR5 ,
VAR3,
VAR7,
VAR4 ,
VAR9
);
output VAR5 ;
input VAR3;
input VAR7;
input VAR4 ;
input VAR9 ;
supply1 VAR6;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/NIOS_Sys_nios2_qsys_0_jtag_debug_module_tck.v | 8,636 | module MODULE1 (
VAR14,
VAR16,
VAR23,
VAR25,
VAR8,
VAR39,
VAR35,
VAR12,
VAR5,
VAR40,
VAR34,
VAR26,
VAR9,
VAR32,
VAR37,
VAR4,
VAR22,
VAR20,
VAR24,
VAR28,
VAR33,
VAR19,
VAR21,
VAR18,
VAR29,
VAR11,
VAR2,
VAR30,
VAR31,
VAR6,
VAR17
)
;
output [ 1: 0] VAR2;
output VAR30;
output [ 37: 0] VAR31;
output VAR6;
output VAR17;
inpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/buf/sky130_fd_sc_hvl__buf_2.v | 2,001 | module MODULE2 (
VAR1 ,
VAR3 ,
VAR4,
VAR8,
VAR6 ,
VAR5
);
output VAR1 ;
input VAR3 ;
input VAR4;
input VAR8;
input VAR6 ;
input VAR5 ;
VAR2 VAR7 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
supply1 VAR4;
supply0 VAR8;... | apache-2.0 |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_0_bank_compare.v | 10,847 | module MODULE1 #
(parameter VAR71 = 3,
parameter VAR15 = 100,
parameter VAR39 = "8",
parameter VAR60 = 12,
parameter VAR82 = 8,
parameter VAR49 = "VAR22",
parameter VAR37 = 2,
parameter VAR5 = 4,
parameter VAR58 = 16)
(
VAR45, VAR11, VAR38, VAR12,
VAR54, VAR26, VAR59, VAR65, VAR73,
VAR3, VAR56, VAR35, VAR13, VAR40,
VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux4/sky130_fd_sc_ms__mux4.functional.v | 1,592 | module MODULE1 (
VAR9 ,
VAR8,
VAR10,
VAR5,
VAR2,
VAR3,
VAR4
);
output VAR9 ;
input VAR8;
input VAR10;
input VAR5;
input VAR2;
input VAR3;
input VAR4;
wire VAR11;
VAR7 VAR6 (VAR11, VAR8, VAR10, VAR5, VAR2, VAR3, VAR4);
buf VAR1 (VAR9 , VAR11 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufinv/sky130_fd_sc_lp__bufinv.functional.pp.v | 1,782 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR7,
VAR11,
VAR3 ,
VAR1
);
output VAR2 ;
input VAR5 ;
input VAR7;
input VAR11;
input VAR3 ;
input VAR1 ;
wire VAR8 ;
wire VAR4;
not VAR6 (VAR8 , VAR5 );
VAR12 VAR10 (VAR4, VAR8, VAR7, VAR11);
buf VAR9 (VAR2 , VAR4 );
endmodule | apache-2.0 |
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