repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
KestrelComputer/polaris | processor/bench/verilog/polaris.v | 30,496 | module MODULE1();
reg [31:0] VAR50;
reg VAR39;
reg VAR43;
reg VAR9;
reg [31:0] VAR62;
wire [63:0] VAR24;
wire VAR52;
wire VAR31;
wire [3:0] VAR57;
reg VAR33;
reg [63:0] VAR40;
wire [63:0] VAR59;
wire [63:0] VAR4;
wire [1:0] VAR20;
wire VAR25;
wire VAR14;
wire VAR23;
wire VAR38;
wire [11:0] VAR61;
wire [63:0] VAR44;
reg... | mpl-2.0 |
hcabrera-/lancetfish | RTL/router/verif/harness.v | 5,291 | module MODULE1();
parameter VAR28 = 2,
VAR45 = 2,
VAR27 = 100,
VAR18 = 15,
VAR33 = 5;
reg clk;
reg reset;
wire VAR36;
wire [VAR10-1:0] VAR2;
wire VAR38;
wire [VAR10-1:0] VAR12;
wire VAR20;
wire[VAR10-1:0] VAR3;
wire VAR24;
wire [VAR10-1:0] VAR6;
wire VAR11;
wire [VAR10-1:0] VAR1;
wire VAR7;
wire [VAR10-1:0] VAR31;
wire... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221o/sky130_fd_sc_ls__a221o.blackbox.v | 1,395 | module MODULE1 (
VAR8 ,
VAR7,
VAR10,
VAR3,
VAR1,
VAR9
);
output VAR8 ;
input VAR7;
input VAR10;
input VAR3;
input VAR1;
input VAR9;
supply1 VAR5;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/softusb/rtl/softusb_rx.v | 5,001 | module MODULE1(
input VAR10,
input VAR1,
input VAR2,
input VAR4,
input VAR13,
output reg [7:0] VAR22,
output reg VAR23,
output reg VAR5,
input VAR11
);
wire VAR27 = VAR2 ^ VAR11;
wire VAR8 = ~VAR4 & ~VAR13;
reg [2:0] VAR25;
reg [2:0] VAR26;
always @(posedge VAR10) begin
if(VAR1)
VAR25 <= 3'd0;
end
else
VAR25 <= VAR26;
... | lgpl-3.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201010_abus3/wasca/synthesis/submodules/wasca_hexdot.v | 2,118 | module MODULE1 (
address,
VAR1,
clk,
VAR2,
VAR7,
VAR4,
VAR9,
VAR6
)
;
output [ 5: 0] VAR9;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input VAR1;
input clk;
input VAR2;
input VAR7;
input [ 31: 0] VAR4;
wire VAR3;
reg [ 5: 0] VAR5;
wire [ 5: 0] VAR9;
wire [ 5: 0] VAR8;
wire [ 31: 0] VAR6;
assign VAR3 = 1;
assign VAR8 ... | gpl-2.0 |
Jawanga/ece385final | finalproject/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v | 11,552 | module MODULE1
parameter VAR17 = 32,
parameter VAR92 = 8,
parameter VAR80 = 10,
parameter VAR37 = 1,
parameter VAR77 = 4,
parameter VAR38 = 4,
parameter VAR55 = 2,
parameter VAR67 = 2,
parameter VAR51 = VAR17 / VAR92
)
(
input VAR19,
input VAR26,
input VAR63,
input VAR87,
output VAR25,
output [VAR17-1:0] VAR62,
output ... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_250/source/pcie_7x_v1_3_axi_basic_tx.v | 10,238 | module MODULE1 #(
parameter VAR34 = 128, parameter VAR46 = "VAR8", parameter VAR3 = "VAR12", parameter VAR6 = "VAR12", parameter VAR5 = 1,
parameter VAR44 = (VAR34 == 128) ? 2 : 1, parameter VAR36 = VAR34 / 8 ) (
input [VAR34-1:0] VAR26, input VAR29, output VAR42, input [VAR36-1:0] VAR39, input VAR13, input [3:0] VAR15... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311ai/sky130_fd_sc_ls__o311ai.functional.v | 1,481 | module MODULE1 (
VAR2 ,
VAR6,
VAR11,
VAR4,
VAR5,
VAR3
);
output VAR2 ;
input VAR6;
input VAR11;
input VAR4;
input VAR5;
input VAR3;
wire VAR7 ;
wire VAR8;
or VAR9 (VAR7 , VAR11, VAR6, VAR4 );
nand VAR1 (VAR8, VAR3, VAR7, VAR5);
buf VAR10 (VAR2 , VAR8 );
endmodule | apache-2.0 |
hcabrera-/lancetfish | RTL/processing_element/des_engine/rtl/des_sbox7.v | 3,336 | module MODULE1
(
input wire [0:5] VAR1,
output reg [0:3] VAR2
);
always @(*)
case ({VAR1[0], VAR1[5]})
2'b00:
case (VAR1[1:4])
4'd0: VAR2 = 4'd4;
4'd1: VAR2 = 4'd11;
4'd2: VAR2 = 4'd2;
4'd3: VAR2 = 4'd14;
4'd4: VAR2 = 4'd15;
4'd5: VAR2 = 4'd0;
4'd6: VAR2 = 4'd8;
4'd7: VAR2 = 4'd13;
4'd8: VAR2 = 4'd3;
4'd9: VAR2 = 4'd12... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22oi/sky130_fd_sc_hvl__a22oi.functional.v | 1,549 | module MODULE1 (
VAR8 ,
VAR7,
VAR12,
VAR2,
VAR5
);
output VAR8 ;
input VAR7;
input VAR12;
input VAR2;
input VAR5;
wire VAR9 ;
wire VAR11 ;
wire VAR10;
nand VAR3 (VAR9 , VAR12, VAR7 );
nand VAR1 (VAR11 , VAR5, VAR2 );
and VAR6 (VAR10, VAR9, VAR11);
buf VAR4 (VAR8 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlclkp/sky130_fd_sc_ls__dlclkp_1.v | 2,154 | module MODULE1 (
VAR7,
VAR8,
VAR4 ,
VAR9,
VAR6,
VAR3 ,
VAR1
);
output VAR7;
input VAR8;
input VAR4 ;
input VAR9;
input VAR6;
input VAR3 ;
input VAR1 ;
VAR5 VAR2 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR7,
VAR8,
VAR4
);
output VAR7;
inpu... | apache-2.0 |
tejchava1460/Evaluation-Project-for-ASIC-FPGA-Design-Engineer | Verilog_Noise_generator/main.v | 1,545 | module MODULE1(clk, reset, VAR1, VAR11, VAR23, VAR14, VAR22, VAR6, VAR28, VAR20);
input clk, reset;
input [31:0]VAR1, VAR11, VAR23, VAR14, VAR22, VAR6;
output [15:0]VAR28, VAR20;
wire [31:0]VAR35, VAR7;
wire [47:0]VAR33;
wire [15:0]VAR2, VAR36, VAR26, VAR36, VAR26;
wire [30:0]VAR29;
wire [16:0]VAR16;
wire [1:0]VAR13, V... | gpl-3.0 |
efabless/openlane | designs/jpeg_encoder/src/div_uu.v | 5,855 | module MODULE1(clk, VAR8, VAR7, VAR3, VAR12, VAR10, VAR2, VAR15);
parameter VAR17 = 16;
parameter VAR19 = VAR17 /2;
input clk; input VAR8;
input [VAR17 -1:0] VAR7; input [VAR19 -1:0] VAR3; output [VAR19 -1:0] VAR12; reg [VAR19-1:0] VAR12;
output [VAR19 -1:0] VAR10; reg [VAR19-1:0] VAR10;
output VAR2;
reg VAR2;
output V... | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/cmp_data.v | 4,607 | module MODULE1(
clk,
VAR6,
VAR3,
VAR4,
rst,
VAR10,
VAR9,
VAR7,
VAR1
);
input clk;
input VAR6;
input [143:0]VAR3;
input [143:0]VAR4;
input rst;
output [143:0] VAR10;
output [143:0] VAR9;
output VAR7;
output VAR1;
reg VAR5;
reg valid;
reg VAR8;
wire VAR12;
reg [3:0]VAR11;
reg [143:0] VAR2;
always @ (posedge clk)
begin
if... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_p_pp_pkg_sn/sky130_fd_sc_hs__udp_dff_p_pp_pkg_sn.blackbox.v | 1,477 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR2 ,
VAR7 ,
VAR6,
VAR4 ,
VAR1 ,
VAR8
);
output VAR3 ;
input VAR5 ;
input VAR2 ;
input VAR7 ;
input VAR6;
input VAR4 ;
input VAR1 ;
input VAR8 ;
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/rw_manager_ac_ROM_reg.v | 1,407 | module MODULE1(
VAR7,
VAR1,
VAR5,
VAR8,
VAR2,
VAR4);
parameter VAR9 = "";
parameter VAR3 = "";
input [(VAR3-1):0] VAR7;
input VAR1;
input [(VAR3-1):0] VAR5;
input [(VAR9-1):0] VAR8;
input VAR2;
output reg [(VAR9-1):0] VAR4;
reg [(VAR9-1):0] VAR6[(2**VAR3-1):0];
always @(posedge VAR1)
begin
if(VAR2)
VAR6[VAR5] <= VAR8;
... | gpl-3.0 |
hhuang25/uwaterloo_ece224 | Lab1/timer_0.v | 6,613 | module MODULE1 (
address,
VAR30,
clk,
VAR11,
VAR32,
VAR21,
irq,
VAR3
)
;
output irq;
output [ 15: 0] VAR3;
input [ 2: 0] address;
input VAR30;
input clk;
input VAR11;
input VAR32;
input [ 15: 0] VAR21;
wire VAR9;
wire VAR12;
wire VAR8;
reg [ 3: 0] VAR6;
wire VAR4;
reg VAR31;
wire VAR18;
wire [ 31: 0] VAR20;
reg [ 31: 0... | mit |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/ex_stage.v | 4,555 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR21, input wire VAR29, input wire VAR10,
output wire [VAR4] VAR34,
input wire [VAR32] VAR3, input wire VAR13, input wire [VAR31] VAR22, input wire [VAR4] VAR37, input wire [VAR4] VAR16, input wire VAR40, input wire [VAR17] VAR19, input wire [VAR4] VAR11, i... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21ba/sky130_fd_sc_ms__o21ba.functional.pp.v | 2,037 | module MODULE1 (
VAR15 ,
VAR5 ,
VAR13 ,
VAR16,
VAR12,
VAR14,
VAR10 ,
VAR3
);
output VAR15 ;
input VAR5 ;
input VAR13 ;
input VAR16;
input VAR12;
input VAR14;
input VAR10 ;
input VAR3 ;
wire VAR4 ;
wire VAR1 ;
wire VAR9;
nor VAR8 (VAR4 , VAR5, VAR13 );
nor VAR2 (VAR1 , VAR16, VAR4 );
VAR11 VAR7 (VAR9, VAR1, VAR12, VAR14... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/source/GDA_St_N8_M8_P5.v | 3,596 | module MODULE1(
input [7:0] VAR9,
input [7:0] VAR16,
output [8:0] VAR104
);
wire [2:0] VAR22, VAR28, VAR43, VAR93, VAR7, VAR65, VAR96, VAR116;
wire VAR13,VAR100,VAR15,VAR2,VAR59,VAR62,VAR36,VAR79,VAR24,VAR30,VAR25,VAR60,VAR33,VAR32,VAR115,VAR27,VAR55,VAR72,VAR94,VAR49,VAR92;
wire VAR45,VAR38,VAR20,VAR17,VAR57,VAR103,VA... | gpl-3.0 |
GREO/gnuradio-git | gr-gpio/src/fpga/lib/rx_chain_dig.v | 1,512 | module MODULE1
(input VAR5,
input reset,
input enable,
input wire [15:0] VAR6,
input wire [15:0] VAR2,
input wire VAR1,
input wire VAR4,
output wire [15:0] VAR7,
output wire [15:0] VAR3
);
assign VAR7 = (enable)?{VAR6[15:1],VAR1}:VAR6;
assign VAR3 = (enable)?{VAR2[15:1],VAR4}:VAR2;
endmodule | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_16.behavioral.pp.v | 1,241 | module MODULE1( VAR7, VAR1, VAR8, VAR2, VAR3 );
input VAR7, VAR1;
inout VAR2, VAR3;
output VAR8;
VAR6 VAR4(.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8),.VAR2(VAR2),.VAR3(VAR3));
VAR6 VAR5(.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8),.VAR2(VAR2),.VAR3(VAR3)); | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_and.v | 1,545 | if (VAR7 && (VAR3==VAR12)) \
begin: VAR2 \
VAR4 VAR5 (.VAR9(VAR10),.VAR14(VAR11),.VAR6); \
end
module MODULE1 #(parameter VAR20(VAR3)
, parameter VAR7=0
)
(input [VAR3-1:0] VAR10
, input [VAR3-1:0] VAR11
, output [VAR3-1:0] VAR6
);
begin :VAR1
end
VAR16 assert(VAR7==0) else ("## %VAR13 VAR8 VAR17 VAR15 VAR18 VAR19 VAR2... | bsd-3-clause |
Fabeltranm/FPGA-Game-D1 | HW/RTL/10KEYBOARD/Version_01/02 verilog/Touch/Bloquetouch/FIFO/fifo.v | 2,590 | module MODULE1
parameter VAR11 = 4,
parameter VAR17 = 8
)
(
input clk, reset,
input rd, wr,
input [VAR17-1:0] VAR18,
output [VAR17-1:0] VAR1,
output VAR3,
output VAR16
);
parameter VAR7 = (1 << VAR11);
reg [VAR17-1:0] VAR4 [VAR7-1:0];
reg [VAR11-1:0] VAR2, VAR14;
reg [VAR11-1:0] VAR12, VAR5;
reg VAR15, VAR10, VAR13, VA... | gpl-3.0 |
efabless/openlane | designs/digital_pll_sky130_fd_sc_hd/src/digital_pll_controller.v | 4,530 | module MODULE1(reset, VAR6, VAR9, VAR10, VAR3);
input reset;
input VAR6;
input VAR9;
input [4:0] VAR10;
output [25:0] VAR3;
wire [25:0] VAR3;
reg [2:0] VAR1;
reg [2:0] VAR7;
reg [4:0] VAR2;
reg [4:0] VAR4;
reg [6:0] VAR5; wire [4:0] VAR8;
wire [5:0] sum;
assign sum = VAR2 + VAR4;
assign VAR8 = VAR5[6:2];
assign VAR3 = ... | apache-2.0 |
YosysHQ/yosys | techlibs/efinix/brams_map.v | 3,603 | module MODULE1 (...);
parameter VAR35 = 0;
parameter VAR21 = "VAR28";
parameter VAR60 = 20;
parameter VAR42 = 1;
parameter VAR27 = 20;
parameter VAR4 = 1;
input VAR44;
input VAR9;
input [11:0] VAR49;
output [VAR60-1:0] VAR51;
input VAR40;
input VAR3;
input [11:0] VAR18;
input [VAR27-1:0] VAR52;
localparam VAR31 = VAR60... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2b/sky130_fd_sc_hd__nor2b.blackbox.v | 1,307 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR6
);
output VAR1 ;
input VAR5 ;
input VAR6;
supply1 VAR7;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_0_arb_mux.v | 19,765 | module MODULE1 #
(
parameter VAR68 = 100,
parameter VAR14 = "VAR10",
parameter VAR104 = "1T",
parameter VAR106 = 11,
parameter VAR15 = 3,
parameter VAR95 = "8",
parameter VAR59 = 4,
parameter VAR9 = 5,
parameter VAR30 = 5,
parameter VAR71 = 31,
parameter VAR6 = 8,
parameter VAR57 = "VAR111",
parameter VAR107 = "VAR51",... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31oi/sky130_fd_sc_hs__a31oi.pp.blackbox.v | 1,338 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR4 ,
VAR7 ,
VAR6 ,
VAR1,
VAR2
);
output VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR6 ;
input VAR1;
input VAR2;
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/eth_rx.v | 2,455 | module MODULE2
(input VAR39, input [1:0] VAR40,
input VAR32,
output [7:0] VAR42,
output VAR12,
output VAR30);
wire [1:0] VAR9;
sync #(2) VAR1
(.in(VAR40), .clk(VAR39), .out(VAR9));
wire VAR27;
sync VAR16
(.in(VAR32), .clk(VAR39), .out(VAR27));
wire VAR18;
d1 VAR3(.VAR42(VAR27), .VAR39(VAR39), .VAR31(VAR18));
wire [7:0]... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2.behavioral.v | 1,440 | module MODULE1 (
VAR1,
VAR9
);
output VAR1;
input VAR9;
supply1 VAR8;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR3 ;
wire VAR2;
not VAR6 (VAR2, VAR9 );
buf VAR5 (VAR1 , VAR2 );
endmodule | apache-2.0 |
aj-michael/Digital-Systems | Lab4-Part2-RAMwithHyperTerminalDisplay/DebouncerWithoutLatch.v | 1,262 | module MODULE1(VAR11, VAR2, VAR4, VAR6) ;
input VAR11, VAR4, VAR6;
output reg VAR2;
parameter VAR7=0, VAR12=1, VAR5=2, VAR9=3;
reg [1:0] VAR3, VAR8;
wire VAR14;
reg VAR13;
always @ (posedge VAR6) begin
if(VAR4==1) VAR3 <= 0;
end
else VAR3<=VAR8;
case (VAR3)
0: begin VAR2<=0; VAR13<=1; end 1: begin VAR2<=0; VAR13<=0; en... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ebufn/sky130_fd_sc_hd__ebufn.pp.symbol.v | 1,327 | module MODULE1 (
input VAR5 ,
output VAR7 ,
input VAR1,
input VAR6 ,
input VAR4,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
jotego/jt12 | hdl/jt12_reg.v | 12,134 | module MODULE1(
input rst,
input clk,
input VAR41 ,
input [7:0] din,
input [2:0] VAR28, input [1:0] VAR33,
input VAR49,
input VAR16,
input VAR39,
input VAR14,
input VAR21,
input VAR30,
input VAR24,
input VAR48,
input VAR10,
input VAR36,
input VAR2,
input VAR44,
input VAR32,
input VAR55,
output reg VAR31, output reg [2:... | gpl-3.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/ddr2/ddr2_phy_alt_mem_phy_dq_dqs.v | 31,991 | module MODULE1
(
VAR28,
VAR25,
VAR33,
VAR60,
VAR5,
VAR7,
VAR29,
VAR3,
VAR41,
VAR57,
VAR34,
VAR47,
VAR11,
VAR45,
VAR65,
VAR44,
VAR27,
VAR6,
VAR52,
VAR36,
VAR13,
VAR63,
VAR48,
VAR38,
VAR2,
VAR53,
VAR22,
VAR56) ;
input [7:0] VAR28;
input [7:0] VAR25;
output [7:0] VAR33;
output [7:0] VAR60;
input [7:0] VAR5;
output [7:0] V... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/gf_14/bsg_async/bsg_sync_sync.v | 4,267 | \
module MODULE2 \
( \
input VAR14 \
, input [VAR22-1:0] VAR19 \
, output [VAR22-1:0] VAR2 ); \
\
\
genvar VAR6; \
\
logic [VAR22-1:0] VAR1; \
\
assign VAR2 = VAR1; \
\
for (VAR6 = 0; VAR6 < VAR22; VAR6 = VAR6 + 1) \
begin : VAR3 \
VAR10 VAR9 \
(.VAR15 (VAR19[VAR6]) \
,.VAR5 (VAR14) \
,.VAR20 (1'b0) \
,.VAR4 (1'b0) \
,... | bsd-3-clause |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/vga640x480.v | 2,282 | module MODULE1(
input wire clk,
input wire [2:0] VAR2,
input wire [2:0] VAR3,
input wire [1:0] VAR11,
output reg [9:0] hc,
output reg [9:0] VAR7,
output wire VAR4,
output wire VAR6,
output reg [2:0] VAR1,
output reg [2:0] VAR9,
output reg [1:0] VAR12
);
parameter VAR10 = 800;parameter VAR16 = 521; parameter VAR8 = 96; ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22o/sky130_fd_sc_ms__a22o.functional.pp.v | 2,151 | module MODULE1 (
VAR6 ,
VAR18 ,
VAR3 ,
VAR17 ,
VAR8 ,
VAR1,
VAR14,
VAR19 ,
VAR12
);
output VAR6 ;
input VAR18 ;
input VAR3 ;
input VAR17 ;
input VAR8 ;
input VAR1;
input VAR14;
input VAR19 ;
input VAR12 ;
wire VAR9 ;
wire VAR11 ;
wire VAR4 ;
wire VAR15;
and VAR10 (VAR9 , VAR17, VAR8 );
and VAR7 (VAR11 , VAR18, VAR3 );
... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/one_hot_mux.v | 4,781 | module MODULE1
parameter VAR9 = 2,
parameter VAR4 = VAR9*VAR2
)
(
input [VAR9-1:0] VAR7,
input [VAR4-1:0] VAR1,
output [VAR2-1:0] VAR6);
genvar VAR8;
wire [VAR2-1:0] VAR5[(1<<VAR9):1];
reg [VAR2-1:0] VAR3;
assign VAR6 = VAR3;
generate
for( VAR8 = 0 ; VAR8 < VAR9; VAR8 = VAR8 + 1 ) begin : VAR10
assign VAR5[(1<<VAR8)] =... | gpl-3.0 |
kevintownsend/R3 | verilog/intermediator.v | 7,617 | module MODULE1(
input reset,
input clk,
input VAR48,
input [63:0] VAR68,
input [9:0] VAR26,
input VAR74,
input [63:0] VAR57,
input [9:0] VAR19,
output VAR41,
output [63:0] VAR75,
output VAR83,
output [63:0] VAR24,
output [63:0] VAR59,
output [9:0] VAR18,
input VAR62
);
reg [2:0] VAR7, VAR28, VAR60, VAR56, VAR67;
reg [2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2b/sky130_fd_sc_hdll__or2b.behavioral.v | 1,450 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR4
);
output VAR3 ;
input VAR8 ;
input VAR4;
supply1 VAR11;
supply0 VAR12;
supply1 VAR7 ;
supply0 VAR1 ;
wire VAR2 ;
wire VAR6;
not VAR5 (VAR2 , VAR4 );
or VAR10 (VAR6, VAR2, VAR8 );
buf VAR9 (VAR3 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd.pp.blackbox.v | 1,175 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tap/sky130_fd_sc_lp__tap_2.v | 1,877 | module MODULE2 (
VAR6,
VAR1,
VAR4 ,
VAR2
);
input VAR6;
input VAR1;
input VAR4 ;
input VAR2 ;
VAR5 VAR3 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE2 ();
supply1 VAR6;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
VAR5 VAR3 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4bb/sky130_fd_sc_lp__or4bb.behavioral.pp.v | 1,988 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR16 ,
VAR2 ,
VAR4 ,
VAR13,
VAR7,
VAR14 ,
VAR6
);
output VAR5 ;
input VAR1 ;
input VAR16 ;
input VAR2 ;
input VAR4 ;
input VAR13;
input VAR7;
input VAR14 ;
input VAR6 ;
wire VAR17 ;
wire VAR11 ;
wire VAR12;
nand VAR8 (VAR17 , VAR4, VAR2 );
or VAR3 (VAR11 , VAR16, VAR1, VAR17 );
VAR9 VAR1... | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/CON SOLO NCO/tec-drums/debounce.v | 1,199 | module MODULE1 (
input VAR10,
input reset,
input VAR13,
input VAR12,
input VAR5,
input VAR9,
input VAR2,
output reg VAR6,
output reg VAR8,
output reg VAR4,
output reg VAR1,
output reg VAR11,
output reg VAR3,
output VAR7
);
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlclkp/sky130_fd_sc_ls__dlclkp.behavioral.pp.v | 1,924 | module MODULE1 (
VAR13,
VAR16,
VAR8 ,
VAR17,
VAR14,
VAR11 ,
VAR1
);
output VAR13;
input VAR16;
input VAR8 ;
input VAR17;
input VAR14;
input VAR11 ;
input VAR1 ;
wire VAR15 ;
wire VAR3 ;
wire VAR6 ;
wire VAR7;
reg VAR9 ;
wire VAR12 ;
not VAR4 (VAR3 , VAR6 );
VAR5 VAR10 (VAR15 , VAR7, VAR3, VAR9, VAR17, VAR14);
and VAR2 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbp/sky130_fd_sc_lp__sdfbbp.pp.symbol.v | 1,579 | module MODULE1 (
input VAR9 ,
output VAR3 ,
output VAR6 ,
input VAR5,
input VAR7 ,
input VAR8 ,
input VAR4 ,
input VAR11 ,
input VAR10 ,
input VAR1 ,
input VAR2 ,
input VAR12
);
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/nios_altmemddr_0_mem_model.v | 24,610 | module MODULE1 (
VAR10,
VAR3,
VAR9,
VAR11,
VAR1,
VAR2
)
;
parameter VAR8 = 2048;
output [ 15: 0] VAR2;
input [ 15: 0] VAR10;
input [ 24: 0] VAR3;
input [ 24: 0] VAR9;
input VAR11;
input VAR1;
wire [ 15: 0] VAR4;
reg [ 41: 0] VAR12 [2047: 0];
wire [ 15: 0] VAR2;
assign VAR4 = VAR12[0][15:0];
reg [ 16 - 1: 0] out;
intege... | gpl-3.0 |
qiuzou/nysa_saya | rtl/sata_stack.v | 25,549 | module MODULE1 (
input rst, input clk, input VAR287,
input VAR51,
input VAR191, output wire VAR237, output VAR156,
output VAR275,
input VAR218,
input [15:0] VAR40,
output VAR15,
output VAR221,
input VAR98,
input VAR251,
input VAR139,
input VAR192,
input VAR232,
input [7:0] VAR76,
output VAR170,
input [15:0] VAR239,
inp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso0n/sky130_fd_sc_hd__lpflow_inputiso0n.pp.blackbox.v | 1,431 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR5,
VAR4 ,
VAR1 ,
VAR7 ,
VAR6
);
output VAR3 ;
input VAR2 ;
input VAR5;
input VAR4 ;
input VAR1 ;
input VAR7 ;
input VAR6 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_serial_in_parallel_out_passthrough.v | 2,281 | module MODULE1
, parameter VAR4(VAR22)
, VAR6 = 0
)
(input VAR20
, input VAR21
, input VAR10
, output logic VAR25
, input [VAR13-1:0] VAR18
, output logic [VAR22-1:0][VAR13-1:0] VAR7
, output logic VAR29
, input VAR31
);
localparam VAR24 = VAR26(VAR22);
logic [VAR22-1:0] VAR16;
assign VAR29 = VAR10 & VAR16[VAR22-1]; as... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/buf/sky130_fd_sc_ls__buf.behavioral.v | 1,319 | module MODULE1 (
VAR9,
VAR1
);
output VAR9;
input VAR1;
supply1 VAR7;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR4 ;
wire VAR6;
buf VAR3 (VAR6, VAR1 );
buf VAR8 (VAR9 , VAR6 );
endmodule | apache-2.0 |
parallella/oh | common/hdl/oh_clockgate.v | 1,064 | module MODULE1 (
input clk, input VAR5, input en, output VAR7 );
VAR3 VAR4 (.en(en),
.VAR5(VAR5),
.clk(clk),
.VAR7(VAR7));
wire VAR8;
wire VAR6;
assign VAR6 = en | VAR5;
VAR1 VAR2 (.out (VAR8),
.in (VAR6),
.clk (clk));
assign VAR7 = clk & VAR8;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtn/sky130_fd_sc_lp__dlxtn.blackbox.v | 1,300 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR3
);
output VAR6 ;
input VAR1 ;
input VAR3;
supply1 VAR2;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21boi/sky130_fd_sc_ms__a21boi.symbol.v | 1,397 | module MODULE1 (
input VAR7 ,
input VAR4 ,
input VAR8,
output VAR1
);
supply1 VAR3;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
Marcoslz22/Tercer_Proyecto | Prueba_Alarma.v | 1,982 | module MODULE1(
input clk,
input VAR14,
input [7:0] VAR26,
input [7:0] VAR3,
input [7:0] VAR15,
input [7:0] VAR4,
input [7:0] VAR18,
input [7:0] VAR7,
input [7:0] VAR6,
output [7:0] VAR25,
output VAR8
);
wire VAR21;
wire [7:0] VAR13;
wire [7:0] VAR24;
wire [7:0] VAR17;
wire [7:0] VAR9;
wire [7:0] VAR12;
VAR28 VAR27 (
.... | mit |
DProvinciani/Arquitectura_TPF | Codigo_fuente/6-pipe_registers/latch_EX_MEM.v | 3,783 | module MODULE1
parameter VAR9=32, VAR23=5
)
(
input wire clk,
input wire reset,
inout wire VAR18,
input wire [VAR9-1:0] VAR2,
input wire [VAR9-1:0] VAR11,
input wire [VAR23-1:0] VAR5,
output wire [VAR9-1:0]VAR10,
output wire [VAR9-1:0]VAR17,
output wire [VAR23-1:0]VAR7,
input wire VAR15,
input wire VAR14,
input wire VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.v | 2,398 | module MODULE1 (
VAR10 ,
VAR9,
VAR11,
VAR7 ,
VAR8 ,
VAR1,
VAR4,
VAR6 ,
VAR5
);
output VAR10 ;
input VAR9;
input VAR11;
input VAR7 ;
input VAR8 ;
input VAR1;
input VAR4;
input VAR6 ;
input VAR5 ;
VAR3 VAR2 (
.VAR10(VAR10),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fill/sky130_fd_sc_hd__fill_1.v | 1,840 | module MODULE2 (
VAR2,
VAR3,
VAR4 ,
VAR5
);
input VAR2;
input VAR3;
input VAR4 ;
input VAR5 ;
VAR1 VAR6 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE2 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR5 ;
VAR1 VAR6 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hs__udp_dff_nsr_pp_pg_n.symbol.v | 1,655 | module MODULE1 (
input VAR6 ,
output VAR7 ,
input VAR3 ,
input VAR5 ,
input VAR4 ,
input VAR2,
input VAR1 ,
input VAR8
);
endmodule | apache-2.0 |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/rtl/switch_port/rx/rx_path_lookup.v | 11,704 | module MODULE1
parameter VAR28 = 48,
parameter VAR39 = 4,
parameter VAR48 = 0,
parameter VAR18 = 9,
parameter VAR12 = 64,
parameter VAR44 = 0,
parameter VAR55 = 0,
parameter VAR14 = 20,
parameter VAR61 = 40,
parameter VAR19 = 0,
parameter VAR25 = 63,
parameter VAR22 = 60,
parameter VAR23 = 48,
parameter VAR45 = 0,
para... | mit |
tmolteno/TART | hardware/FPGA/wishbone/rtl/wb_fetch.v | 8,088 | module MODULE1
parameter VAR13 = 1<<VAR5, parameter VAR14 = VAR13-1, parameter VAR5 = 2, parameter VAR21 = VAR5-1,
parameter VAR30 = 1,
parameter VAR11 = 3) (
input VAR26,
input VAR29,
output reg VAR2 = 1'b0,
output reg VAR8 = 1'b0,
output VAR16,
input VAR18,
input VAR28,
input VAR6,
input VAR10,
output [VAR22:0] VAR23... | lgpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_054.v | 1,527 | module MODULE1 (
VAR14,
VAR12
);
input [31:0] VAR14;
output [31:0]
VAR12;
wire [31:0]
VAR7,
VAR13,
VAR4,
VAR2,
VAR10,
VAR5,
VAR11,
VAR6,
VAR3;
assign VAR7 = VAR14;
assign VAR6 = VAR10 << 2;
assign VAR3 = VAR11 - VAR6;
assign VAR11 = VAR5 - VAR4;
assign VAR5 = VAR10 << 6;
assign VAR10 = VAR4 - VAR2;
assign VAR13 = VAR7 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isobufsrc/sky130_fd_sc_lp__isobufsrc.behavioral.v | 1,517 | module MODULE1 (
VAR10 ,
VAR11,
VAR12
);
output VAR10 ;
input VAR11;
input VAR12 ;
supply1 VAR2;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR9 ;
wire VAR8 ;
wire VAR6;
not VAR4 (VAR8 , VAR11 );
and VAR3 (VAR6, VAR8, VAR12 );
buf VAR1 (VAR10 , VAR6 );
endmodule | apache-2.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/verif/router/ugal_source.v | 9,987 | module MODULE1(
VAR61, VAR79,
clk, reset, VAR19, VAR69, VAR77, VAR26, VAR12,
VAR29
);
parameter VAR22 = 3;
parameter VAR17 = 16;
parameter VAR3 = 1;
localparam VAR56 = 2;
localparam VAR39 = VAR3 * VAR56;
parameter VAR9 = 1;
localparam VAR81 = VAR39 * VAR9;
parameter VAR63 = 6;
parameter VAR46 = 4;
localparam VAR68 = VA... | gpl-2.0 |
fredchen00/MDA-Software | fpga/fpga_hw/top_level/RS232/Altera_UP_RS232_Counters.v | 4,252 | module MODULE1 (
clk,
reset,
VAR7,
VAR8,
VAR3,
VAR11
);
parameter VAR5 = 9;
parameter VAR2 = 9'd1;
parameter VAR1 = 9'd433;
parameter VAR9 = 9'd216;
parameter VAR6 = 11;
input clk;
input reset;
input VAR7;
output reg VAR8;
output reg VAR3;
output reg VAR11;
reg [(VAR5 - 1):0] VAR4;
reg [3:0] VAR10;
always @(posedge clk... | apache-2.0 |
LoniasGR/Just_NTUA_ECE_Stuff | MicroSys/Assignment_2/Exercise_7/exercise_8_10.v | 1,159 | module MODULE1 (output reg [1:0] state, input VAR1, VAR4, VAR3);
VAR2 state = 2'b00;
always @ (posedge VAR3) begin
case ({VAR1,VAR4})
2'b00: begin if (state == 2'b00) state <= state;
end
else if (state == 2'b01) state <= 2'b10;
end
else if (state == 2'b10) state <= 2'b00;
else state <= 2'b10;
end
2'b01: begin if (state... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4b/sky130_fd_sc_lp__or4b_m.v | 2,288 | module MODULE2 (
VAR10 ,
VAR6 ,
VAR8 ,
VAR11 ,
VAR5 ,
VAR1,
VAR4,
VAR9 ,
VAR2
);
output VAR10 ;
input VAR6 ;
input VAR8 ;
input VAR11 ;
input VAR5 ;
input VAR1;
input VAR4;
input VAR9 ;
input VAR2 ;
VAR7 VAR3 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.... | apache-2.0 |
alexforencich/verilog-ethernet | lib/axis/rtl/axis_crosspoint.v | 6,193 | module MODULE1 #
(
parameter VAR27 = 4,
parameter VAR37 = 4,
parameter VAR36 = 8,
parameter VAR16 = (VAR36>8),
parameter VAR25 = ((VAR36+7)/8),
parameter VAR9 = 1,
parameter VAR40 = 0,
parameter VAR1 = 8,
parameter VAR4 = 0,
parameter VAR29 = 8,
parameter VAR20 = 1,
parameter VAR15 = 1
)
(
input wire clk,
input wire rs... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32ai/sky130_fd_sc_ms__o32ai.behavioral.pp.v | 2,191 | module MODULE1 (
VAR10 ,
VAR5 ,
VAR4 ,
VAR14 ,
VAR8 ,
VAR12 ,
VAR6,
VAR1,
VAR16 ,
VAR20
);
output VAR10 ;
input VAR5 ;
input VAR4 ;
input VAR14 ;
input VAR8 ;
input VAR12 ;
input VAR6;
input VAR1;
input VAR16 ;
input VAR20 ;
wire VAR13 ;
wire VAR2 ;
wire VAR19 ;
wire VAR7;
nor VAR11 (VAR13 , VAR14, VAR5, VAR4 );
nor VA... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_3/synth/design_1_auto_pc_3.v | 14,654 | module MODULE1 (
VAR52,
VAR1,
VAR17,
VAR46,
VAR86,
VAR72,
VAR97,
VAR15,
VAR29,
VAR67,
VAR43,
VAR100,
VAR58,
VAR112,
VAR8,
VAR9,
VAR91,
VAR24,
VAR35,
VAR104,
VAR38,
VAR28,
VAR73,
VAR54,
VAR13,
VAR62,
VAR114,
VAR4,
VAR42,
VAR22,
VAR79,
VAR60,
VAR78,
VAR68,
VAR89,
VAR63,
VAR70,
VAR32,
VAR23,
VAR33,
VAR111,
VAR64,
VAR49,
V... | mit |
skyfex/svo-raycaster | raycaster2/raycast_master.v | 10,900 | module MODULE1
(
VAR38, VAR54, VAR22,
VAR8, VAR64, VAR77,
VAR74, VAR68, VAR21,
VAR42, VAR34,
VAR33, VAR61, VAR30,
VAR25, VAR75, VAR72,
VAR15, VAR59,
VAR16, VAR50,
VAR27, VAR3, VAR62, VAR66,
VAR76,
VAR58, VAR37, VAR31, VAR20,
VAR44,
VAR70, VAR19, VAR13, VAR18,
VAR53,
VAR56, VAR10, VAR29, VAR57,
VAR11,
VAR51, VAR52,
);
p... | mit |
mbus/mbus | layer_controller_v1/verilog/mem_ctrl.v | 2,106 | module MODULE1(
VAR19,
VAR4,
VAR16,
VAR11,
VAR10,
VAR8,
VAR17,
VAR3
);
parameter VAR9 = 65536;
parameter VAR2 = 32;
parameter VAR13 = 32;
input VAR19;
input VAR4;
input [VAR13-3:0] VAR16;
input [VAR2-1:0] VAR11;
input VAR10;
input VAR8;
output reg [VAR2-1:0] VAR17;
output reg VAR3;
wire [VAR7(VAR9-1)-1:0] VAR5 = VAR16[... | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_addsub.v | 4,383 | module MODULE1 (
clk,
VAR11,
VAR5,
out,
VAR1
);
parameter VAR3 = 32;
parameter VAR12 = 32'h1;
parameter VAR13 = 0;
localparam VAR10 = 1;
localparam VAR6 = 0;
input clk;
input [(VAR3-1):0] VAR11;
input [(VAR3-1):0] VAR5;
output [(VAR3-1):0] out;
input VAR1;
reg [(VAR3-1):0] out = 'b0;
reg [VAR3:0] VAR7 = 'b0;
reg [VAR3:... | lgpl-3.0 |
lucasrangit/Multicycle_MIPS | mipsparts.v | 2,949 | module MODULE1( input [31:0] VAR18, VAR3,
input [2:0] VAR13,
output reg [31:0] VAR11, output VAR20);
always @ ( * )
case (VAR13[2:0])
3'b000: VAR11 <= VAR18 & VAR3;
3'b001: VAR11 <= VAR18 | VAR3;
3'b010: VAR11 <= VAR18 + VAR3;
3'b011: VAR11 <= VAR18 & ~VAR3;
3'b101: VAR11 <= VAR18 + ~VAR3;
3'b110: VAR11 <= VAR18 - VAR3... | apache-2.0 |
olajep/oh | src/adi/hdl/library/axi_dmac/dest_axi_mm.v | 6,435 | module MODULE1 #(
parameter VAR29 = 3,
parameter VAR40 = 64,
parameter VAR56 = 32,
parameter VAR73 = VAR4(VAR40/8),
parameter VAR5 = 4,
parameter VAR7 = 128,
parameter VAR61 = VAR4(VAR7),
parameter VAR32 = 8)(
input VAR26,
input VAR47,
input VAR34,
output VAR51,
input [VAR56-1:VAR73] VAR36,
input VAR17,
output VAR74,
i... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_2.functional.v | 1,664 | module MODULE1( VAR2, VAR12, VAR22, VAR9, VAR15, VAR7 );
input VAR9, VAR22, VAR2, VAR12, VAR7;
output VAR15;
wire VAR19;
not VAR4( VAR19, VAR22 );
wire VAR17;
not VAR6( VAR17, VAR2 );
wire VAR3;
and VAR21( VAR3, VAR19, VAR17 );
wire VAR10;
not VAR18( VAR10, VAR12 );
wire VAR13;
and VAR5( VAR13, VAR19, VAR10 );
wire VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxtp/sky130_fd_sc_hs__edfxtp.blackbox.v | 1,309 | module MODULE1 (
VAR4 ,
VAR3,
VAR1 ,
VAR2
);
output VAR4 ;
input VAR3;
input VAR1 ;
input VAR2 ;
supply1 VAR5;
supply0 VAR6;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp1/megacells/fifo_1kx16_bb.v | 5,864 | module MODULE1 (
VAR2,
VAR3,
VAR8,
VAR1,
VAR6,
VAR4,
VAR7,
VAR9,
VAR5,
VAR10);
input VAR2;
input VAR3;
input [15:0] VAR8;
input VAR1;
input VAR6;
output VAR4;
output VAR7;
output VAR9;
output [15:0] VAR5;
output [9:0] VAR10;
endmodule | gpl-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/audio_clock/audio_clock_0002.v | 2,141 | module MODULE1(
input wire VAR70,
input wire rst,
output wire VAR8,
output wire VAR49,
output wire VAR50
);
VAR51 #(
.VAR20("false"),
.VAR54("12.0 VAR46"),
.VAR62("VAR63"),
.VAR43(2),
.VAR61("3.072000 VAR46"),
.VAR14("0 VAR35"),
.VAR17(50),
.VAR60("1.000000 VAR46"),
.VAR71("0 VAR35"),
.VAR53(50),
.VAR30("0 VAR46"),
.VA... | gpl-3.0 |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/sfa_2x2_v1_0/sfa_control.v | 6,902 | module MODULE1 (
output wire VAR28 ,
input wire VAR43 ,
input wire [31 : 0] VAR8 ,
input wire VAR2 ,
output wire VAR51 ,
output wire [31 : 0] VAR56 ,
output wire VAR16 ,
input wire VAR31 ,
input wire VAR14 ,
input wire VAR24 ,
output wire VAR47 ,
output wire [23 : 0] VAR1 ,
output wire [23 : 0] VAR7 ,
output wire [23 :... | bsd-3-clause |
qiuzou/nysa_saya | rtl/phy/oob_controller.v | 9,323 | module MODULE1 (
input rst, input clk,
input VAR31, output reg VAR15,
output reg VAR7, output reg VAR4,
input VAR29, input VAR1,
input [31:0] VAR18,
input [3:0] VAR6,
input VAR28,
input VAR5,
output reg [31:0] VAR25,
output reg VAR19,
output reg VAR27,
output [3:0] VAR3
);
parameter VAR8 = 4'h0;
parameter VAR12 = 4'h1;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22ai/sky130_fd_sc_hd__o22ai.behavioral.pp.v | 2,159 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR16 ,
VAR12 ,
VAR8 ,
VAR13,
VAR15,
VAR10 ,
VAR6
);
output VAR1 ;
input VAR5 ;
input VAR16 ;
input VAR12 ;
input VAR8 ;
input VAR13;
input VAR15;
input VAR10 ;
input VAR6 ;
wire VAR3 ;
wire VAR14 ;
wire VAR7 ;
wire VAR2;
nor VAR9 (VAR3 , VAR12, VAR8 );
nor VAR11 (VAR14 , VAR5, VAR16 );
o... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_1.behavioral.pp.v | 2,623 | module MODULE1( VAR3, VAR2, VAR4, VAR1, VAR7, VAR5 );
input VAR2, VAR3, VAR4;
inout VAR7, VAR5;
output VAR1;
VAR6 VAR9(.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR5(VAR5));
VAR6 VAR8(.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR5(VAR5)); | apache-2.0 |
CospanDesign/python | game/panda/panda_path/example_project/rtl/bus/master/wishbone_master.v | 22,457 | module MODULE1 (
input clk,
input rst,
output reg VAR37,
input VAR58,
input VAR64,
input [31:0] VAR15,
input [31:0] VAR6,
input [31:0] VAR27,
input [27:0] VAR60,
input VAR40,
output reg VAR59 = 0,
output reg [31:0] VAR11 = 32'h0,
output reg [31:0] VAR18 = 32'h0,
output reg [31:0] VAR1 = 32'h0,
output wire [27:0] VAR68,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fahcin/sky130_fd_sc_lp__fahcin.blackbox.v | 1,332 | module MODULE1 (
VAR1,
VAR6 ,
VAR5 ,
VAR4 ,
VAR8
);
output VAR1;
output VAR6 ;
input VAR5 ;
input VAR4 ;
input VAR8 ;
supply1 VAR2;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_gsu/ipcore_dir/gsu_mult.v | 5,622 | module MODULE1 (
VAR38, VAR40, VAR24
);
output [15 : 0] VAR38;
input [7 : 0] VAR40;
input [7 : 0] VAR24;
wire \VAR41/VAR32<34>VAR43 ;
wire \VAR41/VAR32<33>VAR43 ;
wire \VAR41/VAR32<32>VAR43 ;
wire \VAR41/VAR32<31>VAR43 ;
wire \VAR41/VAR32<30>VAR43 ;
wire \VAR41/VAR32<29>VAR43 ;
wire \VAR41/VAR32<28>VAR43 ;
wire \VAR41/... | gpl-2.0 |
olajep/oh | src/adi/hdl/library/common/ad_csc_1_add.v | 5,044 | module MODULE1 #(
parameter VAR3 = 16) (
input clk,
input [24:0] VAR6,
input [24:0] VAR26,
input [24:0] VAR16,
input [24:0] VAR22,
output reg [ 7:0] VAR30,
input [VAR21:0] VAR2,
output reg [VAR21:0] VAR9);
localparam VAR21 = VAR3 - 1;
reg [VAR21:0] VAR29 = 'd0;
reg [24:0] VAR31 = 'd0;
reg [24:0] VAR17 = 'd0;
reg [24:0]... | mit |
zaqwes8811/spec-emb | ip-cores/spi_host_ram_host/deserializer.v | 3,532 | module MODULE1 (
output reg VAR15,
input VAR11, VAR9, req, clk, VAR6);
parameter [1:0] VAR7 = 2'b00,
VAR13 = 2'b01,
VAR3 = 2'b10,
VAR4 = 2'b11;
reg [1:0] state;
reg [1:0] VAR14;
always @(posedge clk
) begin
state <= VAR14;
end
always @(state or VAR11 or VAR9 or req) begin
VAR14 = 2'VAR17;
VAR15 = 1'b0;
case (state)
VAR... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_114.v | 1,442 | module MODULE1 (
VAR3,
VAR2
);
input [31:0] VAR3;
output [31:0]
VAR2;
wire [31:0]
VAR10,
VAR8,
VAR12,
VAR11,
VAR5,
VAR6,
VAR7;
assign VAR10 = VAR3;
assign VAR5 = VAR11 - VAR10;
assign VAR11 = VAR12 << 2;
assign VAR12 = VAR8 - VAR10;
assign VAR6 = VAR12 << 10;
assign VAR7 = VAR5 + VAR6;
assign VAR8 = VAR10 << 5;
assign ... | mit |
hoang26/processor_verilog | 0_cpu.v | 4,059 | module MODULE1(
input clk,
input VAR50,
input VAR11,
input [31:0] VAR15,
input [31:0] VAR49,
output wire[31:0] VAR4,
output wire[31:0] VAR59,
output wire[31:0] VAR44,
output wire VAR76,
output wire VAR81
);
wire [31:0] VAR33;
wire [31:0] VAR10;
wire [31:0] VAR20;
wire [31:0] VAR23;
wire [31:0] VAR21;
wire [4:0] VAR13;
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxbp/sky130_fd_sc_ls__sdfxbp.blackbox.v | 1,377 | module MODULE1 (
VAR3 ,
VAR10,
VAR2,
VAR7 ,
VAR5,
VAR4
);
output VAR3 ;
output VAR10;
input VAR2;
input VAR7 ;
input VAR5;
input VAR4;
supply1 VAR8;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and2/sky130_fd_sc_hdll__and2.pp.blackbox.v | 1,268 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR3 ,
VAR6,
VAR4,
VAR5 ,
VAR2
);
output VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR6;
input VAR4;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
marmolejo/zet | cores/ps2/rtl/ps2.v | 19,706 | module MODULE1 (
input VAR37, input VAR46, input [15:0] VAR12, output [15:0] VAR53, input VAR54, input VAR25, input [ 2:1] VAR99, input [ 1:0] VAR4, input VAR49, output VAR93, output VAR8, output VAR26,
input VAR96, inout VAR42, inout VAR91, inout VAR74 );
wire [7:0] VAR85;
wire [2:0] VAR28;
wire VAR59;
wire VAR100;
wi... | gpl-3.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_fifo.v | 6,551 | module MODULE1 (VAR11, VAR3, clk, reset, write, read, VAR26, VAR22, VAR16, VAR23, VAR14, VAR8);
parameter VAR18 = 32;
parameter VAR5 = 8;
parameter VAR15 = 4;
parameter VAR2 = 1;
input clk;
input reset;
input write;
input read;
input VAR26;
input [VAR18-1:0] VAR11;
output [VAR18-1:0] VAR3;
output VAR22;
output VAR16;
o... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_psa_pp_pkg_s/sky130_fd_sc_lp__udp_dlatch_psa_pp_pkg_s.blackbox.v | 1,519 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR6 ,
VAR5,
VAR7 ,
VAR4 ,
VAR1 ,
VAR3
);
output VAR8 ;
input VAR2 ;
input VAR6 ;
input VAR5;
input VAR7 ;
input VAR4 ;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_axis_dma_rx.v | 10,163 | module MODULE1 (
VAR17,
VAR65,
VAR43,
VAR57,
VAR36,
VAR22,
VAR45,
VAR26,
VAR32,
VAR18,
VAR12,
VAR72,
VAR25,
VAR20,
VAR21,
VAR58,
VAR44);
parameter VAR14 = 64;
localparam VAR60 = VAR14 - 1;
localparam VAR1 = 6'd3;
localparam VAR75 = 6'd60;
localparam VAR50 = VAR14/8;
input VAR17;
input VAR65;
output VAR43;
output VAR57;... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4/sky130_fd_sc_hdll__nor4.functional.pp.v | 1,888 | module MODULE1 (
VAR5 ,
VAR13 ,
VAR12 ,
VAR9 ,
VAR15 ,
VAR3,
VAR2,
VAR1 ,
VAR10
);
output VAR5 ;
input VAR13 ;
input VAR12 ;
input VAR9 ;
input VAR15 ;
input VAR3;
input VAR2;
input VAR1 ;
input VAR10 ;
wire VAR14 ;
wire VAR7;
nor VAR11 (VAR14 , VAR13, VAR12, VAR9, VAR15 );
VAR6 VAR4 (VAR7, VAR14, VAR3, VAR2);
buf VAR8... | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/tlu_mon.v | 80,576 | module MODULE1(
clk,
VAR230,
VAR107,
VAR167,
VAR223,
VAR249,
VAR22,
VAR208,
VAR88,
VAR234,
VAR172,
VAR64,
VAR53,
VAR251,
VAR205,
VAR33,
VAR233,
VAR246,
VAR242,
VAR109,
VAR94,
VAR213,
VAR115,
VAR157,
VAR1,
VAR97,
VAR73,
VAR8,
VAR259,
VAR181,
VAR39,
VAR211,
VAR269,
VAR186,
VAR231,
VAR55,
VAR218,
VAR158,
VAR150,
VAR128,
V... | gpl-2.0 |
Rmin1995/NoC | priority_vc_perInput.v | 4,826 | module MODULE1(
output [0:VAR2-1] VAR22,
output [0:VAR2-1] VAR18,
output [1:VAR21 * VAR2] VAR5,
output VAR28,
output [0:VAR6*VAR2-1] VAR16,
input VAR13,
input [0:VAR4-1] VAR8,
input [0:VAR2-1] VAR17,
input [0:VAR2-1] VAR33,
input [0:VAR2-1] VAR1,
input [1:VAR21] VAR24,
input [1:VAR21 * VAR2] VAR27,
input [0:VAR6*VAR2-1... | gpl-3.0 |
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