repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
davidkoltak/tawas-core | ip/rcn/rtl/rcn_bridge_buf.v | 3,040 | module MODULE1
(
input rst,
input clk,
input [68:0] VAR21,
output [68:0] VAR35,
input [68:0] VAR9,
output [68:0] VAR12
);
parameter VAR13 = 0;
parameter VAR32 = 1;
parameter VAR15 = 0;
parameter VAR18 = 1;
wire [5:0] VAR5 = VAR13;
wire [5:0] VAR22 = VAR32;
wire [23:0] VAR25 = VAR15;
wire [23:0] VAR40 = VAR18;
reg [68:0... | mit |
travisg/cpu | rtl/sram-issi.v | 2,622 | module MODULE1 (VAR16, VAR14, VAR12, VAR20, VAR17, VAR1, VAR4);
parameter VAR13 = 16;
parameter VAR3 = 262143;
parameter VAR10 = 18;
parameter VAR18 = 2;
parameter VAR11 = 2;
VAR19 = 3,
VAR2 = 5;
VAR19 = 5,
VAR2 = 6;
input VAR12, VAR20, VAR17, VAR1, VAR4;
input [(VAR10 - 1) : 0] VAR16;
inout [(VAR13 - 1) : 0] VAR14;
wi... | mit |
Progressive-Learning-Platform/progressive-learning-platform | reference/hw/verilog/mod_uart.v | 6,300 | module MODULE3(rst, clk, VAR23, VAR5, VAR33, VAR15, VAR2, din, VAR1, dout, VAR3, VAR26, VAR28, VAR25, VAR10);
input rst;
input clk;
input VAR23,VAR5;
input [31:0] VAR33, VAR15;
input [1:0] VAR2;
input [31:0] din;
output [31:0] VAR1, dout;
output VAR3;
input VAR26;
output VAR28;
output VAR25, VAR10;
wire [31:0] VAR13, V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2a/sky130_fd_sc_lp__o2bb2a.pp.blackbox.v | 1,400 | module MODULE1 (
VAR7 ,
VAR9,
VAR4,
VAR2 ,
VAR8 ,
VAR1,
VAR5,
VAR3 ,
VAR6
);
output VAR7 ;
input VAR9;
input VAR4;
input VAR2 ;
input VAR8 ;
input VAR1;
input VAR5;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/uvispace_top.v | 27,985 | module MODULE1(
inout VAR343,
output VAR185,
input VAR382,
output VAR32,
input VAR320,
inout VAR23,
inout VAR275,
output VAR347,
inout VAR301,
output VAR376,
input VAR9,
input VAR264,
input VAR417,
input VAR187,
output [12:0] VAR237, output [1:0] VAR96, output VAR192, output VAR348, output VAR214, output VAR217, inout ... | gpl-3.0 |
toomij/DE2Labs | Lab2/lab2_part6.v | 2,329 | module MODULE2 (VAR28, VAR4, VAR5, VAR1, VAR16, VAR22, VAR26, VAR14, VAR9, VAR29, VAR2);
input [17:0] VAR28;
output [8:0] VAR5, VAR4;
output [0:6] VAR1, VAR16, VAR22, VAR26, VAR14, VAR9, VAR29, VAR2;
assign VAR5[8:0] = VAR28[8:0];
reg [4:0] VAR13, VAR19;
reg [3:0] VAR10, VAR21, VAR12, VAR27, VAR17;
reg VAR24, VAR18;
al... | gpl-2.0 |
mosukiton/mipsprocessor | Mips_single_cycle.srcs/sources_1/new/alu.v | 1,661 | module MODULE1(
output reg [31:0] VAR10,
output reg VAR8,
input [31:0] VAR2,
input [31:0] VAR1,
input [2:0] VAR11
);
wire [31:0] VAR5, VAR7, VAR9, VAR4, VAR3, VAR6;
wire VAR12;
assign VAR5 = ~VAR1;
assign VAR7 = (VAR11[2]) ? VAR5 : VAR1;
assign {VAR12, VAR9} = VAR7 + VAR2 + VAR11[2];
assign VAR4 = VAR2 & VAR7;
assign V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_pwrgood_pp_p/sky130_fd_sc_ms__udp_pwrgood_pp_p.blackbox.v | 1,251 | module MODULE1 (
VAR2,
VAR1 ,
VAR3
);
output VAR2;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
gbraad/minimig-de1 | bench/cpu_cache_sdram/tg68_ram.v | 1,473 | module MODULE1 #(
parameter VAR8 = 512;
)(
input wire clk,
input wire VAR2,
input wire [ 32-1:0] VAR12,
input wire VAR5,
input wire VAR6,
input wire VAR1,
input wire [ 16-1:0] VAR7,
output wire [ 16-1:0] VAR9,
output wire VAR14
);
reg [8-1:0] VAR4 [0:VAR8-1];
reg [8-1:0] VAR10 [0:VAR8-1];
reg [16-1:0] VAR13 = 0;
reg VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22o/sky130_fd_sc_ms__a22o.blackbox.v | 1,356 | module MODULE1 (
VAR5 ,
VAR6,
VAR3,
VAR8,
VAR7
);
output VAR5 ;
input VAR6;
input VAR3;
input VAR8;
input VAR7;
supply1 VAR2;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxtp/sky130_fd_sc_ms__sedfxtp.pp.symbol.v | 1,493 | module MODULE1 (
input VAR3 ,
output VAR5 ,
input VAR9 ,
input VAR7 ,
input VAR2 ,
input VAR10 ,
input VAR8 ,
input VAR1,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
peteasa/oh | src/common/hdl/oh_mux8.v | 1,280 | module MODULE1 #(parameter VAR2 = 1 ) (
input VAR8,
input VAR1,
input VAR10,
input VAR14,
input VAR12,
input VAR17,
input VAR9,
input VAR3,
input [VAR2-1:0] VAR5,
input [VAR2-1:0] VAR13,
input [VAR2-1:0] VAR11,
input [VAR2-1:0] VAR6,
input [VAR2-1:0] VAR16,
input [VAR2-1:0] VAR15,
input [VAR2-1:0] VAR7,
input [VAR2-1:0... | mit |
Iuliiapl/schoolMIPS | src/sm_hex_display.v | 2,556 | module MODULE2
(
input [3:0] VAR5,
output reg [6:0] VAR1
);
always @*
case (VAR5)
'h0: VAR1 = 'b1000000; 'h1: VAR1 = 'b1111001;
'h2: VAR1 = 'b0100100; 'h3: VAR1 = 'b0110000; 'h4: VAR1 = 'b0011001; 'h5: VAR1 = 'b0010010; 'h6: VAR1 = 'b0000010; 'h7: VAR1 = 'b1111000; 'h8: VAR1 = 'b0000000; 'h9: VAR1 = 'b0011000; 'ha: VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlclkp/sky130_fd_sc_lp__dlclkp.symbol.v | 1,276 | module MODULE1 (
input VAR6 ,
input VAR7,
output VAR1
);
supply1 VAR2;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/dma_queue/megafunctions/async_fifo_256x72_to_36_bb.v | 6,420 | module MODULE1 (
VAR4,
VAR9,
VAR2,
VAR6,
VAR7,
VAR1,
VAR3,
VAR10,
VAR5,
VAR8);
input VAR4;
input [71:0] VAR9;
input VAR2;
input VAR6;
input VAR7;
input VAR1;
output [35:0] VAR3;
output VAR10;
output [8:0] VAR5;
output VAR8;
tri0 VAR4;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2b/sky130_fd_sc_lp__or2b_4.v | 2,127 | module MODULE2 (
VAR5 ,
VAR1 ,
VAR3 ,
VAR7,
VAR8,
VAR4 ,
VAR9
);
output VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR7;
input VAR8;
input VAR4 ;
input VAR9 ;
VAR6 VAR2 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR5 ,
VAR1 ,
VAR3
);
output VAR5... | apache-2.0 |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_static_cmdgen.v | 6,088 | module MODULE1
parameter VAR19 = 32'h12A00000,
parameter VAR14 = 32 ,
parameter VAR9 = 4 , parameter VAR5 = 3,
parameter VAR7 = 0,
parameter VAR17 = 0
) (
input VAR28 ,
input VAR2 ,
input VAR6 ,
input [7:0] VAR11 ,
input [9:0] VAR30,
input [31:0] VAR15 ,
input [31:0] VAR1 ,
output [127:0] VAR21 ,
output [VAR14-1:0] VAR... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_hash_bank_reverse.v | 4,370 | module MODULE1 #(parameter VAR14(VAR36), parameter VAR14(VAR7), VAR4=VAR17((2**VAR7+VAR36-1)/VAR36), VAR16=VAR35(VAR36), VAR42=0)
(
input [VAR4-1:0] VAR8
, input [VAR16-1:0] VAR24
, output [VAR7-1:0] VAR19
);
if (VAR36 == 1)
begin: VAR21
assign VAR19 = VAR8;
end
else
if (VAR36 == 2)
begin: VAR28
assign VAR19 = { VAR24,... | bsd-3-clause |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Clock8346/Clock8346_stub.v | 1,211 | module MODULE1(VAR3, VAR2, VAR1)
;
input VAR3;
output VAR2;
output VAR1;
endmodule | gpl-3.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/reg_file.v | 37,407 | module MODULE1(
input VAR182, input VAR133, input [9:0] VAR19, input [31:0] VAR174, input VAR50, output VAR192, input VAR116, output reg VAR187, output reg [31:0] VAR138, output reg VAR21, output [31:0] VAR235, output VAR234, input VAR73, output VAR29, output [31:0] VAR108, output [31:0] VAR97, output VAR48, output [31... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o.pp.symbol.v | 1,456 | module MODULE1 (
input VAR8,
input VAR1,
input VAR4 ,
input VAR5 ,
output VAR9 ,
input VAR3 ,
input VAR2,
input VAR6,
input VAR7
);
endmodule | apache-2.0 |
Gilberto-Lopez/Arquitectura-Computadoras | Practica5/CUnit.v | 5,751 | module MODULE1(
input wire clk,
input wire reset,
output reg VAR1,
output reg [31:0] VAR26,
input wire [31:0] VAR34,
output reg VAR13,
output reg [9:0] VAR32,
input wire VAR21,
input wire VAR31,
input wire VAR15,
input wire [31:0] VAR25,
output reg [31:0] VAR18,
output reg [31:0] VAR37,
output reg [3:0] VAR5
);
localpa... | lgpl-3.0 |
dwaipayanBiswas/ECG-feature-extraction-using-DWT | ecg_top_stim.v | 20,564 | module MODULE1;
reg [15:0] VAR14;
reg clk, VAR10;
wire [15:0] VAR19,VAR3,VAR4,VAR7,
VAR12,VAR17,VAR13,VAR6,
VAR2,VAR8,VAR16,VAR9,VAR1,VAR20,VAR5,VAR15;
VAR11 VAR18 (VAR19,VAR3,VAR4,VAR7,
VAR12,VAR17,VAR13,VAR6,VAR2,VAR8,VAR16,VAR9,VAR1,VAR20,VAR5,
VAR15, VAR14,clk,VAR10);
always
begin
clk = 0;
clk = 1;
clk = 0;
end
beg... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvpwrvgnd/sky130_fd_sc_ms__tapvpwrvgnd.pp.blackbox.v | 1,226 | module MODULE1 (
VAR4,
VAR2,
VAR1 ,
VAR3
);
input VAR4;
input VAR2;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | rtl/eth_phy_10g_tx.v | 3,247 | module MODULE1 #
(
parameter VAR10 = 64,
parameter VAR4 = (VAR10/8),
parameter VAR2 = 2,
parameter VAR5 = 0,
parameter VAR6 = 0,
parameter VAR1 = 0,
parameter VAR12 = 0
)
(
input wire clk,
input wire rst,
input wire [VAR10-1:0] VAR7,
input wire [VAR4-1:0] VAR11,
output wire [VAR10-1:0] VAR9,
output wire [VAR2-1:0] VAR3... | mit |
neale/CS-program | 474-VLSI/Lab_ADC/ADC_ROM_bb.v | 5,039 | module MODULE1 (
address,
VAR2,
VAR1);
input [10:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtn/sky130_fd_sc_ms__dlxtn_4.v | 2,204 | module MODULE2 (
VAR5 ,
VAR1 ,
VAR2,
VAR4 ,
VAR3 ,
VAR8 ,
VAR7
);
output VAR5 ;
input VAR1 ;
input VAR2;
input VAR4 ;
input VAR3 ;
input VAR8 ;
input VAR7 ;
VAR6 VAR9 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR5 ,
VAR1 ,
VAR2
);
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.v | 2,546 | module MODULE1 (
VAR13 ,
VAR6 ,
VAR1 ,
VAR3 ,
VAR9 ,
VAR8 ,
VAR7,
VAR2 ,
VAR10 ,
VAR12 ,
VAR4
);
output VAR13 ;
output VAR6 ;
input VAR1 ;
input VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR7;
input VAR2 ;
input VAR10 ;
input VAR12 ;
input VAR4 ;
VAR5 VAR11 (
.VAR13(VAR13),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_std_synchronizer_nocut.v | 6,568 | module MODULE1 (
clk,
VAR2,
din,
dout
);
parameter VAR5 = 3; parameter VAR4 = 0;
input clk;
input VAR2;
input din;
output dout;
reg VAR3;
reg [VAR5-2:0] VAR1; | mit |
ehliar/schematic_gui | mux4.v | 1,177 | module MODULE1 #(parameter VAR4 = 1) (input wire [1:0] VAR5,
input wire [VAR4:0] VAR1, VAR2, VAR3,VAR6,
output reg [VAR4:0] VAR7); | gpl-3.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_wbmux.v | 5,643 | module MODULE1(
clk, rst,
VAR5, VAR12,
VAR11, VAR13, VAR10, VAR7,
VAR2, VAR6, VAR8
);
parameter VAR1 = VAR3;
input clk;
input rst;
input VAR5;
input [VAR4-1:0] VAR12;
input [VAR1-1:0] VAR11;
input [VAR1-1:0] VAR13;
input [VAR1-1:0] VAR10;
input [VAR1-1:0] VAR7;
output [VAR1-1:0] VAR2;
output [VAR1-1:0] VAR6;
output VAR... | gpl-2.0 |
P3Stor/P3Stor | pcie/app/BMD_EP.v | 31,548 | module MODULE1#
(
parameter VAR155 = 128,
parameter VAR253 = 4'b0010,
parameter VAR128 = 8'h14
)
(
clk,
VAR278,
en,
VAR216,
VAR176,
VAR35,
VAR310,
VAR75,
VAR71,
VAR36,
VAR220,
VAR287,
VAR337,
VAR260,
VAR52,
VAR331,
VAR32,
VAR322,
VAR333,
VAR100,
VAR339,
VAR130,
VAR106,
VAR345,
VAR114,
VAR248,
VAR95,
VAR162,
VAR150,
VAR... | gpl-2.0 |
vvk/sysrek | uart_echo/UART_loop.v | 1,417 | module MODULE1(
input VAR8,
output VAR4,
input VAR21,
output [7:0]VAR12
);
wire [7:0]VAR19;
reg [7:0]VAR10;
reg VAR5 = 1'b0;
reg VAR14 = 1'b0;
reg VAR1 = 1'b0;
wire VAR16;
wire VAR2;
VAR7 # (
.VAR15(100000000),
.VAR20(115200)
)VAR13 (
.VAR17(VAR21),
.VAR18(VAR19),
.VAR14(VAR14),
.VAR1(VAR1),
.VAR9(VAR8),
.VAR16(VAR16)
... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_1.behavioral.pp.v | 6,220 | module MODULE1( VAR50, VAR52, VAR45, VAR47, VAR42, VAR8, VAR17 );
input VAR45, VAR50, VAR52, VAR47;
inout VAR8, VAR17;
output VAR42;
reg VAR12;
VAR61 VAR2(.VAR50(VAR50),.VAR52(VAR52),.VAR45(VAR45),.VAR47(VAR47),.VAR42(VAR42),.VAR8(VAR8),.VAR17(VAR17),.VAR12(VAR12));
VAR61 VAR60(.VAR50(VAR50),.VAR52(VAR52),.VAR45(VAR45)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111o/sky130_fd_sc_ls__a2111o_2.v | 2,448 | module MODULE2 (
VAR3 ,
VAR9 ,
VAR4 ,
VAR5 ,
VAR7 ,
VAR8 ,
VAR10,
VAR12,
VAR2 ,
VAR6
);
output VAR3 ;
input VAR9 ;
input VAR4 ;
input VAR5 ;
input VAR7 ;
input VAR8 ;
input VAR10;
input VAR12;
input VAR2 ;
input VAR6 ;
VAR11 VAR1 (
.VAR3(VAR3),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR10(VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111o/sky130_fd_sc_ms__a2111o_1.v | 2,448 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR11 ,
VAR9 ,
VAR1 ,
VAR5 ,
VAR6,
VAR12,
VAR8 ,
VAR2
);
output VAR4 ;
input VAR3 ;
input VAR11 ;
input VAR9 ;
input VAR1 ;
input VAR5 ;
input VAR6;
input VAR12;
input VAR8 ;
input VAR2 ;
VAR7 VAR10 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxtp/sky130_fd_sc_ls__sdfxtp_2.v | 2,345 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR1 ,
VAR10 ,
VAR9 ,
VAR2,
VAR5,
VAR11 ,
VAR6
);
output VAR8 ;
input VAR7 ;
input VAR1 ;
input VAR10 ;
input VAR9 ;
input VAR2;
input VAR5;
input VAR11 ;
input VAR6 ;
VAR4 VAR3 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR11(VAR11),
.... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/riffa/translation_xilinx.v | 10,699 | module MODULE1
parameter VAR79 = 256
)
(
input VAR31,
input VAR18,
input [VAR79-1:0] VAR86,
input [(VAR79/8)-1:0] VAR32,
input VAR26,
input VAR40,
output VAR30,
input [VAR83-1:0] VAR37,
output VAR12,
output VAR48,
output [VAR79-1:0] VAR16,
output [(VAR79/8)-1:0] VAR68,
output VAR41,
output VAR74,
input VAR66,
output [V... | mit |
alexforencich/verilog-cam | rtl/ram_dp.v | 2,608 | module MODULE1 #
(
parameter VAR3 = 32,
parameter VAR11 = 10
)
(
input wire VAR12,
input wire VAR13,
input wire [VAR11-1:0] VAR10,
input wire [VAR3-1:0] VAR8,
output wire [VAR3-1:0] VAR16,
input wire VAR9,
input wire VAR6,
input wire [VAR11-1:0] VAR5,
input wire [VAR3-1:0] VAR1,
output wire [VAR3-1:0] VAR4
);
reg [VAR3... | mit |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_AO_RVT_SS_210930.v | 231,279 | module MODULE1 (VAR10, VAR11, VAR2, VAR5, VAR6);
output VAR10;
input VAR11, VAR2, VAR5, VAR6;
wire VAR4, VAR7, VAR9;
wire VAR1, VAR8, VAR3;
not (VAR1, VAR6);
not (VAR9, VAR5);
not (VAR7, VAR2);
and (VAR8, VAR7, VAR9);
not (VAR4, VAR11);
and (VAR3, VAR4, VAR9);
or (VAR10, VAR3, VAR8, VAR1); | bsd-3-clause |
keith-epidev/VHDL-lib | top/lab_2/part_3/ip/clk_base/clk_base_stub.v | 1,241 | module MODULE1(VAR1, VAR4, VAR2, VAR3)
;
input VAR1;
output VAR4;
output VAR2;
output VAR3;
endmodule | gpl-2.0 |
scollinson/xc3sprog | bscan_spi/bscan_s3_spi_isf.v | 1,407 | module MODULE1
(
input VAR2
);
wire VAR10;
wire VAR33;
wire VAR1;
wire VAR4;
wire VAR18;
wire VAR31;
reg [47:0] VAR16;
reg [15:0] VAR30;
reg VAR37 = 0;
wire VAR39;
wire VAR20 = VAR4;
wire VAR27;
wire VAR7;
wire VAR22;
reg VAR38 = 0;
reg VAR44 = 0;
reg VAR42 = 0;
reg VAR14 = 0;
reg [13:0] VAR13;
reg [13:0] VAR12;
wire V... | gpl-2.0 |
KiwiOnChip/Projet_VHDL_-_Paint | 04_IP_Xillinx/Clk_Wizard/Clk_Wizard_stub.v | 1,281 | module MODULE1(VAR5, VAR4, VAR2, VAR1,
VAR3)
;
output VAR5;
output VAR4;
input VAR2;
output VAR1;
input VAR3;
endmodule | gpl-3.0 |
ShepardSiegel/ocpi | coregen/temac_axi_v5_2/example_design/fifo/ten_100_1g_eth_fifo.v | 7,123 | module MODULE1 #
(
parameter VAR39 = 0
)
(
input VAR37, input VAR18, input [7:0] VAR38,
input VAR13,
input VAR23,
output VAR27,
input VAR12, input VAR8, output [7:0] VAR4,
output VAR28,
output VAR2,
input VAR31,
output VAR6,
output VAR16,
output [3:0] VAR17,
input VAR5,
input VAR29,
input VAR34, input VAR36, output [7:... | lgpl-3.0 |
csturton/wirepatch | system/hardware/cores/fabric/ovl_always_wrapped.v | 2,610 | module MODULE1(
clk,
rst,
enable,
VAR5,
VAR2,
out
);
input clk;
input rst;
input enable;
input VAR5;
input VAR2;
output out;
wire [2:0] VAR3;
wire [2:0] VAR4;
VAR6 VAR6(
.VAR1(clk),
.reset(rst),
.enable(enable),
.VAR5(VAR5),
.VAR7(VAR3),
.VAR8(VAR4)
);
assign out = VAR4[0] & ~VAR2;
endmodule | mit |
rhalstea/cidr_15_fpga_join | probe_engine/verilog/filter_rows.v | 2,838 | module MODULE1 (
input clk,
input rst,
output VAR7,
input [63:0] VAR6,
input [63:0] VAR5,
input [63:0] VAR23,
input [63:0] VAR29, input [63:0] VAR14,
output VAR32,
input VAR27,
output [63:0] VAR11,
output [63:0] VAR24,
input VAR21,
output VAR19,
output [47:0] VAR15,
output VAR2,
input VAR26,
input [63:0] VAR18
);
wire ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkinvkapwr/sky130_fd_sc_hd__lpflow_clkinvkapwr.blackbox.v | 1,332 | module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR5;
supply1 VAR6 ;
supply0 VAR3 ;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
SeanZarzycki/openSPARC-FPU | dc_compiler/iscas_benchmarks/s526.v | 7,840 | module MODULE2 (VAR62,VAR368,VAR102);
input VAR62,VAR102;
output VAR368;
wire VAR11,VAR93;
trireg VAR218,VAR124;
nmos VAR323 (VAR124,VAR102,VAR93);
not VAR179 (VAR11,VAR124);
nmos VAR98 (VAR218,VAR11,VAR62);
not VAR338 (VAR368,VAR218);
not VAR10 (VAR93,VAR62);
endmodule
module MODULE1(VAR381,VAR260,VAR62,VAR77,VAR331,V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tap/sky130_fd_sc_hd__tap.behavioral.pp.v | 1,189 | module MODULE1 (
VAR1,
VAR4,
VAR2 ,
VAR3
);
input VAR1;
input VAR4;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/submodules/niosII_system_rs232_0.v | 9,593 | module MODULE1 (
clk,
reset,
address,
VAR34,
VAR27,
read,
write,
VAR17,
VAR32,
irq,
VAR1,
VAR25
);
parameter VAR14 = 13; parameter VAR23 = 5208;
parameter VAR9 = 2604;
parameter VAR31 = 10; parameter VAR35 = 8; parameter VAR22 = 1'b0;
input clk;
input reset;
input address;
input VAR34;
input [ 3: 0] VAR27;
input read;
... | apache-2.0 |
LSaldyt/qnp | output/vs/opt_var19_multi.v | 30,134 | module MODULE1(VAR10, VAR5, VAR3, VAR6, VAR4, VAR13, VAR16, VAR15, VAR8, VAR9, VAR17, VAR2, VAR14, VAR1, VAR19, VAR7, VAR18, VAR11, VAR12, valid);
wire 0000;
wire 0001;
wire 0002;
wire 0003;
wire 0004;
wire 0005;
wire 0006;
wire 0007;
wire 0008;
wire 0009;
wire 0010;
wire 0011;
wire 0012;
wire 0013;
wire 0014;
wire 001... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4bb/sky130_fd_sc_hdll__nor4bb.symbol.v | 1,341 | module MODULE1 (
input VAR9 ,
input VAR6 ,
input VAR5,
input VAR4,
output VAR7
);
supply1 VAR8;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdriver2/sky130_fd_sc_lp__busdriver2.behavioral.v | 1,329 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR7
);
output VAR2 ;
input VAR4 ;
input VAR7;
supply1 VAR5;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR8 ;
bufif0 VAR3 (VAR2 , VAR4, VAR7 );
endmodule | apache-2.0 |
kevintownsend/R3 | verilog/pe/spmv_pe.v | 3,454 | module MODULE1(clk, VAR3, VAR39, VAR45, VAR13, VAR43, VAR8,
VAR6, VAR47, VAR11, VAR50, VAR24,
VAR31, VAR18, VAR17, VAR58,
VAR36, VAR2, VAR9, VAR12,
VAR30);
parameter VAR28 = 0;
localparam VAR23 = 7;
localparam VAR1 = 12;
localparam VAR44 = 16;
input clk;
input [63:0] VAR3;
output [63:0] VAR39;
input VAR45;
output VAR13... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22ai/sky130_fd_sc_hdll__o22ai.functional.pp.v | 2,181 | module MODULE1 (
VAR19 ,
VAR18 ,
VAR6 ,
VAR7 ,
VAR14 ,
VAR16,
VAR3,
VAR11 ,
VAR17
);
output VAR19 ;
input VAR18 ;
input VAR6 ;
input VAR7 ;
input VAR14 ;
input VAR16;
input VAR3;
input VAR11 ;
input VAR17 ;
wire VAR15 ;
wire VAR2 ;
wire VAR8 ;
wire VAR1;
nor VAR10 (VAR15 , VAR7, VAR14 );
nor VAR5 (VAR2 , VAR18, VAR6 );... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_nr_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_nr_pp_pkg_sn.symbol.v | 1,532 | module MODULE1 (
input VAR1 ,
output VAR4 ,
input VAR3 ,
input VAR5 ,
input VAR2 ,
input VAR6 ,
input VAR7,
input VAR8 ,
input VAR9
);
endmodule | apache-2.0 |
ymei/TMSPlane | Firmware/src/tms_sdm_recv.v | 4,827 | module MODULE1
parameter VAR3 = 19
)
(
input VAR74,
input VAR25, input VAR11, input [7:0] VAR57, input [4:0] VAR24, input VAR44, input [3:0] VAR21,
output VAR23,
output VAR35,
input VAR60,
input VAR39,
output VAR75,
input [VAR3-1:0] VAR1,
input [VAR3-1:0] VAR36,
input [VAR3-1:0] VAR2,
input [VAR3-1:0] VAR31,
output reg... | bsd-3-clause |
YoelRP/PROYECTO | bin/example/ram.v | 1,190 | module MODULE1 # ( parameter VAR13= 16, parameter VAR10=8, parameter VAR7=8 )
(
input wire VAR14,
input wire VAR12,
input wire[VAR10-1:0] VAR3,
input wire[VAR10-1:0] VAR8,
input wire[VAR10-1:0] VAR9,
input wire[VAR13-1:0] VAR5,
output reg [VAR13-1:0] VAR1,
output reg [VAR13-1:0] VAR4
);
reg [VAR13-1:0] VAR11 [VAR7:0];
... | gpl-3.0 |
cfib/bf2hw | lib/toplevel/bf2hw_top.v | 1,822 | module MODULE1(input VAR12, input VAR5, output VAR10);
wire VAR6;
wire VAR8;
wire VAR1;
wire [7:0] VAR15;
wire [7:0] VAR4;
wire VAR9;
wire VAR2; wire VAR16;
wire reset;
reg [2:0] VAR11;
assign VAR9 = ~VAR6;
VAR13 VAR3 (.VAR14(VAR12), .VAR7(VAR2), .VAR16(VAR16));
assign reset = VAR11[2]; | gpl-3.0 |
golfit/QcmMasterController | QcmMasterControllerWithFCounterMain.v | 4,139 | module MODULE1(clk, VAR6, VAR1, VAR3, VAR4, VAR8, VAR9, VAR2);
input clk, VAR6; output wire [6:0] VAR1, VAR3; output VAR4, VAR8; output VAR9; output VAR2;
wire [13:0] VAR7; wire [6:0] state;
reg [1:0] VAR5; | mit |
R4PaSs/linguist | samples/Verilog/t_button_debounce.v | 1,990 | module MODULE1();
parameter
VAR6 = 66000000,
VAR4 = 2;
reg clk, VAR2, VAR5;
wire VAR1;
VAR3
.VAR6(VAR6),
.VAR4(VAR4)
)
VAR3
(
.clk(clk),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1)
); | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_4.behavioral.v | 1,341 | module MODULE1( VAR2, VAR7, VAR3, VAR6, VAR4 );
input VAR4, VAR6, VAR2, VAR3;
output VAR7;
VAR8 VAR1(.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3),.VAR6(VAR6),.VAR4(VAR4));
VAR8 VAR5(.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3),.VAR6(VAR6),.VAR4(VAR4)); | apache-2.0 |
open-power/snap | actions/hdl_helloworld/hw/hdl/action_hdl_helloworld.v | 21,969 | module MODULE1 # (
parameter VAR39 = 4,
parameter VAR57 = 33,
parameter VAR79 = 512,
parameter VAR38 = 1,
parameter VAR10 = 1,
parameter VAR85 = 1,
parameter VAR2 = 1,
parameter VAR31 = 1,
parameter VAR58 = 32,
parameter VAR62 = 32,
parameter VAR80 = 2,
parameter VAR16 = 64,
parameter VAR54 = 512,
parameter VAR71 = 8,
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvgnd/sky130_fd_sc_ms__tapvgnd.pp.blackbox.v | 1,256 | module MODULE1 (
VAR3,
VAR4,
VAR1 ,
VAR2
);
input VAR3;
input VAR4;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_tdd_control.v | 23,716 | module MODULE1(
clk,
rst,
VAR69,
VAR95,
VAR55,
VAR60,
VAR7,
VAR87,
VAR96,
VAR102,
VAR16,
VAR21,
VAR46,
VAR39,
VAR94,
VAR100,
VAR28,
VAR80,
VAR83,
VAR23,
VAR5,
VAR93,
VAR11,
VAR36,
VAR71,
VAR31,
VAR34,
VAR19,
VAR116,
VAR56,
VAR61,
VAR104,
VAR44,
VAR54,
VAR33,
VAR50,
VAR6,
VAR9);
parameter integer VAR88 = 0; parameter in... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111o/sky130_fd_sc_lp__a2111o.blackbox.v | 1,394 | module MODULE1 (
VAR3 ,
VAR7,
VAR10,
VAR2,
VAR9,
VAR6
);
output VAR3 ;
input VAR7;
input VAR10;
input VAR2;
input VAR9;
input VAR6;
supply1 VAR8;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221a/sky130_fd_sc_hs__o221a.functional.v | 2,091 | module MODULE1 (
VAR6,
VAR3,
VAR7 ,
VAR13 ,
VAR14 ,
VAR2 ,
VAR9 ,
VAR4
);
input VAR6;
input VAR3;
output VAR7 ;
input VAR13 ;
input VAR14 ;
input VAR2 ;
input VAR9 ;
input VAR4 ;
wire VAR9 VAR1 ;
wire VAR9 VAR18 ;
wire VAR8 ;
wire VAR16;
or VAR11 (VAR1 , VAR9, VAR2 );
or VAR15 (VAR18 , VAR14, VAR13 );
and VAR5 (VAR8 , ... | apache-2.0 |
secworks/blake2 | src/rtl/blake2_G.v | 3,981 | module MODULE1(
input wire [63 : 0] VAR25,
input wire [63 : 0] VAR4,
input wire [63 : 0] VAR1,
input wire [63 : 0] VAR14,
input wire [63 : 0] VAR19,
input wire [63 : 0] VAR2,
output wire [63 : 0] VAR8,
output wire [63 : 0] VAR6,
output wire [63 : 0] VAR15,
output wire [63 : 0] VAR5
);
reg [63 : 0] VAR21;
reg [63 : 0] V... | bsd-2-clause |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_064bits.v | 1,917 | module MODULE1 (
clk,
VAR20, VAR22, VAR3, VAR6, VAR26, VAR4, VAR19, VAR16,
sum,
);
input clk;
input [VAR29+0-1:0] VAR20, VAR22, VAR3, VAR6, VAR26, VAR4, VAR19, VAR16;
output [VAR29 :0] sum;
reg [VAR29 :0] sum;
wire [VAR29+3-1:0] VAR30;
wire [VAR29+2-1:0] VAR12, VAR13;
wire [VAR29+1-1:0] VAR18, VAR28, VAR5, VAR14;
reg [... | mit |
scalable-networks/ext | uhd/fpga/usrp1/sdr_lib/hb/halfband_decim.v | 6,619 | module MODULE1
(input VAR45, input reset, input enable, input VAR35, output wire VAR9,
input wire [15:0] VAR7, output reg [15:0] VAR39,output wire [15:0] VAR26);
reg [3:0] VAR36;
reg [3:0] VAR34;
reg [3:0] VAR10;
reg [3:0] VAR28;
wire signed [15:0] VAR18,VAR42, sum, VAR3;
wire signed [30:0] VAR22;
wire signed [33:0] VA... | gpl-2.0 |
Siliciumer/DOS-Mario-FPGA | sources/draw_mario_score.v | 2,445 | module MODULE1(
input wire clk,
input wire rst,
input wire [9:0] VAR4,
input wire VAR18,
input wire [9:0] VAR5,
input wire VAR13,
input wire [23:0] VAR19,
input wire VAR8,
input wire [7:0] VAR14,
output reg [9:0] VAR6,
output reg VAR3,
output reg [9:0] VAR10,
output reg VAR17,
output reg [23:0] VAR15,
output reg VAR1,
... | mit |
gralco/FPGA-Elevator-Project | Mojo V3 - Xilinx Spartan 6 Project/Elevator IO Shield/source/elevator.v | 2,622 | module MODULE1 (
clk,
reset,
en,
VAR9,
VAR7,
VAR4,
VAR12,
VAR6,
VAR5,
VAR3,
VAR8,
VAR10
);
input clk;
input reset;
input en;
input [3:0] VAR9;
output [3:0] VAR7;
wire [3:0] VAR7;
output [3:0] VAR4;
reg [3:0] VAR4;
output VAR12;
reg VAR12;
output VAR6;
reg VAR6;
output VAR5;
reg VAR5;
output VAR3;
reg VAR3;
output [3:0]... | gpl-2.0 |
The-OpenROAD-Project/asap7 | asap7sc7p5t_27/Verilog/asap7sc7p5t_AO_RVT_TT_201020.v | 210,832 | module MODULE1 (VAR1, VAR7, VAR6, VAR4, VAR10);
output VAR1;
input VAR7, VAR6, VAR4, VAR10;
wire VAR3, VAR5, VAR11;
wire VAR9, VAR2, VAR8;
not (VAR9, VAR10);
not (VAR11, VAR4);
not (VAR5, VAR6);
and (VAR2, VAR5, VAR11);
not (VAR3, VAR7);
and (VAR8, VAR3, VAR11);
or (VAR1, VAR8, VAR2, VAR9); | bsd-3-clause |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_OA_LVT_SS_210930.v | 242,182 | module MODULE1 (VAR13, VAR4, VAR3, VAR10, VAR8, VAR2);
output VAR13;
input VAR4, VAR3, VAR10, VAR8, VAR2;
wire VAR11, VAR1, VAR6;
wire VAR9, VAR12, VAR7;
wire VAR5;
not (VAR12, VAR2);
not (VAR9, VAR8);
not (VAR6, VAR10);
and (VAR7, VAR6, VAR9);
not (VAR1, VAR3);
not (VAR11, VAR4);
and (VAR5, VAR11, VAR1, VAR9);
or (VAR... | bsd-3-clause |
ElegantLin/My-CPU | project_4/project_4.srcs/sources_1/imports/Chapter11/hilo_reg.v | 2,431 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR9,
input wire[VAR1] VAR6,
input wire[VAR1] VAR3,
output reg[VAR1] VAR4,
output reg[VAR1] VAR7
);
always @ (posedge clk) begin
if (rst == VAR2) begin
VAR4 <= VAR8;
VAR7 <= VAR8;
end else if((VAR9 == VAR5)) begin
VAR4 <= VAR6;
VAR7 <= VAR3;
end
end
endmodule | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_mout_csr.v | 7,277 | module MODULE1 (
VAR36, VAR2, VAR12, VAR34,
VAR11, VAR60, VAR46,
VAR58, VAR52,
VAR55, VAR22,
VAR25, VAR53, VAR1, VAR49,
VAR37, VAR54, VAR23, VAR29, VAR59,
VAR19, VAR39, VAR56, VAR18, VAR43, VAR41,
VAR42, VAR48, VAR27, VAR3,
VAR30, VAR6, VAR33,
VAR50, VAR15, clk, VAR16
);
output VAR36;
output VAR2;
input VAR37;
input [3... | gpl-2.0 |
danbone/core | riscv/src/main/riscv_ex_pipe.v | 3,477 | module MODULE1 (
input clk,
input VAR7,
input VAR28,
output VAR25,
input [31:0] VAR5,
input [31:0] VAR9,
input [VAR24-1:0] VAR4,
input [31:0] VAR6,
input [VAR11-1:0] VAR14,
input [VAR13-1:0] VAR16,
output [31:0] VAR10,
output VAR31,
output VAR22,
input VAR15,
input [31:0] VAR1,
output [31:0] VAR20,
output [3:0] VAR30,
... | mit |
Lan-Hekary/ARM | control_unit.v | 4,488 | module MODULE4(input [1:0] VAR50,input [5:0] VAR41,input [3:0]rd,
output reg [1:0] VAR9,output wire VAR49,output wire VAR30,
output wire VAR3,output wire VAR28,output wire VAR10,
output wire [1:0] VAR34,output wire [1:0] VAR42,output reg[1:0] VAR29 ,output wire VAR36
);
reg [9:0] VAR46;
wire VAR20;
wire VAR6;
always @*... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2/sky130_fd_sc_hdll__nand2.pp.symbol.v | 1,277 | module MODULE1 (
input VAR4 ,
input VAR5 ,
output VAR6 ,
input VAR7 ,
input VAR1,
input VAR2,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1.pp.blackbox.v | 1,309 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR5,
VAR2,
VAR6 ,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR5;
input VAR2;
input VAR6 ;
input VAR3 ;
endmodule | apache-2.0 |
liuyenting/CA-Project | src/L1_Cache_Controller_ta.v | 5,174 | module MODULE1
(
input VAR21,
input VAR40,
input [256-1:0] VAR42,
input VAR38,
output [256-1:0] VAR43,
output [32-1:0] VAR28,
output VAR27,
output VAR35,
input [32-1:0] VAR47,
input [32-1:0] VAR23,
input VAR49,
input VAR15,
output [32-1:0] VAR22,
output VAR12
);
integer VAR31;
wire [4:0] VAR8;
wire VAR1;
wire [23:0] VA... | gpl-3.0 |
osrf/wandrr | firmware/motor_controller/fpga/usb_tx_ack.v | 1,084 | module MODULE1
(input VAR18,
input VAR27,
output [7:0] VAR25,
output VAR21);
localparam VAR4 = 3'd0;
localparam VAR26 = 3'd1;
localparam VAR3 = 3'd2;
localparam VAR2=4, VAR12=2;
reg [VAR12+VAR2-1:0] VAR8;
wire [VAR2-1:0] state;
wire [VAR2-1:0] VAR16 = VAR8[VAR2+VAR12-1:VAR12];
VAR11 #(VAR2) VAR5
(.VAR18(VAR18), .rst(1'... | apache-2.0 |
asicguy/gplgpu | hdl/altera_project/dpram_32_32x16_be/dpram_32_32x16_be.v | 9,175 | module MODULE1 (
VAR30,
VAR38,
VAR35,
VAR23,
VAR46,
VAR11,
VAR20,
VAR2);
input [31:0] VAR30;
input VAR38;
input [3:0] VAR35;
input [3:0] VAR23;
input [3:0] VAR46;
input VAR11;
input VAR20;
output [31:0] VAR2;
wire [31:0] VAR33;
wire [31:0] VAR2 = VAR33[31:0];
VAR45 VAR7 (
.VAR9 (VAR38),
.VAR32 (VAR11),
.VAR4 (VAR20),
.... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_engine_classic.v | 36,865 | module MODULE4
parameter VAR94 = 128,
parameter VAR102 = 1,
parameter VAR133 = 1,
parameter VAR115 = 256,
parameter VAR114 = "VAR92"
)
(
input VAR171,
input VAR135,
input [VAR3-1:0] VAR112,
input VAR45,
output [VAR94-1:0] VAR151,
output VAR9,
output VAR119,
output [VAR39(VAR94/32)-1:0] VAR100,
output VAR116,
output [VA... | gpl-3.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_0_rank_cntrl.v | 22,799 | module MODULE1 #
(
parameter VAR28 = 100, parameter VAR22 = "8", parameter VAR104 = 2, parameter VAR57 = 5, parameter VAR85 = 5, parameter VAR43 = 0, parameter VAR56 = 4, parameter VAR79 = 2, parameter VAR19 = 30, parameter VAR35 = 8, parameter VAR80 = 4, parameter VAR49 = 4, parameter VAR75 = 20, parameter VAR55 = 16,... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/V2NFC100DDR_v1_0_0/81152d2e/src/NPCG_Toggle_SCC_PO_reset.v | 4,228 | module MODULE1
(
parameter VAR5 = 4
)
(
VAR11,
VAR14 ,
VAR12 ,
VAR10 ,
VAR9 ,
VAR15 ,
VAR4 ,
VAR17 ,
VAR2 ,
VAR16 ,
VAR8,
VAR13
);
input VAR11 ;
input VAR14 ;
input [5:0] VAR12 ;
input [4:0] VAR10 ;
input [4:0] VAR9 ;
input VAR15 ;
output VAR4 ;
output VAR17 ;
output VAR2 ;
input [7:0] VAR16 ;
input [7:0] VAR8 ;
output... | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/subsys/e203_subsys_clint.v | 3,395 | module MODULE1(
input VAR20,
output VAR7,
input [VAR24-1:0] VAR34,
input VAR37,
input [VAR14-1:0] VAR35,
input [VAR14/8-1:0] VAR13,
output VAR15,
input VAR11,
output VAR38,
output [VAR14-1:0] VAR8,
output VAR18,
output VAR28,
input VAR25,
input VAR12,
input clk,
input VAR21
);
wire VAR31;
wire VAR33;
VAR5 # (
.VAR2(VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2111oi/sky130_fd_sc_ls__a2111oi_2.v | 2,461 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR5 ,
VAR2 ,
VAR10 ,
VAR12 ,
VAR7,
VAR8,
VAR1 ,
VAR4
);
output VAR9 ;
input VAR6 ;
input VAR5 ;
input VAR2 ;
input VAR10 ;
input VAR12 ;
input VAR7;
input VAR8;
input VAR1 ;
input VAR4 ;
VAR11 VAR3 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR12(VAR12),
.VAR7(... | apache-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/PackAdderProcess.v | 2,681 | module MODULE1(
input [31:0] VAR21,
input [3:0] VAR20,
input VAR3,
input [31:0] VAR24,
input [27:0] VAR10,
input [7:0] VAR27,
input VAR7,
output reg [31:0] VAR6,
output reg VAR19 = 1'b0,
output reg [31:0] VAR28,
output reg [3:0] VAR9,
output reg [7:0] VAR22
);
parameter VAR25 = 1'b0,
VAR18 = 1'b1;
wire VAR2;
wire [7:0]... | apache-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_10_a/hdl/verilog/radio_controller_TxTiming.v | 2,985 | module MODULE1
(
clk,
reset,
VAR4,
VAR3,
VAR1,
VAR11,
VAR15,
VAR2,
VAR10,
VAR14,
VAR7,
VAR9,
VAR17,
VAR8
);
input clk;
input reset;
input VAR4;
input [0:5] VAR3;
input [0:3] VAR1;
input [0:3] VAR11;
input [0:7] VAR15;
input [0:7] VAR2;
input [0:7] VAR10;
input [0:7] VAR14;
output VAR7;
output VAR8;
output VAR17;
output... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/maj3/sky130_fd_sc_lp__maj3_m.v | 2,171 | module MODULE2 (
VAR2 ,
VAR4 ,
VAR6 ,
VAR10 ,
VAR3,
VAR5,
VAR8 ,
VAR9
);
output VAR2 ;
input VAR4 ;
input VAR6 ;
input VAR10 ;
input VAR3;
input VAR5;
input VAR8 ;
input VAR9 ;
VAR1 VAR7 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
joaocarlos/udlx-verilog | fpga/rtl/42s86400.v | 39,229 | module MODULE1 (VAR23, VAR40, VAR80, VAR67, VAR70, VAR15, VAR18, VAR29, VAR4);
parameter VAR54 = 13;
parameter VAR95 = 8;
parameter VAR44 = 10;
parameter VAR57 = 8388608;
inout [VAR95 - 1 : 0] VAR23;
input [VAR54 - 1 : 0] VAR40;
input [1 : 0] VAR80;
input VAR67;
input VAR70;
input VAR15;
input VAR18;
input VAR29;
input... | lgpl-3.0 |
Digilent/vivado-library | ip/Pmods/PmodAMP2_v1_0/src/PmodAMP2.v | 16,052 | module MODULE1
(VAR40,
VAR77,
VAR2,
VAR63,
VAR85,
VAR144,
VAR220,
VAR1,
VAR56,
VAR229,
VAR218,
VAR94,
VAR5,
VAR96,
VAR99,
VAR136,
VAR179,
VAR27,
VAR87,
VAR13,
VAR91,
VAR67,
VAR25,
VAR83,
VAR105,
VAR157,
VAR6,
VAR184,
VAR65,
VAR163,
VAR236,
VAR215,
VAR59,
VAR177,
VAR245,
VAR137,
VAR53,
VAR19,
VAR208,
VAR156,
VAR62,
VAR7... | mit |
asicguy/gplgpu | hdl/altera_clk_synth/pll_config_top.v | 1,480 | module MODULE1
(
input VAR17,
input VAR31,
input VAR34,
input VAR5,
input VAR6,
input [2:0] VAR29,
input [3:0] VAR36,
input [8:0] VAR35,
input VAR21,
output VAR23,
output VAR33,
output VAR19
);
wire VAR7;
wire VAR11;
wire VAR8;
wire reset;
wire VAR16;
wire VAR12;
wire VAR14;
wire VAR15;
assign reset = ~VAR31;
VAR2 VAR2... | gpl-3.0 |
jotego/jt12 | hdl/alt/eg_step.v | 1,961 | module MODULE1(
input [2:0] VAR5,
input [5:0] VAR3,
input [2:0] VAR11,
output reg VAR7
);
localparam VAR8=3'd0, VAR9=3'd1, VAR10=3'd2, VAR6=3'd7, VAR1=3'd3;
reg [7:0] VAR4;
always @(*) begin : VAR2
if( VAR3[5:4]==2'b11 ) begin if( VAR3[5:2]==4'hf && VAR5 == VAR8)
end
VAR4 = 8'b11111111; else
case( VAR3[1:0] )
2'd0: VAR... | gpl-3.0 |
Jafet95/I-Proyecto-Laboratorio-de-Dise-o-Sistemas-Digitales | Conversor_BCD_7seg.v | 1,167 | module MODULE1
(
input wire [3:0] VAR1,
output reg [7:0] VAR2
);
always @*
begin
case(VAR1)
4'h0: VAR2 = 8'b00000011; 4'h1: VAR2 = 8'b10011111; 4'h2: VAR2 = 8'b00100101; 4'h3: VAR2 = 8'b00001101; 4'h4: VAR2 = 8'b10011001; 4'h5: VAR2 = 8'b01001001; 4'h6: VAR2 = 8'b01000001; 4'h7: VAR2 = 8'b00011111; 4'h8: VAR2 = 8'b0000... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ba/sky130_fd_sc_ls__o21ba_1.v | 2,316 | module MODULE1 (
VAR4 ,
VAR10 ,
VAR2 ,
VAR1,
VAR6,
VAR8,
VAR3 ,
VAR7
);
output VAR4 ;
input VAR10 ;
input VAR2 ;
input VAR1;
input VAR6;
input VAR8;
input VAR3 ;
input VAR7 ;
VAR9 VAR5 (
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE1 ... | apache-2.0 |
ncos/Xilinx-Verilog | ZOLED/src/OLED/ZedboardOLED.v | 21,451 | module MODULE1
(
output VAR37,
output VAR42,
output VAR5,
output VAR8,
output VAR107,
output VAR3,
input wire VAR2,
input wire [127:0] VAR79,
input wire [127:0] VAR86,
input wire [127:0] VAR95,
input wire [127:0] VAR7
);
reg [143:0] VAR17;
reg [111:0] VAR11;
reg [142:0] VAR50;
reg [95:0] VAR32;
reg [39:0] VAR91;
reg [7... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_jesd_regmap.v | 15,376 | module MODULE1 (
VAR86,
VAR62,
VAR91,
VAR74,
VAR70,
VAR38,
VAR36,
VAR2,
VAR83,
VAR51,
VAR4,
VAR81,
VAR10,
VAR92,
VAR7,
VAR59,
VAR90,
VAR25,
VAR82,
VAR58,
VAR23,
VAR17,
VAR37,
VAR77,
VAR3,
VAR85,
VAR44,
VAR15,
VAR28,
VAR87,
VAR20,
VAR71,
VAR5,
VAR48,
VAR61,
VAR34,
VAR45,
VAR54,
VAR31,
VAR14,
VAR55,
VAR53,
VAR69,
VAR22,
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3.functional.pp.v | 1,832 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR6,
VAR4,
VAR1 ,
VAR5
);
output VAR8 ;
input VAR7 ;
input VAR6;
input VAR4;
input VAR1 ;
input VAR5 ;
wire VAR12 ;
wire VAR10;
buf VAR2 (VAR12 , VAR7 );
VAR3 VAR9 (VAR10, VAR12, VAR6, VAR4);
buf VAR11 (VAR8 , VAR10 );
endmodule | apache-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.