repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.v | 2,286 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR9,
VAR3,
VAR2,
VAR6 ,
VAR8
);
output VAR7 ;
input VAR4 ;
input VAR9;
input VAR3;
input VAR2;
input VAR6 ;
input VAR8 ;
VAR1 VAR5 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR7 ,
VAR4 ,
VAR9
);
output VAR7 ;... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_onchip_memory2_0/synth/pr_region_default_onchip_memory2_0.v | 1,524 | module MODULE1 (
input wire clk, input wire reset, input wire VAR5, input wire [6:0] address, input wire VAR9, input wire VAR2, input wire write, output wire [31:0] VAR4, input wire [31:0] VAR1, input wire [3:0] VAR3 );
VAR8 VAR6 (
.clk (clk), .address (address), .VAR9 (VAR9), .VAR2 (VAR2), .write (write), .VAR4 (VAR4)... | mit |
scalable-networks/ext | uhd/fpga/usrp2/models/cpld_model.v | 2,594 | module MODULE1
(input VAR1, input VAR17, input VAR2, input VAR18,
output dout, output reg VAR11, output VAR10);
reg [7:0] VAR7[0:65535];
reg [15:0] addr;
reg [7:0] VAR12;
assign dout = VAR12[7];
reg [2:0] state, VAR3;
localparam VAR13 = 3'd0;
localparam VAR14 = 3'd1;
localparam VAR6 = 3'd2;
localparam VAR5 = 3'd3;
loca... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_2.functional.pp.v | 1,864 | module MODULE1( VAR22, VAR20, VAR26, VAR10, VAR6, VAR24, VAR2, VAR21, VAR17 );
input VAR2, VAR24, VAR6, VAR10, VAR20, VAR22;
inout VAR21, VAR17;
output VAR26;
wire VAR16;
not VAR25( VAR16, VAR2 );
wire VAR13;
not VAR8( VAR13, VAR24 );
wire VAR12;
not VAR11( VAR12, VAR6 );
wire VAR7;
and VAR5( VAR7, VAR16, VAR13, VAR12 ... | apache-2.0 |
cr88192/bgbtech_bjx1core | bjx1c32b1/DecOp3_0.v | 34,096 | module MODULE1(
clk,
VAR146,
VAR326,
VAR143,
VAR247,
VAR13,
VAR106,
VAR38,
VAR277,
VAR50
);
parameter VAR338 = 0; parameter VAR37 = 0;
input clk; input[47:0] VAR146; input[15:0] VAR326;
output[6:0] VAR143;
output[6:0] VAR247;
output[6:0] VAR13;
output[31:0] VAR106;
output[3:0] VAR38;
output[3:0] VAR277;
output[7:0] VAR... | mit |
sehugg/8bitworkshop | presets/verilog-vga/ram.v | 1,889 | module MODULE1(clk, addr, din, dout, VAR6);
parameter VAR2 = 10; parameter VAR3 = 8;
input clk; input [VAR2-1:0] addr; input [VAR3-1:0] din; output [VAR3-1:0] dout; input VAR6;
reg [VAR3-1:0] VAR5 [0:(1<<VAR2)-1];
always @(posedge clk) begin
if (VAR6) VAR5[addr] <= din; dout <= VAR5[addr]; end
endmodule
module MODULE2(... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv.symbol.v | 1,333 | module MODULE1 (
input VAR1 ,
output VAR2
);
supply1 VAR3;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_2.v | 2,284 | module MODULE1 (
VAR4 ,
VAR3,
VAR6,
VAR5 ,
VAR8 ,
VAR9,
VAR2
);
output VAR4 ;
input VAR3;
input VAR6;
input VAR5 ;
input VAR8 ;
input VAR9;
input VAR2;
VAR7 VAR1 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR4 ,
VAR3,
VAR6,
VAR5 ,
VAR8
);
ou... | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/eth_mac_1g.v | 5,324 | module MODULE1 #
(
parameter VAR11 = 8,
parameter VAR38 = 1,
parameter VAR64 = 64,
parameter VAR28 = 0,
parameter VAR62 = 96,
parameter VAR1 = VAR28,
parameter VAR42 = 16,
parameter VAR4 = 0,
parameter VAR51 = 96,
parameter VAR59 = (VAR1 ? VAR42 : 0) + 1,
parameter VAR43 = (VAR4 ? VAR51 : 0) + 1
)
(
input wire VAR18,
i... | mit |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/ADDSUBWIDE/ADDSUBWIDE_bb.v | 4,025 | module MODULE1 (
VAR3,
VAR4,
VAR1,
VAR2);
input VAR3;
input [25:0] VAR4;
input [25:0] VAR1;
output [25:0] VAR2;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbp/sky130_fd_sc_lp__dfbbp.functional.pp.v | 2,310 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR13 ,
VAR5 ,
VAR15 ,
VAR16,
VAR14 ,
VAR1 ,
VAR6 ,
VAR3
);
output VAR9 ;
output VAR10 ;
input VAR13 ;
input VAR5 ;
input VAR15 ;
input VAR16;
input VAR14 ;
input VAR1 ;
input VAR6 ;
input VAR3 ;
wire VAR19 ;
wire VAR18 ;
wire VAR11 ;
wire VAR17 ;
wire VAR4;
wire VAR12 ;
not VAR2 (VAR19 ... | apache-2.0 |
aospan/NetUP_Dual_Universal_CI-fpga | ip_compiler_for_pci_express-library/altpcie_pll_100_250.v | 10,313 | module MODULE1 (
VAR39,
VAR14,
VAR41);
input VAR39;
input VAR14;
output VAR41;
wire [5:0] VAR36;
wire [0:0] VAR10 = 1'h0;
wire [0:0] VAR47 = 1'h1;
wire [0:0] VAR1 = VAR36[0:0];
wire VAR41 = VAR1;
wire [5:0] VAR37 = {VAR10, VAR10, VAR10, VAR10, VAR10, VAR47};
wire VAR11 = VAR14;
wire [1:0] VAR18 = {VAR10, VAR11};
wire [... | gpl-3.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/nf10_axis_converter.v | 12,985 | module MODULE1
parameter VAR20=64,
parameter VAR15=256,
parameter VAR19=128,
parameter VAR52=16,
parameter VAR9=8,
parameter VAR39=8,
parameter VAR8=0,
parameter VAR30=0,
parameter VAR75=0
)
(
input VAR37,
input VAR56,
output reg [VAR20 - 1:0] VAR3,
output reg [((VAR20 / 8)) - 1:0] VAR54,
output [VAR19-1:0] VAR43,
outp... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a222oi/sky130_fd_sc_hdll__a222oi.blackbox.v | 1,435 | module MODULE1 (
VAR6 ,
VAR2,
VAR4,
VAR9,
VAR5,
VAR1,
VAR10
);
output VAR6 ;
input VAR2;
input VAR4;
input VAR9;
input VAR5;
input VAR1;
input VAR10;
supply1 VAR3;
supply0 VAR8;
supply1 VAR11 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.cache/ip/2017.2/93e5591f9289143f/zynq_design_1_axi_gpio_0_0_stub.v | 2,331 | module MODULE1(VAR9, VAR5, VAR14,
VAR15, VAR1, VAR19, VAR17, VAR12, VAR7,
VAR3, VAR4, VAR2, VAR6, VAR20, VAR13,
VAR16, VAR11, VAR8, VAR10, VAR18)
;
input VAR9;
input VAR5;
input [8:0]VAR14;
input VAR15;
output VAR1;
input [31:0]VAR19;
input [3:0]VAR17;
input VAR12;
output VAR7;
output [1:0]VAR3;
output VAR4;
input VAR2... | mit |
eda-globetrotter/PicenoDecoders | extra_credit/syn/netlist/spare/encoder.syn.v | 1,230 | module MODULE1 ( VAR6, VAR4 );
input [10:0] VAR6;
output [14:0] VAR4;
wire VAR7, VAR37, VAR31, VAR19, VAR1, VAR30, VAR13, VAR32, VAR34, VAR2, VAR36, VAR18, VAR27, VAR10;
assign VAR4[14] = VAR6[10];
assign VAR4[13] = VAR6[9];
assign VAR4[12] = VAR6[8];
assign VAR4[11] = VAR6[7];
assign VAR4[10] = VAR6[6];
assign VAR4[9]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrbp/sky130_fd_sc_hs__sdfrbp.pp.blackbox.v | 1,450 | module MODULE1 (
VAR2,
VAR6 ,
VAR1 ,
VAR7 ,
VAR9 ,
VAR5 ,
VAR4 ,
VAR3 ,
VAR8
);
input VAR2;
input VAR6 ;
input VAR1 ;
output VAR7 ;
output VAR9 ;
input VAR5 ;
input VAR4 ;
input VAR3 ;
input VAR8 ;
endmodule | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/or1200_du.v | 45,213 | module MODULE1(
clk, rst,
VAR164, VAR22, VAR44, VAR104,
VAR19, VAR59,
VAR105, VAR66, VAR30, VAR189,
VAR34, VAR123,
VAR91, VAR176, VAR131, VAR3, VAR173,
VAR115, VAR157, VAR48, VAR43,
VAR170, VAR85, VAR114, VAR50, VAR12,
VAR40, VAR21, VAR182, VAR181, VAR78, VAR68,
VAR7, VAR10, VAR167, VAR124, VAR128, VAR147
);
parameter ... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_1.behavioral.pp.v | 1,246 | module MODULE1( VAR1, VAR5, VAR8, VAR2, VAR6 );
input VAR1, VAR8;
inout VAR2, VAR6;
output VAR5;
VAR3 VAR7(.VAR1(VAR1),.VAR5(VAR5),.VAR8(VAR8),.VAR2(VAR2),.VAR6(VAR6));
VAR3 VAR4(.VAR1(VAR1),.VAR5(VAR5),.VAR8(VAR8),.VAR2(VAR2),.VAR6(VAR6)); | apache-2.0 |
duttondj/DigitalDesignI-P4 | vendingmachine.v | 11,275 | module MODULE1(VAR16, enable, reset, VAR21, VAR28, VAR9, VAR18, VAR23, VAR4, VAR31, VAR5, VAR32);
input VAR16; input enable; input reset; input[1:0] VAR21; input VAR28; output reg [7:0] VAR9, VAR18, VAR23; output reg VAR31, VAR5, VAR32; output VAR4;
reg [7:0] VAR24; reg [27:0] VAR29; reg VAR30, VAR1, VAR26, VAR27, VAR6... | mit |
vipinkmenon/fpgadriver | src/hw/fpga/source/switch_top.v | 27,520 | module MODULE1 #
(
parameter VAR259 = 1,
parameter VAR48 = 3,
parameter VAR124 = 1,
parameter VAR29 = 1,
parameter VAR375 = 10,
parameter VAR342 = 1,
parameter VAR1 = 8,
parameter VAR315 = 64,
parameter VAR455 = 8,
parameter VAR50 = 14,
parameter VAR248 = 4,
parameter VAR88 = 4,
parameter VAR45 = 1,
parameter VAR98 = 1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41a/sky130_fd_sc_ms__o41a.functional.pp.v | 2,047 | module MODULE1 (
VAR14 ,
VAR1 ,
VAR12 ,
VAR7 ,
VAR17 ,
VAR13 ,
VAR3,
VAR2,
VAR8 ,
VAR15
);
output VAR14 ;
input VAR1 ;
input VAR12 ;
input VAR7 ;
input VAR17 ;
input VAR13 ;
input VAR3;
input VAR2;
input VAR8 ;
input VAR15 ;
wire VAR18 ;
wire VAR10 ;
wire VAR6;
or VAR9 (VAR18 , VAR17, VAR7, VAR12, VAR1 );
and VAR4 (VAR... | apache-2.0 |
CatherineH/QubitekkCC | CC1/src/DE0Nano/verilog/four_bit_counter_enable.v | 4,620 | module MODULE1 (
VAR20,
VAR14,
VAR23,
VAR21);
input VAR20;
input VAR14;
input VAR23;
output [3:0] VAR21;
wire [3:0] VAR13;
wire [3:0] VAR21 = VAR13[3:0];
VAR2 VAR6 (
.VAR20 (VAR20),
.VAR14 (VAR14),
.VAR23 (VAR23),
.VAR21 (VAR13),
.VAR16 (1'b0),
.VAR8 (1'b0),
.VAR25 (1'b1),
.VAR5 (1'b1),
.VAR1 (),
.VAR19 ({4{1'b0}}),
.V... | mit |
mbus/mbus | m3_mbus_releases/r04p2g/source/lname_mbus_member_ctrl.tps65.v | 9,473 | module MODULE1 (
input VAR69,
input VAR33,
input VAR2,
input VAR89,
input VAR3,
output VAR94,
output VAR9,
input VAR113,
input VAR104,
output VAR13,
output VAR74,
output VAR116,
output VAR48,
output VAR123,
output VAR126,
input VAR81,
output VAR49,
input VAR30,
input VAR60,
input [3:0] VAR51,
output [3:0] VAR77,
output... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_cpack/util_cpack_mux.v | 109,615 | module MODULE1 (
VAR28,
VAR55,
VAR33,
VAR30,
VAR25,
VAR22,
VAR54,
VAR29,
VAR51,
VAR46,
VAR48,
VAR62,
VAR41,
VAR59,
VAR9,
VAR2,
VAR40,
VAR47,
VAR27,
VAR31,
VAR7);
input VAR28;
input VAR55;
input [ 7:0] VAR33;
input [127:0] VAR30;
output VAR25;
output VAR22;
output [ 15:0] VAR54;
output VAR29;
output [ 31:0] VAR51;
outpu... | gpl-3.0 |
fpgasystems/caribou | hw/src/net/tx_interface.v | 8,989 | module MODULE1 #(
parameter VAR51 = 11 )
(
output [63:0] VAR26,
output [7:0] VAR25,
output VAR53,
output VAR10,
output VAR7,
input VAR12,
input [63:0] VAR19,
input [7:0] VAR45,
input VAR15,
output VAR18,
input VAR24,
input VAR2,
input reset
);
reg VAR35;
reg VAR33;
reg VAR6;
reg VAR42;
reg VAR36;
reg VAR5;
wire VAR54;
... | gpl-3.0 |
HarmonInstruments/verilog | primitives/icape2.v | 1,225 | module MODULE1(input VAR12, VAR3, input [31:0] VAR5);
wire [31:0] VAR1;
genvar VAR11;
generate
for(VAR11=0; VAR11<32; VAR11=VAR11+1)
begin : VAR14
assign VAR1[VAR11] = VAR5[31-VAR11];
end
endgenerate
VAR7 #(.VAR10("VAR4")) VAR13
(.VAR15(),
.VAR8(VAR12),
.VAR9(~VAR3),
.VAR2({VAR1[7:0], VAR1[15:8], VAR1[23:16], VAR1[31:2... | gpl-3.0 |
parallella/oh | common/hdl/oh_csa62.v | 1,688 | module MODULE1 #(parameter VAR24 = 1 )
( input [VAR24-1:0] VAR9, input [VAR24-1:0] VAR12, input [VAR24-1:0] VAR8, input [VAR24-1:0] VAR15, input [VAR24-1:0] VAR5, input [VAR24-1:0] VAR14, input [VAR24-1:0] VAR13, input [VAR24-1:0] VAR23, input [VAR24-1:0] VAR2, output [VAR24-1:0] VAR7, output [VAR24-1:0] VAR19, output ... | mit |
mistryalok/Zedboard | learning/training/MSD/s07/mycore/ip_repo/sample_generator_1.0/hdl/sample_generator_v1_0_M_AXIS.v | 14,410 | module MODULE1 #
(
parameter integer VAR17 = 32,
parameter integer VAR5 = 32
)
(
input wire VAR1,
input wire VAR20,
output wire VAR16,
output wire [VAR17-1 : 0] VAR9,
output wire [(VAR17/8)-1 : 0] VAR6,
output wire VAR26,
input wire VAR15
);
localparam VAR2 = 8;
function integer VAR7 (input integer VAR13);
begin
for(VA... | gpl-3.0 |
cafe-alpha/wascafe | v10/fpga_firmware/wasca/synthesis/submodules/wasca_nios2_gen2_0_cpu_debug_slave_sysclk.v | 6,123 | module MODULE1 (
clk,
VAR8,
VAR30,
VAR28,
VAR1,
VAR9,
VAR18,
VAR2,
VAR17,
VAR4,
VAR26,
VAR5,
VAR15,
VAR3,
VAR6,
VAR19
)
;
output [ 37: 0] VAR9;
output VAR18;
output VAR2;
output VAR17;
output VAR4;
output VAR26;
output VAR5;
output VAR15;
output VAR3;
output VAR6;
output VAR19;
input clk;
input [ 1: 0] VAR8;
input [ 37... | gpl-2.0 |
hitomi2500/wasca | fpga_firmware/wasca/synthesis/submodules/altera_std_synchronizer_nocut.v | 6,568 | module MODULE1 (
clk,
VAR4,
din,
dout
);
parameter VAR1 = 3; parameter VAR3 = 0;
input clk;
input VAR4;
input din;
output dout;
reg VAR5;
reg [VAR1-2:0] VAR2; | gpl-2.0 |
csturton/wirepatch | system/hardware/cores/fabric/ovl_next_wrapped.v | 3,245 | module MODULE1(
clk,
rst,
enable,
VAR5,
VAR8,
VAR7,
VAR10,
out
);
parameter VAR11 = 7;
parameter VAR6 = 3;
input clk;
input rst;
input enable;
input [VAR6-1:0] VAR5;
input VAR8;
input VAR7;
input VAR10;
output out;
wire [2:0] VAR4;
wire [2:0] VAR1;
VAR2 VAR2 (.VAR11(7),
.VAR6(3),
.VAR12(clk),
.reset(rst),
.enable(enabl... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_serdes_out.v | 6,594 | module MODULE1 (
rst,
clk,
VAR84,
VAR60,
VAR86,
VAR5,
VAR34,
VAR30,
VAR6,
VAR51,
VAR54,
VAR28,
VAR25);
parameter VAR73 = 0;
parameter VAR17 = 1;
parameter VAR81 = 16;
localparam VAR22 = 1;
localparam VAR68 = 0;
localparam VAR13 = VAR81 - 1;
input rst;
input clk;
input VAR84;
input [VAR13:0] VAR60;
input [VAR13:0] VAR86... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/register.v | 2,681 | module MODULE1
parameter VAR6 = 0
)
(input VAR7,
input VAR8,
output [VAR5-1:0] VAR3,
input [VAR5-1:0] VAR1,
input VAR4
);
reg [VAR5-1:0] VAR2;
assign VAR3 = VAR2;
always @(posedge VAR7) begin
if(VAR8) begin
VAR2 <= VAR6;
end else if(VAR4) begin
VAR2 <= VAR1;
end
end
endmodule | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/scdata/rtl/scdata_efuse_hdr.v | 9,910 | module MODULE1 (
VAR61, VAR68, VAR9, VAR65,
VAR30, VAR4,
VAR28, VAR14, VAR21,
VAR58, VAR1, VAR60, VAR46, VAR53,
VAR22, VAR41,
VAR2, VAR27, VAR44, VAR33
);
input VAR58, VAR1, VAR60;
output VAR61;
input VAR46;
input VAR53;
input VAR22;
input VAR41;
input VAR2;
input VAR27; input VAR44; input VAR33;
output VAR68; output V... | gpl-2.0 |
mballance/wb_dma | rtl/wb_dma_de.v | 19,654 | module MODULE1(clk, rst,
VAR65, VAR52, VAR5, VAR53,
VAR54, VAR100, VAR97, VAR38,
VAR57, VAR27, VAR39, VAR43,
VAR70, VAR89, VAR64, VAR98,
VAR67, VAR69, VAR25, VAR81, VAR41, VAR84,
VAR62, VAR94, VAR71, VAR77,
VAR1, VAR45, VAR76, VAR12, VAR95,
VAR31, VAR75, VAR15, VAR7, VAR56,
VAR72, VAR99,
VAR26, VAR49,
VAR61, VAR10, VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/diode/sky130_fd_sc_hs__diode.symbol.v | 1,245 | module MODULE1 (
input VAR1
);
supply1 VAR3;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
wendlers/lattice-logic-sniffer | logic/top.v | 7,859 | module MODULE1
(
input clk
,
input VAR1
,
input [7:0] VAR6
,
output VAR5
,
output [7:0] VAR34
,
output VAR31
,
output [7:0] VAR35
,
output VAR52
);
parameter VAR14 = 1'b1;
parameter VAR27 = 1'b0;
parameter VAR29 = 2'b0;
parameter VAR42 = 2'b1;
parameter VAR50 = 7'h0;
parameter VAR48 = 7'h1;
parameter VAR12 = 7'h2;
para... | mit |
Murailab-arch/magukara | cores/asfifo/rtl/asfifo.v | 4,164 | module MODULE1
VAR27 = 4,
VAR20 = (1 << VAR27))
(output wire [VAR5-1:0] dout,
output reg VAR15,
input wire VAR11,
input wire VAR14,
input wire [VAR5-1:0] din,
output reg VAR16,
input wire VAR7,
input wire VAR2,
input wire rst);
reg [VAR5-1:0] VAR3 [VAR20-1:0];
wire [VAR27-1:0] VAR8, VAR19;
wire VAR22;
wire VAR24, VAR9;... | gpl-3.0 |
bluespec/Flute | builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkFBox_Top.v | 5,303 | module MODULE1(VAR5,
VAR1,
VAR2,
VAR8,
VAR34,
VAR25,
VAR21,
VAR40,
VAR23,
VAR24,
VAR17,
VAR31,
VAR29,
VAR14,
VAR38,
valid,
VAR10,
VAR22);
input [3 : 0] VAR5;
input VAR1;
input VAR2;
input VAR8;
output VAR34;
input VAR25;
output VAR21;
input [6 : 0] VAR40;
input [6 : 0] VAR23;
input [2 : 0] VAR24;
input [4 : 0] VAR17;
i... | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/pc_cmp.v | 49,037 | module MODULE1(
clk,
VAR16
);
input clk;
input VAR16;
reg [31:0] VAR2, VAR15;
reg [39:0] VAR27[VAR45-1:0];
reg [39:0] VAR42 [VAR45-1:0];
reg [31:0] VAR10, VAR49, VAR57;
reg [31:0] VAR36, VAR24;
reg [7:0] VAR48;
reg VAR7;
reg VAR1;
integer VAR29, VAR35, VAR37;
wire [1:0] VAR5;
wire [63:0] VAR17;
wire [1:0] VAR53;
wire [... | gpl-2.0 |
zYeoman/32BIT-MIPS-CPU | pipeline/EX2MEM.v | 1,597 | module MODULE1(
input clk, rst,
input VAR1, VAR5, VAR16,
input [31:0] VAR2, VAR8, VAR10,
input [4:0] VAR7,
input [1:0] VAR11,
output reg VAR13, VAR15, VAR14,
output reg [31:0] VAR12, VAR3, VAR6,
output reg [4:0] VAR9,
output reg [1:0] VAR4
);
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR13 <= 0;
VAR15 <... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/v6_mig33_bb.v | 13,676 | module MODULE1 #
(
parameter VAR88 = 200,
parameter VAR114 = "VAR101",
parameter VAR82 = 6, parameter VAR3 = 1,
parameter VAR44 = 3,
parameter VAR108 = 2,
parameter VAR48 = 2500,
parameter VAR31 = "VAR30",
parameter VAR50 = "VAR63",
parameter VAR9 = "VAR63",
parameter VAR61 = 1,
parameter VAR34 = 3,
parameter VAR36 = 1... | lgpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_1/synth/design_1_auto_pc_1.v | 13,151 | module MODULE1 (
VAR107,
VAR8,
VAR46,
VAR43,
VAR37,
VAR88,
VAR72,
VAR100,
VAR79,
VAR1,
VAR58,
VAR106,
VAR42,
VAR101,
VAR90,
VAR19,
VAR39,
VAR44,
VAR102,
VAR89,
VAR29,
VAR6,
VAR112,
VAR56,
VAR2,
VAR14,
VAR66,
VAR53,
VAR110,
VAR80,
VAR96,
VAR78,
VAR76,
VAR83,
VAR62,
VAR68,
VAR36,
VAR91,
VAR34,
VAR5,
VAR67,
VAR32,
VAR63,
... | gpl-3.0 |
tommythorn/yari | shared/rtl/target/ML401/dpram.v | 1,884 | module MODULE1 (VAR20,
VAR15, VAR1, VAR13, VAR8, VAR12,
VAR10, VAR18, VAR14, VAR6, VAR2);
parameter VAR5 = 32;
parameter VAR7 = 7;
parameter VAR11 = "VAR16";
input VAR20;
input [VAR7-1:0] VAR15;
input [VAR5/8-1:0] VAR1;
input [VAR5-1:0] VAR13;
input VAR8;
output [VAR5-1:0] VAR12;
input [VAR7-1:0] VAR10;
input [VAR5-1:0... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_p_pp_pkg_s/sky130_fd_sc_hs__udp_dlatch_p_pp_pkg_s.symbol.v | 1,459 | module MODULE1 (
input VAR3 ,
output VAR7 ,
input VAR6 ,
input VAR5,
input VAR2 ,
input VAR4 ,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211ai/sky130_fd_sc_lp__o211ai_0.v | 2,361 | module MODULE2 (
VAR5 ,
VAR3 ,
VAR2 ,
VAR6 ,
VAR11 ,
VAR10,
VAR1,
VAR4 ,
VAR8
);
output VAR5 ;
input VAR3 ;
input VAR2 ;
input VAR6 ;
input VAR11 ;
input VAR10;
input VAR1;
input VAR4 ;
input VAR8 ;
VAR9 VAR7 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR4(VAR4),
.... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_4.behavioral.pp.v | 2,782 | module MODULE1( VAR11, VAR18, VAR9, VAR20, VAR5, VAR23 );
input VAR9, VAR18, VAR11;
inout VAR5, VAR23;
output VAR20;
reg VAR2;
VAR3 VAR13(.VAR11(VAR11),.VAR18(VAR18),.VAR9(VAR9),.VAR20(VAR20),.VAR5(VAR5),.VAR23(VAR23),.VAR2(VAR2));
VAR3 VAR16(.VAR11(VAR11),.VAR18(VAR18),.VAR9(VAR9),.VAR20(VAR20),.VAR5(VAR5),.VAR23(VAR2... | apache-2.0 |
hydai/Verilog-Practice | HardwareLab/rrab/rrab.v | 1,181 | module MODULE1 (
output reg [1:0] VAR7,
input [1:0] request,
input clk,
input VAR3
);
parameter VAR9 = 2'b00;
parameter VAR6 = 2'b01;
parameter VAR5 = 2'b10;
parameter VAR8 = 2'b11;
reg [1:0] VAR1;
reg VAR2, VAR4;
always @(posedge clk or negedge VAR3) begin
if (!VAR3) begin
VAR2 <= 1'b0;
VAR7 <= VAR9;
end else begin
VA... | mit |
JakeMercer/mac | tx.v | 8,522 | module MODULE1 #(
parameter VAR37 = 4'h0,
parameter VAR35 = 4'h1,
parameter VAR17 = 4'h2,
parameter VAR2 = 4'h3,
parameter VAR51 = 4'h4,
parameter VAR1 = 4'h5,
parameter VAR36 = 4'h6,
parameter VAR32 = 4'h7,
parameter VAR15 = 4'h8,
parameter VAR26 = 4'h9,
parameter VAR47 = 4'hA,
parameter VAR18 = 4'hB
)(
input wire res... | mit |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/rssi.v | 1,512 | module MODULE1 (input VAR6, input reset, input enable,
input [11:0] VAR9, output [15:0] MODULE1, output [15:0] VAR4);
wire VAR8 = (VAR9 == 12'h7FF);
wire VAR1 = (VAR9 == 12'h800);
wire VAR2 = VAR8 | VAR1;
reg [25:0] VAR7;
always @(posedge VAR6)
if(reset | ~enable)
VAR7 <= 26'd0;
else
VAR7 <= VAR7 + (VAR2 ? 26'd65535 : ... | gpl-2.0 |
SymbiFlow/fpga-tool-perf | third_party/jpeg-qnr/div_su.v | 4,686 | module MODULE1(clk, VAR19, VAR3, VAR6, VAR16, VAR9, VAR11, VAR12);
parameter VAR15 = 16;
parameter VAR8 = VAR15 /2;
input clk; input VAR19;
input [VAR15-1:0] VAR3; input [VAR8-1:0] VAR6; output [VAR8 :0] VAR16; output [VAR8-1:0] VAR9; output VAR11;
output VAR12;
reg [VAR8 :0] VAR16;
reg [VAR8-1:0] VAR9;
reg VAR11;
reg ... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4/sky130_fd_sc_hs__nand4_1.v | 2,126 | module MODULE2 (
VAR3 ,
VAR5 ,
VAR6 ,
VAR9 ,
VAR1 ,
VAR8,
VAR2
);
output VAR3 ;
input VAR5 ;
input VAR6 ;
input VAR9 ;
input VAR1 ;
input VAR8;
input VAR2;
VAR4 VAR7 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR3,
VAR5,
VAR6,
VAR9,
VAR1
);
... | apache-2.0 |
jeremycw/tetris-verilog | tetris_blocks.v | 3,747 | module MODULE7(input[2:0] type, input[1:0] VAR3, output reg[0:15] VAR6);
wire[0:15] VAR1, VAR4, VAR31, VAR26, VAR22, VAR11, VAR14;
MODULE4 MODULE6(VAR3, VAR1);
MODULE1 MODULE2(VAR3, VAR4);
MODULE3 MODULE5(VAR3, VAR31);
MODULE8 MODULE7(VAR3, VAR26);
MODULE6 MODULE1(VAR3, VAR22);
MODULE2 MODULE4(VAR3, VAR11);
MODULE5 MOD... | mit |
trivoldus28/pulsarch-verilog | design/sys/edk/pcores/ccx2mb_v1_00_a/hdl/verilog/pcx2mb.v | 14,110 | module MODULE1 (
VAR78,
VAR59,
VAR4,
VAR79,
VAR11,
VAR22,
VAR26,
VAR29,
VAR74,
VAR84
);
parameter VAR25 = 5;
parameter VAR25 = 2;
parameter VAR80 = (((VAR53+VAR25)/VAR35)+1);
parameter VAR23 = (VAR35 * VAR80) -
(VAR53+VAR25+1);
output [4:0] VAR78;
output VAR59;
output [VAR35-1:0] VAR4;
output VAR79;
input VAR11;
input ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4bb/sky130_fd_sc_ms__nand4bb.blackbox.v | 1,336 | module MODULE1 (
VAR1 ,
VAR6,
VAR9,
VAR4 ,
VAR7
);
output VAR1 ;
input VAR6;
input VAR9;
input VAR4 ;
input VAR7 ;
supply1 VAR2;
supply0 VAR3;
supply1 VAR8 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
maltanar/fpga-tidbits | src/main/resources/verilog/GenericSDAccelWrapperTop.v | 4,020 | module MODULE1(input VAR64, input VAR89,
output VAR46,
input VAR105,
input [63:0] VAR28,
input [2:0] VAR92,
output VAR19,
input VAR111,
input [31:0] VAR32,
input [3:0] VAR16,
input VAR108,
output VAR75,
output[1:0] VAR110,
output VAR41,
input VAR50,
input [63:0] VAR103,
input [2:0] VAR94,
input VAR66,
output VAR34,
out... | bsd-2-clause |
google/yaricv32 | uart-tx.v | 4,227 | module MODULE1(
input rst,
input clk,
input VAR13,
input [7 : 0] VAR8,
output VAR26, output VAR15);
localparam VAR2 = 0;
localparam VAR9 = 1;
localparam VAR4 = 2;
localparam VAR11 = 3;
localparam VAR23 = 4;
localparam VAR18 = 5;
localparam VAR14 = 6;
localparam VAR28 = 7;
localparam VAR6 = 8;
localparam VAR20 = 9;
loca... | apache-2.0 |
CprE488/Final | repository/ProcessorIPLib/pcores/fmc_imageon_vita_receiver_v1_13_a/hdl/verilog/serdes_1_to_5_diff_data.v | 14,282 | module MODULE1 # (
parameter VAR60 = "VAR58",
parameter VAR64 = 50,
parameter VAR56 = "VAR16"
)(
input wire VAR62, input wire VAR6, input wire VAR67, input wire VAR94, input wire VAR82, input wire reset, input wire VAR89, input wire VAR1, output wire [4:0] VAR66 );
wire VAR25;
wire VAR74;
wire VAR32;
wire VAR26;
wire V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphetap/sky130_fd_sc_ls__decaphetap.symbol.v | 1,173 | module MODULE1 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21a/sky130_fd_sc_ms__o21a.symbol.v | 1,341 | module MODULE1 (
input VAR4,
input VAR8,
input VAR3,
output VAR1
);
supply1 VAR2;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync_synth.v | 3,173 | module MODULE1 #(parameter VAR26(VAR17)
, parameter VAR26(VAR14)
, parameter VAR8=0
, parameter VAR11=VAR2(VAR14)
, parameter VAR24=0
)
(input VAR5
, input VAR18
, input VAR23
, input [VAR11-1:0] VAR12
, input [VAR3(VAR17, 1):0] VAR20
, input VAR28
, input [VAR11-1:0] VAR9
, output logic [VAR3(VAR17, 1):0] VAR15
, inpu... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4bb/sky130_fd_sc_lp__or4bb.pp.blackbox.v | 1,345 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR8 ,
VAR4 ,
VAR5 ,
VAR9,
VAR7,
VAR3 ,
VAR1
);
output VAR2 ;
input VAR6 ;
input VAR8 ;
input VAR4 ;
input VAR5 ;
input VAR9;
input VAR7;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | communication_assist/upload_fsm_datapath.v | 6,154 | module MODULE1( clk,
rst,
VAR39,
VAR30,
VAR44,
VAR54,
VAR51,
VAR49,
VAR22,
VAR45,
VAR36,
VAR10,
VAR50,
VAR48
);
input clk;
input rst;
input VAR39;
input VAR30;
input VAR44;
input [3:0] VAR54;
input [3:0] VAR51;
input [15:0] VAR49;
input [15:0] VAR22;
input [15:0] VAR45;
output [1:0] VAR36;
output [15:0] VAR10;
output [... | apache-2.0 |
queq/just-stuff | pov/TopFixed/top_teclado.v | 1,239 | module MODULE1(VAR11, VAR12, VAR7, VAR10, VAR22, VAR4, VAR2, VAR15, VAR8,VAR14,string);
input VAR11;
input VAR12;
input VAR7;
input VAR10;
output [6:0] VAR22;
output VAR4, VAR2, VAR15;
output VAR8;
output VAR14;
output wire [76:0] string;
wire VAR20;
wire VAR16;
wire [6:0]VAR5;
VAR18 VAR3(.VAR11(VAR11), .VAR12(VAR12), ... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/ppu/ppu_spr.v | 22,415 | module MODULE1
(
input wire VAR132, input wire VAR68, input wire VAR24, input wire VAR44, input wire VAR75, input wire VAR71, input wire [ 7:0] VAR13, input wire [ 7:0] VAR133, input wire VAR122, input wire [ 9:0] VAR60, input wire [ 9:0] VAR94, input wire [ 9:0] VAR72, input wire VAR55, input wire [ 7:0] VAR50, output... | mit |
mrehkopf/sd2snes | verilog/sd2snes_base/rtc.v | 12,983 | module MODULE1 (
input VAR6,
input VAR53,
input [55:0] VAR33,
input VAR50,
input [59:0] VAR30,
output [59:0] VAR18
);
reg [59:0] VAR2;
reg [59:0] VAR46;
reg [1:0] VAR14;
always @(posedge VAR6) VAR14 <= {VAR14[0], VAR53};
wire VAR42 = (VAR14[1:0] == 2'b01);
reg [2:0] VAR45;
always @(posedge VAR6) VAR45 <= {VAR45[1:0], V... | gpl-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/impl/verilog/FIFO_image_filter_img_1_rows_V.v | 2,987 | module MODULE2 (
clk,
VAR13,
VAR11,
VAR26,
VAR19);
parameter VAR25 = 32'd12;
parameter VAR18 = 32'd2;
parameter VAR23 = 32'd3;
input clk;
input [VAR25-1:0] VAR13;
input VAR11;
input [VAR18-1:0] VAR26;
output [VAR25-1:0] VAR19;
reg[VAR25-1:0] VAR5 [0:VAR23-1];
integer VAR2;
always @ (posedge clk)
begin
if (VAR11)
begin
... | gpl-3.0 |
alexforencich/verilog-ethernet | example/ExaNIC_X25/fpga_10g/rtl/fpga.v | 8,653 | module MODULE1 (
output wire [1:0] VAR25,
output wire [1:0] VAR82,
output wire [1:0] VAR35,
input wire VAR124,
input wire VAR61,
output wire VAR104,
output wire VAR97,
input wire VAR126,
input wire VAR2,
output wire VAR127,
output wire VAR108,
input wire VAR125,
input wire VAR143,
output wire VAR105,
output wire VAR60,... | mit |
dtysky/FPGA-Imaging-Library | InOut/IIC_Ctrl/src/I2C_Controller.v | 6,528 | module MODULE1
(
input VAR12,
input VAR26,
input VAR4,
input VAR25,
input [23:0] VAR9,
output VAR8,
inout VAR22,
input VAR2,
input VAR3,
output VAR13,
output reg VAR16,
output reg [7:0] VAR6
);
reg VAR18;
reg VAR17;
reg [5:0] VAR1;
wire VAR20 = (VAR3 == 1 &&
((VAR1 >= 5 && VAR1 <=12 || VAR1 == 14) ||
(VAR1 >= 16 && VAR... | lgpl-2.1 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/e69044ca/hdl/processing_system7_bfm_v2_0_regc.v | 2,172 | module MODULE1(
VAR38,
VAR37,
VAR15,
VAR22,
VAR16,
VAR19,
VAR24,
VAR11,
VAR6,
VAR18,
VAR20,
VAR43,
VAR42,
VAR32
);
input VAR38;
input VAR37;
input VAR15;
output VAR22;
input[31:0] VAR16;
output[1023:0] VAR19;
input[7:0] VAR24;
input [3:0] VAR11;
input VAR6;
output VAR18;
input[31:0] VAR20;
output[1023:0] VAR43;
input[7... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlstp/sky130_fd_sc_lp__srdlstp.functional.v | 1,732 | module MODULE1 (
VAR13 ,
VAR10 ,
VAR6 ,
VAR1 ,
VAR3
);
output VAR13 ;
input VAR10 ;
input VAR6 ;
input VAR1 ;
input VAR3;
wire VAR4;
wire VAR9;
wire VAR8 ;
wire VAR7 ;
VAR11 VAR12 VAR5 (VAR4 , VAR6, VAR1, VAR10, VAR3, VAR9, VAR8, VAR7);
bufif1 VAR2 (VAR13 , VAR4, VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxtp/sky130_fd_sc_ms__sedfxtp.functional.pp.v | 2,122 | module MODULE1 (
VAR15 ,
VAR6 ,
VAR13 ,
VAR1 ,
VAR4 ,
VAR12 ,
VAR8,
VAR3,
VAR20 ,
VAR2
);
output VAR15 ;
input VAR6 ;
input VAR13 ;
input VAR1 ;
input VAR4 ;
input VAR12 ;
input VAR8;
input VAR3;
input VAR20 ;
input VAR2 ;
wire VAR11 ;
wire VAR10;
wire VAR16 ;
VAR7 VAR17 (VAR10, VAR16, VAR4, VAR12 );
VAR7 VAR18 (VAR16 ... | apache-2.0 |
lvd2/ngs | fpga/obsolete/fpgaD_release/memmap/memmap.v | 3,075 | module MODULE1(
VAR9,VAR4,
VAR10, VAR7, VAR20,
VAR17,VAR15, VAR19,VAR13, VAR6,
VAR3, VAR21, VAR11, VAR12,
VAR16,
VAR18, VAR1,
VAR5, VAR2, VAR8, VAR14 );
input VAR9,VAR4;
input VAR10,VAR7,VAR20;
output reg VAR17,VAR15,VAR19,VAR13,VAR6;
output reg VAR3,VAR21,VAR11,VAR12;
output reg VAR16;
output reg VAR18,VAR1;
input VAR... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_rfifo/util_rfifo.v | 5,569 | module MODULE1 (
VAR2,
VAR23,
VAR11,
VAR16,
VAR17,
VAR8,
VAR12,
VAR22,
VAR6,
VAR21,
VAR9,
VAR24,
VAR5,
VAR7,
VAR15,
VAR18,
VAR3);
parameter VAR1 = 32;
parameter VAR14 = 64;
input VAR2;
input VAR23;
output [VAR1-1:0] VAR11;
output VAR16;
input VAR17;
output VAR8;
input [VAR14-1:0] VAR12;
input VAR22;
output VAR6;
output... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_project/fifo_267x128/fifo_267x128_bb.v | 6,096 | module MODULE1 (
VAR6,
VAR9,
VAR10,
VAR5,
VAR7,
VAR1,
VAR3,
VAR8,
VAR4,
VAR2);
input [266:0] VAR6;
input VAR9;
input VAR10;
input VAR5;
input VAR7;
output [266:0] VAR1;
output VAR3;
output VAR8;
output VAR4;
output [6:0] VAR2;
endmodule | gpl-3.0 |
spacemonkeydelivers/mor1kx | rtl/verilog/pfpu32/pfpu32_f2i.v | 4,866 | module MODULE1
(
input clk,
input rst,
input VAR17, input VAR15, input VAR19, input VAR10, input [9:0] VAR13,
input [23:0] VAR9,
input VAR22, input VAR12,
output reg VAR14, output reg VAR5, output reg [23:0] VAR1, output reg [4:0] VAR23, output reg [3:0] VAR8, output reg VAR11, output reg VAR7 );
wire [9:0] VAR3 = VAR1... | mpl-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/dbg_interface/dbg_register.v | 4,264 | module MODULE1(VAR2, VAR5, VAR1, VAR7, VAR3, VAR6);
parameter VAR4 = 8;
input [VAR4-1:0] VAR2;
input VAR1;
input VAR7;
input VAR3;
input [VAR4-1:0] VAR6;
output [VAR4-1:0] VAR5;
reg [VAR4-1:0] VAR5;
always @ (posedge VAR7)
begin
if(VAR3)
VAR5[VAR4-1:0]<=VAR6;
end
else
begin
if(VAR1) VAR5[VAR4-1:0]<=VAR2[VAR4-1:0];
end
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.v | 2,371 | module MODULE2 (
VAR2 ,
VAR3 ,
VAR5 ,
VAR7,
VAR8 ,
VAR1 ,
VAR10 ,
VAR6
);
output VAR2 ;
input VAR3 ;
input VAR5 ;
input VAR7;
input VAR8 ;
input VAR1 ;
input VAR10 ;
input VAR6 ;
VAR9 VAR4 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR6(VAR6)
);
endmodule
module MODU... | apache-2.0 |
strigeus/fpganes | src/hw_sound.v | 1,628 | module MODULE1(input VAR15, input [15:0] VAR8, input VAR6, input VAR11,
output VAR2, output VAR12, output VAR3, output VAR1);
reg VAR13;
reg [15:0] VAR10;
reg [15:0] VAR5;
reg [16:0] VAR14;
reg [3:0] VAR9;
reg [4:0] VAR4; wire [4:0] VAR7 = VAR4 + 1;
always @(posedge VAR15) begin
if (VAR6) VAR10 <= VAR8;
if (VAR11) VAR5... | gpl-3.0 |
jotego/jt51 | hdl/jt51_phinc_rom.v | 66,279 | module MODULE1(
input [9:0] VAR1,
output reg [11:0] VAR2
);
always @(*) begin : VAR3
case( VAR1 )
10'd0: VAR2 = { 12'd1299 }; 10'd1: VAR2 = { 12'd1300 }; 10'd2: VAR2 = { 12'd1301 }; 10'd3: VAR2 = { 12'd1302 }; 10'd4: VAR2 = { 12'd1303 }; 10'd5: VAR2 = { 12'd1304 }; 10'd6: VAR2 = { 12'd1305 }; 10'd7: VAR2 = { 12'd1306 }... | gpl-3.0 |
bangonkali/sram | i2c_slave_net.v | 3,320 | module MODULE1(VAR4, VAR13, VAR7, VAR24);
inout VAR4;
input VAR13;
output [7:0] VAR24;
input [6:0] VAR7;
VAR22 VAR28(.VAR20(VAR16), .VAR21((~VAR13 | VAR17) ? VAR4 : VAR16));
VAR22 VAR8(.VAR20(VAR17), .VAR21(~VAR13 ? 1'b0 : (VAR4 ^ VAR16)));
wire VAR16 = (~VAR13 | VAR17) ? VAR4 : VAR16 ;
wire VAR17 = ~VAR13 ? 1'b0 : (VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22o/sky130_fd_sc_hd__a22o.pp.symbol.v | 1,368 | module MODULE1 (
input VAR7 ,
input VAR3 ,
input VAR2 ,
input VAR1 ,
output VAR4 ,
input VAR9 ,
input VAR5,
input VAR6,
input VAR8
);
endmodule | apache-2.0 |
jeffkub/n64-cart-reader | old/hdl/ram2048x16.v | 26,817 | module MODULE1 (VAR62, VAR63, VAR7, VAR106, VAR65, VAR91, VAR42);
input wire VAR62;
input wire VAR63;
input wire VAR7;
input wire VAR106;
input wire [10:0] VAR65;
input wire [15:0] VAR91;
output wire [15:0] VAR42;
wire VAR69;
wire VAR139;
VAR52 VAR44 (.VAR125(VAR139), .VAR79(... | mit |
peteasa/parallella-fpga | ohLocal/memory/dv/fifo_async_104x16.v | 1,447 | module MODULE1
(
VAR4, VAR2, VAR3, dout, VAR11, valid,
VAR1, VAR6, VAR8, VAR7, VAR9, din, VAR13
);
parameter VAR12 = 104; parameter VAR10 = 16;
input VAR1; input VAR6; input VAR8; input VAR7;
input VAR9;
input [VAR12-1:0] din;
output VAR4;
output VAR2;
output VAR3;
input VAR13;
output [VAR12-1:0] dout;
output VAR11;
ou... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_2.behavioral.v | 2,848 | module MODULE1( VAR16, VAR19, VAR11, VAR14 );
input VAR11, VAR16, VAR19;
output VAR14;
reg VAR9;
VAR3 VAR8(.VAR16(VAR16),.VAR19(VAR19),.VAR11(VAR11),.VAR14(VAR14),.VAR9(VAR9));
VAR3 VAR21(.VAR16(VAR16),.VAR19(VAR19),.VAR11(VAR11),.VAR14(VAR14),.VAR9(VAR9));
buf VAR1(VAR5,VAR19);
not VAR25(VAR4,VAR11);
and VAR13(VAR15,V... | apache-2.0 |
tsotnep/vhdl_soc_audio_mixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/verilog/user_logic.v | 6,263 | module MODULE1 (
VAR12,
clk,
VAR20,
VAR13,
VAR25,
VAR21,
VAR7,
VAR26,
VAR5,
VAR18,
VAR3,
VAR16);
parameter VAR19 = 32;
parameter VAR10 = 32;
input VAR12;
output clk;
input VAR20;
input VAR13;
input [31:0] VAR25;
input [ 3:0] VAR21;
input [31:0] VAR7;
input [31:0] VAR26;
output [31:0] VAR5;
output VAR18;
output VAR3;
ou... | mit |
alanachtenberg/CSCE-350 | Lab 7/lab7_4.v | 3,018 | module MODULE2(VAR11, VAR4, VAR27, VAR22, VAR2, VAR14, VAR9);
input VAR22, VAR27, VAR2, VAR14, VAR9;
output VAR11, VAR4;
wire VAR25;
wire VAR8, VAR24;
wire VAR18, VAR6;
wire VAR20, VAR21;
wire VAR15, VAR13;
and (VAR25, VAR9, VAR27);
not (VAR8, VAR22);
not (VAR24, VAR25);
nand VAR3(VAR18,VAR25, VAR22);
nand VAR10(VAR6,V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25.behavioral.pp.v | 1,866 | module MODULE1 (
VAR12 ,
VAR1 ,
VAR4,
VAR10,
VAR6 ,
VAR8
);
output VAR12 ;
input VAR1 ;
input VAR4;
input VAR10;
input VAR6 ;
input VAR8 ;
wire VAR2 ;
wire VAR9;
buf VAR5 (VAR2 , VAR1 );
VAR11 VAR3 (VAR9, VAR2, VAR4, VAR10);
buf VAR7 (VAR12 , VAR9 );
endmodule | apache-2.0 |
praveendath92/securePUF | ipcore_dir/emac_single/example_design/emac_single_locallink.v | 14,611 | module MODULE1
(
VAR26,
VAR24,
VAR29,
VAR93,
VAR44,
VAR14,
VAR53,
VAR38,
VAR17,
VAR4,
VAR27,
VAR63,
VAR92,
VAR18,
VAR15,
VAR99,
VAR49,
VAR61,
VAR74,
VAR65,
VAR37,
VAR72,
VAR12,
VAR103,
VAR95,
VAR34,
VAR104,
VAR70,
VAR94,
VAR8,
VAR66,
VAR3,
VAR89,
VAR20,
VAR10,
VAR32,
VAR82 ,
VAR42
);
output VAR26;
input VAR24;
input VA... | gpl-2.0 |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_GeArN8R1P6_syn.v | 7,671 | module MODULE1 ( VAR209, VAR253, VAR11, VAR18 );
input [15:0] VAR253;
input [15:0] VAR11;
output [16:0] VAR18;
input VAR209;
wire VAR92, VAR188, VAR251, VAR265, VAR140, VAR46, VAR136, VAR257, VAR246, VAR27, VAR8, VAR131, VAR238, VAR73,
VAR156, VAR40, VAR5, VAR49, VAR216, VAR101, VAR291, VAR14, VAR269, VAR281, VAR63, VA... | apache-2.0 |
yunqu/PYNQ | boards/ip/interface_slice_1.0/interface_slice.v | 2,318 | module MODULE1(
VAR44,
VAR23,
VAR4,
VAR28,
VAR48,
VAR1,
VAR21,
VAR33,
VAR47,
VAR37,
VAR11,
VAR6,
VAR9,
VAR15,
VAR43,
VAR32,
VAR5,
VAR24,
VAR20,
VAR22,
VAR16,
VAR39,
VAR27,
VAR13,
VAR31,
VAR8,
VAR35,
VAR2,
VAR29,
VAR46,
VAR25,
VAR14,
VAR30,
VAR36,
VAR17,
VAR38,
VAR34,
VAR18,
VAR3,
VAR7,
VAR10,
VAR12
);
parameter VAR41 =... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22o/sky130_fd_sc_lp__a22o_1.v | 2,339 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR5 ,
VAR10 ,
VAR1 ,
VAR6,
VAR2,
VAR7 ,
VAR9
);
output VAR4 ;
input VAR8 ;
input VAR5 ;
input VAR10 ;
input VAR1 ;
input VAR6;
input VAR2;
input VAR7 ;
input VAR9 ;
VAR11 VAR3 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR... | apache-2.0 |
ECE492W2014G4/G4Capstone | DM9000A_IF.v | 1,843 | module MODULE1( VAR2,
VAR11,
VAR6,
VAR14,
VAR3,
VAR8,
VAR12,
VAR5,
VAR10,
VAR7,
VAR15,
VAR4,
VAR16,
VAR1,
VAR17,
VAR9,
VAR18
);
input [15:0] VAR2;
input VAR6;
input VAR14;
input VAR3;
input VAR8;
input VAR12;
input VAR5;
output [15:0] VAR11;
output VAR10;
inout [15:0] VAR7;
output VAR15;
output VAR4;
output VAR16;
outp... | gpl-3.0 |
kkiningh/cs231n-project | src/rtl/SystolicDataSetupRow.v | 1,167 | module MODULE1 #(
parameter VAR1 = 8,
parameter VAR7 = 256,
parameter VAR4 = 2*VAR7-1
) (
input VAR5,
input reset,
input [VAR1-1:0] VAR3 [0:VAR7-1][0:VAR7-1],
output [VAR1-1:0] VAR2[0:VAR7-1][0:VAR4-1]
);
integer VAR8;
integer VAR6;
always @ (posedge VAR5 or posedge reset) begin
if (reset) begin
for( VAR8 = 0; VAR8 < V... | mit |
lokisz/openzcore | pippo-0.9/rtl/verilog/pippo_wbmux.v | 1,897 | module MODULE1(
clk, rst,
VAR1, VAR2,
VAR8, VAR7, VAR6, VAR11,
VAR4, VAR3
);
parameter VAR10 = VAR9;
input clk;
input rst;
input VAR1;
input [VAR10-1:0] VAR8; input [VAR10-1:0] VAR7; input [VAR10-1:0] VAR6; input [VAR10-1:0] VAR11;
input [VAR12-1:0] VAR2;
output [VAR10-1:0] VAR4; output [VAR10-1:0] VAR3;
reg [VAR10-1:0... | gpl-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_us_1/synth/system_auto_us_1.v | 10,766 | module MODULE1 (
VAR39,
VAR36,
VAR76,
VAR41,
VAR68,
VAR58,
VAR70,
VAR6,
VAR30,
VAR9,
VAR43,
VAR2,
VAR71,
VAR94,
VAR84,
VAR49,
VAR38,
VAR65,
VAR77,
VAR90,
VAR63,
VAR37,
VAR48,
VAR85,
VAR22,
VAR87,
VAR31,
VAR54,
VAR4,
VAR88,
VAR29,
VAR10,
VAR62,
VAR21,
VAR60,
VAR100,
VAR97,
VAR86,
VAR80,
VAR82
);
input wire VAR39;
input ... | mit |
olgirard/opengfx430 | core/rtl/verilog/ogfx_backend_lut_fifo.v | 21,644 | module MODULE1 (
VAR7,
VAR39, VAR68,
VAR69, VAR48, VAR2
VAR73, VAR64,
VAR13, VAR62,
VAR40,
VAR8, VAR65, VAR2
VAR35, VAR19,
VAR42, VAR16, VAR31, VAR25, VAR21 );
output VAR7;
output [15:0] VAR39; output VAR68;
output [VAR37:0] VAR69; output VAR48; VAR2
input VAR73; input VAR64;
input [15:0] VAR13; input VAR62;
input [2:0... | bsd-3-clause |
Jawanga/ece385lab9 | lab9_soc/synthesis/submodules/lab9_soc_onchip_memory2_0.v | 3,067 | module MODULE1 (
address,
VAR16,
VAR9,
clk,
VAR32,
reset,
VAR12,
write,
VAR27,
VAR14
)
;
parameter VAR11 = "MODULE1.VAR31";
output [ 31: 0] VAR14;
input [ 1: 0] address;
input [ 3: 0] VAR16;
input VAR9;
input clk;
input VAR32;
input reset;
input VAR12;
input write;
input [ 31: 0] VAR27;
wire VAR2;
wire [ 31: 0] VAR14;
... | apache-2.0 |
alankarkotwal/lca-processor | pipeline/forward_Ex_stage.v | 8,207 | module MODULE1(VAR6,VAR27,VAR9,VAR5,VAR17,VAR8,VAR23,VAR16,VAR20,VAR1,VAR26,
VAR11,VAR14,VAR24,VAR30,VAR15,VAR3);
parameter VAR31 = 6'b000000;
parameter VAR12 = 6'b001000;
parameter VAR21 = 6'b000010;
parameter VAR4 = 6'b000001;
parameter VAR22 = 4'b0001;
parameter VAR18 = 6'b001010;
parameter VAR2 = 6'b001001;
paramet... | gpl-2.0 |
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