repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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vr3d/miaow | src/verilog/rtl/lsu/lsu_in_flight_counter.v | 1,354 | module MODULE1(
VAR5,
VAR12,
VAR15,
VAR10,
clk,
rst
);
parameter VAR11 = 16;
parameter VAR9 = 4;
input [3:0] VAR5;
input [3:0] VAR12;
input VAR15;
output VAR10;
input clk;
input rst;
wire VAR8;
wire VAR6;
wire [VAR9-1:0] VAR1;
reg [VAR9-1:0] VAR4;
assign VAR8 = |VAR5;
assign VAR6 = |VAR12;
VAR13 VAR7[VAR9-1:0](
.VAR14(... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/edfxbp/sky130_fd_sc_hd__edfxbp.functional.v | 1,870 | module MODULE1 (
VAR7 ,
VAR9,
VAR8,
VAR10 ,
VAR2
);
output VAR7 ;
output VAR9;
input VAR8;
input VAR10 ;
input VAR2 ;
wire VAR13 ;
wire VAR5;
VAR4 VAR1 (VAR5, VAR13, VAR10, VAR2 );
VAR3 VAR6 VAR14 (VAR13 , VAR5, VAR8 );
buf VAR12 (VAR7 , VAR13 );
not VAR11 (VAR9 , VAR13 );
endmodule | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pll.v | 6,817 | module MODULE1
( input VAR6,
output VAR49,
output VAR41,
output VAR20,
output VAR18,
input VAR68,
output VAR47
);
VAR22 VAR67
(.VAR29 (VAR55),
.VAR13 (VAR6));
wire [15:0] VAR52;
wire VAR70;
wire VAR53;
wire VAR32;
wire VAR60;
wire VAR4;
wire VAR40;
wire VAR8;
wire VAR11;
wire VAR34;
wire VAR35;
wire VAR66;
wire VAR17;
... | gpl-2.0 |
manu3193/TextEditor | text_editor_keyboard_controller.v | 3,958 | module MODULE1(
input VAR20,
input VAR12,
input VAR26,
inout VAR7,
inout VAR22,
output reg [7:0] VAR25,
output reg VAR23
);
reg [1:0] state;
localparam
VAR9 = 2'b00,
VAR24 = 2'b01,
VAR3 = 2'b10,
VAR21 = 2'VAR2;
wire [7:0] VAR28;
wire VAR19;
reg [7:0] VAR11;
reg VAR4;
reg [7:0] VAR27;
wire VAR10;
VAR16 VAR17(
.VAR8(VAR1... | mit |
hydai/Verilog-Practice | HardwareLab/Lab8/LCD_DISPLAY_CTRL.v | 5,168 | module MODULE1(VAR10, VAR3, VAR6, VAR4, reset, clk);
input clk;
input reset, VAR3, VAR6;
input [15:0] VAR4;
output [255:0] VAR10;
reg [255:0] VAR10, VAR5;
reg [4:0] counter, VAR7;
wire [255:0] VAR1, VAR8;
wire [255:0] VAR2, VAR9;
always @(negedge clk or negedge reset) begin
if (!reset) begin
VAR10 <= 256'd0;
counter <=... | mit |
drichmond/riffa | fpga/altera/de5/DE5Gen1x8If64/hdl/DE5Gen1x8If64.v | 23,796 | module MODULE1
parameter VAR196 = 8,
parameter VAR30 = 64,
parameter VAR170 = 256,
parameter VAR145 = 5
)
(
output [7:0] VAR139,
input VAR46,
input VAR52,
input [VAR196-1:0] VAR25,
output [VAR196-1:0] VAR100,
input VAR105
);
wire VAR181;
wire VAR127;
wire [11:0] VAR204;
wire [31:0] VAR163;
wire VAR133;
wire VAR138;
wir... | bsd-3-clause |
scalable-networks/ext | uhd/fpga/usrp2/top/E1x0/E1x0.v | 8,623 | module MODULE1
(input VAR25, input VAR123, output [3:0] VAR6, output [31:0] VAR146, output [1:0] VAR50,
input VAR42, output VAR45, input VAR100,
output VAR136, input VAR152, input VAR9, output VAR3,
input VAR35, inout [15:0] VAR66, input [10:1] VAR134, input [1:0] VAR115,
input VAR92, input VAR120, input VAR128, input ... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9671/axi_ad9671_pnmon.v | 7,262 | module MODULE1 (
VAR2,
VAR13,
VAR1,
VAR9,
VAR7,
VAR19);
input VAR2;
input VAR13;
input [15:0] VAR1;
output VAR9;
output VAR7;
input [ 3:0] VAR19;
reg VAR5 = 'd0;
reg [31:0] VAR14 = 'd0;
reg [31:0] VAR12 = 'd0;
wire VAR3;
wire [31:0] VAR16;
function [31:0] VAR11;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[2... | gpl-3.0 |
Openlights/hydra-fpga | hydra/hdl/address_generator.v | 1,303 | module MODULE1 (
clk,
VAR4,
VAR5,
VAR1,
VAR3,
addr
);
parameter VAR2 = 24;
parameter VAR6 = 16;
input clk;
input VAR4;
input [VAR6-1:0] VAR5;
input [VAR6-1:0] VAR1;
input [VAR6-1:0] VAR3;
output reg [VAR2-1:0] addr;
always @(posedge clk) begin
if (VAR4 == 1'b0) begin
addr = { VAR2 {1'b0} };
end
else begin
if (VAR1 > VA... | mit |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Voters/Voter.v | 1,237 | module MODULE1 #(parameter VAR6 = 1)(
input [(VAR6-1):0] VAR2, VAR5, VAR4,
output [(VAR6-1):0] VAR1
);
genvar VAR3;
generate
for (VAR3 = 0; VAR3 < VAR6; VAR3 = VAR3 +1) begin : VAR7
assign VAR1[VAR3] = (VAR2[VAR3] && VAR5[VAR3]) || (VAR2[VAR3] && VAR4[VAR3]) || (VAR5[VAR3] && VAR4[VAR3]);
end
endgenerate
endmodule | lgpl-3.0 |
ptracton/wb_soc_template | rtl/XILINX/BUFGCE.v | 4,712 | module MODULE1 #(
parameter VAR8 = "VAR12",
parameter VAR14 = "VAR27",
parameter [0:0] VAR1 = 1'b0,
parameter [0:0] VAR7 = 1'b0
)(
output VAR32,
input VAR29,
input VAR9
);
localparam VAR11 = "MODULE1";
localparam VAR17 = 0;
localparam VAR18 = 0;
localparam VAR35 = 0;
localparam VAR22 = 0;
localparam VAR3 = 1;
localpara... | mit |
ridecore/ridecore | src/fpga/arf.v | 33,559 | module MODULE2
(
input wire clk,
input wire reset,
input wire [VAR148-1:0] VAR23, input wire [VAR148-1:0] VAR90,
input wire [VAR148-1:0] VAR32,
input wire [VAR148-1:0] VAR63,
output wire [VAR14-1:0] VAR113,
output wire [VAR14-1:0] VAR147,
output wire [VAR14-1:0] VAR76,
output wire [VAR14-1:0] VAR144, input wire [VAR148... | bsd-3-clause |
esonghori/TinyGarble | circuit_synthesis/a23/a23_core.v | 11,574 | module MODULE1
(
input VAR93,
input VAR83,
output [31:0] VAR13, output [31:0] VAR60,
output VAR12,
output [3:0] VAR100,
input [31:0] VAR66,
output VAR71
);
wire [31:0] VAR3;
wire [31:0] VAR19; wire [31:0] VAR15;
wire VAR55;
wire [31:0] VAR78;
wire [3:0] VAR102;
wire VAR52;
wire [31:0] VAR68;
wire [4:0] VAR113;
wire [3:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1n/sky130_fd_sc_lp__inputiso1n.pp.blackbox.v | 1,385 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR2,
VAR6 ,
VAR3 ,
VAR1 ,
VAR7
);
output VAR4 ;
input VAR5 ;
input VAR2;
input VAR6 ;
input VAR3 ;
input VAR1 ;
input VAR7 ;
endmodule | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/ram0_top.v | 3,696 | module MODULE1(
input VAR13,
input VAR5,
input VAR4,
input VAR24,
output reg VAR25,
input [31:0] VAR34,
input [3:0] VAR2,
input VAR17,
input [31:0] VAR10,
output [31:0] VAR27,
input VAR26,
input VAR7,
input [15:0] VAR20,
input [31:0] VAR19,
output [31:0] VAR14,
output [7:0] VAR6, input [1:0] VAR15 );
wire [31:0] VAR1;
... | gpl-2.0 |
SymbiFlow/yosys | techlibs/xilinx/xc2v_brams_map.v | 5,842 | module \VAR36 (VAR43, VAR16, VAR23, VAR22, VAR32, VAR6, VAR1, VAR7);
parameter VAR47 = 9;
parameter VAR27 = 36;
parameter VAR45 = 1;
parameter VAR34 = 1;
parameter VAR41 = 1;
parameter [18431:0] VAR25 = 18432'VAR30;
input VAR43;
input VAR16;
input [VAR47-1:0] VAR23;
output [VAR27-1:0] VAR22;
input VAR32;
input [VAR47-1... | isc |
golfit/QcmMasterController | counterDiagnosticVersion.v | 9,213 | module MODULE1 (clk,VAR7,VAR3,VAR2);
input clk,VAR7;
output reg [13:0] VAR3;
reg [13:0] VAR5; reg [13:0] VAR4;
output reg [13:0] VAR2; reg [6:0] VAR8; reg VAR6; reg VAR1; reg reset; | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32oi/sky130_fd_sc_ms__a32oi.functional.pp.v | 2,238 | module MODULE1 (
VAR15 ,
VAR19 ,
VAR8 ,
VAR13 ,
VAR1 ,
VAR4 ,
VAR6,
VAR2,
VAR3 ,
VAR16
);
output VAR15 ;
input VAR19 ;
input VAR8 ;
input VAR13 ;
input VAR1 ;
input VAR4 ;
input VAR6;
input VAR2;
input VAR3 ;
input VAR16 ;
wire VAR18 ;
wire VAR17 ;
wire VAR5 ;
wire VAR10;
nand VAR9 (VAR18 , VAR8, VAR19, VAR13 );
nand V... | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/Video_System/submodules/altera_up_av_config_auto_init_dc2.v | 8,036 | module MODULE1 (
VAR14,
VAR8
);
parameter VAR4 = 16'h000C;
parameter VAR26 = 16'h001E;
parameter VAR12 = 16'h0400;
parameter VAR18 = 16'h0500;
parameter VAR6 = 16'h0088; parameter VAR5 = 16'h0019; parameter VAR1 = 16'h00C6;
parameter VAR3 = 16'h0019;
parameter VAR2 = 16'h0432;
parameter VAR16 = 16'h0011;
parameter VAR2... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4b/sky130_fd_sc_lp__or4b.pp.blackbox.v | 1,335 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR2 ,
VAR4 ,
VAR3 ,
VAR7,
VAR1,
VAR5 ,
VAR6
);
output VAR9 ;
input VAR8 ;
input VAR2 ;
input VAR4 ;
input VAR3 ;
input VAR7;
input VAR1;
input VAR5 ;
input VAR6 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/mul/rtl/sparc_mul_dp.v | 6,733 | module MODULE1(
VAR27,
VAR6,
VAR38,
VAR2,
valid,
VAR9,
VAR33,
VAR52,
VAR28,
VAR23,
VAR43,
VAR37,
VAR24,
VAR7,
VAR30,
VAR16,
VAR21,
VAR49,
VAR8,
VAR45,
VAR53,
VAR19
);
input [63:0] VAR27; input [63:0] VAR6; input [63:0] VAR38; input [63:0] VAR2; input valid; input VAR9; input VAR33; input VAR52; input VAR28; input VAR23... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_1.functional.pp.v | 1,804 | module MODULE1( VAR22, VAR4, VAR18, VAR15, VAR2, VAR19, VAR8 );
input VAR15, VAR2, VAR4, VAR22;
inout VAR19, VAR8;
output VAR18;
wire VAR24;
not VAR7( VAR24, VAR15 );
wire VAR11;
not VAR13( VAR11, VAR4 );
wire VAR17;
and VAR9( VAR17, VAR24, VAR11 );
wire VAR16;
not VAR12( VAR16, VAR22 );
wire VAR1;
and VAR20( VAR1, VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4b/sky130_fd_sc_ms__or4b.functional.v | 1,402 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR9 ,
VAR5 ,
VAR7
);
output VAR6 ;
input VAR1 ;
input VAR9 ;
input VAR5 ;
input VAR7;
wire VAR8 ;
wire VAR2;
not VAR3 (VAR8 , VAR7 );
or VAR4 (VAR2, VAR8, VAR5, VAR9, VAR1);
buf VAR10 (VAR6 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd2/sky130_fd_sc_ms__dlygate4sd2.functional.pp.v | 1,832 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR9,
VAR4,
VAR6 ,
VAR1
);
output VAR5 ;
input VAR8 ;
input VAR9;
input VAR4;
input VAR6 ;
input VAR1 ;
wire VAR7 ;
wire VAR11;
buf VAR3 (VAR7 , VAR8 );
VAR12 VAR10 (VAR11, VAR7, VAR9, VAR4);
buf VAR2 (VAR5 , VAR11 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4bb/sky130_fd_sc_hd__and4bb.functional.pp.v | 1,998 | module MODULE1 (
VAR6 ,
VAR17 ,
VAR12 ,
VAR14 ,
VAR7 ,
VAR13,
VAR1,
VAR2 ,
VAR8
);
output VAR6 ;
input VAR17 ;
input VAR12 ;
input VAR14 ;
input VAR7 ;
input VAR13;
input VAR1;
input VAR2 ;
input VAR8 ;
wire VAR16 ;
wire VAR9 ;
wire VAR4;
nor VAR10 (VAR16 , VAR17, VAR12 );
and VAR11 (VAR9 , VAR16, VAR14, VAR7 );
VAR3 V... | apache-2.0 |
fredmorcos/attic | projects/vo-tools/machines/sbn-machine/sbn.v | 1,917 | module MODULE4 (clk, VAR17, addr, in, out);
parameter VAR7 = 32;
parameter VAR15 = 8;
input clk;
input VAR17;
input [VAR15-1:0] addr;
input [VAR7-1:0] in;
output [VAR7-1:0] out;
reg [VAR7-1:0] VAR12 [0:(2**VAR15)-1];
always @ (posedge clk)
if (VAR17) VAR12[addr] <= in;
always @ (addr)
assign out = VAR12[addr];
endmodul... | isc |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/rxc_engine_ultrascale.v | 19,958 | module MODULE1
parameter VAR45=10,
parameter VAR32 = 0,
parameter VAR2 = 1)
( input VAR17,
input VAR29, input VAR62, output VAR26,
input VAR110,
input VAR121,
input [VAR130-1:0] VAR131,
input [(VAR130/32)-1:0] VAR24,
input [VAR39-1:0] VAR64,
output VAR94,
output [VAR130-1:0] VAR74,
output VAR119,
output [(VAR130/32)-1:... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/spiral_16.v | 3,200 | module MODULE1(
VAR34,
VAR13,
VAR33,
VAR28,
VAR27,
VAR1,
VAR15,
VAR18,
VAR7,
VAR45,
VAR26,
VAR24,
VAR6,
VAR23,
VAR50,
VAR41
);
input signed [16:0] VAR34;
output signed [16+7:0] VAR13;
output signed [16+7:0] VAR33;
output signed [16+7:0] VAR28;
output signed [16+7:0] VAR27;
output signed [16+7:0] VAR1;
output signed [16... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3/sky130_fd_sc_lp__nand3.functional.v | 1,291 | module MODULE1 (
VAR2,
VAR5,
VAR6,
VAR1
);
output VAR2;
input VAR5;
input VAR6;
input VAR1;
wire VAR3;
nand VAR4 (VAR3, VAR6, VAR5, VAR1 );
buf VAR7 (VAR2 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32oi/sky130_fd_sc_hdll__a32oi.blackbox.v | 1,442 | module MODULE1 (
VAR4 ,
VAR7,
VAR8,
VAR3,
VAR2,
VAR10
);
output VAR4 ;
input VAR7;
input VAR8;
input VAR3;
input VAR2;
input VAR10;
supply1 VAR9;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
Elphel/x393_sata | host/gtx_8x10enc.v | 4,989 | module MODULE1(
input wire rst,
input wire clk,
input wire [1:0] VAR10,
input wire [15:0] VAR34,
output wire [19:0] VAR9
);
wire [8:0] VAR23;
wire [8:0] VAR27;
assign VAR23 = {VAR10[0], VAR34[7:0]};
assign VAR27 = {VAR10[1], VAR34[15:8]};
wire [31:0] VAR8;
wire [31:0] VAR44;
reg [19:0] VAR28;
reg [19:0] VAR31;
wire [19... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/spu/rtl/spu_madp.v | 25,971 | module MODULE1 (
VAR147,
VAR109,
VAR1,
VAR100,
VAR33,
VAR141,
VAR58,
VAR122,
VAR88,
VAR13,
VAR169,
VAR112,
VAR80,
VAR41,
VAR152,
VAR5,
VAR15,
VAR12,
VAR108,
VAR67,
VAR97,
VAR91,
VAR64,
VAR167,
VAR118,
VAR131,
VAR96,
VAR76,
VAR36,
VAR106,
VAR55,
VAR90,
VAR27,
VAR51,
VAR60,
VAR176,
VAR135,
VAR30,
VAR71,
VAR85,
VAR14,
VAR... | gpl-2.0 |
ncos/Xilinx-Verilog | SINGEN/src/toplevel.v | 2,224 | module MODULE1
(
VAR14,
VAR39,
VAR46,
VAR33,
VAR43,
VAR15,
VAR18,
VAR35,
VAR24,
VAR31,
VAR22,
VAR23,
VAR28,
VAR19,
VAR38,
VAR29,
VAR40,
VAR2,
VAR12,
VAR48,
VAR4,
VAR13,
VAR49,
VAR50,
VAR8,
VAR32,
VAR44,
VAR16,
VAR17,
VAR36,
VAR21,
VAR1,
VAR6,
VAR7,
VAR11,
VAR20,
VAR25,
VAR10,
VAR3,
VAR37,
VAR42,
VAR30,
VAR27,
VAR26
);
... | mit |
TalentlessAlpaca/Automated_Vacuum_Cleaner | crc_7/peripheral_crc_7.v | 1,814 | module MODULE1(clk , rst , din , VAR1 , addr , rd , wr, dout );
input clk;
input rst;
input [15:0]din;
input VAR1;
input [3:0]addr; input rd;
input wr;
output reg [15:0]dout;
reg [3:0] VAR3;
reg [16:0] VAR8=0;
reg VAR7=0;
wire [6:0] VAR6;
wire VAR5;
always @(*) begin case (addr)
4'h0:begin VAR3 = (VAR1 && wr) ? 4'b0001... | mit |
jairov4/accel-oil | solution_kintex7/syn/verilog/nfa_accept_sample.v | 43,247 | module MODULE1 (
VAR58,
VAR238,
VAR70,
VAR180,
VAR164,
VAR52,
VAR11,
VAR155,
VAR271,
VAR80,
VAR225,
VAR74,
VAR229,
VAR235,
VAR6,
VAR139,
VAR43,
VAR100,
VAR174,
VAR149,
VAR75,
VAR117,
VAR46,
VAR214,
VAR38,
VAR17,
VAR143,
VAR245,
VAR98,
VAR97,
VAR256,
VAR227,
VAR190,
VAR167,
VAR67,
VAR172,
VAR215,
VAR282,
VAR150,
VAR34,
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai.pp.symbol.v | 1,391 | module MODULE1 (
input VAR1,
input VAR7,
input VAR2 ,
input VAR9 ,
output VAR5 ,
input VAR6 ,
input VAR8,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
Jafet95/I-Proyecto-Laboratorio-de-Dise-o-Sistemas-Digitales | DivFrec.v | 1,226 | module MODULE1(clk,rst,VAR7,VAR2,VAR1);
input wire clk,rst;
input wire [10:0]VAR7;
output wire VAR2;
output wire VAR1;
reg [10:0]VAR3 = 0;
reg VAR5 = 0;
reg [15:0]VAR4 = 0;
reg VAR6 = 0;
always@(posedge clk, posedge rst)
if (rst)
begin
VAR3 <= 0;
VAR5 <=0;
end
else
if (VAR3==VAR7)
begin
VAR3 <= 0;
VAR5 <= ~VAR5;
end
el... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor3/sky130_fd_sc_ls__xnor3.behavioral.pp.v | 1,828 | module MODULE1 (
VAR13 ,
VAR4 ,
VAR2 ,
VAR9 ,
VAR14,
VAR7,
VAR5 ,
VAR10
);
output VAR13 ;
input VAR4 ;
input VAR2 ;
input VAR9 ;
input VAR14;
input VAR7;
input VAR5 ;
input VAR10 ;
wire VAR6 ;
wire VAR1;
xnor VAR3 (VAR6 , VAR4, VAR2, VAR9 );
VAR8 VAR12 (VAR1, VAR6, VAR14, VAR7);
buf VAR11 (VAR13 , VAR1 );
endmodule | apache-2.0 |
Marcoslz22/Tercer_Proyecto | Deteccion_Tecla.v | 4,900 | module MODULE1(
input clk,
input reset,
input VAR61,
input VAR36,
input VAR77,
input [7:0] VAR53,
input [7:0] VAR55,
input [7:0] VAR54,
output [7:0] VAR64,
output VAR9,
output [7:0] VAR37,
output [7:0] VAR4,
output [7:0] VAR16,
output [7:0] VAR51,
output [7:0] VAR19,
output [7:0] VAR17,
output [7:0] VAR7,
output VAR29,... | mit |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.cache/ip/1b79005c37c3e993/design_1_axi_gpio_0_0_stub.v | 2,385 | module MODULE1(VAR15, VAR10, VAR17,
VAR11, VAR4, VAR3, VAR6, VAR21, VAR18,
VAR22, VAR19, VAR9, VAR8, VAR12, VAR13,
VAR20, VAR16, VAR7, VAR1, VAR14, VAR5, VAR2)
;
input VAR15;
input VAR10;
input [8:0]VAR17;
input VAR11;
output VAR4;
input [31:0]VAR3;
input [3:0]VAR6;
input VAR21;
output VAR18;
output [1:0]VAR22;
output ... | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/neek/backend/rtl/verilog/ddr_ctrl_ip/alt_mem_ddrx_addr_cmd.v | 24,623 | module MODULE1
VAR75 = 3,
VAR60 = 1,
VAR57 = 1,
VAR11 = 1, VAR38 = 16, VAR7 = 16, VAR70 = 12, VAR66 = 3, VAR44 = "VAR17",
VAR65 = 2
)
(
VAR5,
VAR20,
VAR47,
VAR71,
VAR42,
VAR34,
VAR51,
VAR81,
VAR14,
VAR74,
VAR9,
VAR31,
VAR68,
VAR41,
VAR78,
VAR21,
VAR54,
VAR43,
VAR72, VAR18,
VAR69, VAR32,
VAR80,
VAR3,
VAR25, VAR28,
VAR52... | gpl-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/MultiplyMultDescale.v | 1,872 | module MODULE1(
input [32:0] VAR19,
input [32:0] VAR5,
input [32:0] VAR18,
input VAR2,
input [7:0] VAR11,
input VAR4,
input [31:0] VAR7,
input VAR3,
output reg VAR1,
output reg [32:0] VAR15,
output reg [49:0] VAR22,
output reg [7:0] VAR12,
output reg VAR6,
output reg [31:0] VAR17
);
parameter VAR13 = 1'b0,
VAR16 = 1'b1... | apache-2.0 |
masc-ucsc/cmpe220fall16 | rtl/l2tlb.v | 10,316 | module MODULE1(
input clk
,input reset
,input VAR65
,output VAR62
,input VAR30 VAR31
,output VAR92
,input VAR46
,output VAR96 VAR104
,output VAR110
,input VAR90
,output VAR14 VAR106
,output VAR98
,input VAR79
,output VAR56 VAR97
,input VAR102
,output VAR112
,input VAR41 VAR11
,input VAR2
,output VAR29
,input VAR27 VAR5... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_min/rtl/jbi_min_wdq.v | 9,106 | module MODULE1(
VAR24, VAR35, VAR62, VAR26,
VAR52, VAR59, VAR56, VAR5,
VAR46, VAR13, VAR31, VAR8,
VAR45, VAR6, VAR9,
VAR49, VAR2, VAR36, VAR4, VAR16, VAR37,
VAR41, VAR53, VAR22, VAR38, VAR60,
VAR10, VAR39, VAR54, VAR23,
VAR34, VAR33, VAR25, VAR14,
VAR17, VAR61, VAR1,
VAR3, VAR7,
VAR11, clk, VAR29, VAR44
);
input VAR29;... | gpl-2.0 |
asicguy/gplgpu | hdl/vga/final_cursor.v | 4,049 | module MODULE1
(
input VAR15,
input VAR1,
input VAR8, input VAR13, input VAR2, input VAR4, input VAR11, input VAR7, input VAR14,
output VAR16,
output MODULE1,
output VAR6
);
reg VAR9;
reg [2:0] VAR10;
reg VAR12;
reg [4:0] VAR3;
wire [2:0] VAR17; wire VAR5;
always @(posedge VAR1 or negedge VAR15)
if (!VAR15) VAR10 <= 3'... | gpl-3.0 |
iori-yja/ball_detector | sram.v | 9,076 | module MODULE1 (
VAR43,
VAR35,
VAR20,
VAR33,
VAR4,
VAR41);
input VAR43;
input [15:0] VAR35;
input [11:0] VAR20;
input [11:0] VAR33;
input VAR4;
output [15:0] VAR41;
tri1 VAR43;
tri0 VAR4;
wire [15:0] VAR11;
wire [15:0] VAR41 = VAR11[15:0];
VAR54 VAR23 (
.VAR32 (VAR33),
.VAR12 (VAR43),
.VAR55 (VAR35),
.VAR25 (VAR4),
.VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3b/sky130_fd_sc_ls__nor3b_1.v | 2,254 | module MODULE2 (
VAR2 ,
VAR8 ,
VAR6 ,
VAR10 ,
VAR3,
VAR7,
VAR9 ,
VAR1
);
output VAR2 ;
input VAR8 ;
input VAR6 ;
input VAR10 ;
input VAR3;
input VAR7;
input VAR9 ;
input VAR1 ;
VAR4 VAR5 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2.behavioral.v | 1,724 | module MODULE1 (
VAR10 ,
VAR2 ,
VAR9,
VAR5
);
output VAR10 ;
input VAR2 ;
input VAR9;
input VAR5;
wire VAR7 ;
wire VAR4;
buf VAR8 (VAR7 , VAR2 );
VAR3 VAR6 (VAR4, VAR7, VAR9, VAR5);
buf VAR1 (VAR10 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkbuf/sky130_fd_sc_ms__clkbuf.pp.symbol.v | 1,262 | module MODULE1 (
input VAR2 ,
output VAR6 ,
input VAR3 ,
input VAR1,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4/sky130_fd_sc_hd__and4.pp.blackbox.v | 1,314 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR9 ,
VAR8 ,
VAR4 ,
VAR1,
VAR3,
VAR2 ,
VAR6
);
output VAR5 ;
input VAR7 ;
input VAR9 ;
input VAR8 ;
input VAR4 ;
input VAR1;
input VAR3;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_nto1_mux.v | 4,814 | module MODULE1 #
(
parameter integer VAR3 = 1, parameter integer VAR5 = 1, parameter integer VAR4 = 1, parameter integer VAR6 = 0 )
(
input wire [VAR3-1:0] VAR12, input wire [VAR5-1:0] VAR14, input wire [VAR3*VAR4-1:0] VAR9, output wire [VAR4-1:0] VAR11 );
wire [VAR4*VAR3-1:0] VAR7;
genvar VAR13;
generate
if (VAR6 == 0... | mit |
KorotkiyEugene/LAG_sv_syn_quartus | LAG_matrix_arbiter.v | 5,446 | module MODULE1 (state, VAR15, VAR3);
parameter VAR2=4;
input [VAR2*VAR2-1:0] state;
input [VAR2-1:0] VAR15;
output [VAR2*VAR2-1:0] VAR3;
genvar VAR9,VAR1;
generate
for (VAR9=0; VAR9<VAR2; VAR9=VAR9+1) begin:VAR19
for (VAR1=0; VAR1<VAR2; VAR1=VAR1+1) begin:VAR16
assign VAR3[VAR1*VAR2+VAR9]= (state[VAR1*VAR2+VAR9]&&!VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.blackbox.v | 1,298 | module MODULE1 (
VAR6 ,
VAR2,
VAR4,
VAR3,
VAR7,
VAR5,
VAR1
);
output VAR6 ;
input VAR2;
input VAR4;
input VAR3;
input VAR7;
input VAR5;
input VAR1;
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/data_compression/8-way_2-tree/src/riffa/reset_extender.v | 3,480 | module MODULE1
(input VAR5,
input VAR14,
input VAR2,
output VAR20,
output VAR13);
localparam VAR21 = VAR6(VAR23);
localparam VAR10 = 1 << VAR21;
localparam VAR24 = 4;
wire [VAR21:0] VAR16;
wire [VAR24:0] VAR4;
assign VAR13 = VAR4 != 0;
assign VAR20 = VAR4[VAR24];
counter
.VAR22 (VAR10),
.VAR8 (VAR10 - VAR23)
)
VAR17
( ... | mit |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/wb_ram_dist.v | 1,405 | module MODULE1
(input VAR10,
input VAR7,
input VAR6,
input [VAR8-1:0] VAR1,
input [31:0] VAR2,
input [3:0] VAR9,
output [31:0] VAR3,
output VAR5);
reg [31:0] VAR4 [0:1<<(VAR8-1)];
always @(posedge VAR10)
begin
if(VAR7 & VAR6 & VAR9[3])
VAR4[VAR1][31:24] <= VAR2[31:24];
if(VAR7 & VAR6 & VAR9[2])
VAR4[VAR1][24:16] <= VAR... | gpl-2.0 |
seyedmaysamlavasani/GorillaPP | chisel/Gorilla++/verilogOrig/Offloaded.v | 22,015 | module MODULE2(input clk, input reset,
output VAR162,
input VAR202,
input [31:0] VAR157,
input VAR89,
output VAR111,
output[31:0] VAR122,
input VAR119,
input VAR88,
input [15:0] VAR128,
input [7:0] VAR153,
input [15:0] VAR200,
input [3:0] VAR57,
output VAR172,
output VAR72,
output[15:0] VAR124,
output[7:0] VAR192,
outp... | bsd-3-clause |
q3k/q3kmips | rtl/verilog/qm_alu.v | 2,159 | module MODULE1(
input wire [3:0] VAR1,
input wire [31:0] VAR2,
input wire [31:0] VAR3,
output reg [31:0] VAR4,
always @(VAR1, VAR2, VAR3) begin
case (VAR1)
endcase
end
);
endmodule | bsd-2-clause |
rfotino/consolite-hardware | src/seg_status.v | 1,812 | module MODULE1
(
input VAR10, input VAR14, input VAR16, input VAR4, input VAR19, input VAR15, input VAR18, input [7:0] VAR1, input VAR9, input VAR11, input [7:0] VAR5, input [11:0] VAR17, output reg [11:0] VAR6
);
always @ (*) begin
if (!VAR14) begin
VAR6 = VAR3;
end else if (VAR16) begin
VAR6 = VAR12;
end else if (!VA... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/syn/verilog/convolve_kernel_fcud.v | 2,142 | module MODULE1
VAR3 = 2,
VAR27 = 5,
VAR4 = 32,
VAR2 = 32,
VAR16 = 32
)(
input wire clk,
input wire reset,
input wire VAR22,
input wire [VAR4-1:0] VAR23,
input wire [VAR2-1:0] VAR17,
output wire [VAR16-1:0] dout
);
wire VAR11;
wire VAR5;
wire VAR19;
wire [31:0] VAR28;
wire VAR24;
wire [31:0] VAR13;
wire VAR20;
wire [31:... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_2.behavioral.pp.v | 1,402 | module MODULE1( VAR6, VAR10, VAR2, VAR7, VAR4, VAR5, VAR1 );
input VAR4, VAR7, VAR10, VAR6;
inout VAR5, VAR1;
output VAR2;
VAR9 VAR8(.VAR6(VAR6),.VAR10(VAR10),.VAR2(VAR2),.VAR7(VAR7),.VAR4(VAR4),.VAR5(VAR5),.VAR1(VAR1));
VAR9 VAR3(.VAR6(VAR6),.VAR10(VAR10),.VAR2(VAR2),.VAR7(VAR7),.VAR4(VAR4),.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
ptracton/Picoblaze | PicoBlaze_GPIO_Example/PicoBlaze_GPIO_Example.srcs/sources_1/imports/PicoBlaze_GPIO_Example/cpu.v | 2,782 | module MODULE1 (
VAR11, VAR17, VAR9, VAR4, VAR2,
clk, VAR16, interrupt, VAR3, VAR1
) ;
input clk;
input [7:0] VAR16;
output [7:0] VAR11;
output [7:0] VAR17;
output VAR9;
output VAR4;
input interrupt; output VAR2;
input VAR3;
input VAR1;
wire [11:0] address;
wire [17:0] VAR14;
wire [7:0] VAR17;
wire [7:0] VAR11;
wire VA... | mit |
jmacneal/Design-Project | Display/avconf/avconf.v | 5,376 | module MODULE1 ( VAR6,
reset,
VAR36,
VAR4 );
input VAR6;
input reset;
output VAR36;
inout VAR4;
reg [15:0] VAR24;
reg [23:0] VAR28;
reg VAR31;
reg VAR14;
wire VAR32;
wire VAR2;
wire VAR25 = !reset;
reg [15:0] VAR22;
reg [5:0] VAR1;
reg [3:0] VAR9;
parameter VAR27 = 1'b0;
parameter VAR5 = 9'd24;
parameter VAR21 = 9'd24;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311a/sky130_fd_sc_ms__o311a.behavioral.v | 1,555 | module MODULE1 (
VAR4 ,
VAR5,
VAR13,
VAR2,
VAR3,
VAR9
);
output VAR4 ;
input VAR5;
input VAR13;
input VAR2;
input VAR3;
input VAR9;
supply1 VAR1;
supply0 VAR8;
supply1 VAR12 ;
supply0 VAR7 ;
wire VAR6 ;
wire VAR11;
or VAR15 (VAR6 , VAR13, VAR5, VAR2 );
and VAR10 (VAR11, VAR6, VAR3, VAR9);
buf VAR14 (VAR4 , VAR11 );
end... | apache-2.0 |
Elphel/x393_sata | host/link.v | 61,264 | module MODULE1 #(
parameter VAR175 = 4,
parameter VAR85 = 100 else
parameter VAR85 = 252 VAR229
)
(
input wire rst,
input wire clk,
input wire [VAR175*8 - 1:0] VAR75,
input wire [VAR175/2 - 1:0] VAR62, output wire VAR126, input wire VAR135, input wire VAR54, output wire [VAR175*8 - 1:0] VAR47, output wire [VAR175/2 - 1... | gpl-3.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/amber25/a25_execute.v | 34,097 | module MODULE1 (
input VAR25,
input VAR193, input VAR174, output VAR32,
input [31:0] VAR29, input VAR113, input [10:0] VAR163,
input [31:0] VAR173, input VAR126, input VAR92, input [7:0] VAR185,
output reg [31:0] VAR151 = 'd0,
output reg [31:0] VAR37 = 'd0,
output reg [31:0] VAR143 = 32'hdeaddead,
output [31:0] VAR11, ... | gpl-2.0 |
theapi/de0-nano | pong/score.v | 2,211 | module MODULE1 (
input wire clk,
input wire [10:0] VAR2, VAR10,
input wire [7:0] VAR9, VAR15,
output reg [2:0] VAR19
);
wire [10:0] VAR6;
reg [6:0] VAR13;
reg [3:0] VAR17;
reg [2:0] VAR8;
wire [7:0] VAR11;
wire VAR4;
wire VAR1, VAR3;
VAR5 VAR16
(.clk(clk), .addr(VAR6), .VAR12(VAR11));
reg [10:0] VAR7 = 11'd10;
reg [10:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4bb/sky130_fd_sc_hd__and4bb_1.v | 2,323 | module MODULE2 (
VAR8 ,
VAR7 ,
VAR5 ,
VAR11 ,
VAR9 ,
VAR2,
VAR1,
VAR4 ,
VAR10
);
output VAR8 ;
input VAR7 ;
input VAR5 ;
input VAR11 ;
input VAR9 ;
input VAR2;
input VAR1;
input VAR4 ;
input VAR10 ;
VAR6 VAR3 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31oi/sky130_fd_sc_hdll__a31oi.functional.v | 1,456 | module MODULE1 (
VAR7 ,
VAR2,
VAR1,
VAR6,
VAR9
);
output VAR7 ;
input VAR2;
input VAR1;
input VAR6;
input VAR9;
wire VAR4 ;
wire VAR8;
and VAR3 (VAR4 , VAR6, VAR2, VAR1 );
nor VAR5 (VAR8, VAR9, VAR4 );
buf VAR10 (VAR7 , VAR8 );
endmodule | apache-2.0 |
sabertazimi/hust-lab | digitalLogic/design/washmach_design/src/timer.v | 2,093 | module MODULE1
( input [31:0]VAR9,
input VAR4,
input VAR14,
input [(VAR2-1):0]VAR7,
input VAR13,
output reg VAR8,
output [(VAR2-1):0] VAR10
);
reg VAR6;
wire VAR3;
wire [(VAR2-1):0] VAR12;
reg [(VAR2-1):0] VAR11;
reg [(VAR2-1):0] VAR1;
assign VAR12 = VAR7 * VAR5;
assign VAR10 = VAR11 / VAR5; | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/pow4.v | 8,701 | module MODULE1(VAR1, VAR2);
input wire [232:0] VAR1;
output wire [232:0] VAR2;
assign VAR2[0] = VAR1[0] ^ VAR1[196] ^ VAR1[98];
assign VAR2[1] = VAR1[138] ^ VAR1[175];
assign VAR2[2] = VAR1[117] ^ VAR1[178] ^ VAR1[215];
assign VAR2[3] = VAR1[59] ^ VAR1[218];
assign VAR2[4] = VAR1[1] ^ VAR1[197] ^ VAR1[99];
assign VAR2[... | gpl-3.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_charFromReceiver.v | 1,965 | module MODULE1 (
address,
clk,
VAR4,
VAR3,
VAR1
)
;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input clk;
input [ 7: 0] VAR4;
input VAR3;
wire VAR6;
wire [ 7: 0] VAR2;
wire [ 7: 0] VAR5;
reg [ 31: 0] VAR1;
assign VAR6 = 1;
assign VAR5 = {8 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR3)
begin
if (VAR3... | gpl-3.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/uart/uart_ctrl.v | 4,260 | module MODULE1 (
input wire clk,
input wire reset,
input wire VAR9,
input wire VAR11,
input wire VAR35,
input wire [VAR16] addr,
input wire [VAR21] VAR22,
output reg [VAR21] VAR32,
output reg VAR6,
output reg VAR2,
output reg VAR8,
input wire VAR26,
input wire VAR10,
input wire [VAR24] VAR28,
input wire VAR29,
input wi... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2b/sky130_fd_sc_lp__nand2b.pp.blackbox.v | 1,293 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR1 ,
VAR4,
VAR5,
VAR7 ,
VAR6
);
output VAR2 ;
input VAR3 ;
input VAR1 ;
input VAR4;
input VAR5;
input VAR7 ;
input VAR6 ;
endmodule | apache-2.0 |
dawsonjon/FPGA-TX | synthesis/cmod_a7_15/tx/user_design.v | 2,673 | module MODULE1(clk, rst, VAR14, VAR26, VAR4, VAR15, VAR16, VAR19, VAR12, VAR25, VAR33, VAR34, VAR39, VAR9, VAR36, VAR3, VAR40, VAR28, VAR8, VAR11, VAR35, VAR7, VAR21, VAR30, VAR32, VAR37, VAR2, VAR17, VAR22, VAR27);
input clk;
input rst;
output VAR14;
input [31:0] VAR26;
input VAR16;
output VAR25;
input [31:0] VAR4;
in... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg.pp.symbol.v | 1,577 | module MODULE1 (
input VAR1 ,
output VAR7 ,
input VAR3,
input VAR5 ,
input VAR8 ,
input VAR2 ,
input VAR4 ,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22ai/sky130_fd_sc_hs__o22ai_4.v | 2,225 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR6 ,
VAR7 ,
VAR8 ,
VAR9,
VAR1
);
output VAR5 ;
input VAR2 ;
input VAR6 ;
input VAR7 ;
input VAR8 ;
input VAR9;
input VAR1;
VAR3 VAR4 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR5 ,
VAR2,
VAR6,
VAR7,
VAR8
);... | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_exu_oitf.v | 7,177 | module MODULE1 (
output VAR54,
input VAR31,
input VAR50,
output [VAR49-1:0] VAR66,
output [VAR49-1:0] VAR53,
output [VAR12-1:0] VAR8,
output VAR6,
output VAR48,
output [VAR59-1:0] VAR71,
input VAR62,
input VAR44,
input VAR27,
input VAR64,
input VAR46,
input VAR10,
input VAR5,
input VAR36,
input [VAR12-1:0] VAR14,
input... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311a/sky130_fd_sc_lp__o311a_4.v | 2,422 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR2 ,
VAR11 ,
VAR12 ,
VAR4 ,
VAR10,
VAR7,
VAR5 ,
VAR6
);
output VAR8 ;
input VAR9 ;
input VAR2 ;
input VAR11 ;
input VAR12 ;
input VAR4 ;
input VAR10;
input VAR7;
input VAR5 ;
input VAR6 ;
VAR3 VAR1 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR12(VAR12),
.VAR4(VAR4),
.VAR1... | apache-2.0 |
ineganov/cpu_4 | hw_de0/wiz/vji.v | 7,106 | module MODULE1 (
VAR31,
VAR39,
VAR49,
VAR1,
VAR14,
VAR21,
VAR46,
VAR47,
VAR18,
VAR8,
VAR11,
VAR9,
VAR20);
input [1:0] VAR31;
input VAR39;
output [1:0] VAR49;
output VAR1;
output VAR14;
output VAR21;
output VAR46;
output VAR47;
output VAR18;
output VAR8;
output VAR11;
output VAR9;
output VAR20;
wire VAR34;
wire VAR41;
w... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22o/sky130_fd_sc_hdll__a22o.behavioral.v | 1,615 | module MODULE1 (
VAR14 ,
VAR16,
VAR9,
VAR11,
VAR10
);
output VAR14 ;
input VAR16;
input VAR9;
input VAR11;
input VAR10;
supply1 VAR4;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR12 ;
wire VAR1 ;
wire VAR15 ;
wire VAR5;
and VAR8 (VAR1 , VAR11, VAR10 );
and VAR7 (VAR15 , VAR16, VAR9 );
or VAR13 (VAR5, VAR15, VAR1);
buf VAR6 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21bai/sky130_fd_sc_lp__o21bai_4.v | 2,329 | module MODULE2 (
VAR5 ,
VAR8 ,
VAR4 ,
VAR3,
VAR7,
VAR10,
VAR6 ,
VAR9
);
output VAR5 ;
input VAR8 ;
input VAR4 ;
input VAR3;
input VAR7;
input VAR10;
input VAR6 ;
input VAR9 ;
VAR2 VAR1 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR9(VAR9)
);
endmodule
module MODULE2 ... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtx_x8_125/endpoint_blk_plus_v1_14_bb.v | 10,093 | module MODULE1 (
VAR12,
VAR35,
VAR29,
VAR24,
VAR45,
VAR25,
VAR31,
VAR38,
VAR57,
VAR56,
VAR36,
VAR39,
VAR53,
VAR51,
VAR17,
VAR16,
VAR14,
VAR49,
VAR19,
VAR9,
VAR33,
VAR70,
VAR37,
VAR30,
VAR48,
VAR42,
VAR62,
VAR32,
VAR18,
VAR10,
VAR71,
VAR66,
VAR13,
VAR20,
VAR61,
VAR74,
VAR69,
VAR6,
VAR22,
VAR34,
VAR54,
VAR41,
VAR5,
VAR1,... | lgpl-3.0 |
plindstroem/oh | memory/hdl/fifo_async.v | 3,161 | module MODULE1
(
VAR15, VAR11, dout, VAR6, valid,
VAR9, VAR5, VAR14, VAR8, VAR10, din, VAR16
);
parameter VAR4 = 104; parameter VAR7 = 16;
input VAR9; input VAR5; input VAR14; input VAR8;
input VAR10;
input [VAR4-1:0] din;
output VAR15;
output VAR11;
input VAR16;
output [VAR4-1:0] dout;
output VAR6;
output valid;
VAR13... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_datafmt.v | 3,915 | module MODULE1 (
clk,
valid,
VAR7,
VAR9,
VAR11,
VAR6,
VAR10,
VAR2);
parameter VAR8 = 16;
localparam VAR5 = VAR8 - 1;
input clk;
input valid;
input [VAR5:0] VAR7;
output VAR9;
output [15:0] VAR11;
input VAR6;
input VAR10;
input VAR2;
reg VAR9 = 'd0;
reg [15:0] VAR11 = 'd0;
wire VAR12;
wire VAR3;
wire [VAR5:0] VAR13;
wir... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufbuf/sky130_fd_sc_lp__bufbuf.pp.symbol.v | 1,258 | module MODULE1 (
input VAR5 ,
output VAR2 ,
input VAR6 ,
input VAR1,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or2/gf180mcu_fd_sc_mcu7t5v0__or2_4.behavioral.v | 1,173 | module MODULE1( VAR4, VAR5, VAR6 );
input VAR5, VAR4;
output VAR6;
VAR3 VAR2(.VAR4(VAR4),.VAR5(VAR5),.VAR6(VAR6));
VAR3 VAR1(.VAR4(VAR4),.VAR5(VAR5),.VAR6(VAR6)); | apache-2.0 |
alexforencich/verilog-ethernet | rtl/mii_phy_if.v | 3,760 | module MODULE1 #
(
parameter VAR16 = "VAR34",
parameter VAR36 = "VAR28"
)
(
input wire rst,
output wire VAR17,
output wire VAR35,
output wire [3:0] VAR13,
output wire VAR15,
output wire VAR32,
output wire VAR8,
output wire VAR20,
input wire [3:0] VAR12,
input wire VAR18,
input wire VAR4,
input wire VAR21,
input wire [3... | mit |
aquaxis/FPGAMAG18 | fmrv32im-artya7.nonos/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/5d65/src/fmrv32im_mul.v | 1,510 | module MODULE1
(
input VAR13,
input VAR17,
input VAR2,
input VAR12,
input VAR11,
input VAR19,
input [31:0] VAR4,
input [31:0] VAR16,
output VAR10,
output VAR8,
output [31:0] VAR14
);
wire VAR9, VAR18;
wire VAR20, VAR6;
reg [32:0] VAR5, VAR15;
reg [63:0] VAR3;
reg VAR1, VAR7;
assign VAR9 = VAR2 | VAR12 | VAR11 | VAR19;
... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_250/source/pcie_7x_v1_3_axi_basic_rx.v | 8,469 | module MODULE1 #(
parameter VAR32 = 128, parameter VAR29 = "VAR2", parameter VAR14 = "VAR3", parameter VAR24 = "VAR3", parameter VAR37 = 1,
parameter VAR30 = (VAR32 == 128) ? 2 : 1, parameter VAR7 = VAR32 / 8 ) (
output [VAR32-1:0] VAR36, output VAR23, input VAR20, output [VAR7-1:0] VAR17, output VAR16, output [21:0] V... | lgpl-3.0 |
dvanmali/Superscalar_Pipeline_Processor | aludec.v | 2,364 | module MODULE1(VAR2, VAR5, VAR3, VAR4, VAR6);
input [5:0] VAR2;
input [3:0] VAR5;
output reg [2:0] VAR3;
output reg VAR4, VAR6;
always @(*) begin
case(VAR5)
4'b0000: begin VAR3 <= 3'b010; VAR4 <= 1'b1; VAR6 <= 1'b0; end 4'b0010: begin
case(VAR2) 6'b100000: begin VAR3 <= 3'b010; VAR4 <= 1'b1; VAR6 <= 1'b0; end 6'b100001... | apache-2.0 |
gtaylormb/fpga_nes | hw/src/cpu/apu/apu_div.v | 3,018 | module MODULE1
parameter VAR7 = 16
)
(
input wire VAR4, input wire VAR2, input wire VAR9, input wire VAR5, input wire [VAR7-1:0] VAR3, output wire VAR1 );
reg [VAR7-1:0] VAR8;
wire [VAR7-1:0] VAR6;
always @(posedge VAR4)
begin
if (VAR2)
VAR8 <= 0;
end
else
VAR8 <= VAR6;
end
assign VAR6 = (VAR5 || (VAR9 && (VAR8 == 0)))... | bsd-2-clause |
SWORDfpga/ComputerOrganizationDesign | labs/lab03/lab03/ipcore_dir/ROM_D.v | 3,815 | module MODULE1(
VAR18,
VAR22
);
input [9 : 0] VAR18;
output [31 : 0] VAR22;
VAR10 #(
.VAR31(10),
.VAR43("0"),
.VAR48(1024),
.VAR52("VAR11"),
.VAR55(0),
.VAR38(0),
.VAR7(0),
.VAR45(0),
.VAR16(0),
.VAR49(0),
.VAR54(0),
.VAR1(0),
.VAR32(0),
.VAR3(0),
.VAR26(0),
.VAR9(0),
.VAR53(0),
.VAR28(0),
.VAR33(1),
.VAR19(0),
.VAR36(... | gpl-3.0 |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_processing_system7_1_0/hdl/processing_system7_bfm_v2_0_afi_slave.v | 36,409 | module MODULE1 (
VAR153,
VAR148,
VAR146,
VAR184,
VAR180,
VAR47,
VAR31,
VAR85,
VAR58,
VAR107,
VAR61,
VAR181,
VAR112,
VAR25,
VAR81,
VAR161,
VAR55,
VAR100,
VAR138,
VAR159,
VAR35,
VAR111,
VAR77,
VAR133,
VAR115,
VAR175,
VAR172,
VAR54,
VAR129,
VAR108,
VAR15,
VAR4,
VAR98,
VAR48,
VAR37,
VAR14,
VAR26,
VAR56,
VAR88,
VAR80,
VAR8,... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_1.behavioral.v | 1,098 | module MODULE1( VAR3, VAR1 );
input VAR3;
output VAR1;
VAR5 VAR2(.VAR3(VAR3),.VAR1(VAR1));
VAR5 VAR4(.VAR3(VAR3),.VAR1(VAR1)); | apache-2.0 |
Marcoslz22/Tercer_Proyecto | Control_de_Tiempos.v | 8,492 | module MODULE1(
input VAR4,
input VAR8,
input clk,
input VAR10,
input [3:0] VAR1,
input [2:0] VAR7,
output reg VAR6,
output reg VAR5,
output reg VAR13,
output reg VAR12,
output reg VAR9,
output reg VAR11,
output reg VAR2,
output reg VAR3
);
always @(posedge clk)
begin
if (VAR8 || VAR4 )
begin
case (VAR1)
4'd0: begin
VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211oi/sky130_fd_sc_hs__a211oi.behavioral.pp.v | 1,945 | module MODULE1 (
VAR8,
VAR7,
VAR5 ,
VAR2 ,
VAR10 ,
VAR13 ,
VAR1
);
input VAR8;
input VAR7;
output VAR5 ;
input VAR2 ;
input VAR10 ;
input VAR13 ;
input VAR1 ;
wire VAR1 VAR9 ;
wire VAR11 ;
wire VAR12;
and VAR4 (VAR9 , VAR2, VAR10 );
nor VAR6 (VAR11 , VAR9, VAR13, VAR1 );
VAR14 VAR3 (VAR12, VAR11, VAR8, VAR7);
buf VAR15... | apache-2.0 |
ServerTech/neptune | code/bcd_converter.v | 3,387 | module MODULE1(clk, wr, VAR10, VAR13);
parameter VAR11 = 'd16;
input wire clk , wr ;
input wire [VAR11-1:0] VAR10 ;
output wire [20:0] VAR13 ;
reg VAR4 ;
reg [1:0] VAR5 ;
reg [4:0] VAR6 ;
reg [3:0] VAR7, VAR8, VAR3, VAR12, VAR2; reg [VAR11-1:0] VAR9 ;
reg [20:0] VAR1 ; | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp/sky130_fd_sc_lp__sdfrtp.blackbox.v | 1,444 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR10 ,
VAR4 ,
VAR6 ,
VAR8
);
output VAR7 ;
input VAR1 ;
input VAR10 ;
input VAR4 ;
input VAR6 ;
input VAR8;
supply1 VAR9;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invlp/sky130_fd_sc_lp__invlp_8.v | 2,025 | module MODULE2 (
VAR2 ,
VAR7 ,
VAR8,
VAR6,
VAR5 ,
VAR3
);
output VAR2 ;
input VAR7 ;
input VAR8;
input VAR6;
input VAR5 ;
input VAR3 ;
VAR4 VAR1 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR2,
VAR7
);
output VAR2;
input VAR7;
supply1 VAR8;
supply0 VAR6;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxbp/sky130_fd_sc_hs__sedfxbp.pp.symbol.v | 1,485 | module MODULE1 (
input VAR7 ,
output VAR6 ,
output VAR8 ,
input VAR5 ,
input VAR2 ,
input VAR3 ,
input VAR4 ,
input VAR1,
input VAR9
);
endmodule | apache-2.0 |
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