repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_041.v | 1,572 | module MODULE1 (
VAR12,
VAR14
);
input [31:0] VAR12;
output [31:0]
VAR14;
wire [31:0]
VAR7,
VAR9,
VAR8,
VAR11,
VAR5,
VAR6,
VAR13,
VAR1,
VAR15,
VAR2;
assign VAR7 = VAR12;
assign VAR13 = VAR5 + VAR6;
assign VAR9 = VAR7 << 7;
assign VAR8 = VAR7 + VAR9;
assign VAR2 = VAR15 << 1;
assign VAR5 = VAR11 - VAR7;
assign VAR11 = V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvgnd/sky130_fd_sc_lp__tapvgnd.pp.blackbox.v | 1,256 | module MODULE1 (
VAR3,
VAR2,
VAR4 ,
VAR1
);
input VAR3;
input VAR2;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_dsp/dma.v | 4,882 | module MODULE1(
input VAR1,
input reset,
input enable,
input [3:0] VAR8,
input [7:0] VAR7,
output [7:0] VAR18,
input VAR11,
input VAR6,
output VAR17,
input VAR21,
output VAR20,
output VAR9,
output [23:0] VAR16,
output [15:0] VAR2,
output VAR12,
input [15:0] VAR3
);
parameter VAR10 = 0;
parameter VAR4 = 1;
parameter VAR... | gpl-2.0 |
mbus/mbus | releases/mbus_example-v1.1/verilog/rf.v | 5,071 | module MODULE1
(
VAR14,
VAR9,
VAR15,
VAR5,
VAR13,
VAR2,
VAR17,
VAR4,
VAR12,
VAR10,
VAR1,
VAR6,
VAR11,
VAR18,
VAR16
);
input VAR14;
input VAR9;
input [18:0] VAR15;
input [3:0] VAR5;
output reg [3:0] VAR13;
output reg VAR2;
output reg VAR17;
output reg VAR4;
output reg [7:0] VAR12;
output reg [7:0] VAR10;
output reg VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32o/sky130_fd_sc_ls__a32o.blackbox.v | 1,425 | module MODULE1 (
VAR3 ,
VAR2,
VAR7,
VAR5,
VAR8,
VAR1
);
output VAR3 ;
input VAR2;
input VAR7;
input VAR5;
input VAR8;
input VAR1;
supply1 VAR4;
supply0 VAR6;
supply1 VAR9 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3b/sky130_fd_sc_hs__or3b.functional.pp.v | 1,880 | module MODULE1 (
VAR13,
VAR5,
VAR4 ,
VAR3 ,
VAR7 ,
VAR14
);
input VAR13;
input VAR5;
output VAR4 ;
input VAR3 ;
input VAR7 ;
input VAR14 ;
wire VAR9 ;
wire VAR6 ;
wire VAR12;
not VAR1 (VAR9 , VAR14 );
or VAR8 (VAR6 , VAR7, VAR3, VAR9 );
VAR11 VAR10 (VAR12, VAR6, VAR13, VAR5);
buf VAR2 (VAR4 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_nr_pp_pkg_sn/sky130_fd_sc_hs__udp_dff_nr_pp_pkg_sn.symbol.v | 1,532 | module MODULE1 (
input VAR3 ,
output VAR5 ,
input VAR7 ,
input VAR1 ,
input VAR8 ,
input VAR4 ,
input VAR9,
input VAR2 ,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32a/sky130_fd_sc_lp__o32a.behavioral.pp.v | 2,188 | module MODULE1 (
VAR1 ,
VAR20 ,
VAR5 ,
VAR11 ,
VAR15 ,
VAR8 ,
VAR16,
VAR13,
VAR9 ,
VAR10
);
output VAR1 ;
input VAR20 ;
input VAR5 ;
input VAR11 ;
input VAR15 ;
input VAR8 ;
input VAR16;
input VAR13;
input VAR9 ;
input VAR10 ;
wire VAR7 ;
wire VAR14 ;
wire VAR6 ;
wire VAR17;
or VAR19 (VAR7 , VAR5, VAR20, VAR11 );
or VA... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/sram_ctl.v | 6,066 | module MODULE1 (
input wire VAR30,
input wire VAR39,
input wire [3:0] VAR38,
input wire [7:0] VAR37,
output wire [7:0] VAR8,
input wire VAR19,
input wire VAR4,
output reg VAR36,
output reg VAR13,
input VAR26,
input wire [23:0] VAR20,
input wire [7:0] VAR25,
output wire [7:0] VAR12,
input wire VAR11,
input wire VAR15,
i... | gpl-3.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_prime_fifo_plain.v | 13,772 | module MODULE1(
rst,
VAR386,
VAR89,
din,
VAR218,
VAR11,
dout,
VAR55,
VAR101,
VAR210
);
input rst;
input VAR386;
input VAR89;
input [71 : 0] din;
input VAR218;
input VAR11;
output [71 : 0] dout;
output VAR55;
output VAR101;
output VAR210;
VAR388 #(
.VAR23(0),
.VAR206(0),
.VAR268(0),
.VAR197(0),
.VAR357(0),
.VAR195(0),
.... | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/DOUBLE/Barrel_Shifter_syn.v | 34,958 | module MODULE3 ( VAR24, VAR151, VAR80, VAR2 );
input [25:0] VAR24;
output [25:0] VAR2;
input VAR151, VAR80;
wire VAR11, VAR77, VAR121, VAR81, VAR6, VAR74;
VAR61 VAR63 ( .VAR145(VAR11), .VAR7(VAR6) );
VAR120 VAR57 ( .VAR145(VAR6), .VAR7(VAR77) );
VAR120 VAR89 ( .VAR145(VAR6), .VAR7(VAR121) );
VAR120 VAR23 ( .VAR145(VAR6... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlxtn/sky130_fd_sc_hdll__dlxtn.pp.symbol.v | 1,349 | module MODULE1 (
input VAR4 ,
output VAR7 ,
input VAR1,
input VAR3 ,
input VAR2 ,
input VAR5 ,
input VAR6
);
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_tt.v | 7,448 | module MODULE1(
clk, rst, VAR2,
VAR4, VAR1, VAR20, VAR7, VAR13,
VAR17
);
input clk; input rst; input VAR2; input VAR4; input VAR1; input [31:0] VAR20; input [31:0] VAR7; output [31:0] VAR13; output VAR17;
reg [31:0] VAR22; else
wire [31:0] VAR22; VAR24
reg [31:0] VAR5; else
wire [31:0] VAR5; VAR24
wire VAR9; wire VAR16... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/decap/sky130_fd_sc_hvl__decap.pp.symbol.v | 1,204 | module MODULE1 (
input VAR3 ,
input VAR2,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/image_filter_Dilate_0_0_1080_1920_s.v | 73,198 | module MODULE1 (
VAR115,
VAR306,
VAR130,
VAR123,
VAR40,
VAR248,
VAR199,
VAR47,
VAR160,
VAR219,
VAR144,
VAR1,
VAR4,
VAR54,
VAR245
);
parameter VAR233 = 1'b1;
parameter VAR74 = 1'b0;
parameter VAR289 = 5'b1;
parameter VAR167 = 5'b10;
parameter VAR316 = 5'b100;
parameter VAR129 = 5'b1000;
parameter VAR16 = 5'b10000;
param... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_isowell/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4.v | 2,484 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR4,
VAR9 ,
VAR5 ,
VAR2 ,
VAR7
);
output VAR6 ;
input VAR8 ;
input VAR4;
input VAR9 ;
input VAR5 ;
input VAR2 ;
input VAR7 ;
VAR1 VAR3 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR6,
VAR8
);
output VAR6;
inpu... | apache-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_fp_fptosi_double.v | 36,189 | module MODULE1
(
VAR4,
VAR1,
VAR15,
VAR14,
VAR18,
VAR13) ;
input VAR4;
input VAR1;
input VAR15;
input [83:0] VAR14;
input [6:0] VAR18;
output [83:0] VAR13;
tri0 VAR4;
tri1 VAR1;
tri0 VAR15;
reg [1:0] VAR11;
reg [83:0] VAR3;
reg [83:0] VAR8;
reg VAR7;
reg VAR2;
reg VAR5;
wire [7:0] VAR6;
wire VAR16;
wire [63:0] VAR9;
wi... | mit |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/b2b/src/aur1_tx_stream.v | 7,196 | module MODULE1
(
VAR16,
VAR19,
VAR7,
VAR5,
VAR4,
VAR13,
VAR14,
VAR9,
VAR20,
VAR18,
VAR11,
VAR6,
VAR2
);
input [0:63] VAR16;
input VAR19;
output VAR7;
input VAR5;
input VAR4;
input VAR13;
output VAR14;
output VAR9;
output [0:3] VAR20;
output [0:3] VAR18;
output [0:63] VAR11;
output VAR6;
input VAR2;
reg VAR6;
reg VAR3;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfstp/sky130_fd_sc_lp__dfstp.symbol.v | 1,387 | module MODULE1 (
input VAR7 ,
output VAR4 ,
input VAR6,
input VAR5
);
supply1 VAR2;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
rkrajnc/minimig-de1 | rtl/or1200/or1200_spram_256x21.v | 8,650 | module MODULE1(
VAR43, VAR11, VAR22,
clk, rst, VAR29, VAR4, VAR15, addr, VAR21, VAR30
);
parameter VAR1 = 8;
parameter VAR12 = 21;
input VAR43;
input [VAR13 - 1:0] VAR22;
output VAR11;
input clk; input rst; input VAR29; input VAR4; input VAR15; input [VAR1-1:0] addr; input [VAR12-1:0] VAR21; output [VAR12-1:0] VAR30;
w... | gpl-3.0 |
ServerTech/neptune | code/alu_core.v | 4,991 | module MODULE1(clk, rst, en, VAR7, VAR2, VAR1, VAR8, VAR5, VAR6, VAR10, dout);
parameter VAR9 = 'd16;
input wire clk , rst , en ; input wire [4:0] VAR7 ;
input wire signed [VAR9-1:0] VAR2 , VAR1 ;
output reg VAR8 ;
output wire VAR5 , VAR6 ;
output reg VAR10 ;
output wire [VAR9-1:0] dout ;
reg [1:0] VAR4 ;
reg signed [V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2o/sky130_fd_sc_lp__a2bb2o.blackbox.v | 1,454 | module MODULE1 (
VAR9 ,
VAR5,
VAR8,
VAR2 ,
VAR7
);
output VAR9 ;
input VAR5;
input VAR8;
input VAR2 ;
input VAR7 ;
supply1 VAR6;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_4.functional.v | 1,218 | module MODULE1( VAR4, VAR6, VAR1, VAR3 );
input VAR3, VAR4, VAR1;
output VAR6;
wire VAR5;
not VAR2( VAR5, VAR3 );
wire VAR9;
not VAR8( VAR9, VAR4 );
wire VAR11;
not VAR7( VAR11, VAR1 );
or VAR10( VAR6, VAR5, VAR9, VAR11 );
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/pcie_7x_v1_8_gtp_pipe_reset.v | 14,950 | module MODULE1 #
(
parameter VAR26 = "VAR44", parameter VAR23 = 1, parameter VAR37 = 6'd63, parameter VAR42 = 1
)
(
input VAR21,
input VAR1,
input VAR49,
input VAR5,
input VAR17,
input [VAR23-1:0] VAR54,
input [VAR23-1:0] VAR27,
input VAR32,
input [VAR23-1:0] VAR46,
input [VAR23-1:0] VAR15,
input [VAR23-1:0] VAR31,
out... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_1.behavioral.v | 1,336 | module MODULE1( VAR4, VAR1, VAR7, VAR5, VAR8 );
input VAR8, VAR5, VAR7, VAR4;
output VAR1;
VAR3 VAR6(.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR5(VAR5),.VAR8(VAR8));
VAR3 VAR2(.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR5(VAR5),.VAR8(VAR8)); | apache-2.0 |
drichmond/riffa | fpga/riffa_hdl/counter.v | 3,284 | module MODULE1
parameter VAR7 = 10,
parameter VAR8 = 0)
(
input VAR10,
input VAR2,
input VAR5,
output [VAR6(VAR11+1)-1:0] VAR9
);
wire VAR1;
reg [VAR6(VAR11+1)-1:0] VAR3;
reg [VAR6(VAR11+1)-1:0] VAR4;
assign VAR1 = VAR5 & (VAR7 > VAR4);
assign VAR9 = VAR4;
always @(posedge VAR10) begin
if(VAR2) begin
VAR4 <= VAR8[VAR6(... | bsd-3-clause |
jaechoon2/FPGA-Imaging-Library | Connector/Mux8/srcs/Mux8.v | 1,173 | module MODULE1(sel, VAR3, VAR4, VAR7, VAR6, VAR5, VAR2, VAR10, VAR8, VAR1);
parameter VAR11 = 8;
input[2 : 0] sel;
input[VAR11 - 1 : 0] VAR3;
input[VAR11 - 1 : 0] VAR4;
input[VAR11 - 1 : 0] VAR7;
input[VAR11 - 1 : 0] VAR6;
input[VAR11 - 1 : 0] VAR5;
input[VAR11 - 1 : 0] VAR2;
input[VAR11 - 1 : 0] VAR10;
input[VAR11 - 1... | lgpl-2.1 |
kernelpanics/Grad | CORDIC-Natural-Logarithm/Verilog/Natural-Logarithm/Mux_Array.v | 1,790 | module MODULE1#(parameter VAR13=26, parameter VAR4=5)(
input wire clk,
input wire rst,
input wire VAR14,
input wire [VAR13-1:0] VAR11,
input wire VAR16,
input wire [VAR4-1:0] VAR21,
input wire VAR22,
output wire [VAR13-1:0] VAR20
);
wire [VAR13-1:0] VAR1[VAR4+1:0];
genvar VAR18; VAR10 #(.VAR13(VAR13)) VAR7(
.VAR11(VAR1... | gpl-3.0 |
Triple-Z/COExperiment_Repo | Project_Assignment_OnBoard/CoProcessor0RF.v | 1,414 | module MODULE1(clk, din, VAR16, VAR2, sel, dout, VAR4, VAR1, VAR9, VAR14, VAR17);
input clk;
input [1:0] VAR16;
input [4:0] VAR2;
input [2:0] sel;
input [31:0] din;
input [31:0] VAR9;
input [31:0] VAR4;
output [31:0] dout;
output reg [31:0] VAR1;
input [4:0] VAR14;
output [31:0] VAR17;
reg [31:0] VAR10 [0:31];
wire [5:... | mit |
orbancedric/DeepGate | src/interface/mojo/deepgate_top.v | 4,930 | module MODULE1(
input VAR51,
input VAR37,
input VAR60,
output wire [7:0] VAR71,
output VAR9,
input VAR67,
input VAR59,
input VAR38,
output [3:0] VAR74,
input VAR77, output VAR32, input VAR12,
output VAR81,
output VAR22,
output VAR44,
output VAR66,
output VAR64,
output VAR82,
output VAR40,
output [1:0] VAR80,
output [12... | gpl-3.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/example_design/PIO_EP.v | 8,391 | module MODULE1 #(
parameter VAR43 = 64,
parameter VAR26 = VAR43 / 8, parameter VAR8 = 1
) (
input clk,
input VAR29,
input VAR3,
output [VAR43-1:0] VAR19,
output [VAR26-1:0] VAR12,
output VAR36,
output VAR23,
output VAR46,
input [VAR43-1:0] VAR20,
input [VAR26-1:0] VAR37,
input VAR11,
input VAR1,
output VAR33,
input [21... | gpl-2.0 |
manili/Pipelined_6502 | ALU.v | 3,921 | module MODULE1(
VAR7,
VAR23,
VAR17,
VAR6,
VAR25,
VAR1
);
input wire [4:0] VAR7;
input wire [7:0] VAR23;
input wire [15:0] VAR17;
input wire [15:0] VAR6;
output wire [7:0] VAR25;
output wire [15:0] VAR1;
reg [15:0] VAR20;
reg VAR16;
reg VAR12;
assign VAR1 = VAR20;
assign VAR25[VAR14] = (VAR7 == VAR18) ? VAR17[VAR14] :
(... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4b/sky130_fd_sc_hs__or4b.symbol.v | 1,281 | module MODULE1 (
input VAR1 ,
input VAR5 ,
input VAR2 ,
input VAR4,
output VAR3
);
supply1 VAR7;
supply0 VAR6;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4bb/sky130_fd_sc_hdll__or4bb_1.v | 2,330 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR2 ,
VAR9 ,
VAR11 ,
VAR7,
VAR10,
VAR1 ,
VAR8
);
output VAR4 ;
input VAR6 ;
input VAR2 ;
input VAR9 ;
input VAR11 ;
input VAR7;
input VAR10;
input VAR1 ;
input VAR8 ;
VAR5 VAR3 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR1(VAR1),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21oi/sky130_fd_sc_hdll__a21oi.symbol.v | 1,357 | module MODULE1 (
input VAR5,
input VAR1,
input VAR6,
output VAR7
);
supply1 VAR2;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_exu_branchslv.v | 6,096 | module MODULE1(
input VAR23,
output VAR11,
input VAR6,
input VAR25, input VAR17, input VAR19, input VAR18,
input VAR20, input VAR13, input [VAR27-1:0] VAR7,
input [VAR2-1:0] VAR15,
input [VAR27-1:0] VAR21,
input [VAR27-1:0] VAR5,
input VAR10,
input VAR22,
output VAR16,
output [VAR27-1:0] VAR26,
output [VAR27-1:0] VAR14... | apache-2.0 |
cr88192/bgbtech_bjx1core | bjx1core32/FpuFp64_Mul.v | 1,399 | module MODULE1(
clk,
enable,
VAR7,
VAR4,
VAR14
);
input clk;
input enable;
input[63:0] VAR7;
input[63:0] VAR4;
output[63:0] VAR14;
reg VAR11;
reg VAR9;
reg VAR1;
reg[12:0] VAR2;
reg[12:0] VAR13;
reg[12:0] VAR3;
reg[105:0] VAR5;
reg[105:0] VAR6;
reg[105:0] VAR15;
reg[63:0] VAR8;
reg[63:0] VAR5;
reg[63:0] VAR6;
reg[63:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkbuf/sky130_fd_sc_hdll__clkbuf_4.v | 2,050 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR6,
VAR4,
VAR8 ,
VAR3
);
output VAR1 ;
input VAR2 ;
input VAR6;
input VAR4;
input VAR8 ;
input VAR3 ;
VAR7 VAR5 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
supply1 VAR6;
supply0 VAR4;... | apache-2.0 |
zYeoman/32BIT-MIPS-CPU | pipeline/MEM2WB.v | 1,228 | module MODULE1(
input clk, rst,
input VAR6,
input [31:0] VAR2, VAR1, VAR10,
input [4:0] VAR7,
input [1:0] VAR11,
output reg VAR12,
output reg [31:0] VAR9, VAR4, VAR5,
output reg [4:0] VAR8,
output reg [1:0] VAR3
);
always @(posedge clk or posedge rst) begin
if (rst) begin
VAR12 <= 0;
VAR9 <= 0;
VAR4 <= 0;
VAR8 <= 0;
VA... | gpl-2.0 |
rkrajnc/minimig-mist | rtl/or1200/or1200_immu_tlb.v | 7,202 | module MODULE1(
clk, rst,
VAR44, VAR32, VAR3, VAR45, VAR24, VAR23, VAR19,
VAR28, VAR39, VAR27,
VAR47, VAR49, VAR17, VAR43, VAR33
);
parameter VAR37 = VAR5;
parameter VAR13 = VAR5;
input clk;
input rst;
input VAR44;
input [VAR13-1:0] VAR32;
output VAR3;
output [31:VAR54] VAR45;
output VAR24;
output VAR23;
output VAR19;
... | gpl-3.0 |
karshan/fpga-rgbmatrix | src/message_printer.v | 1,210 | module MODULE1 (
input clk,
input rst,
output [7:0] VAR4,
output reg VAR11,
input VAR16,
input [7:0] VAR2,
input VAR5
);
localparam VAR3 = 1;
localparam VAR7 = 0,
VAR15 = 1;
localparam VAR8 = 14;
reg [VAR3-1:0] VAR10, VAR14;
reg [3:0] VAR12, VAR1;
VAR13 VAR13 (
.clk(clk),
.addr(VAR1),
.VAR9(VAR4)
);
always @(*) begin
V... | gpl-3.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_sb_fifo.v | 5,310 | module MODULE1(
VAR6, VAR4, VAR10, VAR12, VAR9, VAR1, VAR17, VAR8
);
parameter VAR3 = 68;
parameter VAR16 = VAR2;
parameter VAR15 = VAR14;
input VAR6; input VAR4; input [VAR3-1:0] VAR10; input VAR12; input VAR9; output [VAR3-1:0] VAR1; output VAR17; output VAR8;
reg [VAR3-1:0] VAR18 [VAR15-1:0];
reg [VAR3-1:0] VAR1;
re... | mit |
aj-michael/Digital-Systems | Lab6-Part2/ControllerReadTempI2C.v | 1,891 | module MODULE1(VAR7,VAR25,VAR5,VAR26,VAR27,VAR22,VAR24,VAR14,VAR3,VAR4,VAR23,VAR15);
input VAR7;
input VAR25;
input VAR5;
input VAR26;
input VAR27;
output VAR22;
output VAR24;
output VAR14;
output VAR3;
output VAR4;
output VAR23;
output VAR15;
reg [3:0] VAR19;
reg [2:0] VAR12;
reg [2:0] VAR1;
parameter VAR9 = 3'd0;
par... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_20.behavioral.pp.v | 1,172 | module MODULE1( VAR4, VAR5, VAR7, VAR6 );
input VAR4;
inout VAR7, VAR6;
output VAR5;
VAR1 VAR2(.VAR4(VAR4),.VAR5(VAR5),.VAR7(VAR7),.VAR6(VAR6));
VAR1 VAR3(.VAR4(VAR4),.VAR5(VAR5),.VAR7(VAR7),.VAR6(VAR6)); | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/ddr3_s4_amphy_example_driver.v | 30,890 | module MODULE1 (
clk,
VAR36,
VAR52,
VAR47,
VAR6,
VAR85,
VAR23,
VAR41,
VAR44,
VAR12,
VAR64,
VAR42,
VAR54,
VAR56,
VAR1,
VAR15,
VAR45,
VAR91,
VAR81
)
;
output [ 2: 0] VAR85;
output [ 3: 0] VAR23;
output VAR41;
output [ 9: 0] VAR44;
output VAR12;
output VAR64;
output [ 12: 0] VAR42;
output [ 2: 0] VAR54;
output [ 31: 0] VA... | lgpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/daq2/common/daq2_spi.v | 3,816 | module MODULE1 (
VAR5,
VAR8,
VAR7,
VAR11,
VAR2,
VAR1);
input [ 2:0] VAR5;
input VAR8;
input VAR7;
output VAR11;
inout VAR2;
output VAR1;
reg [ 5:0] VAR4 = 'd0;
reg VAR9 = 'd0;
reg VAR10 = 'd0;
wire VAR3;
wire VAR6;
assign VAR3 = & VAR5;
assign VAR1 = ~VAR6;
assign VAR6 = VAR10 & ~VAR3;
always @(posedge VAR8 or posedge ... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/V2NFC100DDR_v1_0_0/81152d2e/src/NPM_Toggle_PHY_B_Reset.v | 7,493 | module MODULE1
(
VAR7 ,
VAR22 ,
VAR20 ,
VAR2 ,
VAR21 ,
VAR19 ,
VAR6 ,
VAR4 ,
VAR9 ,
VAR8
);
input VAR7 ;
input VAR22 ;
output VAR20 ;
output VAR2 ;
input VAR21 ;
output VAR19 ;
output VAR6 ;
output VAR4 ;
output [7:0] VAR9 ;
output VAR8 ;
parameter VAR16 = 4;
parameter VAR17 = 4'b0001;
parameter VAR13 = 4'b0010;
parame... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41ai/sky130_fd_sc_hd__o41ai.pp.blackbox.v | 1,408 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR2 ,
VAR10 ,
VAR5 ,
VAR6 ,
VAR3,
VAR1,
VAR4 ,
VAR8
);
output VAR9 ;
input VAR7 ;
input VAR2 ;
input VAR10 ;
input VAR5 ;
input VAR6 ;
input VAR3;
input VAR1;
input VAR4 ;
input VAR8 ;
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/correlator/correlate_cos_sin_DSP.v | 3,732 | module MODULE1
parameter VAR19 = VAR8+VAR45,
parameter VAR60 = 0, parameter VAR38 = 3)
(
input clk,
input VAR24,
input en,
input VAR25,
input VAR3,
input VAR53,
input VAR23,
input VAR37,
input [VAR45:0] VAR27,
input [VAR45:0] VAR52,
output [VAR45:0] VAR32,
output [VAR45:0] VAR21
);
wire [7:0] VAR28 = 8'b00001111;
wire ... | lgpl-3.0 |
nyaxt/dmix | ise/tepla/ipcore_dir/nkmd_ddr3/example_design/par/ipcore_dir/dcm.v | 5,632 | module MODULE1
( input VAR19,
output VAR41,
input VAR33,
output VAR37
);
VAR25 VAR2
(.VAR40 (VAR47),
.VAR13 (VAR19));
wire VAR18;
wire VAR31;
wire [7:0] VAR48;
wire VAR14;
wire VAR26;
wire VAR35;
VAR17
.VAR45 (3),
.VAR29 (10),
.VAR36 ("VAR15"),
.VAR43 (10.0),
.VAR44 ("VAR34"),
.VAR10 ("VAR34"),
.VAR38 ("VAR20"),
.VAR8 ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_4.functional.pp.v | 1,235 | module MODULE1( VAR1, VAR5, VAR7, VAR2, VAR3, VAR13 );
input VAR2, VAR1, VAR7;
inout VAR3, VAR13;
output VAR5;
wire VAR4;
not VAR10( VAR4, VAR2 );
wire VAR11;
not VAR9( VAR11, VAR1 );
wire VAR8;
not VAR12( VAR8, VAR7 );
and VAR6( VAR5, VAR4, VAR11, VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxtp/sky130_fd_sc_ls__sdfxtp.functional.v | 1,752 | module MODULE1 (
VAR2 ,
VAR1,
VAR11 ,
VAR7,
VAR9
);
output VAR2 ;
input VAR1;
input VAR11 ;
input VAR7;
input VAR9;
wire VAR4 ;
wire VAR8;
VAR6 VAR13 (VAR8, VAR11, VAR7, VAR9 );
VAR5 VAR3 VAR12 (VAR4 , VAR8, VAR1 );
buf VAR10 (VAR2 , VAR4 );
endmodule | apache-2.0 |
Dennis-Chhun/Pong-Game | src/ScoreDecoder.v | 1,459 | module MODULE1(in, VAR10, VAR2);
input [4:0]in;
output reg [6:0] VAR10,VAR2;
parameter VAR8 = 7'b1000000;
parameter VAR6 = 7'b1111001;
parameter VAR1 = 7'b0100100;
parameter VAR4 = 7'b0110000;
parameter VAR9 = 7'b0011001;
parameter VAR13 = 7'b0010010;
parameter VAR11 = 7'b0000010;
parameter VAR12 = 7'b1111000;
paramete... | mit |
Marcoslz22/Tercer_Proyecto | Decodificador.v | 3,356 | module MODULE1(
input [6:0] VAR3,
output reg [7:0] VAR5,VAR1,VAR4,VAR2
);
always @(*)
begin
case (VAR3)
6'd0: begin
VAR5 <= 8'b00000011;
VAR1 <= 8'b00000011;
VAR4 <= 8'b00000011;
VAR2 <= 8'b00000011;
end
6'd1: begin
VAR5 <= 8'b10011111;
VAR1 <= 8'b00000011;
VAR4 <= 8'b00000011;
VAR2 <= 8'b00000011;
end
6'd2: begin
VAR5... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd1/sky130_fd_sc_ms__dlygate4sd1.functional.pp.v | 1,832 | module MODULE1 (
VAR1 ,
VAR12 ,
VAR4,
VAR2,
VAR10 ,
VAR6
);
output VAR1 ;
input VAR12 ;
input VAR4;
input VAR2;
input VAR10 ;
input VAR6 ;
wire VAR9 ;
wire VAR8;
buf VAR3 (VAR9 , VAR12 );
VAR5 VAR7 (VAR8, VAR9, VAR4, VAR2);
buf VAR11 (VAR1 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor2/sky130_fd_sc_hdll__xnor2_1.v | 2,148 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR5 ,
VAR3,
VAR9,
VAR2 ,
VAR7
);
output VAR6 ;
input VAR1 ;
input VAR5 ;
input VAR3;
input VAR9;
input VAR2 ;
input VAR7 ;
VAR4 VAR8 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR6,
VAR1,
VAR5
);
output VAR6;
... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/slaveController/endpMux.v | 8,001 | module MODULE1 (
clk,
rst,
VAR21,
VAR36,
VAR23,
VAR25,
VAR35,
VAR17,
VAR9,
VAR12,
VAR26,
VAR1,
VAR33,
VAR22,
VAR7,
VAR2,
VAR34,
VAR20,
VAR8,
VAR32,
VAR4,
VAR11,
VAR29,
VAR28,
VAR27,
VAR15,
VAR3,
VAR16,
VAR13,
VAR14,
VAR19,
VAR31,
VAR30,
VAR24,
VAR18,
VAR5);
input clk;
input rst;
input [3:0] VAR21;
input VAR36;
input VA... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_2.functional.v | 3,002 | module MODULE1( VAR17, VAR6, VAR5, VAR4, VAR28, VAR31, VAR10 );
input VAR31, VAR10, VAR28, VAR4, VAR5, VAR6;
output VAR17;
wire VAR21;
not VAR8( VAR21, VAR31 );
wire VAR18;
not VAR23( VAR18, VAR28 );
wire VAR26;
not VAR33( VAR26, VAR5 );
wire VAR32;
and VAR1( VAR32, VAR21, VAR18, VAR26 );
wire VAR35;
not VAR34( VAR35, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4b/sky130_fd_sc_lp__and4b.pp.blackbox.v | 1,341 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR9 ,
VAR6 ,
VAR5 ,
VAR1,
VAR3,
VAR8 ,
VAR4
);
output VAR2 ;
input VAR7 ;
input VAR9 ;
input VAR6 ;
input VAR5 ;
input VAR1;
input VAR3;
input VAR8 ;
input VAR4 ;
endmodule | apache-2.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/rtr_flags_mux.v | 4,127 | module MODULE1
(VAR14, VAR7, VAR17, VAR13, VAR1);
parameter VAR5 = 2;
parameter VAR18 = 2;
parameter VAR2 = 5;
parameter VAR15 = 1;
localparam VAR9 = VAR5 * VAR18;
input [0:VAR5-1] VAR14;
input [0:VAR2-1] VAR7;
input [0:VAR18-1] VAR17;
input [0:VAR2*VAR9*VAR15-1] VAR13;
output [0:VAR15-1] VAR1;
wire [0:VAR15-1] VAR1;
w... | gpl-2.0 |
alexforencich/verilog-ethernet | example/fb2CG/fpga_10g/rtl/led_sreg_driver.v | 3,700 | module MODULE1 #(
parameter VAR15 = 8,
parameter VAR12 = 0,
parameter VAR4 = 31
)
(
input wire clk,
input wire rst,
input wire [VAR15-1:0] VAR8,
output wire VAR20,
output wire VAR13,
output wire VAR16
);
localparam VAR11 = VAR9(VAR15+1);
localparam VAR14 = VAR9(VAR4+1);
reg [VAR11-1:0] VAR7 = 0;
reg [VAR14-1:0] VAR17 =... | mit |
kevintownsend/multi-pump_memory | multipumped_memory.v | 1,279 | module MODULE1(clk, wr, addr, VAR6, VAR12);
parameter VAR1 = 8;
parameter VAR3 = 64;
parameter VAR11 = 512;
parameter VAR8 = VAR15(VAR11 - 1);
parameter VAR19 = VAR15(VAR1 - 1);
input clk;
input [0:VAR1 - 1] wr;
input [VAR1 * VAR8 - 1:0] addr;
input [VAR1 * VAR3 - 1:0] VAR6;
output reg [VAR1 * VAR3 - 1:0] VAR12;
reg [V... | apache-2.0 |
tugrulyatagan/RISC-processor | xilinx_processor/uart_rx.v | 4,077 | module MODULE1 #
(
parameter VAR16 = 8
)
(
input wire clk,
input wire rst,
output wire [VAR16-1:0] VAR5,
output wire VAR4,
input wire VAR11,
input wire VAR1,
output wire VAR9,
output wire VAR15,
output wire VAR10,
input wire [15:0] VAR8
);
reg [VAR16-1:0] VAR2 = 0;
reg VAR7 = 0;
reg VAR3 = 1;
reg VAR14 = 0;
reg VAR13 =... | gpl-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_mm_interconnect_0_avalon_st_adapter_008.v | 6,185 | module MODULE1 #(
parameter VAR3 = 130,
parameter VAR23 = 0,
parameter VAR5 = 130,
parameter VAR9 = 0,
parameter VAR4 = 0,
parameter VAR2 = 0,
parameter VAR24 = 1,
parameter VAR19 = 1,
parameter VAR10 = 0,
parameter VAR1 = 130,
parameter VAR6 = 0,
parameter VAR25 = 1,
parameter VAR11 = 0,
parameter VAR16 = 1,
parameter... | gpl-3.0 |
toyoshim/mc6502 | rtl/MC6502RegisterFile.v | 6,414 | module MODULE1(
clk,
VAR90,
VAR31,
VAR9,
VAR25,
VAR61,
VAR81,
VAR41,
VAR28,
VAR10,
VAR33,
VAR63,
VAR20,
VAR60,
VAR50,
VAR73,
VAR37,
VAR77,
VAR42,
VAR57,
VAR27,
VAR38,
VAR68,
VAR52,
VAR84,
VAR2,
VAR24,
VAR7,
VAR11,
VAR85,
VAR87,
VAR74,
VAR86,
VAR19,
VAR4,
VAR15,
VAR18,
VAR32,
VAR66,
VAR89,
VAR71,
VAR29,
VAR35,
VAR22,
VA... | bsd-3-clause |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/redundant/ovl_no_underflow.v | 1,514 | module MODULE1 (VAR12, reset, enable, VAR10, VAR7);
parameter VAR8 = VAR16;
parameter VAR21 = 1;
parameter VAR4 = 0;
parameter VAR9 = ((1<<VAR21)-1);
parameter VAR11 = VAR23;
parameter VAR17 = VAR18;
parameter VAR19 = VAR14;
parameter VAR5 = VAR13;
parameter VAR3 = VAR2;
parameter VAR24 = VAR15;
input VAR12, reset, ena... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221ai/sky130_fd_sc_hs__o221ai.functional.pp.v | 2,113 | module MODULE1 (
VAR15,
VAR13,
VAR1 ,
VAR18 ,
VAR7 ,
VAR11 ,
VAR16 ,
VAR14
);
input VAR15;
input VAR13;
output VAR1 ;
input VAR18 ;
input VAR7 ;
input VAR11 ;
input VAR16 ;
input VAR14 ;
wire VAR16 VAR10 ;
wire VAR16 VAR5 ;
wire VAR9 ;
wire VAR4;
or VAR6 (VAR10 , VAR16, VAR11 );
or VAR3 (VAR5 , VAR7, VAR18 );
nand VAR8... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2/sky130_fd_sc_ls__mux2.behavioral.pp.v | 1,902 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR8 ,
VAR11 ,
VAR7,
VAR5,
VAR2 ,
VAR15
);
output VAR1 ;
input VAR3 ;
input VAR8 ;
input VAR11 ;
input VAR7;
input VAR5;
input VAR2 ;
input VAR15 ;
wire VAR10 ;
wire VAR14;
VAR12 VAR9 (VAR10 , VAR3, VAR8, VAR11 );
VAR6 VAR13 (VAR14, VAR10, VAR7, VAR5);
buf VAR4 (VAR1 , VAR14 );
endmodule | apache-2.0 |
cr88192/bgbtech_bjx1core | bjx1core32/DecOp.v | 11,886 | module MODULE1(
clk,
VAR13,
VAR3,
VAR6,
VAR2,
VAR9,
VAR11,
VAR8,
VAR4,
VAR10
);
input clk; input[31:0] VAR13; input[31:0] VAR3;
output[6:0] VAR6;
output[6:0] VAR2;
output[6:0] VAR9;
output[31:0] VAR11;
output[3:0] VAR8;
output[11:0] VAR4;
output[31:0] VAR10;
reg[11:0] VAR7[256];
reg[31:0] VAR1[4096];
reg[7:0] VAR5;
reg... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_io | cells/bi_24t/gf180mcu_fd_io__bi_24t.v | 1,949 | module MODULE1 (VAR2, VAR7, VAR9, VAR3, VAR10, VAR5, VAR4, VAR15, VAR13, VAR8, VAR12, VAR6, VAR11);
input VAR2;
input VAR7;
input VAR9;
input VAR3;
input VAR10;
input VAR5;
input VAR4;
inout VAR15;
output VAR13;
inout VAR8;
inout VAR12;
inout VAR6;
inout VAR11;
supply0 VAR14;
supply1 VAR1;
and (VAR13, VAR15, VAR9);
buf... | apache-2.0 |
kyzhai/NUNY | src/hardware/phd_new.v | 6,389 | module MODULE1 (
address,
VAR35,
VAR9);
input [11:0] address;
input VAR35;
output [11:0] VAR9;
tri1 VAR35;
wire [11:0] VAR6;
wire [11:0] VAR9 = VAR6[11:0];
VAR21 VAR20 (
.VAR27 (address),
.VAR23 (VAR35),
.VAR19 (VAR6),
.VAR10 (1'b0),
.VAR39 (1'b0),
.VAR3 (1'b1),
.VAR8 (1'b0),
.VAR4 (1'b0),
.VAR12 (1'b1),
.VAR7 (1'b1),
... | gpl-2.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/sgpr/reg_512x32b_3r_2w.v | 17,268 | module MODULE1
(
VAR44, VAR15, VAR9,
clk, VAR68, VAR59, VAR22, VAR71, VAR17, VAR58,
VAR45, VAR48, VAR6
);
input clk;
output [127:0] VAR44;
output [63:0] VAR15;
output [63:0] VAR9;
input [8:0] VAR68;
input [8:0] VAR59;
input [8:0] VAR22;
input [8:0] VAR71;
input [8:0] VAR17;
input [3:0] VAR58;
input [1:0] VAR45;
input [... | bsd-3-clause |
MegaShow/college-programming | Homework/Computer Organization and Interfacing/Multi Cycle CPU/Multi Cycle CPU.srcs/sources_1/new/Print.v | 1,565 | module MODULE1(
input VAR5,
input [15:0] VAR6,
output reg [7:0] VAR4,
output reg [3:0] VAR2
);
reg [3:0] VAR7;
reg [15:0] counter;
parameter [15:0] VAR1 = 16'VAR3; | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx2mb/rtl/pcx2mb_entry.v | 3,207 | module MODULE1 (
VAR15,
VAR2,
VAR10,
VAR6,
VAR3,
VAR17,
VAR16,
VAR12,
VAR19,
VAR8,
VAR14,
VAR18,
VAR13,
VAR5,
VAR1,
VAR4,
VAR9
);
parameter VAR11 = 5;
parameter VAR11 = 2;
output [VAR7+VAR11:0] VAR15;
output VAR2;
output [4:0] VAR10;
input VAR6;
input VAR3;
input VAR17;
input [VAR7-1:0] VAR16;
input [4:0] VAR12;
input ... | gpl-2.0 |
jairov4/accel-oil | solution_virtex5_plb/syn/verilog/p_bsf32_hw.v | 31,212 | module MODULE1 (
VAR58,
VAR6
);
parameter VAR12 = 5'b00000;
parameter VAR50 = 1'b1;
parameter VAR18 = 1'b0;
parameter VAR80 = 5'b1;
parameter VAR4 = 5'b10;
parameter VAR99 = 5'b11;
parameter VAR96 = 5'b100;
parameter VAR36 = 5'b101;
parameter VAR48 = 5'b110;
parameter VAR52 = 5'b111;
parameter VAR14 = 5'b1000;
paramete... | lgpl-3.0 |
mbus/mbus | m3_mbus_releases/r04p2g/sample/FLPv3L/verilog/mbus/flpv3l_mbus_isolation.bh.v | 3,322 | module MODULE1(
input VAR15,
input [VAR8-1:0] VAR6,
input [VAR7-1:0] VAR31,
input VAR12,
input VAR20,
input VAR25,
input VAR16,
input VAR28,
output reg [VAR8-1:0] VAR27,
output reg [VAR7-1:0] VAR18,
output reg VAR30,
output reg VAR19,
output reg VAR29,
output reg VAR2,
output reg VAR14,
input [VAR1-1:0] VAR3,
output re... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/data_compression/4-way_2-tree/src/riffa/async_fifo_fwft.v | 4,803 | module MODULE1 #(
parameter VAR22 = 32, parameter VAR16 = 1024, parameter VAR5 = 2**VAR3(VAR16),
parameter VAR28 = VAR10(VAR5),
parameter VAR18 = VAR10(VAR5+1)
)
(
input VAR21, input VAR14, input VAR25, input VAR7, input [VAR22-1:0] VAR4, input VAR6, output [VAR22-1:0] VAR27, input VAR9, output VAR12, output VAR24 );
r... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_mux_4to2/sky130_fd_sc_hdll__udp_mux_4to2.blackbox.v | 1,306 | module MODULE1 (
VAR7 ,
VAR1,
VAR5,
VAR6,
VAR3,
VAR2,
VAR4
);
output VAR7 ;
input VAR1;
input VAR5;
input VAR6;
input VAR3;
input VAR2;
input VAR4;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/SyncFIFO.v | 12,537 | module MODULE1(
VAR12,
VAR9,
VAR13,
VAR24,
VAR23,
VAR34,
VAR26,
VAR35,
VAR30
) ;
parameter VAR8 = 1 ;
parameter VAR20 = 2 ; parameter VAR25 = 1 ;
input VAR12 ;
input VAR9 ;
input VAR24 ;
input [VAR8 -1 : 0] VAR23 ;
output VAR34 ;
input VAR13 ;
input VAR26 ;
output VAR30 ;
output [VAR8 -1 : 0] VAR35 ;
wire [VAR25 : 0] V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21bo/sky130_fd_sc_ls__a21bo.behavioral.v | 1,579 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR8 ,
VAR3
);
output VAR4 ;
input VAR7 ;
input VAR8 ;
input VAR3;
supply1 VAR13;
supply0 VAR11;
supply1 VAR9 ;
supply0 VAR5 ;
wire VAR6 ;
wire VAR2;
nand VAR1 (VAR6 , VAR8, VAR7 );
nand VAR10 (VAR2, VAR3, VAR6);
buf VAR12 (VAR4 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invkapwr/sky130_fd_sc_lp__invkapwr.pp.blackbox.v | 1,315 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR2 ,
VAR1 ,
VAR5,
VAR6 ,
VAR7
);
output VAR3 ;
input VAR4 ;
input VAR2 ;
input VAR1 ;
input VAR5;
input VAR6 ;
input VAR7 ;
endmodule | apache-2.0 |
codustry/cuckoo | cuckooExten/display (Nutchanon Ninyawee's conflicted copy 2016-04-20).v | 1,152 | module MODULE1(
output [6:0] VAR6,
output [3:0] VAR4,
output VAR2,
input VAR9
);
wire VAR7,VAR1;
wire [1:0] VAR8;
wire [3:0] VAR10;
reg [3:0] VAR3,VAR3,VAR5,VAR5; | mit |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_01/011J1G2/hdl/j1.v | 4,340 | module MODULE1#(
parameter VAR35 = "./VAR1.VAR6" )
(
VAR7, VAR3, VAR14,
VAR44, VAR33, VAR12, VAR19);
input VAR7; input VAR3; input [15:0] VAR14; output VAR44; output VAR33; output [15:0] VAR12; output [15:0] VAR19;
wire [15:0] VAR21;
wire [15:0] VAR37 = { 1'b0, VAR21[14:0] };
wire [15:0] VAR32;
reg [4:0] VAR24;
reg [4:... | gpl-3.0 |
benreynwar/fpga-sdrlib | verilog/fpgamath/qa_multiply.v | 1,224 | module MODULE1
parameter VAR1 = 32,
parameter VAR10 = 1
)
(
input wire clk,
input wire VAR14,
input wire [VAR1-1:0] VAR6,
input wire VAR3,
input wire [VAR10-1:0] VAR11,
input wire [VAR15-1:0] VAR18,
input wire VAR4,
output wire [VAR1-1:0] VAR17,
output reg VAR13,
output reg [VAR10-1:0] VAR20,
output wire [VAR15-1:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd3/sky130_fd_sc_ls__dlygate4sd3.functional.pp.v | 1,832 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR5,
VAR7,
VAR3 ,
VAR11
);
output VAR8 ;
input VAR9 ;
input VAR5;
input VAR7;
input VAR3 ;
input VAR11 ;
wire VAR2 ;
wire VAR10;
buf VAR1 (VAR2 , VAR9 );
VAR6 VAR4 (VAR10, VAR2, VAR5, VAR7);
buf VAR12 (VAR8 , VAR10 );
endmodule | apache-2.0 |
spesialstyrker/boula | gen/PCIe/example_design/PIO_64_RX_ENGINE.v | 19,779 | module MODULE1 #(
parameter VAR4 = 1,
parameter VAR31 = 64,
parameter VAR6 = VAR31 / 8 ) (
input clk,
input VAR17,
input [VAR31-1:0] VAR9,
input [VAR6-1:0] VAR18,
input VAR14,
input VAR46,
output reg VAR32,
input [21:0] VAR22,
output reg VAR16,
output reg VAR41,
input VAR39,
output reg [2:0] VAR11, output reg VAR28, ou... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_queues/sram_rr_output_queues/src/oq_regs_host_iface.v | 5,433 | module MODULE1
parameter VAR15 = 13,
parameter VAR16 = 8,
parameter VAR21 = 2,
parameter VAR42 = 8,
parameter VAR25 = VAR13(VAR42),
parameter VAR18 = 17,
parameter VAR27 = VAR13(VAR18)
)
(
input VAR17,
input VAR38,
input VAR39,
input [VAR41-1:0] VAR36,
input [VAR6-1:0] VAR7,
input [VAR21-1:0] VAR9,
output reg VAR3,
out... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_2.behavioral.pp.v | 2,820 | module MODULE1( VAR1, VAR22, VAR6, VAR12, VAR17, VAR10 );
input VAR6, VAR22, VAR1;
inout VAR17, VAR10;
output VAR12;
reg VAR2;
VAR26 VAR25(.VAR1(VAR1),.VAR22(VAR22),.VAR6(VAR6),.VAR12(VAR12),.VAR17(VAR17),.VAR10(VAR10),.VAR2(VAR2));
VAR26 VAR13(.VAR1(VAR1),.VAR22(VAR22),.VAR6(VAR6),.VAR12(VAR12),.VAR17(VAR17),.VAR10(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfstp/sky130_fd_sc_hd__dfstp.symbol.v | 1,387 | module MODULE1 (
input VAR5 ,
output VAR1 ,
input VAR6,
input VAR4
);
supply1 VAR7;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_burst_gen.v | 61,872 | module MODULE1 #
( parameter
VAR85 = 4,
VAR81 = "VAR105",
VAR7 = 0,
VAR150 = 1,
VAR63 = 1,
VAR38 = 3,
VAR49 = 13,
VAR115 = 10,
VAR29 = 10,
VAR9 = 10,
VAR28 = 4,
VAR124 = 2,
VAR75 = 0,
VAR103 = 0,
VAR121 = 3,
VAR79 = 5,
VAR62 = 4,
VAR87 = 0
)
(
VAR137,
VAR1,
VAR100,
VAR94,
VAR67,
VAR70,
VAR88,
VAR98,
VAR134,
VAR127,
VAR... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_3.behavioral.v | 1,101 | module MODULE1( VAR3, VAR5 );
input VAR3;
output VAR5;
VAR2 VAR4(.VAR3(VAR3),.VAR5(VAR5));
VAR2 VAR1(.VAR3(VAR3),.VAR5(VAR5)); | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/amber.v | 16,582 | module MODULE1
(
input wire clk, input wire VAR47, input wire VAR18, input wire [ 2-1:0] VAR39, input wire [ 2-1:0] VAR22, input wire [ 2-1:0] VAR81, input wire [ 2-1:0] VAR42, input wire [ 9-1:0] VAR21, input wire VAR1, input wire VAR43, input wire VAR50, input wire [ 8-1:0] VAR28, input wire [ 8-1:0] VAR83, input wir... | gpl-3.0 |
jmt329/PitchShifter | delta_rom.v | 35,702 | module MODULE1 (VAR1, address, VAR2);
input VAR1;
input [9:0] address;
output [31:0] VAR2;
reg [31:0] VAR2;
always@(posedge VAR1)
begin
case(address)
10'd0: VAR2 = 32'b00010000000000000000000000000000;
10'd1: VAR2 = 32'b00010000001000000000000000000000;
10'd2: VAR2 = 32'b00010000010000000000000000000000;
10'd3: VAR2 = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxbp/sky130_fd_sc_hs__sedfxbp.blackbox.v | 1,396 | module MODULE1 (
VAR4 ,
VAR8,
VAR7,
VAR2 ,
VAR9 ,
VAR1,
VAR6
);
output VAR4 ;
output VAR8;
input VAR7;
input VAR2 ;
input VAR9 ;
input VAR1;
input VAR6;
supply1 VAR5;
supply0 VAR3;
endmodule | apache-2.0 |
jmahler/mips-cpu | im_slow.v | 1,843 | module MODULE1(
input wire clk,
input wire [31:0] addr,
output wire VAR14,
output wire [31:0] VAR13);
parameter VAR1 = 128; parameter VAR5 = "VAR6.VAR7";
parameter VAR10 = 128;
parameter VAR3 = 3;
wire [31:0] VAR9;
VAR12 #(.VAR1(VAR1), .VAR5(VAR5))
VAR11(.clk(clk), .addr(addr), .VAR13(VAR9));
reg [31:0] VAR4;
wire VAR8... | gpl-3.0 |
Jam-G/MIPS | MEM_WR.v | 1,105 | module MODULE1(
input clk,
input VAR5,
input VAR8,
input [31:0] VAR11,
input [3:0] VAR13,
input [31:0] VAR14,
input VAR6,
input VAR12,
input [4:0] VAR10,
output reg [31:0] VAR9,
output reg [3:0] VAR3,
output reg [31:0] VAR1,
output reg VAR7,
output reg VAR4,
output reg [4:0] VAR2
);
begin | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxtp/sky130_fd_sc_lp__dfxtp.functional.pp.v | 1,644 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR6 ,
VAR5,
VAR9,
VAR7 ,
VAR3
);
output VAR2 ;
input VAR8 ;
input VAR6 ;
input VAR5;
input VAR9;
input VAR7 ;
input VAR3 ;
wire VAR12;
VAR4 VAR11 VAR1 (VAR12 , VAR6, VAR8, , VAR5, VAR9);
buf VAR10 (VAR2 , VAR12 );
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/4-way/src/ip_dram/phy/mig_7series_v2_3_ddr_phy_wrcal.v | 54,326 | module MODULE1 #
(
parameter VAR41 = 100, parameter VAR127 = 2, parameter VAR98 = 2500,
parameter VAR171 = 64, parameter VAR146 = 3, parameter VAR214 = 8, parameter VAR91 = 8, parameter VAR140 = "VAR51", parameter VAR207 = "VAR77" )
(
input clk,
input rst,
input VAR4,
input VAR134,
input VAR152,
input VAR136,
input VAR... | mit |
gajjanag/6111_Project | src/ycrcb2rgb.v | 2,589 | module MODULE1 ( VAR9, VAR18, VAR20, clk, rst, VAR16, VAR14, VAR13 );
output [7:0] VAR9, VAR18, VAR20;
input clk,rst;
input[9:0] VAR16, VAR14, VAR13;
wire [7:0] VAR9,VAR18,VAR20;
reg [20:0] VAR6,VAR2,VAR3,VAR21,VAR23,VAR17,VAR4,VAR5;
reg [9:0] VAR15,VAR12,VAR8,VAR11,VAR10;
reg[9:0] VAR22, VAR1, VAR19;
always @ (posedge... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtn/sky130_fd_sc_hs__dlrtn.functional.v | 1,907 | module MODULE1 (
VAR3 ,
VAR12 ,
VAR1 ,
VAR15,
VAR5 ,
VAR7
);
input VAR3 ;
input VAR12 ;
output VAR1 ;
input VAR15;
input VAR5 ;
input VAR7 ;
wire VAR14 ;
wire VAR10;
wire VAR6 ;
not VAR11 (VAR14 , VAR15 );
not VAR9 (VAR10, VAR7 );
VAR8 VAR13 VAR2 (VAR6 , VAR5, VAR10, VAR14, VAR3, VAR12);
buf VAR4 (VAR1 , VAR6 );
endmod... | apache-2.0 |
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