repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_lvc_wpad/sky130_fd_io__top_power_lvc_wpad.functional.pp.v | 1,251 | module MODULE1 ( VAR18, VAR5, VAR13
, VAR3, VAR4, VAR14, VAR19, VAR16, VAR7, VAR17, VAR1, VAR10, VAR11, VAR15, VAR2, VAR8, VAR12, VAR20, VAR9, VAR6
);
inout VAR18;
inout VAR5;
inout VAR13;
inout VAR7;
inout VAR17;
inout VAR16;
inout VAR14;
inout VAR4;
inout VAR19;
inout VAR3;
inout VAR8;
inout VAR15;
inout VAR10;
inout... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3/sky130_fd_sc_lp__nor3.pp.blackbox.v | 1,321 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR4 ,
VAR1 ,
VAR6,
VAR3,
VAR5 ,
VAR8
);
output VAR2 ;
input VAR7 ;
input VAR4 ;
input VAR1 ;
input VAR6;
input VAR3;
input VAR5 ;
input VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor2/sky130_fd_sc_hdll__xnor2_4.v | 2,148 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR9 ,
VAR3,
VAR7,
VAR6 ,
VAR8
);
output VAR5 ;
input VAR4 ;
input VAR9 ;
input VAR3;
input VAR7;
input VAR6 ;
input VAR8 ;
VAR1 VAR2 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR5,
VAR4,
VAR9
);
output VAR5;
... | apache-2.0 |
GSejas/Aproximate-Arithmetic-Operators | src_lib/multlib/UDM.v | 1,576 | module MODULE1
(
input wire [1:0] VAR2,
input wire [1:0] VAR3,
output reg [2:0] VAR1
);
always @* begin
case ({VAR2,VAR3})
4'b0000 : begin
VAR1 = 3'b000;
end
4'b0001 : begin
VAR1 = 3'b000;
end
4'b0010 : begin
VAR1 = 3'b000;
end
4'b0011 : begin
VAR1 = 3'b000;
end
4'b0100 : begin
VAR1 = 3'b000;
end
4'b0101 : begin
VAR1 =... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.v | 2,818 | module MODULE2 (
VAR12 ,
VAR7 ,
VAR8 ,
VAR1 ,
VAR13 ,
VAR6,
VAR11,
VAR5 ,
VAR3 ,
VAR2 ,
VAR14 ,
VAR10
);
output VAR12 ;
input VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR13 ;
input VAR6;
input VAR11;
input VAR5 ;
input VAR3 ;
input VAR2 ;
input VAR14 ;
input VAR10 ;
VAR4 VAR9 (
.VAR12(VAR12),
.VAR7(VAR7),
.VAR8(VAR8),
.V... | apache-2.0 |
osecpu/fpga | led7seg.v | 1,467 | module MODULE1(clk, VAR1, VAR8, VAR3);
output [7:0] VAR1;
output [3:0] VAR8;
input clk;
input [15:0] VAR3;
reg [18:0] counter;
wire [3:0] VAR4, VAR9, VAR11, VAR12;
assign VAR4 = VAR3[3:0];
assign VAR9 = VAR3[7:4];
assign VAR11 = VAR3[11:8];
assign VAR12 = VAR3[15:12];
wire [1:0] VAR2 = counter[18:17];
assign VAR8 = ~(1... | mit |
neale/CS-program | 474-VLSI/Lab_ADC/ADC_PLL_bb.v | 11,212 | module MODULE1 (
VAR1,
VAR4,
VAR2,
VAR3);
input VAR1;
input VAR4;
output VAR2;
output VAR3;
tri0 VAR1;
endmodule | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkinv/sky130_fd_sc_ls__clkinv.symbol.v | 1,264 | module MODULE1 (
input VAR6,
output VAR3
);
supply1 VAR4;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
jedimatt42/pi-messaging | hardware/tipi-peb/ise/tipi_top.v | 4,485 | module MODULE1(
output VAR34,
input[0:3] VAR62,
output VAR31,
output VAR40,
output VAR7,
output VAR8,
output VAR14,
input VAR19,
input VAR44,
input VAR15,
input VAR3,
input VAR39,
output VAR1,
output VAR21,
input VAR38,
input VAR28,
input VAR22,
input VAR65,
input VAR2,
output VAR57,
output VAR51,
input[0:15] VAR4,
ino... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/maj3/sky130_fd_sc_ls__maj3.pp.symbol.v | 1,290 | module MODULE1 (
input VAR8 ,
input VAR7 ,
input VAR6 ,
output VAR5 ,
input VAR1 ,
input VAR2,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x1_125/example_design/PIO_EP_MEM_ACCESS.v | 12,522 | module MODULE1 (
clk,
VAR80,
VAR74, VAR59, VAR35,
VAR21, VAR82, VAR66, VAR23, VAR17
);
input clk;
input VAR80;
input [10:0] VAR74;
input [3:0] VAR59;
output [31:0] VAR35;
input [10:0] VAR21;
input [7:0] VAR82;
input [31:0] VAR66;
input VAR23;
output VAR17;
wire [31:0] VAR35;
reg [31:0] VAR51;
wire [31:0] VAR3, VAR42, V... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_16.behavioral.v | 1,098 | module MODULE1( VAR5, VAR1 );
input VAR5;
output VAR1;
VAR2 VAR4(.VAR5(VAR5),.VAR1(VAR1));
VAR2 VAR3(.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/wb_bfm/wb_bfm_master.v | 4,056 | module MODULE1
parameter VAR10 = 32,
parameter VAR16 = 0,
parameter VAR7 = 32)
(
input VAR4,
input VAR33,
output reg [VAR36-1:0] VAR38,
output reg [VAR10-1:0] VAR13,
output reg [3:0] VAR21,
output reg VAR5,
output reg VAR1,
output reg VAR28,
output reg [2:0] VAR9,
output reg [1:0] VAR15,
input [VAR10-1:0] VAR23,
input ... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_2.behavioral.pp.v | 1,868 | module MODULE1( VAR10, VAR3, VAR7, VAR5, VAR6, VAR2, VAR9 );
input VAR3, VAR10, VAR5, VAR6;
inout VAR2, VAR9;
output VAR7;
VAR1 VAR4(.VAR10(VAR10),.VAR3(VAR3),.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR9(VAR9));
VAR1 VAR8(.VAR10(VAR10),.VAR3(VAR3),.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR9(VAR9)); | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_cmos2_pad_dn.v | 2,546 | module MODULE1(VAR15 ,VAR17 ,VAR16 ,VAR25 ,VAR11, VAR3 );
output VAR16 ;
input VAR15 ;
input VAR17 ;
input VAR11 ;
inout VAR25 ;
input VAR3 ;
supply1 VAR14 ;
supply0 VAR8 ;
wire VAR4 ;
wire VAR9 ;
wire VAR30 ;
wire VAR2 ;
wire VAR7 ;
wire VAR23 ;
VAR27 VAR10 (
.VAR4 (VAR4 ),
.VAR16 (VAR16 ),
.VAR1 (VAR8 ),
.VAR28 (VAR2... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211ai/sky130_fd_sc_hs__o211ai.pp.symbol.v | 1,347 | module MODULE1 (
input VAR4 ,
input VAR1 ,
input VAR6 ,
input VAR7 ,
output VAR3 ,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/CS_bak/synthesis/submodules/altera_up_edge_detection_hysteresis.v | 5,419 | module MODULE1 (
clk,
reset,
VAR5,
VAR14,
VAR4
);
parameter VAR9 = 640;
input clk;
input reset;
input [ 7: 0] VAR5;
input VAR14;
output [ 7: 0] VAR4;
wire [ 8: 0] VAR3[ 1: 0];
wire VAR7;
wire [ 8: 0] VAR15;
wire VAR16;
wire VAR21;
reg [ 8: 0] VAR6[ 1: 0];
reg [ 2: 0] VAR20[ 2: 0];
reg [ 7: 0] VAR18;
integer VAR11;
alwa... | mit |
azonenberg/antikernel-ipcores | math/CRC8_ATM.v | 8,815 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR1,
input wire[31:0] din,
output reg[7:0] VAR3 = 0,
output reg[7:0] VAR5 = 0
);
wire[23:0] VAR2 = din[31:8];
reg[7:0] VAR4 = 0;
always @(*) begin
if(reset)
VAR4 <= 8'h00;
end
else
VAR4 <= VAR3;
end
always @(posedge clk) begin
if(VAR1) begin
VAR3[0] <= din[3... | bsd-3-clause |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_0_axi_mc_b_channel.v | 8,172 | module MODULE1 #
(
parameter integer VAR14 = 4
)
(
input wire clk,
input wire reset,
output wire [VAR14-1:0] VAR18,
output wire [1:0] VAR16,
output wire VAR4,
input wire VAR32,
input wire VAR27,
input wire [VAR14-1:0] VAR31,
input wire VAR11,
output wire VAR12
);
localparam VAR29 = VAR14;
localparam VAR33 = 8;
localpar... | mit |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/b2b/src/aur1_rx_stream.v | 4,371 | module MODULE1
(
VAR10,
VAR6,
VAR2,
VAR7,
VAR9,
VAR1,
VAR3,
VAR8,
VAR11
);
output [0:63] VAR10;
output VAR6;
input VAR2;
input [0:3] VAR7;
input [0:63] VAR9;
input [0:3] VAR1;
input [0:3] VAR3;
input [0:3] VAR8;
input VAR11;
reg VAR5;
always @(posedge VAR11)
if(!VAR2)
VAR5 <= VAR4 1'b0;
else if(VAR3 > 4'd0)
VAR5 <= VAR... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative_controller.v | 5,136 | module MODULE1 #(parameter VAR24=32)
(input VAR28
,input VAR9
,input VAR27
,output VAR13
,input VAR36
,input VAR37
,input VAR15
,input VAR4
,input VAR2
,output logic VAR44
,output logic VAR3
,output logic VAR29
,output logic VAR23
,output logic [2:0] VAR31
,output logic VAR6
,output logic VAR8
,output logic VAR11
,outp... | bsd-3-clause |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/rw_manager_ddr2.v | 6,721 | module MODULE1 (
VAR44,
VAR26,
VAR36,
VAR30,
VAR34,
VAR48,
VAR52,
VAR18,
VAR23,
VAR41,
VAR53,
VAR61,
VAR33,
VAR25,
VAR16,
VAR69,
VAR63,
VAR42,
VAR6,
VAR29,
VAR11,
VAR43,
VAR54,
VAR37,
VAR15,
VAR71,
VAR55,
VAR24,
VAR60,
VAR64
);
parameter VAR5 = 32;
parameter VAR66 = 16;
parameter VAR57 = 19;
parameter VAR21 = 4;
parame... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211a/sky130_fd_sc_hs__o211a.behavioral.pp.v | 1,937 | module MODULE1 (
VAR15,
VAR4,
VAR3 ,
VAR7 ,
VAR9 ,
VAR14 ,
VAR12
);
input VAR15;
input VAR4;
output VAR3 ;
input VAR7 ;
input VAR9 ;
input VAR14 ;
input VAR12 ;
wire VAR12 VAR5 ;
wire VAR1 ;
wire VAR11;
or VAR10 (VAR5 , VAR9, VAR7 );
and VAR8 (VAR1 , VAR5, VAR14, VAR12 );
VAR13 VAR2 (VAR11, VAR1, VAR15, VAR4);
buf VAR6... | apache-2.0 |
hanw/connectal | verilog/SyncReset.v | 2,988 | module MODULE1 (
VAR2,
VAR5,
VAR4
);
parameter VAR3 = 1 ;
input VAR5 ;
input VAR2 ;
output VAR4 ;
reg VAR7;
reg [VAR3:1] VAR6 ;
wire [VAR3+1:0] VAR1 = {VAR6, VAR7, ~ VAR9};
assign VAR4 = VAR6[VAR3] ;
always @( posedge VAR5 ) begin
if (VAR2 == VAR9)
begin
VAR7 <= VAR8 VAR9 ;
VAR6 <= VAR8 {(VAR3) {VAR9}} ;
end
else
begin... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22ai/sky130_fd_sc_lp__o22ai_lp.v | 2,360 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR10 ,
VAR2 ,
VAR5 ,
VAR3,
VAR11,
VAR4 ,
VAR6
);
output VAR1 ;
input VAR9 ;
input VAR10 ;
input VAR2 ;
input VAR5 ;
input VAR3;
input VAR11;
input VAR4 ;
input VAR6 ;
VAR7 VAR8 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR4(VAR4),
.... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_and.v | 1,546 | if (VAR20 && (VAR19==VAR2)) \
begin: VAR7 \
VAR12 VAR17 (.VAR4(VAR9),.VAR16(VAR6),.VAR10); \
end
module MODULE1 #(parameter VAR1(VAR19)
, parameter VAR20=0
)
(input [VAR19-1:0] VAR9
, input [VAR19-1:0] VAR6
, output [VAR19-1:0] VAR10
);
begin :VAR14
end
VAR3 assert(VAR20==0) else ("## %VAR18 VAR13 VAR8 VAR15 VAR5 VAR11... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/ui/ui_cmd.v | 7,860 | module MODULE1 #
(
parameter VAR30 = 100,
parameter VAR37 = 33,
parameter VAR46 = 3,
parameter VAR15 = 12,
parameter VAR17 = 5,
parameter VAR5 = 2,
parameter VAR1 = 16,
parameter VAR57 = 4,
parameter VAR50 = "VAR47"
)
(
VAR44, VAR28, VAR42, VAR2, VAR36, VAR20, VAR6, VAR12, VAR26,
VAR31, VAR35, VAR33,
rst, clk, VAR11, V... | lgpl-3.0 |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v | 10,391 | module MODULE1 #(
parameter VAR8 = 5'b00000
) (
input reset,
input VAR48,
input VAR22,
output VAR16,
output VAR15,
output [4:0] VAR37,
input [15:0] VAR7,
output [15:0] VAR49,
output reg VAR14
);
enum logic [3:0] {
localparam
VAR41 = 0,
VAR10 = 1,
VAR11 = 2,
VAR3 = 3,
VAR12 = 4,
VAR19 = 5,
VAR40 = 6,
VAR17 = 7,
VAR5 = 8... | gpl-2.0 |
jon-whit/4-bit_comp | verilog modules/internal_rom.v | 1,617 | module MODULE1(clk, VAR1, VAR2, VAR3, VAR5);
input clk, VAR1, VAR2;
output reg [7:0] VAR3;
output reg VAR5;
reg [3:0] VAR4;
always@(posedge clk)
if(VAR1)
VAR4 <= 0;
else if(~VAR5)
begin
if(VAR2 & (VAR4 < 10))
VAR4 <= VAR4 + 1;
end
else
VAR4 <= 0;
always@(*)
begin
VAR5 = 1'b0;
case(VAR4)
0: VAR3 = 8'b00000101; 1: VAR3 =... | mit |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_0_axi_mc_fifo.v | 5,741 | module MODULE1 #
(
parameter VAR18 = 8,
parameter VAR3 = 4,
parameter VAR7 = 16
)
(
input wire clk, input wire rst, input wire VAR17, input wire VAR12, input wire [VAR18-1:0] din, output wire [VAR18-1:0] dout, output wire VAR15,
output wire VAR10, output wire VAR8,
output wire VAR9 );
localparam [VAR3:0] VAR11 = ~(0);
... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x1_125/pci_exp_1_lane_64b_ep.v | 10,061 | module MODULE1 (
VAR62,
VAR67,
VAR53,
VAR32,
VAR12,
VAR70,
VAR7,
VAR54,
VAR9,
VAR21,
VAR43,
VAR18,
VAR23,
VAR25,
VAR33,
VAR69,
VAR39,
VAR61,
VAR64,
VAR45,
VAR19,
VAR2,
VAR38,
VAR26,
VAR74,
VAR20,
VAR30,
VAR51,
VAR37,
VAR72,
VAR73,
VAR22,
VAR6,
VAR56,
VAR13,
VAR68,
VAR28,
VAR27,
VAR55,
VAR47,
VAR14,
VAR17,
VAR34,
VAR35,... | lgpl-3.0 |
r2apu/Labo_Digitales | L2/miniALU_L2/MiniAlu.v | 4,851 | module MODULE1
(
input wire VAR1,
input wire VAR20,
output wire [7:0] VAR33
);
wire [15:0] VAR16,VAR32;
reg VAR37,VAR26;
wire [27:0] VAR28;
wire [3:0] VAR15;
reg signed [15:0] VAR3;
wire [7:0] VAR25,VAR40,VAR2, VAR7, VAR42;
wire [15:0] VAR39,VAR36,VAR38,VAR27;
VAR4 VAR10
(
.VAR48( VAR16 ),
.VAR6( VAR28 )
);
VAR12 VAR5
... | gpl-3.0 |
Digilent/vivado-library | ip/video_scaler/hdl/verilog/Mat2AXIvideo.v | 44,625 | module MODULE1 (
VAR45,
VAR67,
VAR31,
VAR114,
VAR128,
VAR5,
VAR103,
VAR46,
VAR9,
VAR107,
VAR108,
VAR95,
VAR104,
VAR73,
VAR1,
VAR99,
VAR30,
VAR13,
VAR52,
VAR81,
VAR141,
VAR62,
VAR89,
VAR136,
VAR10,
VAR42,
VAR34,
VAR83,
VAR156,
VAR20,
VAR8
);
parameter VAR120 = 4'd1;
parameter VAR32 = 4'd2;
parameter VAR80 = 4'd4;
parame... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrbp/sky130_fd_sc_ms__sdfrbp_2.v | 2,695 | module MODULE2 (
VAR2 ,
VAR1 ,
VAR6 ,
VAR7 ,
VAR4 ,
VAR12 ,
VAR5,
VAR3 ,
VAR9 ,
VAR13 ,
VAR11
);
output VAR2 ;
output VAR1 ;
input VAR6 ;
input VAR7 ;
input VAR4 ;
input VAR12 ;
input VAR5;
input VAR3 ;
input VAR9 ;
input VAR13 ;
input VAR11 ;
VAR8 VAR10 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR4(VAR4)... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_fifo_v1_00_a/hdl/verilog/address_gray_pipelined.v | 2,384 | module MODULE1 (
input VAR19,
input VAR17,
input VAR12,
output reg VAR14,
output [VAR3-1:0] VAR24,
input VAR20,
input VAR11,
output reg VAR23,
input VAR13,
output reg VAR1,
output [VAR3-1:0] VAR7
);
parameter VAR3 = 4;
reg [VAR3:0] VAR7 = 'h00;
reg [VAR3:0] VAR9;
wire [VAR3:0] VAR5;
reg [VAR3:0] VAR2 = 'h00;
reg [VAR3:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/conb/sky130_fd_sc_hvl__conb.pp.blackbox.v | 1,259 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR5,
VAR2,
VAR4 ,
VAR1
);
output VAR3 ;
output VAR6 ;
input VAR5;
input VAR2;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21oi/sky130_fd_sc_ms__a21oi.functional.v | 1,420 | module MODULE1 (
VAR4 ,
VAR6,
VAR8,
VAR1
);
output VAR4 ;
input VAR6;
input VAR8;
input VAR1;
wire VAR9 ;
wire VAR7;
and VAR5 (VAR9 , VAR6, VAR8 );
nor VAR3 (VAR7, VAR1, VAR9 );
buf VAR2 (VAR4 , VAR7 );
endmodule | apache-2.0 |
ultraembedded/riscv | top_tcm_wrapper/riscv_tcm_wrapper.v | 12,878 | module MODULE1
parameter VAR87 = 0
,parameter VAR205 = 0
,parameter VAR25 = 0
,parameter VAR29 = 0
,parameter VAR201 = 32'hffffffff
)
(
input VAR196
,input VAR235
,input VAR122
,input VAR171
,input VAR256
,input VAR74
,input [ 1:0] VAR231
,input [ 3:0] VAR168
,input VAR173
,input VAR145
,input [ 31:0] VAR152
,input [ 1... | bsd-3-clause |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/V2NFC100DDR/src/NPM_Toggle_PHYOutMux.v | 26,283 | module MODULE1
(
parameter VAR10 = 4
)
(
VAR94 ,
VAR59 ,
VAR74 ,
VAR24 ,
VAR13 ,
VAR54 ,
VAR75 ,
VAR56 ,
VAR63 ,
VAR32 ,
VAR57 ,
VAR52 ,
VAR42 ,
VAR30 ,
VAR39 ,
VAR95 ,
VAR27 ,
VAR33 ,
VAR28 ,
VAR87 ,
VAR88 ,
VAR84 ,
VAR3 ,
VAR49 ,
VAR43 ,
VAR61 ,
VAR6 ,
VAR72 ,
VAR79 ,
VAR9 ,
VAR89 ,
VAR2 ,
VAR21 ,
VAR22 ,
VAR11 ,
VAR... | gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/verilog/FIFO_image_filter_p_src_data_stream_1_V.v | 3,017 | module MODULE1 (
clk,
VAR2,
VAR4,
VAR17,
VAR14);
parameter VAR23 = 32'd8;
parameter VAR22 = 32'd1;
parameter VAR13 = 32'd2;
input clk;
input [VAR23-1:0] VAR2;
input VAR4;
input [VAR22-1:0] VAR17;
output [VAR23-1:0] VAR14;
reg[VAR23-1:0] VAR9 [0:VAR13-1];
integer VAR11;
always @ (posedge clk)
begin
if (VAR4)
begin
for (... | gpl-3.0 |
cpulabs/gci-std-display | rtl/display_controller/gci_std_display_register.v | 2,952 | module MODULE1 #(
parameter VAR19 = 307200 (
input wire VAR27,
input wire VAR1,
input wire VAR2,
input wire VAR22,
input wire [3:0] VAR24,
input wire [31:0] VAR14,
input wire VAR29,
output wire VAR16,
input wire [3:0] VAR11,
output wire VAR15,
input wire VAR6,
output wire [31:0] VAR13,
output VAR23,
output [1:0] VAR10
... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31o/sky130_fd_sc_hs__a31o.functional.pp.v | 1,927 | module MODULE1 (
VAR9,
VAR6,
VAR11 ,
VAR7 ,
VAR2 ,
VAR13 ,
VAR4
);
input VAR9;
input VAR6;
output VAR11 ;
input VAR7 ;
input VAR2 ;
input VAR13 ;
input VAR4 ;
wire VAR4 VAR14 ;
wire VAR3 ;
wire VAR1;
and VAR15 (VAR14 , VAR13, VAR7, VAR2 );
or VAR10 (VAR3 , VAR14, VAR4 );
VAR12 VAR8 (VAR1, VAR3, VAR9, VAR6);
buf VAR5 (V... | apache-2.0 |
karatekid/ultrasonic-fountain | hardware/src/spi_addressing.v | 2,839 | module MODULE1 (
input clk,
input rst,
output VAR38,
input VAR33,
input VAR28,
input VAR39,
output [5:0] VAR20,
output write,
output VAR7,
output [7:0] VAR34,
input [7:0] VAR3,
output VAR5
);
wire VAR17;
wire [7:0] VAR27;
wire VAR16, VAR1;
wire VAR19;
VAR36 VAR36 (
.clk(clk),
.rst(VAR29),
.VAR41(VAR39),
.VAR12(VAR33),
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtn/sky130_fd_sc_lp__dfrtn.behavioral.pp.v | 2,391 | module MODULE1 (
VAR21 ,
VAR9 ,
VAR1 ,
VAR14,
VAR4 ,
VAR23 ,
VAR15 ,
VAR10
);
output VAR21 ;
input VAR9 ;
input VAR1 ;
input VAR14;
input VAR4 ;
input VAR23 ;
input VAR15 ;
input VAR10 ;
wire VAR16 ;
wire VAR22 ;
wire VAR2 ;
reg VAR12 ;
wire VAR13 ;
wire VAR5;
wire VAR8 ;
wire VAR19 ;
wire VAR17 ;
wire VAR6 ;
not VAR3 ... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/SINGLE/fpaddsub_arch2_syn.v | 6,146 | module MODULE2 ( clk, rst, VAR120, VAR102, VAR5,
VAR142, VAR73, VAR152, VAR141, VAR75,
VAR156, VAR165, VAR115, VAR58, VAR178, VAR38,
VAR132, VAR29, VAR80, VAR71, VAR101, VAR22,
VAR10, VAR61, VAR97, ready );
output [1:0] VAR101;
input clk, rst, VAR120, VAR102, VAR5, VAR142,
VAR73, VAR152;
output VAR141, VAR75, VAR156, V... | gpl-3.0 |
monotone-RK/FACE | IEICE-Trans/data_compression/8-way_2-tree/src/ip_pcie/PCIeGen2x8If128_stub.v | 7,253 | module MODULE1(VAR51, VAR60, VAR28, VAR73, VAR21, VAR24, VAR29, VAR15, VAR80, VAR82, VAR14, VAR17, VAR66, VAR43, VAR49, VAR23, VAR78, VAR44, VAR16, VAR65, VAR87, VAR81, VAR48, VAR47, VAR59, VAR63, VAR86, VAR36, VAR68, VAR62, VAR77, VAR27, VAR38, VAR35, VAR54, VAR42, VAR26, VAR31, VAR85, VAR9, VAR4, VAR33, VAR83, VAR76,... | mit |
jairov4/accel-oil | solution_kintex7/impl/ip/hdl/verilog/sample_iterator_get_offset.v | 36,471 | module MODULE1 (
VAR61,
VAR28,
VAR98,
VAR27,
VAR100,
VAR48,
VAR116,
VAR91,
VAR89,
VAR4,
VAR90,
VAR22,
VAR26,
VAR41,
VAR6,
VAR106,
VAR58,
VAR84,
VAR75,
VAR68,
VAR78,
VAR66,
VAR120,
VAR12,
VAR92,
VAR64,
VAR53,
VAR20,
VAR99,
VAR14,
VAR76,
VAR56,
VAR96,
VAR54,
VAR49,
VAR5,
VAR87,
VAR1,
VAR112
);
input VAR61;
input VAR28;
i... | lgpl-3.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/imports/impl_axi_fpga.v | 24,941 | module MODULE1(
input VAR83,
input VAR114,
input VAR62,
output VAR134,
output VAR193,
output VAR63,
output VAR212,
output VAR7,
output VAR38,
input VAR198,
input VAR151,
input VAR94,
output VAR29,
output VAR129,
input VAR84,
output VAR172,
output VAR46,
output VAR177,
output [12:0] VAR32,
output [2:0] VAR141,
output VA... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_017bits.v | 1,917 | module MODULE1 (
clk,
VAR18, VAR29, VAR32, VAR28, VAR31, VAR8, VAR10, VAR19,
sum,
);
input clk;
input [VAR16+0-1:0] VAR18, VAR29, VAR32, VAR28, VAR31, VAR8, VAR10, VAR19;
output [VAR16 :0] sum;
reg [VAR16 :0] sum;
wire [VAR16+3-1:0] VAR2;
wire [VAR16+2-1:0] VAR15, VAR24;
wire [VAR16+1-1:0] VAR25, VAR1, VAR17, VAR26;
re... | mit |
ncos/Xilinx-Verilog | INTERFACES/src/ARINC429/ARINC429.v | 1,777 | module MODULE1(
input wire [1 : 0] VAR22,
input wire [7 : 0] VAR13,
input wire [22 : 0] VAR15,
input wire VAR28,
output wire VAR2,
output wire VAR14,
input wire VAR8,
input wire VAR1,
input wire VAR3,
output reg [7:0] VAR29,
output reg [22:0] VAR24,
output reg VAR6,
input wire VAR7, input wire reset
);
VAR17 VAR12
(
.c... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21boi/sky130_fd_sc_ms__a21boi.blackbox.v | 1,392 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR5 ,
VAR3
);
output VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR3;
supply1 VAR8;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
mda-ut/SubZero | fpga/fpga_hw/top_level/SONAR/FancySlave.v | 4,056 | module MODULE1 (VAR34, VAR26, VAR44, VAR51, VAR35, VAR2, VAR28, VAR16, VAR53, VAR31, VAR15, VAR25, VAR1, VAR17, VAR38, VAR7);
input VAR34;
input [17:0] VAR1;
input [1:0] VAR17;
output [6:0] VAR28, VAR16, VAR53, VAR31, VAR15, VAR25;
output [17:0] VAR38;
output [2:0] VAR7;
input VAR26;
input VAR44;
input VAR2;
output VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbn/sky130_fd_sc_ms__dlxbn.functional.pp.v | 1,959 | module MODULE1 (
VAR13 ,
VAR15 ,
VAR6 ,
VAR3,
VAR16 ,
VAR4 ,
VAR5 ,
VAR7
);
output VAR13 ;
output VAR15 ;
input VAR6 ;
input VAR3;
input VAR16 ;
input VAR4 ;
input VAR5 ;
input VAR7 ;
wire VAR11 ;
wire VAR8;
not VAR9 (VAR11 , VAR3 );
VAR1 VAR14 VAR12 (VAR8 , VAR6, VAR11, , VAR16, VAR4);
buf VAR10 (VAR13 , VAR8 );
not V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ba/sky130_fd_sc_hd__o21ba.behavioral.v | 1,563 | module MODULE1 (
VAR12 ,
VAR13 ,
VAR5 ,
VAR1
);
output VAR12 ;
input VAR13 ;
input VAR5 ;
input VAR1;
supply1 VAR8;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR7 ;
wire VAR10 ;
wire VAR4;
nor VAR9 (VAR10 , VAR13, VAR5 );
nor VAR3 (VAR4, VAR1, VAR10 );
buf VAR11 (VAR12 , VAR4 );
endmodule | apache-2.0 |
omicronns/studies-sys-rek | de1-soc/v/I2C_CCD_Config.v | 10,435 | module MODULE1 ( VAR25,
VAR41,
VAR34,
VAR15,
VAR23,
VAR10,
VAR11
);
input VAR25;
input VAR41;
input VAR34;
output VAR10;
inout VAR11;
reg [15:0] VAR35;
reg [31:0] VAR5;
reg VAR3;
reg VAR28;
wire VAR16;
wire VAR40;
reg [23:0] VAR20;
reg [5:0] VAR27;
reg [3:0] VAR44;
input VAR15;
input VAR23;
parameter VAR42 = 16'h0797;
... | mit |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/altera_std_synchronizer_nocut.v | 5,650 | module MODULE1 (
clk,
VAR1,
din,
dout
);
parameter VAR3 = 3;
input clk;
input VAR1;
input din;
output dout;
reg VAR4;
reg [VAR3-2:0] VAR2; | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/Tiger4NSC/src/d_CS_evaluation_matrices.v | 148,177 | module MODULE60(VAR3, VAR2);
input wire [VAR1-1:0] VAR3;
output wire [VAR1-1:0] VAR2;
assign VAR2[0] = VAR3[0] ^ VAR3[2] ^ VAR3[3] ^ VAR3[4] ^ VAR3[5] ^ VAR3[10] ^ VAR3[11];
assign VAR2[1] = VAR3[0] ^ VAR3[1] ^ VAR3[3] ^ VAR3[4] ^ VAR3[5] ^ VAR3[6] ^ VAR3[11];
assign VAR2[2] = VAR3[0] ^ VAR3[1] ^ VAR3[2] ^ VAR3[4] ^ VA... | gpl-3.0 |
zhaishaomin/ring_network-based-multicore- | communication_assist/dc_download.v | 5,302 | module MODULE1( clk,
rst,
VAR7,
VAR27,
VAR5,
VAR4,
VAR24,
VAR19,
VAR28
);
parameter VAR8=5'b10000;
parameter VAR2=5'b10001;
parameter VAR26=5'b10010;
parameter VAR39=5'b10011;
parameter VAR38=5'b11000;
parameter VAR3=5'b11001;
parameter VAR23=5'b11010;
parameter VAR31=5'b11100;
parameter VAR13=5'b10100;
parameter VAR33... | apache-2.0 |
cpulabs/mist1032sa | src/dps/device/utim64/main_counter.v | 1,065 | module MODULE1(
input wire VAR9,
input wire VAR6,
input wire VAR5,
input wire VAR8,
input wire VAR4,
input wire [1:0] VAR1,
input wire [63:0] VAR2,
output wire VAR10,
output wire [63:0] VAR7
);
reg VAR3;
reg [63:0] VAR11;
always@(posedge VAR9 or negedge VAR6)begin
if(!VAR6)begin
VAR3 <= 1'b0;
VAR11 <= {64{1'b0}};
end
e... | bsd-2-clause |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/ovl_width.v | 1,651 | module MODULE1 (VAR3, reset, enable, VAR13, VAR21);
parameter VAR9 = VAR16;
parameter VAR12 = 1;
parameter VAR18 = 1;
parameter VAR22 = VAR19;
parameter VAR2 = VAR20;
parameter VAR4 = VAR10;
parameter VAR17 = VAR8;
parameter VAR1 = VAR15;
parameter VAR5 = VAR7;
input VAR3, reset, enable;
input VAR13;
output [VAR11-1:0]... | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/verilog/FIFO_image_filter_src0_data_stream_2_V.v | 3,013 | module MODULE2 (
clk,
VAR13,
VAR15,
VAR1,
VAR14);
parameter VAR22 = 32'd8;
parameter VAR2 = 32'd1;
parameter VAR3 = 32'd2;
input clk;
input [VAR22-1:0] VAR13;
input VAR15;
input [VAR2-1:0] VAR1;
output [VAR22-1:0] VAR14;
reg[VAR22-1:0] VAR9 [0:VAR3-1];
integer VAR27;
always @ (posedge clk)
begin
if (VAR15)
begin
for (V... | gpl-3.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/mkCRC32.v | 16,946 | module MODULE1(VAR37,
VAR7,
VAR33,
VAR28,
VAR38,
VAR34,
VAR44,
VAR6,
VAR41,
VAR20,
VAR4,
VAR1);
input VAR37;
input VAR7;
input [7 : 0] VAR33;
input VAR28;
output VAR38;
input VAR34;
output VAR44;
output [31 : 0] VAR6;
output VAR41;
input VAR20;
output [31 : 0] VAR4;
output VAR1;
wire [31 : 0] VAR4, VAR6;
wire VAR38, VA... | lgpl-3.0 |
theapi/de1-soc | vga/ip/pll/vga_pll/vga_pll_0002.v | 2,272 | module MODULE1(
input wire VAR47,
input wire rst,
output wire VAR64,
output wire VAR22,
output wire VAR20,
output wire VAR61,
output wire VAR34
);
VAR68 #(
.VAR31("false"),
.VAR35("50.0 VAR26"),
.VAR65("VAR73"),
.VAR12(4),
.VAR40("25.000000 VAR26"),
.VAR36("0 VAR46"),
.VAR37(50),
.VAR7("40.000000 VAR26"),
.VAR17("0 VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ai/sky130_fd_sc_hs__o21ai_2.v | 2,134 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR2 ,
VAR4 ,
VAR6,
VAR8
);
output VAR1 ;
input VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR6;
input VAR8;
VAR7 VAR3 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR1 ,
VAR5,
VAR2,
VAR4
);
output VAR1 ;
input VAR5;
input VAR2;
... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_spram_512x20.v | 11,088 | module MODULE1(
VAR1, VAR50, VAR31,
clk, rst, VAR42, VAR19, VAR34, addr, VAR15, VAR51
);
parameter VAR26 = 9;
parameter VAR41 = 20;
input VAR1;
input [VAR3 - 1:0] VAR31;
output VAR50;
input clk; input rst; input VAR42; input VAR19; input VAR34; input [VAR26-1:0] addr; input [VAR41-1:0] VAR15; output [VAR41-1:0] VAR51;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvgnd/sky130_fd_sc_ms__tapvgnd.behavioral.v | 1,193 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufinv/sky130_fd_sc_ms__bufinv.functional.v | 1,259 | module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
wire VAR5;
not VAR3 (VAR5, VAR4 );
buf VAR2 (VAR1 , VAR5 );
endmodule | apache-2.0 |
JakeMercer/mac | gmii.v | 1,193 | module MODULE1
(
input wire reset,
input wire VAR12,
output wire VAR19,
output wire [7:0] VAR17,
output wire VAR11,
output wire VAR3,
input wire VAR18,
input wire [7:0] VAR21,
input wire VAR9,
input wire VAR15,
input wire VAR1,
input wire VAR8,
input wire VAR5,
input wire [7:0] VAR7,
input wire VAR2,
output wire VAR13,... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_axi_basic_rx_null_gen.v | 15,537 | module MODULE1 # (
parameter VAR4 = 128, parameter VAR9 = 1,
parameter VAR1 = VAR4 / 8 ) (
input [VAR4-1:0] VAR25, input VAR21, input VAR28, input VAR35, input [21:0] VAR16,
output VAR13, output VAR31, output [VAR1-1:0] VAR3, output VAR11, output reg [4:0] VAR17,
input VAR26, input VAR2 );
localparam VAR29 = (VAR4 == 1... | lgpl-3.0 |
jhol/butterflylogic | lib/xilinx/IOBUF.v | 3,168 | module MODULE1 (VAR10, VAR9, VAR16, VAR19);
parameter VAR4 = "VAR21";
parameter integer VAR20 = 12;
parameter VAR18 = "0";
parameter VAR15 = "VAR8";
parameter VAR11 = "VAR7";
parameter VAR1 = "VAR12";
parameter VAR6 = "VAR14";
output VAR10;
inout VAR9;
input VAR16, VAR19;
wire VAR2;
tri0 VAR13 = VAR17.VAR13;
or VAR3 (V... | gpl-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_fp_custom_reduced_normalize_mult_double.v | 4,568 | module MODULE1(
VAR17, VAR5,
VAR16, VAR9, VAR10,
VAR23, VAR2, VAR20, VAR6,
enable,
VAR19, VAR18, VAR7);
parameter VAR21 = 1;
parameter VAR15 = 1;
parameter VAR1 = 1;
input VAR17, VAR5;
input VAR23, VAR2;
output VAR20, VAR6;
input enable;
input [56:0] VAR16;
input [11:0] VAR9; input VAR10;
output [55:0] VAR19; output [1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvn/sky130_fd_sc_hd__einvn.symbol.v | 1,335 | module MODULE1 (
input VAR6 ,
output VAR2 ,
input VAR4
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
ptracton/wb_soc_template | rtl/jtag_tap/tap/rtl/verilog/tap_top.v | 20,863 | module MODULE1 #(parameter
VAR34 = 32'h149511c3,
VAR43 = 4)
(
VAR32,
VAR29,
VAR24,
VAR27,
VAR33,
VAR42,
VAR12,
VAR59,
VAR49,
VAR46,
VAR62,
VAR6,
VAR17,
VAR54,
VAR35,
VAR36, VAR26, VAR40 );
input VAR32; input VAR29; input VAR24; input VAR27; output VAR33; output VAR42;
output VAR12;
output VAR59;
output VAR49;
output VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41oi/sky130_fd_sc_hd__a41oi.functional.pp.v | 2,070 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR18 ,
VAR10 ,
VAR1 ,
VAR14 ,
VAR17,
VAR13,
VAR8 ,
VAR11
);
output VAR4 ;
input VAR9 ;
input VAR18 ;
input VAR10 ;
input VAR1 ;
input VAR14 ;
input VAR17;
input VAR13;
input VAR8 ;
input VAR11 ;
wire VAR16 ;
wire VAR15 ;
wire VAR12;
and VAR6 (VAR16 , VAR9, VAR18, VAR10, VAR1 );
nor VAR5 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2/sky130_fd_sc_hdll__mux2.functional.v | 1,524 | module MODULE1 (
VAR7 ,
VAR5,
VAR4,
VAR6
);
output VAR7 ;
input VAR5;
input VAR4;
input VAR6 ;
wire VAR1;
VAR8 VAR3 (VAR1, VAR5, VAR4, VAR6 );
buf VAR2 (VAR7 , VAR1);
endmodule | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/phy/mig_7series_v1_8_ddr_if_post_fifo.v | 8,521 | module MODULE1 #
(
parameter VAR6 = 100, parameter VAR24 = 4, parameter VAR29 = 32 )
(
input clk, input rst, input [3:0] VAR10,
input VAR28,
input [VAR29-1:0] din, output VAR11,
output VAR12,
output [VAR29-1:0] dout );
localparam VAR14
= (VAR24 == 2) ? 1 :
(((VAR24 == 3) || (VAR24 == 4)) ? 2 : 'VAR26);
integer VAR27;
r... | lgpl-3.0 |
hoglet67/opc | opc3/opc3cpu.v | 2,199 | module MODULE1( inout[15:0] VAR14, output[15:0] address, output VAR9, input clk, input VAR28);
parameter VAR2=0, VAR3=1, VAR23=2, VAR12=3, VAR21=4 ;
parameter VAR24=5'VAR30, VAR16=5'VAR33, VAR6=5'VAR22, VAR25=5'VAR19;
parameter VAR5=5'b01001, VAR8=5'b11000, VAR18=5'b01000;
parameter VAR4=5'b11001, VAR13=5'b11010, VAR27... | gpl-3.0 |
ngoel9/progressive-learning-platform | reference/hw/unused/mod_skeleton.v | 1,274 | module MODULE1(rst, clk, VAR3, VAR7, VAR5, VAR2, VAR8, din, VAR4, dout);
input rst;
input clk;
input VAR3,VAR7;
input [31:0] VAR5, VAR2;
input [1:0] VAR8;
input [31:0] din;
output [31:0] VAR4, dout;
wire [31:0] VAR6, VAR1;
assign VAR4 = VAR6;
assign dout = VAR1;
always @(negedge clk) begin
if (VAR8[0] && VAR7 && !rst) ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2b/sky130_fd_sc_hdll__nand2b.symbol.v | 1,305 | module MODULE1 (
input VAR4,
input VAR5 ,
output VAR2
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_16.behavioral.v | 1,113 | module MODULE1( VAR5, VAR1 );
input VAR5;
output VAR1;
VAR4 VAR3(.VAR5(VAR5),.VAR1(VAR1));
VAR4 VAR2(.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Detect_Change.v | 1,792 | module MODULE1
(
VAR6,
reset,
VAR4,
VAR8,
VAR9
);
input VAR6;
input reset;
input VAR4;
input signed [17:0] VAR8; output VAR9;
reg signed [17:0] VAR10; wire signed [18:0] VAR3; wire signed [18:0] VAR5; wire signed [18:0] VAR1; wire VAR7;
always @(posedge VAR6)
begin : VAR12
if (reset == 1'b1) begin
VAR10 <= 18'VAR2;
end... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221ai/sky130_fd_sc_hs__o221ai.pp.blackbox.v | 1,383 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR8 ,
VAR4 ,
VAR3 ,
VAR5 ,
VAR7,
VAR6
);
output VAR2 ;
input VAR1 ;
input VAR8 ;
input VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR7;
input VAR6;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_mux_4to2/sky130_fd_sc_hd__udp_mux_4to2.symbol.v | 1,327 | module MODULE1 (
input VAR6,
input VAR1,
input VAR2,
input VAR4,
output VAR7 ,
input VAR3,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hs__udp_dff_pr_pp_pg_n.blackbox.v | 1,437 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR5 ,
VAR3 ,
VAR4,
VAR2 ,
VAR6
);
output VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR3 ;
input VAR4;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.cache/ip/2018.2/ad4f3760cb81ab99/zybo_zynq_design_rst_ps7_0_100M_0_stub.v | 1,891 | module MODULE1(VAR4, VAR6, VAR7,
VAR10, VAR1, VAR2, VAR5, VAR9,
VAR3, VAR8)
;
input VAR4;
input VAR6;
input VAR7;
input VAR10;
input VAR1;
output VAR2;
output [0:0]VAR5;
output [0:0]VAR9;
output [0:0]VAR3;
output [0:0]VAR8;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21boi/sky130_fd_sc_ls__a21boi_2.v | 2,332 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR5 ,
VAR7,
VAR8,
VAR3,
VAR10 ,
VAR6
);
output VAR1 ;
input VAR2 ;
input VAR5 ;
input VAR7;
input VAR8;
input VAR3;
input VAR10 ;
input VAR6 ;
VAR4 VAR9 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR6(VAR6)
);
endmodule
module MODULE1 ... | apache-2.0 |
titorgalaxy/Titor | rtl/verilog/unused/Decoder.v | 1,228 | module MODULE1 (
address,
VAR2,
enable,
);
parameter VAR1=0;
input [VAR1-1:0] address;
output reg [(1<<VAR1)-1:0] VAR2;
input enable;
always @(*) begin
if(!enable) begin VAR2 <= 0;
end else begin VAR2 <= (1<<address);
end
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fahcon/sky130_fd_sc_hd__fahcon.functional.pp.v | 2,730 | module MODULE1 (
VAR22,
VAR25 ,
VAR4 ,
VAR20 ,
VAR7 ,
VAR1 ,
VAR23 ,
VAR24 ,
VAR5
);
output VAR22;
output VAR25 ;
input VAR4 ;
input VAR20 ;
input VAR7 ;
input VAR1 ;
input VAR23 ;
input VAR24 ;
input VAR5 ;
wire VAR18 ;
wire VAR17 ;
wire VAR10 ;
wire VAR6 ;
wire VAR15 ;
wire VAR12 ;
wire VAR14;
xor VAR3 (VAR18 , VAR4,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_p_pp_pg/sky130_fd_sc_hs__udp_dlatch_p_pp_pg.symbol.v | 1,389 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR3,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/ipcore_dir/ddr_rd_fifo.v | 13,514 | module MODULE1(
rst,
VAR224,
VAR387,
din,
VAR209,
VAR48,
dout,
VAR41,
VAR277,
VAR181,
VAR212
);
input rst;
input VAR224;
input VAR387;
input [255 : 0] din;
input VAR209;
input VAR48;
output [63 : 0] dout;
output VAR41;
output VAR277;
output [10 : 0] VAR181;
output VAR212;
VAR398 #(
.VAR127(0),
.VAR67(0),
.VAR351(0),
.V... | mit |
gigglesninja/digital-system-design | uart/ipcore_dir/fifo_tx.v | 13,646 | module MODULE1(
clk,
rst,
din,
VAR84,
VAR406,
dout,
VAR206,
VAR148
);
input clk;
input rst;
input [7 : 0] din;
input VAR84;
input VAR406;
output [7 : 0] dout;
output VAR206;
output VAR148;
VAR271 #(
.VAR257(0),
.VAR293(0),
.VAR399(0),
.VAR366(0),
.VAR184(0),
.VAR12(0),
.VAR10(0),
.VAR116(32),
.VAR142(1),
.VAR31(1),
.VA... | gpl-2.0 |
mosukiton/mipsprocessor | Mips_single_cycle.srcs/sources_1/new/singlecycleprocessor.v | 3,921 | module MODULE1(
input clk, reset
);
wire [31:0] VAR81, VAR13;
wire [31:0] VAR106, VAR77;
wire [31:0] VAR24;
wire [31:0] VAR19, VAR47;
wire [31:0] VAR29;
wire [31:0] VAR4;
wire [27:0] VAR15;
wire [4:0] VAR52, VAR41, VAR111;
wire [2:0] VAR20;
wire VAR40, VAR36, VAR22, VAR12, VAR64, VAR91, VAR51, VAR21;
wire VAR105;
wire ... | gpl-3.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/de0_nano/rtl/verilog/rom.v | 4,706 | module MODULE1
parameter VAR17 = 0)
(
input VAR9,
input VAR8,
input [(VAR4+2)-1:2] VAR14,
input VAR1,
input VAR16,
input [2:0] VAR12,
input [1:0] VAR15,
output reg [31:0] VAR11,
output reg VAR3);
reg [VAR4-1:0] VAR13;
always @ (posedge VAR9 or posedge VAR8)
if (VAR8)
VAR11 <= 32'h15000000;
else
case (VAR13)
0 : VAR11 <... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fme/fme_ctrl.v | 12,897 | module MODULE1 (
clk ,
VAR40 ,
VAR74 ,
VAR37 ,
VAR39 ,
VAR71 ,
VAR54 ,
VAR38 ,
VAR52 ,
VAR20 ,
VAR60 ,
VAR64 ,
VAR56 ,
VAR11 ,
VAR30 ,
VAR12 ,
VAR73 ,
VAR69 ,
VAR72 ,
VAR36 ,
VAR34 ,
VAR47 ,
VAR13 ,
VAR6 ,
VAR43
);
input [1-1:0] clk ; input [1-1:0] VAR40 ; input [1-1:0] VAR74 ; output [1-1:0] VAR37 ; output [4-1:0] VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1.symbol.v | 1,360 | module MODULE1 (
input [7:0] VAR4,
output VAR5,
input [7:0] VAR7
);
supply1 VAR2;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2/sky130_fd_sc_hd__nand2.pp.blackbox.v | 1,266 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR3 ,
VAR4,
VAR6,
VAR7 ,
VAR5
);
output VAR1 ;
input VAR2 ;
input VAR3 ;
input VAR4;
input VAR6;
input VAR7 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s.functional.v | 1,345 | module MODULE1 (
VAR5,
VAR2
);
output VAR5;
input VAR2;
wire VAR3;
buf VAR4 (VAR3, VAR2 );
buf VAR1 (VAR5 , VAR3 );
endmodule | apache-2.0 |
parallella/oh | common/hdl/oh_csa32.v | 1,155 | module MODULE1 #(parameter VAR7 = 1 )
( input [VAR7-1:0] VAR6, input [VAR7-1:0] VAR3, input [VAR7-1:0] VAR5, output [VAR7-1:0] VAR2, output [VAR7-1:0] VAR1 );
genvar VAR4;
for (VAR4=0;VAR4<VAR7;VAR4=VAR4+1)
begin
VAR8 VAR8 (.VAR2(VAR2[VAR4]),
.VAR1(VAR1[VAR4]),
.VAR5(VAR5[VAR4]),
.VAR3(VAR3[VAR4]),
.VAR6(VAR6[VAR4]));
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4bb/sky130_fd_sc_ms__nand4bb.symbol.v | 1,339 | module MODULE1 (
input VAR9,
input VAR7,
input VAR1 ,
input VAR5 ,
output VAR4
);
supply1 VAR3;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
AndreaCorallo/KPU | rtl/kpu_soc.v | 7,726 | module MODULE1(
input VAR33,
input VAR47,
input VAR132,
input [VAR60-1:0] VAR48,
input VAR94,
output VAR109,
output reg [7:0] VAR143,
output wire [VAR154-1:0] VAR83,
inout wire [VAR9-1:0] VAR15,
output wire VAR113,
output wire VAR137,
output wire VAR54,
output wire VAR16,
output wire VAR20,
input VAR53, input VAR141, i... | gpl-3.0 |
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