repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
OrganicMonkeyMotion/fpga_experiments | bmax10/embedded_lab/pwm_pll_bb.v | 11,816 | module MODULE1 (
VAR1,
VAR2,
VAR3);
input VAR1;
output VAR2;
output VAR3;
endmodule | unlicense |
hhuang25/uwaterloo_ece224 | ANT/led_pio.v | 2,048 | module MODULE1 (
address,
VAR9,
clk,
VAR6,
VAR5,
VAR4,
VAR3,
VAR8
)
;
output [ 7: 0] VAR3;
output [ 7: 0] VAR8;
input [ 1: 0] address;
input VAR9;
input clk;
input VAR6;
input VAR5;
input [ 7: 0] VAR4;
wire VAR2;
reg [ 7: 0] VAR7;
wire [ 7: 0] VAR3;
wire [ 7: 0] VAR1;
wire [ 7: 0] VAR8;
assign VAR2 = 1;
assign VAR1 = {... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlxtn/sky130_fd_sc_hdll__dlxtn.symbol.v | 1,349 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR6
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/nes_top.v | 11,696 | module MODULE1 (
input clk, input rst, input VAR152, input [3:0] VAR42,
output [9:0] VAR80, output [9:0] VAR10, output VAR133, output VAR101, output [2:0] VAR58, output [2:0] VAR39, output [1:0] VAR120,
input [7:0] VAR8, input [7:0] VAR70,
output VAR93,
input VAR69,
input [7:0] VAR123,
input VAR99,
output [15:0] VAR44,... | mit |
freecores/orsoc_graphics_accelerator | bench/verilog/gfx/wbm_w_bench.v | 1,750 | module MODULE1();
reg VAR16; reg VAR13; wire VAR11; wire VAR10; wire [ 2:0] VAR8; wire [ 1:0] VAR15; wire VAR5; wire [31:0] VAR14; wire [ 3:0] VAR3; reg VAR4; reg VAR18; wire [31:0] VAR1;
wire VAR6;
reg VAR9;
wire VAR2;
reg [31:2] VAR17;
reg [3:0] VAR7;
reg [31:0] VAR12;
begin | gpl-3.0 |
merckhung/zet | cores/zet/rtl/zet.v | 2,739 | module MODULE1 (
input VAR29,
input VAR9,
input [15:0] VAR26,
output [15:0] VAR20,
output [19:1] VAR1,
output VAR4,
output VAR27, output [ 1:0] VAR6,
output VAR18,
output VAR21,
input VAR10,
input VAR23, output VAR30, input VAR15,
output VAR12,
output [19:0] VAR24 );
wire [15:0] VAR25;
wire VAR5;
wire [19:0] VAR14;
wir... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fill/sky130_fd_sc_lp__fill.symbol.v | 1,186 | module MODULE1 ();
supply1 VAR3;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/chris/Qsys/soc_design/synthesis/submodules/soc_design_dma_0.v | 36,119 | module MODULE3 (
VAR32,
clk,
VAR122,
VAR133,
VAR38,
VAR7,
VAR123,
VAR2,
VAR36,
VAR114,
VAR29,
VAR42,
VAR17,
word,
VAR97
)
;
output [ 31: 0] VAR97;
input VAR32;
input clk;
input VAR122;
input [ 2: 0] VAR133;
input VAR38;
input VAR7;
input [ 14: 0] VAR123;
input VAR2;
input [ 31: 0] VAR36;
input VAR114;
input [ 10: 0] VA... | gpl-2.0 |
seyedmaysamlavasani/GorillaPP | apps/pageRank/build/verilog/types_float_double_grp_fu_100_ACMP_ddiv_4.v | 1,186 | module MODULE1(
clk,
reset,
VAR8,
VAR1,
VAR5,
VAR7,
VAR3);
input clk;
input reset;
input VAR8;
output VAR1;
input[64 - 1:0] VAR5;
input[64 - 1:0] VAR7;
output[64 - 1:0] VAR3;
MODULE2 MODULE1(
.clk(clk),
.VAR6(VAR8),
.VAR9(VAR1),
.VAR10(VAR5),
.VAR11(VAR7),
.VAR4(VAR3));
endmodule
module MODULE2(
clk,
VAR6,
VAR9,
VAR10,... | bsd-3-clause |
sh-chris110/chris | FPGA/HPS.bak/Qsys/hps_design/synthesis/submodules/hps_design_smp_hps.v | 10,056 | module MODULE1 #(
parameter VAR2 = 0,
parameter VAR62 = 0
) (
output wire VAR18, input wire VAR11, output wire [11:0] VAR8, output wire [20:0] VAR48, output wire [3:0] VAR47, output wire [2:0] VAR56, output wire [1:0] VAR39, output wire [1:0] VAR13, output wire [3:0] VAR31, output wire [2:0] VAR52, output wire VAR16, i... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvp/sky130_fd_sc_lp__einvp.pp.blackbox.v | 1,289 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR5 ,
VAR2,
VAR1,
VAR3 ,
VAR7
);
output VAR6 ;
input VAR4 ;
input VAR5 ;
input VAR2;
input VAR1;
input VAR3 ;
input VAR7 ;
endmodule | apache-2.0 |
boylansr/Prop_Muse | P1V/P8X32A_Emulation/P8X32A_DE2_115/cog_vid.v | 3,949 | module MODULE1
(
input VAR26,
input VAR17,
input VAR3,
input VAR15,
input VAR24,
input [31:0] VAR25,
input [31:0] VAR10,
input [31:0] VAR30,
input [7:0] VAR28,
input VAR19,
output ack,
output [31:0] VAR16
);
reg [31:0] VAR2;
reg [31:0] VAR11;
always @(posedge VAR26 or negedge VAR3)
if (!VAR3)
VAR2 <= 32'b0;
else if (VA... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.behavioral.v | 1,027 | module MODULE1( );
VAR3 VAR1();
VAR3 VAR2(); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtp/sky130_fd_sc_hd__dfrtp.symbol.v | 1,395 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR7,
input VAR8
);
supply1 VAR5;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111ai/sky130_fd_sc_hd__o2111ai.behavioral.v | 1,610 | module MODULE1 (
VAR6 ,
VAR5,
VAR11,
VAR10,
VAR4,
VAR7
);
output VAR6 ;
input VAR5;
input VAR11;
input VAR10;
input VAR4;
input VAR7;
supply1 VAR8;
supply0 VAR15;
supply1 VAR13 ;
supply0 VAR14 ;
wire VAR2 ;
wire VAR3;
or VAR9 (VAR2 , VAR11, VAR5 );
nand VAR12 (VAR3, VAR4, VAR10, VAR7, VAR2);
buf VAR1 (VAR6 , VAR3 );
en... | apache-2.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/source/rtl/Round_Sgf_Dec.v | 1,907 | module MODULE1(
input wire [1:0] VAR4,
input wire [1:0] VAR2,
input wire VAR3,
output reg VAR1
);
always @*
case ({VAR3,VAR2,VAR4})
5'b10101: VAR1 <=1;
5'b10110: VAR1 <=1;
5'b10111: VAR1 <=1;
5'b01001: VAR1 <=1;
5'b01010: VAR1 <=1;
5'b01011: VAR1 <=1;
default: VAR1 <=0;
endcase
endmodule | gpl-3.0 |
combinatorylogic/soc | backends/small1/hw/rtl/3rdparty/arbiter.v | 3,846 | module MODULE1 (
clk,
rst,
VAR1,
VAR2,
VAR6,
VAR11,
VAR9,
VAR3,
VAR20,
VAR13
);
input clk;
input rst;
input VAR1;
input VAR2;
input VAR6;
input VAR11;
output VAR9;
output VAR3;
output VAR20;
output VAR13;
wire [1:0] VAR15 ;
wire VAR14 ;
wire VAR4 ;
wire [1:0] VAR16 ;
wire VAR12 ;
reg VAR10 ;
reg VAR18 ;
reg VAR21 ;
reg... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/logicblock_counter.v | 1,779 | module MODULE1(VAR4, VAR2, VAR7, VAR8,
VAR6, VAR3, VAR1, VAR5);
parameter VAR9 = 32;
input VAR4, VAR2;
input VAR7;
input [VAR9-1:0] VAR8;
output [VAR9-1:0] VAR6;
output VAR3;
input VAR1;
input VAR5;
reg [VAR9-1:0] counter;
always @(posedge VAR4 or negedge VAR2)
begin
if (~VAR2)
begin
counter <= 32'h00000000;
end
else
b... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.symbol.v | 1,331 | module MODULE1 (
input VAR6,
input VAR3,
input VAR1,
input VAR7,
output VAR4 ,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
fallen/milkymist-mmu | cores/hpdmc_ddr32/rtl/hpdmc_mgmt.v | 8,893 | module MODULE1 #(
parameter VAR14 = 26,
parameter VAR47 = 9
) (
input VAR13,
input VAR12,
input [2:0] VAR23,
input [2:0] VAR27,
input [10:0] VAR36,
input [3:0] VAR43,
input VAR51,
input VAR11,
input [VAR14-3-1:0] address,
output reg ack,
output reg read,
output reg write,
output [3:0] VAR45,
input VAR5,
input VAR22,
in... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_1.behavioral.v | 1,188 | module MODULE1( VAR6, VAR1, VAR4 );
input VAR4, VAR6;
output VAR1;
VAR3 VAR5(.VAR6(VAR6),.VAR1(VAR1),.VAR4(VAR4));
VAR3 VAR2(.VAR6(VAR6),.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufinv/sky130_fd_sc_lp__bufinv_16.v | 2,050 | module MODULE2 (
VAR1 ,
VAR3 ,
VAR4,
VAR8,
VAR6 ,
VAR2
);
output VAR1 ;
input VAR3 ;
input VAR4;
input VAR8;
input VAR6 ;
input VAR2 ;
VAR5 VAR7 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
supply1 VAR4;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o32a/sky130_fd_sc_hs__o32a.functional.v | 2,080 | module MODULE1 (
VAR4,
VAR14,
VAR3 ,
VAR11 ,
VAR8 ,
VAR10 ,
VAR16 ,
VAR9
);
input VAR4;
input VAR14;
output VAR3 ;
input VAR11 ;
input VAR8 ;
input VAR10 ;
input VAR16 ;
input VAR9 ;
wire VAR16 VAR7 ;
wire VAR16 VAR17 ;
wire VAR1 ;
wire VAR13;
or VAR5 (VAR7 , VAR8, VAR11, VAR10 );
or VAR12 (VAR17 , VAR9, VAR16 );
and V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21bo/sky130_fd_sc_ms__a21bo.blackbox.v | 1,383 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR5 ,
VAR3
);
output VAR6 ;
input VAR7 ;
input VAR5 ;
input VAR3;
supply1 VAR2;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
yipenghuang0302/csee4840_14 | software/peripheral/synthesis/submodules/altera_avalon_st_clock_crosser.v | 5,029 | module MODULE1(
VAR29,
VAR15,
VAR21,
VAR8,
VAR31,
VAR7,
VAR9,
VAR27,
VAR19,
VAR13
);
parameter VAR18 = 1;
parameter VAR6 = 8;
parameter VAR23 = 2;
parameter VAR17 = 2;
parameter VAR24 = 1;
localparam VAR28 = VAR18 * VAR6;
input VAR29;
input VAR15;
output VAR21;
input VAR8;
input [VAR28-1:0] VAR31;
input VAR7;
input VAR... | mit |
asicguy/gplgpu | hdl/lucy_tc/de3d_tc_mc_sigs.v | 10,601 | module MODULE1
(
input VAR22, input VAR1, input VAR35, input [3:0] VAR30, input VAR4, input VAR17, input [3:0] VAR19, input [8:0] VAR13, input [8:0] VAR27, input [8:0] VAR23, input [8:0] VAR2, input [8:0] VAR12, input [8:0] VAR34, input [8:0] VAR37, input [8:0] VAR28, input [2:0] VAR14, input [3:0] VAR15,
output reg VA... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3/ddr3_int_example_top_5.v | 7,205 | module MODULE1 (
VAR14,
VAR20,
VAR22,
VAR71,
VAR4,
VAR30,
VAR33,
VAR53,
VAR65,
VAR32,
VAR19,
VAR50,
VAR67,
VAR47,
VAR18,
VAR28,
VAR44,
VAR10,
VAR46,
VAR54,
VAR56
)
;
output [ 13: 0] VAR22;
output [ 2: 0] VAR71;
output VAR4;
output [ 0: 0] VAR30;
inout [ 0: 0] VAR33;
inout [ 0: 0] VAR53;
output [ 0: 0] VAR65;
output [ 3... | gpl-3.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/up_hdmi_rx.v | 10,614 | module MODULE1 (
VAR28,
VAR50,
VAR69,
VAR1,
VAR5,
VAR54,
VAR34,
VAR21,
VAR4,
VAR49,
VAR60,
VAR29,
VAR64,
VAR61,
VAR53,
VAR70,
VAR39,
VAR24,
VAR44,
VAR71,
VAR35,
VAR59,
VAR38,
VAR7,
VAR58,
VAR22,
VAR36,
VAR25);
localparam VAR62 = 32'h00040063;
parameter VAR14 = 0;
input VAR28;
output VAR50;
output VAR69;
output VAR1;
ou... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_2.v | 2,440 | module MODULE1 (
VAR8,
VAR1 ,
VAR7 ,
VAR5 ,
VAR10 ,
VAR2 ,
VAR3 ,
VAR9
);
input VAR8;
input VAR1 ;
input VAR7 ;
output VAR5 ;
input VAR10 ;
input VAR2 ;
input VAR3 ;
input VAR9 ;
VAR6 VAR4 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2b/sky130_fd_sc_ls__nand2b_2.v | 2,147 | module MODULE2 (
VAR9 ,
VAR5 ,
VAR6 ,
VAR8,
VAR2,
VAR7 ,
VAR1
);
output VAR9 ;
input VAR5 ;
input VAR6 ;
input VAR8;
input VAR2;
input VAR7 ;
input VAR1 ;
VAR3 VAR4 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR9 ,
VAR5,
VAR6
);
output VAR9 ... | apache-2.0 |
hitomi2500/wasca | fpga_firmware/wasca/synthesis/submodules/wasca_nios2_gen2_0_cpu_debug_slave_wrapper.v | 9,389 | module MODULE1 (
VAR57,
VAR38,
clk,
VAR35,
VAR55,
VAR21,
VAR9,
VAR14,
VAR25,
VAR24,
VAR50,
VAR41,
VAR3,
VAR7,
VAR32,
VAR56,
VAR45,
VAR26,
VAR4,
VAR44,
VAR37,
VAR43,
VAR11,
VAR12,
VAR16,
VAR8,
VAR40,
VAR17,
VAR22,
VAR34,
VAR18,
VAR46,
VAR42
)
;
output [ 37: 0] VAR37;
output VAR43;
output VAR11;
output VAR12;
output VAR1... | gpl-2.0 |
lkesteloot/alice | alice4/fpga/Alice4-DE0-Nano-SoC/LCD_debug.v | 1,888 | module MODULE1(
input wire [6:0] VAR13,
input wire [5:0] VAR7,
input wire [31:0] VAR4,
input wire [31:0] VAR12,
input wire [31:0] VAR9,
output reg [6:0] VAR3
);
reg [31:0] VAR2;
reg [3:0] VAR5;
wire [6:0] VAR6;
VAR10 VAR8(
.VAR11(VAR5),
.VAR6(VAR6)
);
reg VAR1;
always @ begin
case (VAR13)
7'd0: { VAR1, VAR5 } = { 1'b1,... | apache-2.0 |
archlabo/Frix | fpga/nexys4/rtl/clock/clk_wiz_0_clk_wiz.v | 7,238 | module MODULE1
( input VAR43,
output VAR44,
output VAR19,
output VAR11
);
VAR37 VAR18
(.VAR78 (VAR7),
.VAR76 (VAR43));
wire [15:0] VAR65;
wire VAR10;
wire VAR79;
wire VAR74;
wire VAR50;
wire VAR33;
wire VAR32;
wire VAR2;
wire VAR53;
wire VAR81;
wire VAR45;
wire VAR39;
wire VAR42;
wire VAR16;
wire VAR12;
wire VAR83;
wir... | bsd-2-clause |
praveendath92/DDR2_Interface_Xilinx_XUPV5 | source/mig_36_1.v | 27,213 | module MODULE1 #
(
parameter VAR114 = 2,
parameter VAR76 = 1,
parameter VAR117 = 2,
parameter VAR43 = 10,
parameter VAR51 = 1,
parameter VAR134 = 1,
parameter VAR66 = 0,
parameter VAR38 = 8,
parameter VAR68 = 64,
parameter VAR80 = 8,
parameter VAR75 = 8,
parameter VAR9 = 6,
parameter VAR86 = 3,
parameter VAR105 = 1,
pa... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrbp/sky130_fd_sc_ms__dlrbp.symbol.v | 1,456 | module MODULE1 (
input VAR1 ,
output VAR5 ,
output VAR9 ,
input VAR8,
input VAR2
);
supply1 VAR6;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
TonyBrewer/OpenHT | ht_lib/platform/convey/verilog/HtResetFlop1x.v | 1,167 | module MODULE1 (
input VAR9,
input VAR12,
input VAR7,
output VAR1
);
reg VAR3;
always @(posedge VAR9) begin
if (VAR7)
VAR3 <= 1'b1;
end
else
VAR3 <= 1'b0;
end
VAR6 rst (.VAR11(VAR9), .VAR2(VAR7), .VAR5(VAR3), .VAR10(!VAR3), .VAR8(VAR3));
reg VAR4;
always @(posedge VAR12) begin
VAR4 <= VAR3;
end
assign VAR1 = VAR4;
reg ... | bsd-3-clause |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_068.v | 1,532 | module MODULE1 (
VAR2,
VAR9
);
input [31:0] VAR2;
output [31:0]
VAR9;
wire [31:0]
VAR11,
VAR6,
VAR8,
VAR10,
VAR12,
VAR1,
VAR13,
VAR4,
VAR14;
assign VAR11 = VAR2;
assign VAR10 = VAR11 << 7;
assign VAR13 = VAR1 - VAR12;
assign VAR1 = VAR11 << 14;
assign VAR14 = VAR13 + VAR4;
assign VAR12 = VAR8 - VAR10;
assign VAR6 = VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41a/sky130_fd_sc_ms__o41a_1.v | 2,411 | module MODULE2 (
VAR3 ,
VAR1 ,
VAR9 ,
VAR6 ,
VAR12 ,
VAR7 ,
VAR10,
VAR11,
VAR8 ,
VAR2
);
output VAR3 ;
input VAR1 ;
input VAR9 ;
input VAR6 ;
input VAR12 ;
input VAR7 ;
input VAR10;
input VAR11;
input VAR8 ;
input VAR2 ;
VAR5 VAR4 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR10(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4b/sky130_fd_sc_hd__and4b.behavioral.pp.v | 1,988 | module MODULE1 (
VAR1 ,
VAR16 ,
VAR15 ,
VAR2 ,
VAR11 ,
VAR7,
VAR4,
VAR3 ,
VAR9
);
output VAR1 ;
input VAR16 ;
input VAR15 ;
input VAR2 ;
input VAR11 ;
input VAR7;
input VAR4;
input VAR3 ;
input VAR9 ;
wire VAR8 ;
wire VAR5 ;
wire VAR10;
not VAR14 (VAR8 , VAR16 );
and VAR6 (VAR5 , VAR8, VAR15, VAR2, VAR11 );
VAR17 VAR12... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvn/sky130_fd_sc_hs__einvn.behavioral.v | 1,766 | module MODULE1 (
VAR1 ,
VAR6,
VAR4 ,
VAR11,
VAR8
);
input VAR1 ;
input VAR6;
output VAR4 ;
input VAR11;
input VAR8;
wire VAR3 ;
wire VAR2;
VAR10 VAR5 (VAR3 , VAR1, VAR11, VAR8 );
VAR10 VAR7 (VAR2, VAR6, VAR11, VAR8 );
notif0 VAR9 (VAR4 , VAR3, VAR2);
endmodule | apache-2.0 |
myriadrf/A2300 | hdl/wca/WcaReadFifo32W8R.v | 1,943 | module MODULE1(
input wire reset,
input wire VAR17, input wire VAR16, input wire [31:0] in,
output wire VAR1, output wire VAR10,
input wire [11:0] VAR4, inout wire [7:0] VAR6
);
parameter VAR7 = 0;
wire [7:0] dout;
wire VAR9 = (VAR7 == VAR4[11:4]);
assign VAR6 = ( VAR9 & VAR4[3] ) ? dout : 8'VAR12;
VAR3 VAR13(
.rst(res... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3/sky130_fd_sc_ms__and3_2.v | 2,164 | module MODULE2 (
VAR4 ,
VAR7 ,
VAR2 ,
VAR8 ,
VAR1,
VAR5,
VAR10 ,
VAR3
);
output VAR4 ;
input VAR7 ;
input VAR2 ;
input VAR8 ;
input VAR1;
input VAR5;
input VAR10 ;
input VAR3 ;
VAR6 VAR9 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
HarmonInstruments/verilog | uart/uart.v | 3,444 | module MODULE1
(
input VAR3, input VAR21, input [1:0] VAR14, input [31:0] VAR18, output reg [31:0] rd = 0, inout VAR2 );
reg [3:0] VAR12 = 0;
reg [6:0] VAR17 = 0;
reg [6:0] VAR16 = 0;
reg [6:0] VAR9 = 100; reg VAR6 = 1;
reg VAR19 = 0;
reg VAR13 = 0;
reg [5:0] VAR7 = 0; reg [6:0] VAR1 = 0;
reg [6:0] VAR8 = 0;
reg [38:0]... | gpl-3.0 |
megari/sd2snes | verilog/sd2snes_gsu/dcm.v | 2,986 | module MODULE1 (
input VAR36,
output VAR10,
output VAR32,
input VAR38,
output[7:0] VAR24
);
VAR3 #(
.VAR2("VAR14"), .VAR37(2.0), .VAR40(5), .VAR18(18), .VAR12("VAR13"), .VAR6(41.667), .VAR16("VAR21"), .VAR35("VAR21"), .VAR33("VAR22"), .VAR9("VAR7"), .VAR8("VAR7"), .VAR26("VAR17"), .VAR41(16'hFFFF), .VAR28(0), .VAR39("V... | gpl-2.0 |
revaldinho/opc | opc1/opccpu.v | 2,615 | module MODULE1( inout[7:0] VAR31, output[10:0] address, output VAR15, input clk, input VAR8);
parameter VAR27=0, VAR13=1, VAR28=2, VAR34=3, VAR7=4 ;
parameter VAR32=5'VAR33, VAR25=5'VAR35, VAR29=5'VAR5, VAR10=5'VAR20;
parameter VAR9=5'b01001, VAR24=5'b11000, VAR3=5'b01000;
parameter VAR22=5'b11001, VAR14=5'b11010, VAR6... | gpl-3.0 |
timtian090/Playground | UVM/UVMPlayground/Lab3/Lab3-Project/TF_EECS301_Lab3_TopLevel.v | 2,513 | module MODULE1();
localparam VAR1 = 50000000; localparam VAR3 = ((1.0 / VAR1) * 1000000000.0) / 2.0;
reg VAR2;
begin
begin | mit |
nikhilghanathe/HLS-for-EMTF | verilog/sp_ptlut_address.v | 14,164 | module MODULE1 (
VAR112,
VAR91,
VAR80,
VAR27,
VAR5,
VAR6,
VAR21,
VAR45,
VAR120,
VAR22,
VAR114,
VAR105,
VAR64,
VAR116,
VAR30,
VAR24,
VAR58,
VAR46,
VAR55,
VAR15,
VAR77,
VAR40,
VAR89,
VAR79,
VAR115,
VAR121,
VAR90,
VAR73,
VAR93,
VAR109,
VAR44,
VAR100,
VAR47,
VAR48,
VAR35,
VAR11,
VAR1,
VAR28,
VAR107,
VAR74,
VAR110,
VAR61,
V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso0n/sky130_fd_sc_hdll__inputiso0n.pp.blackbox.v | 1,397 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR4,
VAR5 ,
VAR3 ,
VAR1 ,
VAR6
);
output VAR7 ;
input VAR2 ;
input VAR4;
input VAR5 ;
input VAR3 ;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_add.v | 5,879 | module MODULE1 (
clk,
VAR31,
VAR9,
VAR18,
VAR1,
VAR20,
VAR30,
VAR29);
parameter VAR4 = 16;
parameter VAR21 = VAR4 - 1;
input clk;
input [24:0] VAR31;
input [24:0] VAR9;
input [24:0] VAR18;
input [24:0] VAR1;
output [ 7:0] VAR20;
input [VAR21:0] VAR30;
output [VAR21:0] VAR29;
reg [VAR21:0] VAR11 = 'd0;
reg [24:0] VAR15 ... | mit |
CospanDesign/nysa-sdio-device | rtl/sdio_device_stack.v | 6,097 | module MODULE1 (
input clk,
input rst,
output VAR3,
input VAR22,
inout VAR16,
inout [3:0] VAR18
);
wire [3:0] VAR30;
wire VAR2;
wire VAR12;
wire VAR19;
wire [3:0] VAR13;
wire [3:0] VAR29;
wire VAR5;
wire VAR7;
wire VAR26;
wire VAR10;
wire VAR32;
wire VAR25;
wire VAR31;
wire [5:0] VAR23;
wire [31:0] VAR33;
wire [127:0] ... | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/neek/backend/rtl/verilog/ddr_ctrl_ip/alt_mem_ddrx_ecc_decoder_32_syn.v | 32,582 | module MODULE1
(
VAR27,
VAR8) ;
input [5:0] VAR27;
output [63:0] VAR8;
tri0 [5:0] VAR27;
wire [5:0] VAR71;
wire [63:0] VAR28;
wire [63:0] VAR86;
wire [3:0] VAR111;
wire [3:0] VAR16;
wire [3:0] VAR47;
wire [3:0] VAR66;
wire [3:0] VAR113;
wire [3:0] VAR56;
wire [3:0] VAR2;
wire [3:0] VAR48;
wire [3:0] VAR78;
wire [3:0] V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311a/sky130_fd_sc_ls__o311a_1.v | 2,422 | module MODULE2 (
VAR9 ,
VAR6 ,
VAR7 ,
VAR5 ,
VAR4 ,
VAR12 ,
VAR11,
VAR1,
VAR8 ,
VAR2
);
output VAR9 ;
input VAR6 ;
input VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR12 ;
input VAR11;
input VAR1;
input VAR8 ;
input VAR2 ;
VAR10 VAR3 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR12(VAR12),
.VAR11(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2b/sky130_fd_sc_hd__or2b.behavioral.v | 1,442 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR9
);
output VAR5 ;
input VAR10 ;
input VAR9;
supply1 VAR8;
supply0 VAR12;
supply1 VAR2 ;
supply0 VAR6 ;
wire VAR4 ;
wire VAR7;
not VAR3 (VAR4 , VAR9 );
or VAR11 (VAR7, VAR4, VAR10 );
buf VAR1 (VAR5 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21o/sky130_fd_sc_hdll__a21o.symbol.v | 1,349 | module MODULE1 (
input VAR3,
input VAR1,
input VAR4,
output VAR5
);
supply1 VAR6;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/DOUBLE/FSM_Add_Subtract_syn.v | 5,547 | module MODULE1 ( clk, rst, VAR148, VAR158, VAR48,
VAR55, VAR112, VAR16, VAR22, VAR25,
VAR167, VAR128, VAR168, VAR159, VAR153, VAR69,
VAR175, VAR8, VAR81, VAR88, VAR100, VAR140,
VAR161, VAR97, VAR121, ready );
output [1:0] VAR100;
input clk, rst, VAR148, VAR158, VAR48, VAR55,
VAR112, VAR16;
output VAR22, VAR25, VAR167, ... | gpl-3.0 |
ElegantLin/My-CPU | Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/id.v | 30,092 | module MODULE1(
input wire rst,
input wire[VAR40] VAR26,
input wire[VAR60] VAR15,
input wire[VAR51] VAR10,
input wire VAR52,
input wire[VAR59] VAR28,
input wire[VAR27] VAR58,
input wire VAR7,
input wire[VAR59] VAR45,
input wire[VAR27] VAR25,
input wire[VAR59] VAR24,
input wire[VAR59] VAR17,
input wire VAR5,
output reg ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s4s/sky130_fd_sc_hd__dlymetal6s4s.functional.pp.v | 1,868 | module MODULE1 (
VAR8 ,
VAR11 ,
VAR12,
VAR2,
VAR9 ,
VAR5
);
output VAR8 ;
input VAR11 ;
input VAR12;
input VAR2;
input VAR9 ;
input VAR5 ;
wire VAR3 ;
wire VAR1;
buf VAR7 (VAR3 , VAR11 );
VAR6 VAR10 (VAR1, VAR3, VAR12, VAR2);
buf VAR4 (VAR8 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211oi/sky130_fd_sc_hd__a211oi.functional.pp.v | 2,044 | module MODULE1 (
VAR6 ,
VAR13 ,
VAR10 ,
VAR11 ,
VAR16 ,
VAR5,
VAR14,
VAR1 ,
VAR9
);
output VAR6 ;
input VAR13 ;
input VAR10 ;
input VAR11 ;
input VAR16 ;
input VAR5;
input VAR14;
input VAR1 ;
input VAR9 ;
wire VAR2 ;
wire VAR17 ;
wire VAR4;
and VAR12 (VAR2 , VAR13, VAR10 );
nor VAR7 (VAR17 , VAR2, VAR11, VAR16 );
VAR8 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbp/sky130_fd_sc_hs__sdfbbp.blackbox.v | 1,496 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR3 ,
VAR2 ,
VAR7 ,
VAR8 ,
VAR1 ,
VAR4
);
output VAR9 ;
output VAR6 ;
input VAR3 ;
input VAR2 ;
input VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR4;
supply1 VAR10;
supply0 VAR5;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21o/sky130_fd_sc_ms__a21o.pp.blackbox.v | 1,351 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR2 ,
VAR5 ,
VAR8,
VAR1,
VAR4 ,
VAR3
);
output VAR7 ;
input VAR6 ;
input VAR2 ;
input VAR5 ;
input VAR8;
input VAR1;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_098.v | 1,421 | module MODULE1 (
VAR8,
VAR7
);
input [31:0] VAR8;
output [31:0]
VAR7;
wire [31:0]
VAR11,
VAR9,
VAR1,
VAR4,
VAR12,
VAR5,
VAR2;
assign VAR11 = VAR8;
assign VAR1 = VAR9 - VAR11;
assign VAR9 = VAR11 << 2;
assign VAR12 = VAR4 - VAR1;
assign VAR4 = VAR11 << 6;
assign VAR2 = VAR5 - VAR1;
assign VAR5 = VAR12 << 7;
assign VAR7 ... | mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_crossbar_v2_1/9368eebf/hdl/verilog/axi_crossbar_v2_1_wdata_mux.v | 6,881 | module MODULE1 #
(
parameter VAR37 = "none", parameter integer VAR14 = 1, parameter integer VAR43 = 1, parameter integer VAR47 = 1, parameter integer VAR8 = 0 )
(
input wire VAR4,
input wire VAR1,
input wire [VAR43*VAR14-1:0] VAR17,
input wire [VAR43-1:0] VAR19,
input wire [VAR43-1:0] VAR27,
output wire [VAR43-1:0] VAR... | mit |
jamesbowman/swapforth | j1a/icestorm/j4a.v | 20,129 | module MODULE2(
output [1:0] VAR45,
input VAR99, VAR67, VAR29,
input [10:0] VAR149,
input VAR158, VAR100, VAR121,
input [10:0] VAR147,
input [1:0] VAR75, VAR115
);
parameter VAR127 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR102 = 256'h000000000000000000000000000000000000000000... | bsd-3-clause |
olajep/oh | src/adi/hdl/library/axi_dmac/request_generator.v | 7,507 | module MODULE1 #(
parameter VAR10 = 3,
parameter VAR18 = 17)(
input clk,
input VAR4,
output [VAR10-1:0] VAR16,
input [VAR10-1:0] VAR9,
input VAR33,
input [VAR10+3-1:0] VAR15,
output VAR8,
output VAR35,
output reg VAR1 = 1'b0,
output VAR37,
output [1:0] VAR20,
input VAR36,
output reg VAR26,
input [VAR18-1:0] VAR13,
inpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311o/sky130_fd_sc_ms__a311o.functional.pp.v | 2,064 | module MODULE1 (
VAR2 ,
VAR10 ,
VAR15 ,
VAR13 ,
VAR11 ,
VAR8 ,
VAR7,
VAR14,
VAR4 ,
VAR17
);
output VAR2 ;
input VAR10 ;
input VAR15 ;
input VAR13 ;
input VAR11 ;
input VAR8 ;
input VAR7;
input VAR14;
input VAR4 ;
input VAR17 ;
wire VAR16 ;
wire VAR9 ;
wire VAR1;
and VAR18 (VAR16 , VAR13, VAR10, VAR15 );
or VAR6 (VAR9 ,... | apache-2.0 |
walkthetalk/fsref | ip/axis_window/src/axis_window.v | 3,658 | module MODULE1 #
(
parameter integer VAR34 = 8,
parameter integer VAR29 = 12,
parameter integer VAR26 = 12
)
(
input wire clk,
input wire VAR16,
input wire [VAR29-1 : 0] VAR15,
input wire [VAR26-1 : 0] VAR36,
input wire [VAR29-1 : 0] VAR39,
input wire [VAR26-1 : 0] VAR11,
input wire VAR19,
input wire [VAR34-1:0] VAR13,... | gpl-3.0 |
seyedmaysamlavasani/GorillaPP | apps/multiProtocolNpu/build/synthesis/asic/FreePDK45/osu_soc/ref_design/Synthesis/cla16.v | 2,632 | module MODULE2(sum, VAR24, VAR12);
output [16:0] sum;
input [15:0] VAR24,VAR12;
wire [14:0] VAR29;
wire [15:0] VAR22, VAR14;
wire [4:0] VAR32, VAR34;
VAR5 VAR26(sum[0], VAR22[0], VAR14[0], VAR24[0], VAR12[0], 1'b0);
VAR5 VAR17(sum[1], VAR22[1], VAR14[1], VAR24[1], VAR12[1], VAR29[0]);
VAR5 VAR25(sum[2], VAR22[2], VAR14... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4/sky130_fd_sc_hd__or4.behavioral.v | 1,382 | module MODULE1 (
VAR6,
VAR12,
VAR4,
VAR9,
VAR2
);
output VAR6;
input VAR12;
input VAR4;
input VAR9;
input VAR2;
supply1 VAR10;
supply0 VAR11;
supply1 VAR8 ;
supply0 VAR7 ;
wire VAR1;
or VAR3 (VAR1, VAR2, VAR9, VAR4, VAR12 );
buf VAR5 (VAR6 , VAR1 );
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/16-way_2-tree/src/ip_dram/phy/mig_7series_v2_3_poc_meta.v | 11,937 | module MODULE1 #
(parameter VAR9 = 0,
parameter VAR73 = 100,
parameter VAR33 = 7,
parameter VAR3 = 112)
(
VAR60, VAR39, VAR10,
rst, clk, VAR71, VAR8, VAR24, VAR66,
VAR28, VAR57, VAR43,
VAR64, VAR14, VAR16, VAR2,
VAR37, VAR52, VAR59
);
localparam VAR36 = VAR3/4;
function [VAR33-1:0] VAR45 (input [VAR33-1:0] VAR1,
input ... | mit |
cr88192/bgbtech_bjx1core | bjx1core32/GpReg.v | 6,054 | parameter[5:0] VAR4 = 6'h00;
parameter[5:0] VAR48 = 6'h0F;
parameter[5:0] VAR2 = 6'h20;
parameter[5:0] VAR25 = 6'h2F;
parameter[5:0] VAR1 = 6'h30;
parameter[5:0] VAR52 = 6'h3F;
parameter[6:0] VAR29 = 7'h00;
parameter[6:0] VAR34 = 7'h0F;
parameter[6:0] VAR23 = 7'h20;
parameter[6:0] VAR12 = 7'h2F;
parameter[6:0] VAR5 = 7... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_clk_wiz_0_0/zynq_1_clk_wiz_0_0.v | 3,862 | module MODULE1
(
input VAR4,
output VAR1
);
VAR3 VAR2
(
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule | mit |
masson2013/heterogeneous_hthreads | src/hardware/XilinxProcessorIP/pcores/opb_ps2_dual_ref_v1_00_a/hdl/verilog/ps2_reg.v | 14,028 | module MODULE1(
VAR46, VAR61,
VAR28, VAR42, VAR29, VAR58, VAR73, VAR51, VAR17, VAR14, VAR43, VAR16, VAR30,
VAR48, VAR62, VAR40, VAR8, VAR12, VAR66, VAR32, VAR45, VAR49, VAR13,
VAR50, VAR55
);
input VAR46; input VAR61;
input [0:7] VAR28; input [0:7] VAR42; input VAR29; input VAR58; output [0:7] VAR73; output VAR51; outp... | bsd-3-clause |
kristianpaul/milkyminer | boards/milkymist-one/rtl/system.v | 5,363 | module MODULE1(
input VAR32,
input VAR34,
output VAR47,
output VAR1,
output VAR59
);
parameter VAR38 = VAR48;
parameter VAR38 = 5;
localparam [5:0] VAR52 = (6'd1 << VAR38);
localparam [31:0] VAR35 = (32'd1 << (7 - VAR38)) + 32'd1;
reg [255:0] state = 0;
reg [511:0] VAR57 = 0;
reg [31:0] VAR20 = 32'h00000000;
wire VAR39... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2/sky130_fd_sc_hs__mux2.blackbox.v | 1,233 | module MODULE1 (
VAR2 ,
VAR6,
VAR3,
VAR5
);
output VAR2 ;
input VAR6;
input VAR3;
input VAR5 ;
supply1 VAR4;
supply0 VAR1;
endmodule | apache-2.0 |
devinacker/sd2snes | verilog/sd2snes/msu.v | 5,243 | module MODULE1(
input VAR30,
input enable,
input [13:0] VAR14,
input [7:0] VAR28,
input VAR12,
input [2:0] VAR44,
input [7:0] VAR19,
output [7:0] VAR5,
input VAR32,
input VAR18,
input VAR15,
output [7:0] VAR45,
output [7:0] VAR17,
output VAR39,
output [31:0] VAR23,
output [15:0] VAR13,
input [5:0] VAR7,
input [5:0] VAR... | gpl-2.0 |
calee0219/Course | DLAB/Lab08/LCD.v | 3,842 | module MODULE1(
input clk,
input rst,
input [127:0] VAR6,
input [127:0] VAR2,
output VAR9,
output VAR8,
output VAR7,
output [3:0] VAR3
);
reg [23:0] VAR5 = 0;
reg VAR4;
reg [5:0] VAR1;
assign {VAR9, VAR8, VAR7, VAR3} = {VAR4, VAR1};
always@(posedge clk, posedge rst)
begin
if(rst) VAR5 <= VAR5;
end
else VAR5 <= (VAR5[23... | mit |
ptracton/wb_soc_template | behvioral/wb_master/wb_master_model.v | 16,209 | module MODULE1(clk, rst, VAR2, din, dout, VAR6, VAR5, sel, VAR3, ack, VAR1, VAR4);
input clk, rst;
output [31:0] VAR2;
input [31:0] din;
output [31:0] dout;
output VAR6, VAR5;
output [3:0] sel;
output VAR3;
input ack, VAR1, VAR4;
parameter VAR7 = 4096;
reg [31:0] VAR2;
reg [31:0] dout;
reg VAR6, VAR5;
reg [3:0] sel;
re... | mit |
shailcoolboy/Warp-Trinity | PlatformSupport/CustomPeripherals/pcores/clock_board_config_v1_04_a/hdl/verilog/clock_board_config.v | 27,610 | module MODULE1 (
VAR43,
VAR25,
VAR55,
VAR63,
VAR37,
VAR54,
VAR30,
VAR51,
VAR36,
VAR73,
VAR26
);
parameter VAR23 = 120000000;
parameter VAR62 = 16'h1Aff;
parameter VAR4 = 16'h1Aff;
parameter VAR12 = 16'h01ff; parameter VAR18 = 16'h1eff; parameter VAR19 = 16'h1eff; parameter VAR47 = 16'h01ff;
parameter VAR3 = 16'h0BFF;
p... | bsd-2-clause |
rkrajnc/minimig-mist | rtl/minimig/agnus_bitplanedma.v | 18,154 | module MODULE1 (
input wire clk, input wire VAR41, input wire reset, input wire VAR67,
input wire VAR54, input wire VAR1, input wire VAR4, input wire VAR8, input wire VAR35, input wire [ 11-1:0] VAR29, input wire [ 9-1:0] VAR34, output wire VAR47, input wire [ 9-1:1] VAR2, output reg [ 9-1:1] VAR20, input wire [ 16-1:0... | gpl-3.0 |
danbone/core | riscv_core_fdi.v | 1,500 | module MODULE2 (
clk,
VAR13,
VAR24,
VAR8,
VAR34,
VAR30,
VAR12,
VAR28,
VAR32,
VAR43,
VAR20
);
reg [31:0] VAR10;
assign VAR24 = VAR10;
always @ (*) begin
if (VAR14) begin
VAR36 = VAR10;
end
else if (VAR35) begin
VAR36 = VAR23;
end
else begin
VAR36 = VAR10 + 4;
end
end
assign VAR44 = (VAR42 == VAR40) ? VAR37 : VAR22;
assi... | mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/acl_fp_asin_s5.v | 1,184 | module MODULE1 (
enable,
VAR3,
VAR6,
VAR9);
input enable;
input VAR3;
input [31:0] VAR6;
output [31:0] VAR9;
wire [31:0] VAR7;
wire [31:0] VAR9 = VAR7[31:0];
VAR4 VAR1 (
.en (enable),
.VAR5(1'b0),
.clk(VAR3),
.VAR2(VAR6),
.VAR8(VAR7));
endmodule | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/megafunctions/pci2net_dma_16x32_bb.v | 5,985 | module MODULE1 (
VAR1,
VAR6,
VAR10,
VAR2,
VAR5,
VAR7,
VAR3,
VAR4,
VAR9,
VAR8);
input VAR1;
input VAR6;
input [31:0] VAR10;
input VAR2;
input VAR5;
output VAR7;
output VAR3;
output VAR4;
output [31:0] VAR9;
output [3:0] VAR8;
endmodule | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/prcfg/bist/prcfg_dac.v | 7,423 | module MODULE1(
clk,
VAR4,
VAR17,
VAR15,
VAR2,
VAR8,
VAR11,
VAR14,
VAR1,
VAR9,
VAR19
);
localparam VAR12 = 8'hA1;
parameter VAR16 = 0;
input clk;
input [31:0] VAR4;
output [31:0] VAR17;
output VAR15;
input [31:0] VAR2;
input VAR8;
input VAR11;
input VAR14;
output [31:0] VAR1;
output VAR9;
output VAR19;
reg VAR9 = 0;
re... | gpl-3.0 |
amrmorsey/Digital-Design-Project | sbox5.v | 3,542 | module MODULE1(
VAR2,
VAR1
);
input [6:1] VAR2;
output reg [4:1] VAR1;
wire [6:1] VAR3;
assign VAR3 = {VAR2[6], VAR2[1], VAR2[5 : 2]};
always @(VAR3)
begin
case (VAR3)
6'b000000: VAR1 <= 4'd2;
6'b000001: VAR1 <= 4'd12;
6'b000010: VAR1 <= 4'd4;
6'b000011: VAR1 <= 4'd1;
6'b000100: VAR1 <= 4'd7;
6'b000101: VAR1 <= 4'd10;
... | gpl-2.0 |
chahuja/hilbert-fpga | fft32.v | 2,099 | module MODULE1( VAR19 ,VAR20 ,VAR3 ,VAR17 ,VAR23 ,VAR13 ,VAR1 ,VAR15 ,VAR4, VAR22 );
parameter VAR6 = 32;
input VAR19;
input VAR20;
input VAR3;
input VAR17;
input VAR22;
input [VAR6-1:0] VAR23;
input [VAR6-1:0] VAR13;
output reg VAR1;
output [VAR6-1:0] VAR15;
output [VAR6-1:0] VAR4;
wire [VAR6-1:0] VAR24;
wire [VAR6-1:... | gpl-2.0 |
khldragon/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_BYTE_Alignment.v | 9,498 | module MODULE1(
input clk,
input enable, input [7:0] VAR8,
output reg VAR4,
output reg [7:0] VAR11
);
reg [7:0] VAR5; reg [7:0] VAR6; reg [7:0] VAR1; reg [2:0] VAR3; reg VAR10; reg [7:0] VAR7; reg [2:0] VAR12;
reg [7:0] VAR9;
reg [7:0] VAR2;
always @(negedge clk) begin
if (!enable)begin
VAR9 <= 8'h00; end
else
begin
ca... | bsd-2-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9144/axi_ad9144.v | 10,664 | module MODULE1 (
VAR20,
VAR100,
VAR105,
VAR33,
VAR107,
VAR76,
VAR72,
VAR114,
VAR7,
VAR89,
VAR62,
VAR41,
VAR91,
VAR68,
VAR78,
VAR92,
VAR25,
VAR65,
VAR51,
VAR2,
VAR35,
VAR27,
VAR56,
VAR60,
VAR70,
VAR23,
VAR73,
VAR80,
VAR111,
VAR17,
VAR40,
VAR79,
VAR84,
VAR37,
VAR6,
VAR29,
VAR28,
VAR113);
parameter VAR8 = 0;
parameter VAR... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_1.behavioral.pp.v | 2,576 | module MODULE1( VAR7, VAR5, VAR6, VAR9, VAR8, VAR4 );
input VAR5, VAR7, VAR6;
inout VAR8, VAR4;
output VAR9;
VAR2 VAR1(.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR9(VAR9),.VAR8(VAR8),.VAR4(VAR4));
VAR2 VAR3(.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR9(VAR9),.VAR8(VAR8),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3/sky130_fd_sc_hs__and3.symbol.v | 1,238 | module MODULE1 (
input VAR5,
input VAR3,
input VAR4,
output VAR6
);
supply1 VAR2;
supply0 VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4bb/sky130_fd_sc_hs__and4bb_2.v | 2,196 | module MODULE2 (
VAR7 ,
VAR1 ,
VAR2 ,
VAR3 ,
VAR5 ,
VAR4,
VAR6
);
output VAR7 ;
input VAR1 ;
input VAR2 ;
input VAR3 ;
input VAR5 ;
input VAR4;
input VAR6;
VAR9 VAR8 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR7 ,
VAR1,
VAR2,
VAR3 ,
VAR5
)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ebufn/sky130_fd_sc_hd__ebufn.functional.pp.v | 1,870 | module MODULE1 (
VAR1 ,
VAR11 ,
VAR12,
VAR3,
VAR13,
VAR6 ,
VAR4
);
output VAR1 ;
input VAR11 ;
input VAR12;
input VAR3;
input VAR13;
input VAR6 ;
input VAR4 ;
wire VAR2 ;
wire VAR7;
VAR8 VAR5 (VAR2 , VAR11, VAR3, VAR13 );
VAR8 VAR10 (VAR7, VAR12, VAR3, VAR13 );
bufif0 VAR9 (VAR1 , VAR2, VAR7);
endmodule | apache-2.0 |
ThomasLee969/verilog-homework | exp2/sequence_detector_fsm/sequence_detector_fsm.v | 1,237 | module MODULE1(VAR7, state, reset, VAR1, clk);
output VAR7;
output reg [2:0] state;
input reset, VAR1, clk;
parameter VAR9 = 1'b1,
VAR3 = 1'b0;
parameter VAR11 = 3'd0,
VAR13 = 3'd1,
VAR12 = 3'd2,
VAR4 = 3'd3,
VAR2 = 3'd4,
VAR8 = 3'd5,
VAR5 = 3'd6;
reg VAR10;
reg [2:0] VAR6;
always @(posedge clk or posedge reset) begin
... | mit |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/store_pkt.v | 12,019 | module MODULE1
parameter VAR1 = 64,
parameter VAR2=VAR1/8,
parameter VAR17 = 5,
parameter VAR23 = 13,
parameter VAR19 = 11,
parameter VAR11 = VAR19-VAR4(VAR2),
parameter VAR15 = 6,
parameter VAR45 = VAR4(VAR17)
)
( VAR56,
VAR37,
VAR47,
VAR59,
VAR36,
VAR30,
VAR39,
VAR24,
VAR55,
VAR9,
VAR60,
VAR29,
VAR5,
VAR52,
VAR61,
VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2b/sky130_fd_sc_ms__and2b.functional.v | 1,356 | module MODULE1 (
VAR4 ,
VAR2,
VAR3
);
output VAR4 ;
input VAR2;
input VAR3 ;
wire VAR8 ;
wire VAR1;
not VAR6 (VAR8 , VAR2 );
and VAR5 (VAR1, VAR8, VAR3 );
buf VAR7 (VAR4 , VAR1 );
endmodule | apache-2.0 |
justinzhf/MIPS-CPU | SwapUnit.v | 1,051 | module MODULE1(VAR1,VAR3,rd,VAR5,VAR7,VAR8,VAR6,VAR4,VAR2,rst);
input[4:0] VAR1,VAR3,rd,VAR7,VAR8;
input VAR5,VAR6;
output[1:0] VAR2,VAR4;
reg[1:0] VAR4,VAR2;
input rst;
always @(VAR1 or VAR3 or rd or VAR5 or VAR7 or VAR8 or VAR6 or VAR4 or VAR2 or rst) begin
if (rst) begin
VAR4<=0;
VAR2<=0;
end
else begin
if(VAR6 && (... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | processor/regfile.v | 1,845 | module MODULE1(VAR2, VAR3, VAR7, VAR1, VAR5, clk);
parameter VAR6 = 8; parameter VAR4 = 8;
output [VAR4-1:0] VAR2;
input [VAR4-1:0] VAR3;
input clk;
input VAR5;
input [VAR6-1:0] VAR7, VAR1;
reg [VAR4-1:0] VAR2; reg [VAR6-1:0] MODULE1 [VAR4-1:0];
always @(posedge clk)
begin
if(VAR5)
begin
MODULE1[VAR7] <= VAR3;
end
else... | mit |
klaNath/synth1 | sine.v | 1,932 | module MODULE1 (
VAR22,
VAR25
);
input wire [20:0] VAR22;
output wire [15:0] VAR25;
wire [8:0] VAR1;
wire [9:0] VAR7;
wire [15:0] VAR24;
wire [15:0] VAR4;
wire [25:0] VAR19;
wire [15:0] VAR11;
wire [15:0] VAR3;
function [8:0] VAR14;
input [8:0] VAR8;
input sel;
begin
case(sel)
0 : VAR14 = VAR8;
1 : VAR14 = 9'VAR20 - VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvpwrvgnd/sky130_fd_sc_ms__tapvpwrvgnd.behavioral.v | 1,163 | module MODULE1 ();
supply1 VAR3;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbp/sky130_fd_sc_ms__dlxbp.functional.v | 1,640 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR1 ,
VAR9
);
output VAR2 ;
output VAR3 ;
input VAR1 ;
input VAR9;
wire VAR8;
VAR6 VAR5 VAR4 (VAR8 , VAR1, VAR9 );
buf VAR10 (VAR2 , VAR8 );
not VAR7 (VAR3 , VAR8 );
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_csc_1.v | 4,244 | module MODULE1 (
clk,
sync,
VAR21,
VAR8,
VAR11,
VAR2,
VAR12,
VAR19,
VAR28);
parameter VAR4 = 16;
localparam VAR23 = VAR4 - 1;
input clk;
input [VAR23:0] sync;
input [23:0] VAR21;
input [16:0] VAR8;
input [16:0] VAR11;
input [16:0] VAR2;
input [24:0] VAR12;
output [VAR23:0] VAR19;
output [ 7:0] VAR28;
wire [24:0] VAR27;... | gpl-3.0 |
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