repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
asicguy/gplgpu | hdl/altera_clk_synth/clk_gen_ipll.v | 2,950 | module MODULE1
(
input VAR3,
input VAR12,
input VAR1,
input [1:0] VAR5,
input VAR17,
input VAR10, input [3:0] VAR21, input [2:0] VAR9, input [8:0] VAR8, input VAR16, input VAR2,
output VAR18, output VAR7,
output VAR6,
output reg VAR20,
output VAR4
);
VAR11 VAR13
(
.VAR3 (VAR3),
.VAR22 (VAR12),
.VAR1 (VAR1),
.VAR16 (VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ha/sky130_fd_sc_ms__ha_1.v | 2,184 | module MODULE2 (
VAR3,
VAR1 ,
VAR6 ,
VAR7 ,
VAR10,
VAR5,
VAR8 ,
VAR9
);
output VAR3;
output VAR1 ;
input VAR6 ;
input VAR7 ;
input VAR10;
input VAR5;
input VAR8 ;
input VAR9 ;
VAR2 VAR4 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(VAR9)
);
endmodule
module MODULE2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s18/sky130_fd_sc_hd__clkdlybuf4s18.blackbox.v | 1,322 | module MODULE1 (
VAR1,
VAR6
);
output VAR1;
input VAR6;
supply1 VAR3;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_dff_reset.v | 4,356 | if (VAR2 && VAR13==VAR5) \
begin: VAR8 \
VAR6 VAR11(.VAR7 \
,.VAR1 \
,.VAR15(~VAR12) \
,.VAR3); \
end
module MODULE1 #(VAR13=-1, VAR2=1)
(input VAR14
,input VAR12
,input [VAR13-1:0] VAR1
,output [VAR13-1:0] VAR3
);
else VAR4(89)
else VAR4(88)
else VAR4(87)
else VAR4(86)
else VAR4(85)
else VAR4(84)
else VAR4(83)
else VA... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/fillcap/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.behavioral.v | 1,027 | module MODULE1( );
VAR3 VAR1();
VAR3 VAR2(); | apache-2.0 |
ptracton/pmodacl2 | rtl/spi_regs.v | 4,516 | module MODULE1 (
VAR16, VAR8, VAR3, VAR19, VAR18, VAR9, VAR4,
VAR20, VAR22, VAR15, VAR24,
clk, reset, VAR14, VAR6, VAR25, VAR17, VAR11,
VAR2
) ;
parameter VAR5 = 8'h00;
input clk;
input reset;
output reg [15:0] VAR16;
input wire [7:0] VAR14;
input wire [7:0] VAR6;
output reg [7:0] VAR8;
input VAR25;
input VAR17;
input ... | mit |
jotego/jt51 | syn/xilinx/ym09/hdl/fsm_control.v | 3,536 | module MODULE1 #(parameter VAR4=10)(
input clk,
input rst,
input VAR25,
output reg VAR12,
output [VAR4-1:0] VAR23,
output reg VAR21,
input VAR1,
input VAR9,
output reg VAR13,
output reg VAR3,
output reg [7:0] VAR14
);
reg [ 1:0] VAR17; reg VAR20,
VAR6,
VAR11,
VAR10,
VAR18;
reg [VAR4-1:0] VAR5,
VAR7;
always @(negedge cl... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311ai/sky130_fd_sc_hd__o311ai_0.v | 2,435 | module MODULE1 (
VAR10 ,
VAR11 ,
VAR4 ,
VAR8 ,
VAR6 ,
VAR1 ,
VAR12,
VAR5,
VAR9 ,
VAR7
);
output VAR10 ;
input VAR11 ;
input VAR4 ;
input VAR8 ;
input VAR6 ;
input VAR1 ;
input VAR12;
input VAR5;
input VAR9 ;
input VAR7 ;
VAR2 VAR3 (
.VAR10(VAR10),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR1... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_tx_v1_00_a/hdl/verilog/axi_hdmi_tx.v | 11,285 | module MODULE1 (
VAR87,
VAR119,
VAR143,
VAR18,
VAR52,
VAR109,
VAR136,
VAR26,
VAR102,
VAR51,
VAR135,
VAR91,
VAR125,
VAR166,
VAR108,
VAR68,
VAR149,
VAR48,
VAR12,
VAR116,
VAR31,
VAR5,
VAR55,
VAR162,
VAR36,
VAR64,
VAR95,
VAR90,
VAR85,
VAR24,
VAR104,
VAR4,
VAR75,
VAR15,
VAR60,
VAR122,
VAR130,
VAR43,
VAR113,
VAR111,
VAR145,
... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v | 1,828 | module MODULE1 #(parameter VAR29(VAR16)
,parameter VAR5 = VAR20(VAR16)
,parameter VAR29(VAR25 )
,parameter VAR11=0
,parameter VAR19 = VAR25>>3
,parameter VAR4=0
)
( input VAR1
,input VAR15
,input VAR7
,input VAR9
,input [VAR5-1:0] VAR33
,input [VAR10(VAR25, 1):0] VAR22
,input [VAR10(VAR19, 1):0] VAR13
,output logic [VA... | bsd-3-clause |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/acl_fp_custom_mul_op.v | 13,912 | module MODULE1 (
VAR24, VAR52,
VAR4, VAR13, VAR6,
VAR54, VAR68, VAR10,
VAR5,
VAR41,
VAR46,
VAR40, VAR64, VAR66, VAR28,
enable);
parameter VAR61 = 1;
parameter VAR21 = 0;
parameter VAR70 = 1;
parameter VAR15 = 1;
parameter VAR75 = 1;
input VAR24, VAR52;
input [26:0] VAR4;
input [8:0] VAR13;
input VAR6;
input [26:0] VAR5... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probe_p/sky130_fd_sc_hd__probe_p_8.v | 2,055 | module MODULE2 (
VAR8 ,
VAR1 ,
VAR3,
VAR7 ,
VAR4 ,
VAR2
);
output VAR8 ;
input VAR1 ;
input VAR3;
input VAR7 ;
input VAR4 ;
input VAR2;
VAR5 VAR6 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR8,
VAR1
);
output VAR8;
input VAR1;
supply0 VAR3;
supply0 VAR7... | apache-2.0 |
8l/soc | backends/small1/hw/rtl/icache.v | 6,856 | module MODULE1(input clk,
input reset,
input [31:0] VAR25,
input VAR21,
output reg VAR23,
output reg [31:0] VAR20,
input [31:0] VAR24, input VAR18, output reg VAR13, output reg [31:0] VAR14 );
always @(posedge clk)
begin
VAR14 <= VAR25;
VAR13 <= VAR21;
VAR20 <= VAR24;
VAR23 <= VAR18;
end
endmodule
module MODULE1(input ... | mit |
hcabrera-/lancetfish | RTL/processing_element/des_engine/verif/sink.v | 1,520 | module MODULE1 #(parameter VAR4 = 5)
(
input wire clk,
input wire VAR2,
input wire [0:63] VAR1
);
integer VAR3;
begin | gpl-3.0 |
bluespec/Flute | builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkNear_Mem_IO_AXI4.v | 107,587 | module MODULE1(VAR222,
VAR272,
VAR194,
VAR178,
VAR151,
VAR119,
VAR170,
VAR97,
VAR221,
VAR326,
VAR267,
VAR251,
VAR67,
VAR159,
VAR261,
VAR10,
VAR239,
VAR126,
VAR145,
VAR49,
VAR54,
VAR332,
VAR285,
VAR113,
VAR34,
VAR205,
VAR132,
VAR9,
VAR291,
VAR41,
VAR45,
VAR227,
VAR268,
VAR116,
VAR105,
VAR35,
VAR182,
VAR206,
VAR186,
VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fah/sky130_fd_sc_hd__fah.functional.v | 1,648 | module MODULE1 (
VAR7,
VAR1 ,
VAR16 ,
VAR3 ,
VAR14
);
output VAR7;
output VAR1 ;
input VAR16 ;
input VAR3 ;
input VAR14 ;
wire VAR17;
wire VAR12 ;
wire VAR13 ;
wire VAR8 ;
wire VAR6;
xor VAR11 (VAR17, VAR16, VAR3, VAR14 );
buf VAR10 (VAR1 , VAR17 );
and VAR9 (VAR12 , VAR16, VAR3 );
and VAR5 (VAR13 , VAR16, VAR14 );
and... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/edfxtp/sky130_fd_sc_hd__edfxtp_1.v | 2,277 | module MODULE2 (
VAR6 ,
VAR8 ,
VAR3 ,
VAR10 ,
VAR4,
VAR2,
VAR5 ,
VAR1
);
output VAR6 ;
input VAR8 ;
input VAR3 ;
input VAR10 ;
input VAR4;
input VAR2;
input VAR5 ;
input VAR1 ;
VAR7 VAR9 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfrtp/sky130_fd_sc_hdll__dfrtp.pp.blackbox.v | 1,375 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR1 ,
VAR2,
VAR7 ,
VAR5 ,
VAR4 ,
VAR6
);
output VAR8 ;
input VAR3 ;
input VAR1 ;
input VAR2;
input VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR6 ;
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/shd_fifo_stub.v | 1,420 | module MODULE1(rst, VAR2, VAR5, din, VAR3, VAR1, dout, VAR6, VAR4)
;
input rst;
input VAR2;
input VAR5;
input [127:0]din;
input VAR3;
input VAR1;
output [127:0]dout;
output VAR6;
output VAR4;
endmodule | gpl-3.0 |
olofk/oh | elink/hdl/etx_cfg.v | 5,667 | module MODULE1 (
VAR20, VAR5, VAR22, VAR34, VAR17,
VAR13, VAR23, VAR3,
reset, clk, VAR27, VAR31, VAR32, VAR16, VAR9
);
parameter VAR6 = 104;
parameter VAR4 = 6;
parameter VAR7 = 16'h0000;
input reset;
input clk;
input VAR27;
input VAR31;
input [VAR4+1:0] VAR32; input [31:0] VAR16; output [31:0] VAR20;
output VAR5; outp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfstp/sky130_fd_sc_ls__dfstp_1.v | 2,273 | module MODULE2 (
VAR3 ,
VAR7 ,
VAR2 ,
VAR5,
VAR8 ,
VAR6 ,
VAR10 ,
VAR4
);
output VAR3 ;
input VAR7 ;
input VAR2 ;
input VAR5;
input VAR8 ;
input VAR6 ;
input VAR10 ;
input VAR4 ;
VAR1 VAR9 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR4(VAR4)
);
endmodule
module MODU... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/3b549dcc377eab42/zynq_design_1_system_ila_0_0_stub.v | 2,491 | module MODULE1(clk, VAR7, VAR11,
VAR14, VAR3, VAR10, VAR15,
VAR4, VAR18, VAR16, VAR2,
VAR12, VAR5, VAR8, VAR1,
VAR9, VAR6, VAR13, VAR17)
;
input clk;
input [8:0]VAR7;
input VAR11;
input VAR14;
input [31:0]VAR3;
input [3:0]VAR10;
input VAR15;
input VAR4;
input [1:0]VAR18;
input VAR16;
input VAR2;
input [8:0]VAR12;
input... | mit |
tanelikaivola/blinkenlichten | fpga/ws2812b.v | 2,821 | module MODULE1(
input VAR26,
input [VAR3-1:0] VAR32,
input VAR5, input VAR7,
input VAR14,
output reg VAR19,
output reg[2:0] VAR13,
output [7:0] VAR43
);
parameter VAR3 = 8*32;
localparam VAR37 = 3'd0,
VAR9 = 3'd1, VAR23 = 3'd2,
VAR17 = 3'd3,
VAR22 = 3'd4,
VAR41 = 3'd6;
localparam VAR36 = 4000,
VAR34 = 2500, VAR33 = 17,... | mit |
boylansr/Prop_Muse | P1V/P8X32A_Emulation/P8X32A_DE0_Nano/cog_ram.v | 1,181 | module MODULE1
(
input clk,
input VAR3,
input VAR1,
input [8:0] VAR2,
input [31:0] VAR5,
output reg [31:0] VAR4
);
reg [511:0] [31:0] VAR6;
always @(posedge clk)
begin
if (VAR3 && VAR1)
VAR6[VAR2] <= VAR5;
if (VAR3)
VAR4 <= VAR6[VAR2];
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtp/sky130_fd_sc_ls__sdfrtp_1.v | 2,583 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR12 ,
VAR4 ,
VAR7 ,
VAR1,
VAR6 ,
VAR10 ,
VAR5 ,
VAR11
);
output VAR2 ;
input VAR8 ;
input VAR12 ;
input VAR4 ;
input VAR7 ;
input VAR1;
input VAR6 ;
input VAR10 ;
input VAR5 ;
input VAR11 ;
VAR3 VAR9 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR12(VAR12),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221ai/sky130_fd_sc_hdll__o221ai.behavioral.v | 1,696 | module MODULE1 (
VAR7 ,
VAR3,
VAR11,
VAR5,
VAR6,
VAR13
);
output VAR7 ;
input VAR3;
input VAR11;
input VAR5;
input VAR6;
input VAR13;
supply1 VAR10;
supply0 VAR17;
supply1 VAR15 ;
supply0 VAR14 ;
wire VAR9 ;
wire VAR8 ;
wire VAR1;
or VAR2 (VAR9 , VAR6, VAR5 );
or VAR4 (VAR8 , VAR11, VAR3 );
nand VAR12 (VAR1, VAR8, VAR9... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fahcon/sky130_fd_sc_ms__fahcon_1.v | 2,412 | module MODULE1 (
VAR4,
VAR7 ,
VAR2 ,
VAR5 ,
VAR10 ,
VAR1 ,
VAR9 ,
VAR11 ,
VAR6
);
output VAR4;
output VAR7 ;
input VAR2 ;
input VAR5 ;
input VAR10 ;
input VAR1 ;
input VAR9 ;
input VAR11 ;
input VAR6 ;
VAR3 VAR8 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR11(VAR11)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd1/sky130_fd_sc_ls__dlygate4sd1.behavioral.pp.v | 1,832 | module MODULE1 (
VAR12 ,
VAR4 ,
VAR3,
VAR11,
VAR7 ,
VAR10
);
output VAR12 ;
input VAR4 ;
input VAR3;
input VAR11;
input VAR7 ;
input VAR10 ;
wire VAR5 ;
wire VAR9;
buf VAR6 (VAR5 , VAR4 );
VAR8 VAR1 (VAR9, VAR5, VAR3, VAR11);
buf VAR2 (VAR12 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3/sky130_fd_sc_hs__nor3_4.v | 2,071 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR1 ,
VAR7 ,
VAR2,
VAR6
);
output VAR3 ;
input VAR5 ;
input VAR1 ;
input VAR7 ;
input VAR2;
input VAR6;
VAR8 VAR4 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR3,
VAR5,
VAR1,
VAR7
);
output VAR3;
input VAR5;
input VAR1;
in... | apache-2.0 |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/ps2_tx.v | 3,733 | module MODULE1
(
input wire clk, reset,
input wire VAR7,
input wire [7:0] din,
inout wire VAR11, VAR28,
output reg VAR1, VAR13
);
localparam [2:0]
VAR10 = 3'b000,
VAR29 = 3'b001,
VAR8 = 3'b010,
VAR14 = 3'b011,
VAR6 = 3'b100;
reg [2:0] VAR26, VAR15;
reg [7:0] VAR19;
wire [7:0] VAR22;
reg VAR20;
wire VAR5;
reg [3:0] VAR1... | mit |
nishtahir/arty-blaze | src/bd/system/ip/system_auto_us_1/synth/system_auto_us_1.v | 9,757 | module MODULE1 (
VAR48,
VAR101,
VAR18,
VAR7,
VAR20,
VAR58,
VAR81,
VAR30,
VAR63,
VAR26,
VAR42,
VAR10,
VAR90,
VAR57,
VAR33,
VAR76,
VAR11,
VAR59,
VAR47,
VAR43,
VAR89,
VAR23,
VAR32,
VAR45,
VAR88,
VAR4,
VAR12,
VAR72,
VAR100,
VAR35,
VAR25,
VAR92,
VAR17,
VAR87
);
input wire VAR48;
input wire VAR101;
input wire [31 : 0] VAR18;... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/top/mem_buf.v | 52,585 | module MODULE1 (
clk ,
VAR224 ,
VAR27 ,
VAR257 ,
VAR215 ,
VAR186 ,
VAR164 ,
VAR188 ,
VAR170 ,
VAR258 ,
VAR193 ,
VAR150 ,
VAR243 ,
VAR251 ,
VAR71 ,
VAR198 ,
VAR248 ,
VAR245 ,
VAR199 ,
VAR67 ,
VAR44 ,
VAR203 ,
VAR135 ,
VAR240 ,
VAR76 ,
VAR108 ,
VAR66 ,
VAR238 ,
VAR46 ,
VAR54 ,
VAR152 ,
VAR38 ,
VAR113 ,
VAR206 ,
VAR106 ,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill/sky130_fd_sc_ls__fill_4.v | 1,840 | module MODULE1 (
VAR1,
VAR3,
VAR5 ,
VAR4
);
input VAR1;
input VAR3;
input VAR5 ;
input VAR4 ;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODULE1 ();
supply1 VAR1;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR4 ;
VAR6 VAR2 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxtp/sky130_fd_sc_ls__dlxtp.functional.pp.v | 1,656 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR4,
VAR2,
VAR7,
VAR6 ,
VAR10
);
output VAR5 ;
input VAR3 ;
input VAR4;
input VAR2;
input VAR7;
input VAR6 ;
input VAR10 ;
wire VAR1;
VAR9 VAR8 (VAR1 , VAR3, VAR4, , VAR2, VAR7);
buf VAR11 (VAR5 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a222oi/sky130_fd_sc_hd__a222oi.blackbox.v | 1,427 | module MODULE1 (
VAR9 ,
VAR2,
VAR5,
VAR3,
VAR7,
VAR4,
VAR6
);
output VAR9 ;
input VAR2;
input VAR5;
input VAR3;
input VAR7;
input VAR4;
input VAR6;
supply1 VAR1;
supply0 VAR10;
supply1 VAR11 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_rxeq_scan.v | 14,873 | module MODULE1 #
(
parameter VAR34 = "VAR32", parameter VAR21 = "VAR40", parameter VAR17 = 1, parameter VAR36 = 22'd3125000, parameter VAR28 = 22'd2083333 )
(
input VAR38,
input VAR18,
input [ 1:0] VAR42,
input [ 2:0] VAR50,
input VAR12,
input [ 3:0] VAR5,
input [17:0] VAR11,
input VAR29,
input [ 5:0] VAR2,
input [ 5:0... | gpl-3.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/Computer_System/synthesis/submodules/altera_up_video_clipper_drop.v | 8,657 | module MODULE1 (
clk,
reset,
VAR33,
VAR24,
VAR30,
VAR43,
VAR19,
VAR22,
VAR31,
VAR5,
VAR12,
VAR34,
VAR27,
VAR36
);
parameter VAR16 = 15; parameter VAR7 = 0;
parameter VAR25 = 640; parameter VAR23 = 480; parameter VAR14 = 9; parameter VAR11 = 8;
parameter VAR17 = 0;
parameter VAR39 = 0;
parameter VAR8 = 0;
parameter VAR4... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_pwrgood_pp_pg_s/sky130_fd_sc_hdll__udp_pwrgood_pp_pg_s.symbol.v | 1,368 | module MODULE1 (
input VAR5 ,
output VAR4,
input VAR2 ,
input VAR3 ,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.v | 2,395 | module MODULE1 (
VAR5 ,
VAR11,
VAR1,
VAR3 ,
VAR7 ,
VAR10,
VAR2,
VAR9 ,
VAR6
);
output VAR5 ;
input VAR11;
input VAR1;
input VAR3 ;
input VAR7 ;
input VAR10;
input VAR2;
input VAR9 ;
input VAR6 ;
VAR4 VAR8 (
.VAR5(VAR5),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6... | apache-2.0 |
superibk/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/sdhc/rtl/verilog/nandc_hamm.v | 5,266 | module MODULE1 (
input wire [31:0] VAR10,
input wire [6:0] VAR5,
output wire [23:0] VAR7
);
wire [31:0] VAR19 = VAR10;
wire [7:0] VAR2 = ^VAR19;
assign VAR7[0] = VAR19[0] ^ VAR19[2] ^ VAR19[4] ^ VAR19[6] ^ VAR19[8] ^ VAR19[10] ^ VAR19[12] ^ VAR19[14] ^ VAR19[16] ^ VAR19[18] ^ VAR19[20] ^ VAR19[22] ^ VAR19[24] ^ VAR19[2... | apache-2.0 |
asicguy/gplgpu | hdl/vga/crt_op_stage.v | 5,693 | module MODULE1
(
input VAR11,
input VAR18, input VAR29, input VAR4, input VAR27, input VAR20, input VAR16, input VAR19, input VAR5, input VAR24, input hde, input VAR12, input VAR35, input VAR26,
input VAR33,
input VAR6,
output VAR37, output VAR17,
output VAR8, output VAR21, output VAR23,
output VAR14
);
reg VAR15;
reg ... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_p0_fr_cycle_extender.v | 3,111 | module MODULE1(
clk,
VAR11,
VAR12,
VAR8,
VAR10
);
parameter VAR5 = "";
parameter VAR1 = "false";
localparam VAR2 = 2;
localparam VAR15 = 2;
localparam VAR7 = VAR5*VAR2;
input clk;
input VAR11;
input [1:0] VAR12;
input [VAR7-1:0] VAR8;
output [VAR7-1:0] VAR10;
reg [VAR7-1:0] VAR14 [VAR15-1:0] ;
generate
genvar VAR16;
fo... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22ai/sky130_fd_sc_ms__o22ai_4.v | 2,352 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR4 ,
VAR6 ,
VAR8 ,
VAR3,
VAR10,
VAR5 ,
VAR9
);
output VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR6 ;
input VAR8 ;
input VAR3;
input VAR10;
input VAR5 ;
input VAR9 ;
VAR2 VAR11 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2.behavioral.v | 1,759 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR3,
VAR5
);
output VAR7 ;
input VAR1 ;
input VAR3;
input VAR5;
wire VAR2 ;
wire VAR9;
not VAR8 (VAR2 , VAR1 );
VAR10 VAR4 (VAR9, VAR2, VAR3, VAR5);
buf VAR6 (VAR7 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s.blackbox.v | 1,324 | module MODULE1 (
VAR2,
VAR4
);
output VAR2;
input VAR4;
supply1 VAR6;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/acl_multireadport_mem.v | 16,949 | module MODULE3
parameter VAR34=10,
parameter VAR14=32,
parameter VAR50=13, parameter VAR147=1,
parameter VAR131=0
)
(
input clk,
input VAR8,
input VAR57,
input [VAR34-1:0] VAR59,
input [VAR14-1:0] VAR58,
input VAR82,
input VAR48,
output VAR144,
output VAR136,
output [VAR14-1:0] VAR126,
input [VAR50*VAR34-1:0] VAR39,
in... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/diode/sky130_fd_sc_ls__diode.pp.blackbox.v | 1,226 | module MODULE1 (
VAR2,
VAR5 ,
VAR1 ,
VAR4 ,
VAR3
);
input VAR2;
input VAR5 ;
input VAR1 ;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtp/sky130_fd_sc_ls__sdfrtp.behavioral.pp.v | 2,884 | module MODULE1 (
VAR25 ,
VAR19 ,
VAR29 ,
VAR18 ,
VAR30 ,
VAR12,
VAR1 ,
VAR14 ,
VAR11 ,
VAR21
);
output VAR25 ;
input VAR19 ;
input VAR29 ;
input VAR18 ;
input VAR30 ;
input VAR12;
input VAR1 ;
input VAR14 ;
input VAR11 ;
input VAR21 ;
wire VAR15 ;
wire VAR10 ;
wire VAR5 ;
reg VAR17 ;
wire VAR26 ;
wire VAR6 ;
wire VAR27... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31a/sky130_fd_sc_hd__o31a.behavioral.pp.v | 2,015 | module MODULE1 (
VAR9 ,
VAR14 ,
VAR16 ,
VAR4 ,
VAR5 ,
VAR8,
VAR13,
VAR1 ,
VAR2
);
output VAR9 ;
input VAR14 ;
input VAR16 ;
input VAR4 ;
input VAR5 ;
input VAR8;
input VAR13;
input VAR1 ;
input VAR2 ;
wire VAR15 ;
wire VAR17 ;
wire VAR12;
or VAR11 (VAR15 , VAR16, VAR14, VAR4 );
and VAR6 (VAR17 , VAR15, VAR5 );
VAR10 VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fah/sky130_fd_sc_ms__fah.behavioral.pp.v | 2,616 | module MODULE1 (
VAR12,
VAR5 ,
VAR19 ,
VAR21 ,
VAR25 ,
VAR7,
VAR17,
VAR8 ,
VAR16
);
output VAR12;
output VAR5 ;
input VAR19 ;
input VAR21 ;
input VAR25 ;
input VAR7;
input VAR17;
input VAR8 ;
input VAR16 ;
wire VAR3 ;
wire VAR11 ;
wire VAR1 ;
wire VAR18 ;
wire VAR6 ;
wire VAR14 ;
wire VAR26;
xor VAR22 (VAR3 , VAR19, VA... | apache-2.0 |
trun/fpgaboy | src/gb/video_converter.v | 3,457 | module MODULE1 (
input wire reset,
input wire VAR40,
input wire [1:0] VAR33,
input wire VAR16, input wire VAR23, input wire VAR42,
input wire VAR11,
output wire [23:0] VAR9,
output wire VAR39,
output wire VAR44
);
parameter VAR8 = 10'd160;
parameter VAR43 = 10'd144;
reg VAR12;
wire[14:0] VAR7;
wire[1:0] VAR3;
wire[14:0... | mit |
smithe0/GestureControlInterface | DE2Component_FLASH/db/ip/niosII_system/submodules/niosII_system_nios2_qsys_0_jtag_debug_module_tck.v | 8,572 | module MODULE1 (
VAR5,
VAR1,
VAR19,
VAR18,
VAR30,
VAR3,
VAR7,
VAR10,
VAR17,
VAR20,
VAR2,
VAR13,
VAR4,
VAR27,
VAR24,
VAR40,
VAR36,
VAR25,
VAR21,
VAR26,
VAR38,
VAR15,
VAR39,
VAR12,
VAR23,
VAR14,
VAR32,
VAR16,
VAR9,
VAR11,
VAR28
)
;
output [ 1: 0] VAR32;
output VAR16;
output [ 37: 0] VAR9;
output VAR11;
output VAR28;
inpu... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_1.functional.pp.v | 1,190 | module MODULE1( VAR10, VAR8, VAR3, VAR4, VAR12, VAR5 );
input VAR8, VAR3;
inout VAR12, VAR5;
output VAR10, VAR4;
and VAR16( VAR10, VAR8, VAR3 );
wire VAR2;
not VAR13( VAR2, VAR3 );
wire VAR9;
and VAR11( VAR9, VAR2, VAR8 );
wire VAR6;
not VAR1( VAR6, VAR8 );
wire VAR7;
and VAR15( VAR7, VAR6, VAR3 );
or VAR14( VAR4, VAR9... | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/verilog/FIFO_image_filter_src1_data_stream_1_V.v | 3,990 | module MODULE1
VAR27 = "VAR14",
VAR22 = 8,
VAR18 = 15,
VAR24 = 20000
)
(
input wire clk,
input wire reset,
output wire VAR7,
input wire VAR2,
input wire VAR1,
input wire [VAR22-1:0] VAR8,
output wire VAR12,
input wire VAR26,
input wire VAR13,
output wire [VAR22-1:0] VAR23
);
reg [VAR22-1:0] VAR16[0:VAR24-1];
reg [VAR22... | gpl-3.0 |
borti4938/sd2snes | verilog/sd2snes_sa1/ipcore_dir/sa1_mult.v | 9,820 | module MODULE1 (
clk, VAR105, VAR19, VAR90
);
input clk;
output [31 : 0] VAR105;
input [15 : 0] VAR19;
input [15 : 0] VAR90;
wire \VAR70/VAR62 ;
wire \VAR70/VAR11 ;
wire \VAR70/VAR44 ;
wire \VAR70/VAR76 ;
wire \VAR70/VAR33 ;
wire \VAR70/VAR23 ;
wire \VAR70/VAR59 ;
wire \VAR70/VAR29 ;
wire \VAR70/VAR1 ;
wire \VAR70/VAR2... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ba/sky130_fd_sc_hd__o21ba.functional.pp.v | 2,037 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR3 ,
VAR1,
VAR11,
VAR10,
VAR2 ,
VAR5
);
output VAR6 ;
input VAR7 ;
input VAR3 ;
input VAR1;
input VAR11;
input VAR10;
input VAR2 ;
input VAR5 ;
wire VAR13 ;
wire VAR8 ;
wire VAR14;
nor VAR16 (VAR13 , VAR7, VAR3 );
nor VAR4 (VAR8 , VAR1, VAR13 );
VAR15 VAR9 (VAR14, VAR8, VAR11, VAR10);
b... | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_020.v | 1,475 | module MODULE1 (
VAR9,
VAR3
);
input [31:0] VAR9;
output [31:0]
VAR3;
wire [31:0]
VAR2,
VAR6,
VAR13,
VAR12,
VAR1,
VAR11,
VAR8,
VAR4;
assign VAR2 = VAR9;
assign VAR11 = VAR13 << 5;
assign VAR4 = VAR8 << 1;
assign VAR6 = VAR2 << 2;
assign VAR13 = VAR2 + VAR6;
assign VAR8 = VAR1 - VAR11;
assign VAR1 = VAR12 - VAR13;
assig... | mit |
eda-globetrotter/PicenoDecoders | zhiyang_and_andrew/syncommschannel.v | 11,761 | module MODULE1();
wire VAR32; wire [1:0] VAR33; wire [1:0] VAR18; wire VAR25; wire [1:0] VAR2;
reg VAR13[0:255];
reg VAR35;
reg [7:0] VAR3;
reg VAR16;
reg VAR21;
reg [7:0] VAR17;
reg [1:0] VAR5;
reg [7:0] VAR14;
wire [1:0] VAR27;
wire [1:0] VAR6;
reg VAR30;
reg [7:0] VAR26;
reg [1:0] VAR4;
reg [1:0] VAR20;
reg VAR24;
r... | mit |
hoglet67/CoPro6502 | src/amber23/a23_barrel_shift.v | 16,320 | module MODULE1 (
input [31:0] VAR14,
input VAR7,
input [7:0] VAR3, input VAR6, input [1:0] VAR4,
output [31:0] VAR8,
output VAR9
);
wire [32:0] VAR5;
wire [32:0] VAR10;
wire [32:0] VAR12;
wire [32:0] VAR15;
assign VAR5 = VAR6 ? {VAR7, VAR14 } :
VAR3 == 8'VAR2 0 ? {VAR7, VAR14 } : VAR3 == 8'VAR2 1 ? {VAR14[31], VAR14[30... | gpl-3.0 |
manu3193/ControladorElevadorTDD | VerificadorSentidoMovimiento.v | 3,849 | module MODULE1(
clk,
VAR2,
VAR6,
VAR4,
VAR14,
VAR15,
VAR13,
VAR7,
VAR16,
VAR5,
VAR9,
VAR12,
VAR17,
VAR10
);
input [2:0] VAR6;
input [1:0] VAR4, VAR14, VAR15, VAR13, VAR7;
input clk, VAR2;
output reg [1:0] VAR16;
always @(posedge clk)
begin
if (VAR6 == 3'b000)
begin
if (VAR4 == 2'VAR11) VAR16 <= 2'b00;
if (VAR4 == 2'VAR... | mit |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/sha256_dsp48e1.v | 9,358 | module MODULE2 (
input clk,
input [511:0] VAR151,
input [255:0] VAR66,
output reg [255:0] VAR119,
output [31:0] VAR165
);
localparam VAR95 = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/triple_speed_ethernet-library/altera_tse_pcs_pma.v | 12,261 | module MODULE1 (
address,
clk,
VAR94,
VAR83,
VAR19,
VAR79,
VAR2,
VAR75,
VAR57,
VAR56,
read,
VAR20,
reset,
VAR72,
VAR99,
VAR38,
write,
VAR26,
VAR81,
VAR11,
VAR16,
VAR104,
VAR58,
VAR32,
VAR96,
VAR95,
VAR64,
VAR7,
VAR43,
VAR29,
VAR9,
VAR34,
VAR54,
VAR93,
VAR51,
VAR40,
VAR53,
VAR36,
VAR47,
VAR17,
VAR85,
VAR86,
VAR76,
VAR35... | mit |
ashish-17/x86_decoder | register_file.v | 1,197 | module MODULE1(
input VAR11,
input VAR5,
input[4:0] VAR6,
output[31:0] VAR2,
input[4:0] VAR10,
output[31:0] VAR1,
input[4:0] VAR3,
input[31:0] VAR12);
reg[31:0] VAR8[VAR7-1:0];
reg[31:0] VAR4[1:0];
assign VAR2 = VAR4[0];
assign VAR1 = VAR4[1];
integer VAR9; | gpl-3.0 |
vvk/sysrek | martix_multiplier/ipcore_dir/sum.v | 43,152 | module MODULE2 (
clk, VAR107, VAR89, VAR343
);
input clk;
output [26 : 0] VAR107;
input [25 : 0] VAR89;
input [25 : 0] VAR343;
wire \VAR70/VAR307 ;
wire \VAR70/VAR436 ;
wire \VAR70/VAR234 ;
wire \VAR70/VAR74 ;
wire \VAR70/VAR132 ;
wire \VAR70/VAR308 ;
wire \VAR70/VAR327 ;
wire \VAR70/VAR445 ;
wire \VAR70/VAR19 ;
wire \... | gpl-2.0 |
timtian090/Playground | UVM/UVMPlayground/Lab2/Lab2-Project/CLS_PWM_DutyCycle_Timer.v | 1,962 | module MODULE1
parameter VAR1 = 50000000, parameter VAR6 = 1000, parameter VAR3 = 50 )
(
input VAR4,
output reg VAR5,
input VAR2
);
begin
begin
begin
end
begin | mit |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/bd_mig_7series_0_0_mig.v | 69,873 | module MODULE1 #
(
parameter VAR341 = 1,
parameter VAR239 = 3,
parameter VAR130 = 1,
parameter VAR45 = 10,
parameter VAR95 = 1,
parameter VAR3 = 1,
parameter VAR92 = 1,
parameter VAR427 = 4,
parameter VAR143 = 4,
parameter VAR423 = 8,
parameter VAR367 = 2,
parameter VAR101 = 16,
parameter VAR246 = 2,
parameter VAR351 =... | mit |
fabianz66/cursos-tec | taller-digital/Lab3/laboratorio3/Clock_Divider.v | 1,038 | module MODULE1(input VAR1, input reset, output reg VAR2);
reg [25:0] counter;
begin
begin
begin
end
begin | mit |
mbus/mbus | layer_controller_v3/verilog/rf_ctrl.v | 1,387 | module MODULE1 #(
parameter VAR4 = 256, parameter VAR5 = 24
)
(
input VAR6,
input [VAR5-1:0] VAR7,
input [VAR4-1:0] VAR8,
output [VAR5*VAR4-1:0] VAR2
);
reg [VAR5-1:0] VAR9 [0:VAR4-1];
genvar VAR1;
generate
for (VAR1=0; VAR1<(VAR4); VAR1=VAR1+1)
begin: VAR10
assign VAR2[VAR5*(VAR1+1)-1:VAR5*VAR1] = VAR9[VAR1];
end
for ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfxtp/sky130_fd_sc_hvl__dfxtp.functional.pp.v | 1,897 | module MODULE1 (
VAR8 ,
VAR12 ,
VAR4 ,
VAR1,
VAR2,
VAR9 ,
VAR3
);
output VAR8 ;
input VAR12 ;
input VAR4 ;
input VAR1;
input VAR2;
input VAR9 ;
input VAR3 ;
wire VAR11 ;
wire VAR5;
VAR15 VAR6 VAR10 (VAR11 , VAR4, VAR12, , VAR1, VAR2 );
buf VAR13 (VAR5, VAR11 );
VAR14 VAR7 (VAR8 , VAR5, VAR1, VAR2);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp.behavioral.pp.v | 3,205 | module MODULE1 (
VAR16 ,
VAR2 ,
VAR30 ,
VAR15 ,
VAR17 ,
VAR7 ,
VAR25,
VAR20 ,
VAR31 ,
VAR18 ,
VAR11
);
output VAR16 ;
output VAR2 ;
input VAR30 ;
input VAR15 ;
input VAR17 ;
input VAR7 ;
input VAR25;
input VAR20 ;
input VAR31 ;
input VAR18 ;
input VAR11 ;
wire VAR13 ;
wire VAR26 ;
wire VAR23 ;
reg VAR21 ;
wire VAR36 ;
... | apache-2.0 |
Yarr/Yarr-fw | rtl/kintex7/rx-core/scrambler.v | 1,342 | module MODULE1 #
(
parameter VAR2 = 64
)
(
input [0:(VAR2-1)] VAR3,
output [(VAR2+1):0] VAR4,
input enable,
input [1:0] VAR8,
input clk,
input rst
);
integer VAR7;
reg [((VAR2*2)-7):0] VAR6;
reg [((VAR2*2)-7):0] MODULE1;
reg [0:(VAR2-1)] VAR1 = {VAR2{1'b0}};
reg VAR5;
always @(MODULE1,VAR3)
begin
VAR6 = MODULE1;
for (V... | gpl-3.0 |
UA3MQJ/fpga-synth | modules/note2dds_5st_gen.v | 1,334 | module MODULE1(clk, VAR4, VAR5);
input wire clk;
input wire [6:0] VAR4;
output [31:0] VAR5;
reg [31:0] VAR3;
reg [4:0] VAR2;
wire [3:0] VAR1 = (VAR4 < 12) ? 4'd00 :
(VAR4 < 24) ? 4'd01 :
(VAR4 < 36) ? 4'd02 :
(VAR4 < 48) ? 4'd03 :
(VAR4 < 60) ? 4'd04 :
(VAR4 < 72) ? 4'd05 :
(VAR4 < 84) ? 4'd06 :
(VAR4 < 96) ? 4'd07 :
(... | gpl-3.0 |
neurobiofisica/IntelSBESC2014 | hw/AcqSys.v | 2,316 | module MODULE1(
input VAR26,
input VAR32,
input VAR25,
input [3:0] VAR23,
output [8:0] VAR6,
output [17:0] VAR27,
input VAR20,
input VAR10,
input [0:0] VAR19,
output [0:0] VAR4,
output VAR2,
inout [35:0] VAR29,
inout VAR7
);
VAR1 VAR30 (
.VAR16 (VAR10),
.VAR8 (VAR20),
.VAR31 (VAR2),
.VAR17 (VAR2),
.VAR24 (VAR19[0]),
.V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3/sky130_fd_sc_hs__and3.functional.v | 1,699 | module MODULE1 (
VAR4,
VAR9,
VAR10 ,
VAR5 ,
VAR2 ,
VAR8
);
input VAR4;
input VAR9;
output VAR10 ;
input VAR5 ;
input VAR2 ;
input VAR8 ;
wire VAR1 ;
wire VAR11;
and VAR3 (VAR1 , VAR8, VAR5, VAR2 );
VAR12 VAR6 (VAR11, VAR1, VAR4, VAR9);
buf VAR7 (VAR10 , VAR11 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4b/sky130_fd_sc_lp__nor4b_m.v | 2,299 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR8 ,
VAR11 ,
VAR4 ,
VAR2,
VAR6,
VAR3 ,
VAR10
);
output VAR7 ;
input VAR5 ;
input VAR8 ;
input VAR11 ;
input VAR4 ;
input VAR2;
input VAR6;
input VAR3 ;
input VAR10 ;
VAR9 VAR1 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VA... | apache-2.0 |
sergachev/spi_mem_programmer | spi_cmd.v | 3,398 | module MODULE1(
input clk,
input reset,
input VAR11,
output reg VAR5,
input [8:0] VAR10,
input VAR15,
input [260 * 8 - 1 : 0] VAR12, output reg [7:0] VAR13,
input VAR9,
inout [3:0] VAR6,
output reg VAR16
);
wire [2:0] VAR8 = VAR9 ? 4 : 1;
reg [11:0] VAR4;
reg [3:0] VAR14 = 4'b1111;
reg VAR3;
reg [1:0] state;
assign VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.v | 2,449 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR8 ,
VAR9 ,
VAR11,
VAR6 ,
VAR5 ,
VAR4 ,
VAR7
);
output VAR1 ;
output VAR10 ;
input VAR8 ;
input VAR9 ;
input VAR11;
input VAR6 ;
input VAR5 ;
input VAR4 ;
input VAR7 ;
VAR2 VAR3 (
.VAR1(VAR1),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtp/sky130_fd_sc_lp__dlrtp.behavioral.pp.v | 2,177 | module MODULE1 (
VAR14 ,
VAR18,
VAR7 ,
VAR12 ,
VAR15 ,
VAR20 ,
VAR2 ,
VAR6
);
output VAR14 ;
input VAR18;
input VAR7 ;
input VAR12 ;
input VAR15 ;
input VAR20 ;
input VAR2 ;
input VAR6 ;
wire VAR3 ;
reg VAR10 ;
wire VAR8 ;
wire VAR11 ;
wire VAR9 ;
wire VAR17 ;
wire VAR4;
wire VAR13 ;
not VAR5 (VAR3 , VAR4 );
VAR1 VAR16... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211oi/sky130_fd_sc_hd__a211oi.blackbox.v | 1,368 | module MODULE1 (
VAR5 ,
VAR1,
VAR3,
VAR4,
VAR2
);
output VAR5 ;
input VAR1;
input VAR3;
input VAR4;
input VAR2;
supply1 VAR9;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4/sky130_fd_sc_hd__nand4.blackbox.v | 1,281 | module MODULE1 (
VAR6,
VAR5,
VAR4,
VAR1,
VAR9
);
output VAR6;
input VAR5;
input VAR4;
input VAR1;
input VAR9;
supply1 VAR3;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/inv/sky130_fd_sc_hd__inv_2.v | 1,995 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR2,
VAR6,
VAR1 ,
VAR7
);
output VAR8 ;
input VAR3 ;
input VAR2;
input VAR6;
input VAR1 ;
input VAR7 ;
VAR4 VAR5 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR8,
VAR3
);
output VAR8;
input VAR3;
supply1 VAR2;
supply0 VAR6;... | apache-2.0 |
hoangt/NOCulator | hring/hw/buffered/src/whr_routing_logic.v | 7,144 | module MODULE1
(clk, reset, VAR13, VAR23, VAR16);
parameter VAR19 = 4;
localparam VAR20 = VAR9(VAR19);
parameter VAR5 = 2;
localparam VAR2 = VAR5 * VAR20;
parameter VAR12 = 1;
localparam VAR26 = VAR9(VAR12);
localparam VAR27 = VAR2 + VAR26;
parameter VAR7 = VAR15;
localparam VAR17
= ((VAR7 == VAR15) ||
(VAR7 == VAR18))... | mit |
MarkBlanco/FPGA_Sandbox | VHDL_UART/DE1_SOC_golden_top.v | 7,365 | module MODULE1(
output VAR102,
output VAR4,
input VAR77,
output VAR10,
input VAR24,
inout VAR65,
inout VAR56,
output VAR110,
inout VAR108,
output VAR46,
input VAR89,
input VAR98,
input VAR44,
input VAR21,
output [12:0] VAR68,
output [1:0] VAR69,
output VAR76,
output VAR7,
output VAR5,
output VAR84,
inout [15:0] VAR59,
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15.pp.symbol.v | 1,356 | module MODULE1 (
input VAR3 ,
output VAR5 ,
input VAR2 ,
input VAR1,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
BBN-Q/APS2-Comms | src/ip/cpld_bridge/axis_adapter.v | 19,237 | module MODULE1 #
(
parameter VAR8 = 8,
parameter VAR2 = (VAR8/8),
parameter VAR7 = 8,
parameter VAR16 = (VAR7/8)
)
(
input wire clk,
input wire rst,
input wire [VAR8-1:0] VAR12,
input wire [VAR2-1:0] VAR1,
input wire VAR10,
output wire VAR3,
input wire VAR13,
input wire VAR9,
output wire [VAR7-1:0] VAR22,
output wire [... | mpl-2.0 |
alexforencich/verilog-flowgen | rtl/fg_bd_fifo.v | 4,428 | module MODULE1 #
(
parameter VAR5 = 10,
parameter VAR21 = 8
)
(
input wire clk,
input wire rst,
input wire VAR23,
output wire VAR6,
input wire [VAR21-1:0] VAR22,
input wire [31:0] VAR17,
output wire VAR7,
input wire VAR3,
output wire [VAR21-1:0] VAR10,
output wire [31:0] VAR8,
output wire [VAR5-1:0] VAR14,
output wire ... | mit |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/wb_conmax/wb_conmax_pri_dec.v | 6,062 | module MODULE1(valid, VAR2, VAR4);
parameter [1:0] VAR3 = 2'd0;
input valid;
input [1:0] VAR2;
output [3:0] VAR4;
wire [3:0] VAR4;
reg [3:0] VAR1;
reg [3:0] VAR5;
always @(valid or VAR2)
if(!valid) VAR5 = 4'b0001;
else
if(VAR2==2'h0) VAR5 = 4'b0001;
else
if(VAR2==2'h1) VAR5 = 4'b0010;
else
if(VAR2==2'h2) VAR5 = 4'b0100... | gpl-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/system_acl_iface_mm_interconnect_0_avalon_st_adapter.v | 6,182 | module MODULE1 #(
parameter VAR1 = 34,
parameter VAR15 = 0,
parameter VAR9 = 34,
parameter VAR7 = 0,
parameter VAR12 = 0,
parameter VAR25 = 0,
parameter VAR18 = 1,
parameter VAR16 = 1,
parameter VAR4 = 0,
parameter VAR14 = 34,
parameter VAR21 = 0,
parameter VAR13 = 1,
parameter VAR6 = 0,
parameter VAR17 = 1,
parameter ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkbuf/sky130_fd_sc_hdll__clkbuf.pp.symbol.v | 1,270 | module MODULE1 (
input VAR5 ,
output VAR3 ,
input VAR1 ,
input VAR6,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
anderson1008/PAB-NOC | RTL/permuterBlock.v | 2,124 | module MODULE1 (VAR7, VAR42, VAR23, VAR40, VAR24, VAR26, VAR6);
input VAR23, VAR40;
input [4*VAR13-1:0] VAR24;
input [VAR8-1:0] VAR7,VAR42;
output [VAR8-1:0] VAR26, VAR6;
wire VAR1, VAR30, VAR44;
wire [VAR8-1:0] VAR20 [1:0];
wire [VAR8-1:0] VAR14 [1:0];
reg VAR10;
wire [VAR13-1:0] VAR9 [3:0];
genvar VAR11;
generate
for... | gpl-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/up_clock_mon.v | 4,976 | module MODULE1 (
VAR17,
VAR3,
VAR2,
VAR5,
VAR12);
input VAR17;
input VAR3;
output [31:0] VAR2;
input VAR5;
input VAR12;
reg [15:0] VAR14 = 'd0;
reg VAR4 = 'd0;
reg VAR10 = 'd0;
reg VAR9 = 'd0;
reg VAR1 = 'd0;
reg [31:0] VAR2 = 'd0;
reg VAR7 = 'd0;
reg VAR6 = 'd0;
reg VAR11 = 'd0;
reg VAR13 = 'd0;
reg [31:0] VAR15 = 'd0... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4/sky130_fd_sc_hs__nor4.pp.blackbox.v | 1,294 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR2 ,
VAR4 ,
VAR5 ,
VAR3,
VAR6
);
output VAR1 ;
input VAR7 ;
input VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR3;
input VAR6;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2a/sky130_fd_sc_ms__o2bb2a.functional.v | 1,562 | module MODULE1 (
VAR8 ,
VAR2,
VAR9,
VAR4 ,
VAR5
);
output VAR8 ;
input VAR2;
input VAR9;
input VAR4 ;
input VAR5 ;
wire VAR10 ;
wire VAR12 ;
wire VAR11;
nand VAR6 (VAR10 , VAR9, VAR2 );
or VAR3 (VAR12 , VAR5, VAR4 );
and VAR1 (VAR11, VAR10, VAR12);
buf VAR7 (VAR8 , VAR11 );
endmodule | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_rf.v | 11,894 | module MODULE1(
clk, rst,
VAR30, VAR41, VAR34, VAR19, VAR15, VAR32,
VAR14, VAR35, VAR17, VAR24, VAR18, VAR25, VAR48,
VAR26, VAR8, VAR37, VAR5, VAR11
);
parameter VAR12 = VAR42;
parameter VAR54 = VAR3;
input clk;
input rst;
input VAR30;
input VAR41;
input [VAR54-1:0] VAR34;
input [VAR12-1:0] VAR19;
input VAR15;
input VA... | gpl-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_SEQ_RVT_FF_210930.v | 73,174 | module MODULE1 (VAR15, VAR9, VAR10, VAR7);
output VAR15;
input VAR9, VAR10, VAR7;
reg VAR13;
wire VAR11, VAR8;
wire VAR12, VAR5, VAR4;
wire VAR6;
not (VAR12, VAR11);
not (VAR4, VAR10);
VAR14 (VAR6, VAR8, VAR12, VAR4);
VAR2 (VAR5, VAR13, VAR8, VAR12, VAR4, VAR6);
buf (VAR15, VAR5);
wire VAR1, VAR3, VAR16;
and (VAR1, VAR... | bsd-3-clause |
eda-globetrotter/MarcheProcessor | processor/spare/build2/regfileww.v | 4,751 | module MODULE1(VAR10,VAR1,VAR2,VAR16,VAR5,VAR14,
VAR12,VAR3,VAR7,VAR4,clk);
output [127:0] VAR10,VAR1;
input [0:127] VAR2;
input clk;
input VAR7;
input VAR12, VAR3;
input [4:0] VAR14, VAR16, VAR5;
input [15:0] VAR4;
reg [127:0] VAR10,VAR1;
reg [127:0] VAR9 [31:0];
reg [127:0] VAR13; reg [127:0] VAR8; reg [7:0] VAR6;
al... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21boi/sky130_fd_sc_hs__a21boi.behavioral.pp.v | 2,063 | module MODULE1 (
VAR10,
VAR6,
VAR5 ,
VAR7 ,
VAR2 ,
VAR14
);
input VAR10;
input VAR6;
output VAR5 ;
input VAR7 ;
input VAR2 ;
input VAR14;
wire VAR15 ;
wire VAR16 ;
wire VAR12 ;
wire VAR11;
not VAR8 (VAR15 , VAR14 );
and VAR9 (VAR16 , VAR7, VAR2 );
nor VAR13 (VAR12 , VAR15, VAR16 );
VAR3 VAR1 (VAR11, VAR12, VAR10, VAR6)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21bo/sky130_fd_sc_lp__a21bo.behavioral.pp.v | 2,043 | module MODULE1 (
VAR11 ,
VAR5 ,
VAR4 ,
VAR7,
VAR3,
VAR10,
VAR8 ,
VAR15
);
output VAR11 ;
input VAR5 ;
input VAR4 ;
input VAR7;
input VAR3;
input VAR10;
input VAR8 ;
input VAR15 ;
wire VAR2 ;
wire VAR14 ;
wire VAR9;
nand VAR1 (VAR2 , VAR4, VAR5 );
nand VAR13 (VAR14 , VAR7, VAR2 );
VAR12 VAR16 (VAR9, VAR14, VAR3, VAR10);... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrbp/sky130_fd_sc_hs__sdfrbp_2.v | 2,552 | module MODULE1 (
VAR11,
VAR7 ,
VAR6 ,
VAR5 ,
VAR4 ,
VAR2 ,
VAR3 ,
VAR9 ,
VAR10
);
input VAR11;
input VAR7 ;
input VAR6 ;
output VAR5 ;
output VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR9 ;
input VAR10 ;
VAR1 VAR8 (
.VAR11(VAR11),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9),
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fill/sky130_fd_sc_hd__fill.behavioral.pp.v | 1,147 | module MODULE1 (
VAR2,
VAR3,
VAR1 ,
VAR4
);
input VAR2;
input VAR3;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
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