repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_csc_RGB2CrYCb.v | 4,247 | module MODULE1 (
clk,
VAR17,
VAR15,
VAR11,
VAR3);
parameter VAR7 = 16;
localparam VAR1 = VAR7 - 1;
input clk;
input [VAR1:0] VAR17;
input [23:0] VAR15;
output [VAR1:0] VAR11;
output [23:0] VAR3;
VAR12 #(.VAR7(VAR7)) VAR14 (
.clk (clk),
.sync (VAR17),
.VAR6 (VAR15),
.VAR2 (17'h00707),
.VAR9 (17'h105e2),
.VAR16 (17'h1012... | lgpl-3.0 |
monotone-RK/FACE | MCSoC-15/8-way/src/vivado_ip_dram/ip_top/mig_7series_v2_3_memc_ui_top_std.v | 38,707 | module MODULE1 #
(
parameter VAR28 = 100,
parameter VAR109 = "135", parameter VAR119 = 64,
parameter VAR198 = "VAR170",
parameter VAR264 = "0", parameter VAR140 = 3, parameter VAR18 = 2, parameter VAR217 = "8", parameter VAR324 = "VAR99", parameter VAR111 = "VAR62", parameter VAR8 = 1, parameter VAR287 = 5,
parameter V... | mit |
marqs85/ossc | ip/i2c_opencores/i2c_master_top.v | 10,178 | module MODULE1(
VAR1, VAR37, VAR20, VAR21, VAR7, VAR11,
VAR25, VAR57, VAR47, VAR4, VAR54,
VAR50, VAR56, VAR40, VAR53, VAR39, VAR46, VAR13 );
parameter VAR26 = 1'b0; parameter VAR49 = 0;
input VAR1; input VAR37; input VAR20; input [2:0] VAR21; input [7:0] VAR7; output [7:0] VAR11; input VAR25; input VAR57; input VAR47; ... | gpl-3.0 |
csturton/wirepatch | system/hardware/cores/or1200/or1200_spram.v | 5,201 | module MODULE1
(
VAR4, VAR5, VAR11,
clk, VAR12, VAR3, addr, VAR8, VAR2
);
parameter VAR13 = 10;
parameter VAR10 = 32;
input VAR4;
input [VAR6 - 1:0] VAR11;
output VAR5;
input clk; input VAR12; input VAR3; input [VAR13-1:0] addr; input [VAR10-1:0] VAR8; output [VAR10-1:0] VAR2;
reg [VAR10-1:0] VAR9 [(1<<VAR13)-1:0] ;
re... | mit |
VitorCBSB/hw-verilog | C++/Verilog/circ_gen/sampler.v | 1,302 | module MODULE1(VAR8, VAR4, VAR5, VAR2, VAR9);
parameter VAR7 = 2'b00,
VAR1 = 2'b01,
VAR10 = 2'b10,
VAR6 = 2'b11;
input VAR8;
input VAR4;
input VAR5;
output reg [15:0] VAR2;
output VAR9;
reg [1:0] state = VAR7;
wire [1:0] VAR3;
assign VAR3 = VAR11(state, VAR5, VAR2);
function [1:0] VAR11(input [1:0] state, input VAR12, ... | mit |
tloinuy/opencpi-opencv | opencpi/hdl/prims/bsv/MakeResetA.v | 2,544 | module MODULE1 (
VAR9,
VAR12,
VAR10,
VAR4,
VAR5,
VAR1
);
parameter VAR7 = 2 ; parameter VAR2 = 1 ;
input VAR9 ;
input VAR12 ;
input VAR10 ;
output VAR4 ;
input VAR5 ;
output VAR1 ;
reg rst ;
wire VAR1 ;
assign VAR4 = !rst ;
VAR3 #(VAR7) VAR8 (.VAR9(VAR5),
.VAR11(rst),
.VAR1(VAR1));
always@(posedge VAR9 or negedge VAR12... | gpl-2.0 |
asicguy/gplgpu | hdl/de_temp/dex_smline.v | 8,996 | module MODULE1
(
input VAR62,
input VAR31,
input VAR26,
input [2:0] VAR8,
input VAR54,
input VAR25,
input VAR51,
input VAR20,
input VAR30,
input VAR22,
input VAR48,
input VAR13,
input VAR9,
output reg VAR14,
output reg VAR5,
output reg VAR41,
output reg VAR38,
output reg VAR12,
output reg VAR16,
output reg VAR6,
output... | gpl-3.0 |
hwstar/bdcmotor | bdcmotorchannel.v | 2,453 | module MODULE1(
output [7:0] VAR11,
output [7:0] VAR4,
output [1:0] VAR16,
output [3:0] VAR17,
input clk,
input VAR2,
input VAR12,
input VAR13,
input VAR6,
input VAR3,
input VAR14,
input VAR19,
input VAR5,
input VAR1,
input [1:0] VAR8,
input [7:0] VAR15);
VAR9 VAR18(
.clk(clk),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR12(VAR12),
... | gpl-2.0 |
CospanDesign/nysa-artemis-usb2-platform | artemis_usb2/slave/wb_artemis_usb2_platform/rtl/artemis_pcie_sata.v | 17,095 | module MODULE1 (
input VAR158,
input VAR171,
output VAR161,
output VAR167,
output VAR67,
output VAR79,
output VAR43,
output VAR114,
output VAR50,
output VAR154,
output VAR201,
output [1:0] VAR25,
output [1:0] VAR41,
output [3:0] VAR97,
output [3:0] VAR155,
output [3:0] VAR144,
output [3:0] VAR1,
output [3:0] VAR187,
ou... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai33/gf180mcu_fd_sc_mcu7t5v0__oai33_2.behavioral.v | 5,359 | module MODULE1( VAR3, VAR2, VAR4, VAR9, VAR8, VAR5, VAR10 );
input VAR10, VAR5, VAR8, VAR9, VAR2, VAR3;
output VAR4;
VAR1 VAR7(.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4),.VAR9(VAR9),.VAR8(VAR8),.VAR5(VAR5),.VAR10(VAR10));
VAR1 VAR6(.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4),.VAR9(VAR9),.VAR8(VAR8),.VAR5(VAR5),.VAR10(VAR10)); | apache-2.0 |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/whr_op_ctrl_mac.v | 18,688 | module MODULE1
(clk, reset, VAR112, VAR65, VAR63, VAR12, VAR97,
VAR71, VAR130, VAR72, VAR62, VAR22);
parameter VAR8 = 8;
localparam VAR94 = VAR121(VAR8);
localparam VAR14 = VAR121(VAR8+1);
parameter VAR126 = 4;
parameter VAR17 = 4;
parameter VAR31 = 2;
parameter VAR116 = 1;
parameter VAR74 = VAR55;
localparam VAR54
= (... | mit |
hcabrera-/lancetfish | RTL/processing_element/des_engine/rtl/des_sbox8.v | 3,336 | module MODULE1
(
input wire [0:5] VAR2,
output reg [0:3] VAR1
);
always @(*)
case ({VAR2[0], VAR2[5]})
2'b00:
case (VAR2[1:4])
4'd0: VAR1 = 4'd13;
4'd1: VAR1 = 4'd2;
4'd2: VAR1 = 4'd8;
4'd3: VAR1 = 4'd4;
4'd4: VAR1 = 4'd6;
4'd5: VAR1 = 4'd15;
4'd6: VAR1 = 4'd11;
4'd7: VAR1 = 4'd1;
4'd8: VAR1 = 4'd10;
4'd9: VAR1 = 4'd9;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/einvp/sky130_fd_sc_hvl__einvp.functional.pp.v | 1,872 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR1 ,
VAR12,
VAR8,
VAR13 ,
VAR6
);
output VAR5 ;
input VAR9 ;
input VAR1 ;
input VAR12;
input VAR8;
input VAR13 ;
input VAR6 ;
wire VAR7 ;
wire VAR10;
VAR4 VAR2 (VAR7 , VAR9, VAR12, VAR8 );
VAR4 VAR11 (VAR10, VAR1, VAR12, VAR8 );
notif1 VAR3 (VAR5 , VAR7, VAR10);
endmodule | apache-2.0 |
htogarcia/Microcontrolador-Calculadora | VGA Mouse/num_chooser.v | 1,645 | module MODULE1(
output reg [4:0] VAR21,
input wire [2:0] VAR2,
input wire [3:0] VAR35
);
wire [4:0] VAR28, VAR7, VAR26, VAR14, VAR31, VAR15, VAR19, VAR13, VAR12, VAR33;
VAR3 VAR27 (
.VAR1(VAR2),
.VAR34(VAR28)
);
VAR22 VAR5 (
.VAR1(VAR2),
.VAR34(VAR7)
);
VAR6 VAR24 (
.VAR1(VAR2),
.VAR34(VAR26)
);
VAR9 VAR23 (
.VAR1(VAR2... | mit |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx.v | 9,968 | module MODULE1 #(
parameter VAR44 = 128, parameter VAR37 = "VAR38", parameter VAR28 = "VAR46", parameter VAR8 = "VAR46", parameter VAR30 = 1,
parameter VAR31 = (VAR44 == 128) ? 2 : 1, parameter VAR17 = VAR44 / 8 ) (
input [VAR44-1:0] VAR43, input VAR23, output VAR33, input [VAR17-1:0] VAR24, input VAR41, input [3:0] VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4/sky130_fd_sc_ms__or4.symbol.v | 1,282 | module MODULE1 (
input VAR4,
input VAR9,
input VAR6,
input VAR3,
output VAR2
);
supply1 VAR1;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_12.v | 11,390 | module MODULE3 (
clk,
reset,
VAR38,
VAR16,
VAR84,
VAR55,
VAR20
);
parameter VAR82 = 18;
parameter VAR70 = 12;
parameter VAR13 = 6;
localparam VAR29 = 17;
input clk;
input reset;
input VAR38;
input VAR16;
input [VAR82-1:0] VAR84; output VAR55;
output [VAR82-1:0] VAR20;
localparam VAR58 = 18; localparam VAR1 = 36; localp... | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/neek/rtl/verilog/lcd_ctrl.v | 7,893 | module MODULE1 #(
parameter VAR41 = 50000000
)
(
input VAR29,
input VAR4,
output VAR3,
output VAR31,
output VAR40,
output [7:0] VAR24,
output VAR26,
output VAR12,
output VAR35,
output VAR38,
input VAR17,
input VAR2,
input VAR11,
input VAR22,
input VAR27,
input [7:0] VAR43,
input [7:0] VAR23,
input [7:0] VAR37
);
localp... | gpl-2.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/ram/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v | 48,802 | module MODULE1 #
( parameter
VAR127 = 80,
VAR107 = 32,
VAR81 = 2,
VAR21 = 40,
VAR87 = 5,
VAR25 = 8,
VAR141 = 1,
VAR89 = 0,
VAR46 = 0,
VAR95 = 0,
VAR45 = 0,
VAR63 = 8,
VAR15 = 1,
VAR131 = 1,
VAR38 = 1,
VAR26 = 1,
VAR97 = 1,
VAR96 = 1,
VAR64 = 1,
VAR80 = 1,
VAR91 = 1,
VAR71 = 1,
VAR60 = 8,
VAR92 = 8,
VAR36 = 1,
VAR112 = ... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_4.behavioral.v | 8,258 | module MODULE1( VAR6, VAR4, VAR9, VAR8, VAR5, VAR7, VAR1 );
input VAR1, VAR7, VAR6, VAR9, VAR4, VAR5;
output VAR8;
VAR10 VAR3(.VAR6(VAR6),.VAR4(VAR4),.VAR9(VAR9),.VAR8(VAR8),.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1));
VAR10 VAR2(.VAR6(VAR6),.VAR4(VAR4),.VAR9(VAR9),.VAR8(VAR8),.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1)); | apache-2.0 |
donnaware/AGC | rtl/de0/agc/JTAG_Probe1.v | 3,865 | module MODULE1 (
VAR18,
VAR6);
input [0:0] VAR18;
output VAR6;
wire VAR20;
wire VAR6 = VAR20;
VAR1 VAR11 (
.VAR18 (VAR18),
.VAR6 (VAR20)
,
.VAR32 (),
.VAR24 (),
.VAR2 (),
.VAR16 (),
.VAR26 (),
.VAR17 (),
.VAR13 (),
.VAR4 (),
.VAR5 (),
.VAR14 (),
.VAR8 (),
.VAR15 (),
.VAR29 (),
.VAR12 (),
.VAR3 (),
.VAR9 (),
.VAR7 ()
);... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221o/sky130_fd_sc_lp__a221o.functional.pp.v | 2,199 | module MODULE1 (
VAR12 ,
VAR14 ,
VAR15 ,
VAR13 ,
VAR20 ,
VAR16 ,
VAR8,
VAR4,
VAR5 ,
VAR17
);
output VAR12 ;
input VAR14 ;
input VAR15 ;
input VAR13 ;
input VAR20 ;
input VAR16 ;
input VAR8;
input VAR4;
input VAR5 ;
input VAR17 ;
wire VAR2 ;
wire VAR9 ;
wire VAR7 ;
wire VAR18;
and VAR11 (VAR2 , VAR13, VAR20 );
and VAR10... | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_data_in.v | 1,942 | module MODULE1 (
address,
clk,
VAR1,
VAR4,
VAR2
)
;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input clk;
input [ 7: 0] VAR1;
input VAR4;
wire VAR6;
wire [ 7: 0] VAR3;
wire [ 7: 0] VAR5;
reg [ 31: 0] VAR2;
assign VAR6 = 1;
assign VAR5 = {8 {(address == 0)}} & VAR3;
always @(posedge clk or negedge VAR4)
begin
if (VAR4... | gpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo_bb.v | 3,064 | module MODULE1 (
VAR5,
VAR36,
VAR25,
VAR1,
VAR15,
VAR22,
VAR11,
VAR37,
VAR2,
VAR27,
VAR19,
VAR29,
VAR21,
VAR20,
VAR12,
VAR33,
VAR32,
VAR38,
VAR14,
VAR18,
VAR41,
VAR17,
VAR10,
VAR30,
VAR13,
VAR9,
VAR24,
VAR6,
VAR4,
VAR34,
VAR40,
VAR35,
VAR3,
VAR8,
VAR16,
VAR39,
VAR28,
VAR42,
VAR23,
VAR7,
VAR26,
VAR31);
output VAR5;
inpu... | gpl-3.0 |
SymbiFlow/yosys-f4pga-plugins | ql-qlf-plugin/qlf_k4n8/arith_map.v | 4,534 | module MODULE1(
module 80quicklogicalu (VAR25, VAR8, VAR22, VAR7, VAR1, VAR13, VAR34);
parameter VAR33 = 0;
parameter VAR21 = 0;
parameter VAR12 = 1;
parameter VAR23 = 1;
parameter VAR30 = 1;
parameter VAR19 = 0;
parameter VAR2 = 0;
input [VAR12-1:0] VAR25;
input [VAR23-1:0] VAR8;
output [VAR30-1:0] VAR1, VAR13;
input ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputisolatch/sky130_fd_sc_hd__lpflow_inputisolatch.functional.pp.v | 1,786 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR11,
VAR5 ,
VAR8 ,
VAR4 ,
VAR7
);
output VAR3 ;
input VAR1 ;
input VAR11;
input VAR5 ;
input VAR8 ;
input VAR4 ;
input VAR7 ;
wire VAR10;
VAR6 VAR9 (VAR10 , VAR1, VAR11, 1'b0, VAR5, VAR8);
buf VAR2 (VAR3 , VAR10 );
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/de_temp/ded_ca_top.v | 4,201 | module MODULE1
(
input VAR11,
input VAR13,
input VAR14,
input VAR6,
input [4:0] VAR15,
input [(VAR3*8)-1:0] VAR7,
output [31:0] VAR4,
output [4:0] VAR1,
output [4:0] VAR5,
output [4:0] VAR10
);
wire [2:0] VAR2;
assign VAR2 = VAR9 + 3'h1;
assign VAR4 = VAR7[VAR15[1:0]*32 +: 32];
assign VAR12[0] = VAR6 & (VAR15[1:0] == 2... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_ss_422to444.v | 5,503 | module MODULE1 (
clk,
VAR16,
VAR20,
VAR23,
VAR3,
VAR4,
VAR15,
VAR9,
VAR18,
VAR1);
input clk;
input VAR16;
input VAR20;
input VAR23;
input [15:0] VAR3;
output VAR4;
output VAR15;
output VAR9;
output [23:0] VAR18;
input VAR1;
reg VAR26 = 'd0;
reg VAR11 = 'd0;
reg VAR13 = 'd0;
reg VAR22 = 'd0;
reg [23:0] VAR7 = 'd0;
reg V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1.pp.symbol.v | 1,357 | module MODULE1 (
input VAR4 ,
output VAR1 ,
input VAR6 ,
input VAR3,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4b/sky130_fd_sc_ms__and4b.pp.symbol.v | 1,324 | module MODULE1 (
input VAR1 ,
input VAR8 ,
input VAR9 ,
input VAR2 ,
output VAR4 ,
input VAR3 ,
input VAR5,
input VAR7,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3b/sky130_fd_sc_hs__and3b.blackbox.v | 1,259 | module MODULE1 (
VAR5 ,
VAR4,
VAR1 ,
VAR2
);
output VAR5 ;
input VAR4;
input VAR1 ;
input VAR2 ;
supply1 VAR3;
supply0 VAR6;
endmodule | apache-2.0 |
zhangly/azpr_cpu | rtl/cpu/rtl/alu.v | 2,590 | module MODULE1 (
input wire [VAR4] VAR2, input wire [VAR4] VAR9, input wire [VAR8] VAR10, output reg [VAR4] out, output reg VAR3 );
wire signed [VAR4] VAR5 = (VAR2); wire signed [VAR4] VAR1 = (VAR9); wire signed [VAR4] VAR11 = (out);
always @ begin
case (VAR10)
((VAR5 < 0) && (VAR1 < 0) && (VAR11 > 0))) begin
VAR3 = VA... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4NSC_v1_2_5/ab882192/src/SCFIFO_80x64_withCount.v | 2,690 | module MODULE1
(
input VAR10 ,
input VAR6 ,
input [79:0] VAR8 ,
input VAR3 ,
output VAR15 ,
output [79:0] VAR7 ,
input VAR16 ,
output VAR17 ,
output [5:0] VAR1
);
VAR2
VAR9
(
.clk (VAR10 ),
.VAR4 (VAR6 ),
.din (VAR8 ),
.VAR14 (VAR3 ),
.VAR13 (VAR15 ),
.dout (VAR7 ),
.VAR12 (VAR16 ),
.VAR5 (VAR17 ),
.VAR11 (VAR1 )
);
en... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9361_v1_00_a/hdl/verilog/axi_ad9361_rx_pnmon.v | 6,599 | module MODULE1 (
VAR15,
VAR1,
VAR6,
VAR11,
VAR23,
VAR12);
input VAR15;
input VAR1;
input [11:0] VAR6;
input [11:0] VAR11;
output VAR23;
output VAR12;
reg [15:0] VAR3 = 'd0;
reg [15:0] VAR20 = 'd0;
reg VAR18 = 'd0;
reg VAR17 = 'd0;
reg VAR13 = 'd0;
reg VAR26 = 'd0;
reg VAR12 = 'd0;
reg [ 6:0] VAR8 = 'd0;
reg VAR23 = 'd0... | mit |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/new/pwm/pwm_ctrl.v | 10,903 | module MODULE1(clk,VAR96,VAR20,VAR23,VAR25,VAR88,VAR58,VAR36,VAR45,VAR59,VAR66,VAR1,VAR3);
input clk,VAR96;
output wire VAR58,VAR36,VAR45,VAR59,VAR66,VAR1;
input [3:0] VAR23;
input [23:0] VAR20;
wire VAR51; wire VAR80; input VAR25; input VAR88;
reg VAR69;
reg VAR16;
wire VAR81,VAR38,VAR21;
output wire VAR3;
assign VAR3... | gpl-3.0 |
VitorCBSB/hw-verilog | C++/Verilog/circ_gen/genetico.v | 1,416 | module MODULE1(VAR7, VAR3, in, out);
input [10:0] VAR7[8:0];
input [3:0] VAR3[1:0];
input [2:0] in;
output [1:0] out;
wire [8:0] VAR2;
wire [11:0] VAR15;
assign VAR15 = {VAR2, in};
assign out = {VAR15[VAR3[1]], VAR15[VAR3[0]]};
VAR13 VAR14(
.VAR16(VAR7[0][10:8]),
.VAR10(VAR7[0][7:0]),
.VAR15(VAR15),
.out(VAR2[0])
);
VA... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbus_common/rtl/bw_io_dtl_edgelogic.v | 4,682 | module MODULE1 (
VAR28, VAR22, VAR21, VAR40, VAR25, VAR12, VAR43,
VAR18, VAR7, VAR41, VAR31,
VAR29, VAR54, VAR19, VAR39, VAR53, clk, VAR26, VAR63, VAR11, VAR60,
VAR3, VAR44
);
input VAR29;
input VAR54;
input VAR19;
input VAR39;
input VAR53;
input clk;
input VAR26;
input VAR63;
input VAR11;
input VAR60;
input VAR3;
inpu... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dmc/bsg_dmc_clk_rst_gen.v | 2,864 | module MODULE1
import VAR14::VAR44;
,parameter VAR31(VAR6 ))
(input VAR44 VAR38
,input VAR44 [VAR6-1:0] VAR37
,input VAR44 [VAR6-1:0] VAR4
,input VAR44 VAR34
,output VAR17
,input [VAR6-1:0] VAR13
,output [VAR6-1:0] VAR28
,input VAR8
,output VAR30);
localparam VAR16 = 0;
genvar VAR11;
VAR43 #(.VAR9(1)) VAR39
(.VAR18 ( V... | bsd-3-clause |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/source/rtl/Ninth_Phase_M.v | 1,799 | module MODULE1
(
input wire clk, input wire rst, input wire VAR12, input wire VAR4,
input wire [VAR3-1:0] VAR2, input wire [VAR3-1:0] VAR11,
output wire [VAR3:0] VAR25, output wire VAR23 );
wire [VAR3:0] VAR8;
wire [VAR3:0] VAR26;
wire VAR15;
VAR10 #(.VAR18(VAR3)) VAR6 (
.VAR7(1'b0),
.VAR14(VAR2),
.VAR5(VAR11),
.VAR9(V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.v | 2,385 | module MODULE2 (
VAR7 ,
VAR9 ,
VAR11 ,
VAR4 ,
VAR5,
VAR3 ,
VAR2 ,
VAR10 ,
VAR1
);
output VAR7 ;
output VAR9 ;
input VAR11 ;
input VAR4 ;
input VAR5;
input VAR3 ;
input VAR2 ;
input VAR10 ;
input VAR1 ;
VAR8 VAR6 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR10(VAR10)... | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_pcie_bram_top_7x.v | 8,586 | module MODULE1
parameter VAR8 = "VAR28", parameter VAR30 = 0, parameter [3:0] VAR13 = 4'h1, parameter [5:0] VAR24 = 6'h08,
parameter VAR19 = 31, parameter VAR3 = 24, parameter VAR5 = 1, parameter VAR21 = 2, parameter VAR22 = 1,
parameter VAR35 = 'h1FFF, parameter VAR4 = 1, parameter VAR11 = 2, parameter VAR9 = 1 )
(
in... | gpl-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_43.v | 30,704 | module MODULE3 (
clk,
reset,
VAR82,
VAR21,
VAR37,
VAR62,
VAR107
);
parameter VAR155 = 18;
parameter VAR172 = 43;
parameter VAR170 = 22;
localparam VAR227 = 50;
input clk;
input reset;
input VAR82;
input VAR21;
input [VAR155-1:0] VAR37; output VAR62;
output [VAR155-1:0] VAR107;
localparam VAR141 = 18; localparam VAR8 = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/diode/sky130_fd_sc_lp__diode_1.v | 1,978 | module MODULE2 (
VAR3,
VAR4 ,
VAR5 ,
VAR2 ,
VAR6
);
input VAR3;
input VAR4 ;
input VAR5 ;
input VAR2 ;
input VAR6 ;
VAR7 VAR1 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR3
);
input VAR3;
supply1 VAR4;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR6 ;
VAR7 VAR1 (
.VAR3(VA... | apache-2.0 |
jotego/jt51 | hdl/jt51_exp2lin.v | 1,210 | module MODULE1(
output reg signed [15:0] VAR3,
input signed [9:0] VAR1,
input [2:0] VAR2
);
always @(*) begin
case( VAR2 )
3'd7: VAR3 = { VAR1, 6'b0 };
3'd6: VAR3 = { {1{VAR1[9]}}, VAR1, 5'b0 };
3'd5: VAR3 = { {2{VAR1[9]}}, VAR1, 4'b0 };
3'd4: VAR3 = { {3{VAR1[9]}}, VAR1, 3'b0 };
3'd3: VAR3 = { {4{VAR1[9]}}, VAR1, 2'b0... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/correlator/rmw_address_unit.v | 5,759 | module MODULE2
parameter VAR5 = VAR39-1,
parameter VAR18 = 0,
parameter VAR21 = 11,
parameter VAR13 = 3,
parameter VAR16 = 3)
(
input VAR6,
input VAR27,
input VAR17,
output [VAR5:0] VAR3,
output VAR34,
output [VAR5:0] VAR31,
output VAR32
);
wire [VAR5:0] VAR23, VAR24;
wire [VAR5:0] VAR25;
reg [VAR5:0] VAR8 = VAR18;
ass... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_1.behavioral.pp.v | 2,820 | module MODULE1( VAR10, VAR2, VAR5, VAR7, VAR11, VAR1 );
input VAR5, VAR2, VAR10;
inout VAR11, VAR1;
output VAR7;
reg VAR21;
VAR26 VAR22(.VAR10(VAR10),.VAR2(VAR2),.VAR5(VAR5),.VAR7(VAR7),.VAR11(VAR11),.VAR1(VAR1),.VAR21(VAR21));
VAR26 VAR19(.VAR10(VAR10),.VAR2(VAR2),.VAR5(VAR5),.VAR7(VAR7),.VAR11(VAR11),.VAR1(VAR1),.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor3/sky130_fd_sc_hs__xor3_4.v | 2,072 | module MODULE2 (
VAR7 ,
VAR5 ,
VAR6 ,
VAR1 ,
VAR2,
VAR4
);
output VAR7 ;
input VAR5 ;
input VAR6 ;
input VAR1 ;
input VAR2;
input VAR4;
VAR3 VAR8 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR7,
VAR5,
VAR6,
VAR1
);
output VAR7;
input VAR5;
input VAR6;
in... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad6676/axi_ad6676_pnmon.v | 7,006 | module MODULE1 (
VAR11,
VAR6,
VAR1,
VAR13,
VAR4);
input VAR11;
input [31:0] VAR6;
output VAR1;
output VAR13;
input [ 3:0] VAR4;
reg [31:0] VAR10 = 'd0;
reg [31:0] VAR14 = 'd0;
wire [31:0] VAR16;
function [31:0] VAR12;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[22] ^ din[17];
dout[30] = din[21] ^ din[16];
d... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor3/sky130_fd_sc_lp__xnor3_lp.v | 2,192 | module MODULE2 (
VAR7 ,
VAR3 ,
VAR8 ,
VAR2 ,
VAR10,
VAR9,
VAR4 ,
VAR5
);
output VAR7 ;
input VAR3 ;
input VAR8 ;
input VAR2 ;
input VAR10;
input VAR9;
input VAR4 ;
input VAR5 ;
VAR1 VAR6 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32oi/sky130_fd_sc_hd__a32oi_4.v | 2,483 | module MODULE2 (
VAR1 ,
VAR12 ,
VAR10 ,
VAR6 ,
VAR3 ,
VAR9 ,
VAR2,
VAR11,
VAR4 ,
VAR7
);
output VAR1 ;
input VAR12 ;
input VAR10 ;
input VAR6 ;
input VAR3 ;
input VAR9 ;
input VAR2;
input VAR11;
input VAR4 ;
input VAR7 ;
VAR5 VAR8 (
.VAR1(VAR1),
.VAR12(VAR12),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR2... | apache-2.0 |
aj-michael/Digital-Systems | Pong/Phase2/CRTcontroller2015fall.v | 2,238 | module MODULE1(VAR20, VAR11, VAR13, VAR7, VAR8, VAR3, VAR14, VAR19, reset, VAR9);
parameter VAR15=10, VAR17=10;
input [VAR15-1:0] VAR20, VAR11;
input [VAR17-1:0] VAR13, VAR7;
input reset, VAR9;
output VAR8, VAR3;
output [VAR15-1:0] VAR14, VAR19;
parameter VAR10=10'd2, VAR1=10'd9, VAR5=10'd29; parameter VAR12=10'd95, VA... | mit |
travisg/cpu | rtl/cpu/stage5_writeback.v | 1,739 | module MODULE1(
input VAR2,
input VAR5,
input VAR1,
input [4:0] VAR3,
input [31:0] VAR7,
output reg VAR6,
output reg [4:0] VAR4,
output reg [31:0] VAR8
);
always @(posedge VAR2)
begin
if (VAR5) begin
VAR6 <= 0;
VAR4 <= 0;
VAR8 <= 0;
end else begin
VAR6 <= VAR1;
VAR4 <= VAR3;
VAR8 <= VAR7;
end
end
endmodule | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_processing_system7_0_0/led_controller_design_processing_system7_0_0_stub.v | 5,318 | module MODULE1(VAR51, VAR39,
VAR16, VAR23, VAR3, VAR17,
VAR25, VAR44, VAR50, VAR34,
VAR35, VAR20, VAR46, VAR42, VAR11,
VAR57, VAR32, VAR8, VAR4,
VAR56, VAR14, VAR29, VAR40, VAR41,
VAR43, VAR64, VAR21, VAR33, VAR15,
VAR38, VAR47, VAR31, VAR48, VAR37,
VAR30, VAR1, VAR27, VAR49,
VAR58, VAR67, VAR63, VAR6, VAR65,
VAR18, VA... | mit |
horia141/bachelor-thesis | prj/components/VGA1/VGA1.v | 5,911 | module MODULE1(VAR21,reset,VAR18,VAR28,VAR36,VAR33,VAR24,VAR35,VAR3);
input wire VAR21;
input wire reset;
input wire [11:0] VAR18;
input wire VAR28;
output wire VAR36;
output wire VAR33;
output wire VAR24;
output wire VAR35;
output wire VAR3;
reg [1:0] VAR14;
reg [63:0] VAR30;
wire [3:0] VAR15;
wire [7:0] VAR26;
reg [2... | mit |
yipenghuang0302/csee4840_14 | software/peripheral/db/ip/ik_swift/submodules/altera_avalon_st_jtag_interface.v | 2,776 | module MODULE1 (
clk,
VAR15,
VAR16,
VAR5,
VAR18,
VAR2,
VAR10,
VAR19,
VAR24,
VAR1,
VAR4,
VAR13,
VAR21
);
input clk;
input VAR15;
output [7:0] VAR5;
input VAR16;
output VAR18;
input [7:0] VAR2;
input VAR10;
output VAR19;
output VAR24;
output VAR1;
output VAR4;
output VAR21;
parameter VAR7 = 0; parameter VAR20 = 0;
parame... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/diode/sky130_fd_sc_lp__diode.pp.blackbox.v | 1,226 | module MODULE1 (
VAR5,
VAR4 ,
VAR2 ,
VAR3 ,
VAR1
);
input VAR5;
input VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
AngelTerrones/Antares | Hardware/verilog/antares_hazard_unit.v | 9,275 | module MODULE1 (
input [7:0] VAR51, input [4:0] VAR46, input [4:0] VAR20, input [4:0] VAR52, input [4:0] VAR22, input [4:0] VAR38, input [4:0] VAR41, input [4:0] VAR63, input VAR12, input VAR31, input VAR15, input VAR16, input VAR40, input VAR48, input VAR25, input VAR55, input VAR9, input VAR14, input VAR50, input VAR... | mit |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_dc_fsm.v | 11,855 | module MODULE1(
clk, rst,
VAR23, VAR32, VAR17, VAR26, VAR19,
VAR13, VAR5, VAR7, VAR6, VAR20,
VAR4, VAR11, VAR22, VAR18, VAR2, VAR25,
VAR15, VAR1, VAR28
);
input clk;
input rst;
input VAR23;
input VAR32;
input VAR17;
input VAR26;
input [3:0] VAR19;
input VAR13;
input VAR5;
input VAR7;
input [31:0] VAR6;
output [31:0] VA... | apache-2.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Proyectos Funcionales Francis Jeffrey/CORDICO/CORDICO.srcs/sources_1/imports/Floating-Point-Unit-master/Coprocesador_CORDIC_RTL/sine_cosine_CORDIC/CORDIC_FSM_v2.v | 8,653 | module MODULE1
(
input wire clk, input wire reset, input wire VAR5, input wire VAR23, input wire VAR21, input wire VAR48,
input wire [1:0] VAR30, input wire [1:0] VAR47, input wire VAR36, input wire VAR49, VAR40, input wire VAR38, VAR11,
output reg VAR39,
output reg VAR26, output reg VAR12, output reg VAR32, output reg... | gpl-3.0 |
everskar2013/PentiumX | Hardware/Code/PS2_IO.v | 2,915 | module MODULE1(
VAR7,
VAR6,
VAR13,
VAR19,
VAR23,
VAR22,
VAR24,
VAR21,
rst,
VAR11,
VAR15,
VAR4,
VAR16,
VAR5,
VAR10,
VAR12,
VAR25
);
input wire [31:0] VAR7;
input wire [31:0] VAR6;
input wire VAR13;
input wire VAR19;
output reg [31:0] VAR23;
output VAR22;
input VAR24, VAR21, rst, VAR11, VAR15;
input VAR5;
output VAR4, VA... | mit |
hoglet67/ElectronFpga | src/altera/qpi_flash.v | 16,216 | module MODULE1(
input wire clk,
output reg ready = 0,
input wire reset,
input wire read,
input wire [23:0] addr,
output reg [7:0] VAR31 = 8'hFF,
input wire VAR36,
input wire VAR30,
input wire VAR37,
input wire VAR3,
output reg VAR9 = 1,
output reg VAR1 = 0,
inout wire VAR5,
inout wire VAR26,
inout wire VAR11,
inout wir... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/diode/sky130_fd_sc_hd__diode.behavioral.v | 1,177 | module MODULE1 (
VAR1
);
input VAR1;
supply1 VAR2;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_convert_with_rounding_16.v | 10,609 | module MODULE1(VAR21, VAR1, VAR6, VAR33, VAR2, VAR26, VAR37, VAR8, enable);
parameter VAR25 = 1;
parameter VAR22 = 0;
parameter VAR19 = 1;
input VAR21;
input enable, VAR1;
input [31:0] VAR6;
output [15:0] VAR33;
input VAR2, VAR37;
output VAR8, VAR26;
wire VAR13;
wire [7:0] VAR14;
wire [22:0] VAR15;
wire [23:0] VAR43;
a... | mit |
xuefei1/ElectronicEngineControl | db/ip/niosII_system/submodules/niosII_system_onchip_memory2_0.v | 4,028 | module MODULE1 (
address,
VAR11,
VAR5,
clk,
VAR21,
reset,
write,
VAR28,
VAR18
)
;
parameter VAR31 = "../MODULE1.VAR22";
output [ 31: 0] VAR18;
input [ 11: 0] address;
input [ 3: 0] VAR11;
input VAR5;
input clk;
input VAR21;
input reset;
input write;
input [ 31: 0] VAR28;
wire [ 31: 0] VAR18;
wire VAR3;
assign VAR3 = VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3/sky130_fd_sc_hdll__and3.pp.symbol.v | 1,288 | module MODULE1 (
input VAR7 ,
input VAR2 ,
input VAR4 ,
output VAR1 ,
input VAR5 ,
input VAR3,
input VAR6,
input VAR8
);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_mux_butterfly.v | 1,724 | module MODULE1
, parameter VAR16(VAR12)
, VAR5=VAR2(VAR12)
)
(
input [VAR12-1:0][VAR6-1:0] VAR8
, input [VAR5-1:0] VAR4
, output logic [VAR12-1:0][VAR6-1:0] VAR1
);
logic [VAR5:0][(VAR12*VAR6)-1:0] VAR9;
assign VAR9[0] = VAR8;
for (genvar VAR7 = 0; VAR7 < VAR5; VAR7++) begin: VAR14
for (genvar VAR3 = 0; VAR3 < VAR12/(2... | bsd-3-clause |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/wrapper/usbSlave.v | 15,818 | module MODULE1(
VAR152,
VAR55,
VAR38,
VAR95,
VAR139,
VAR167,
VAR143,
VAR26,
VAR126,
VAR50,
VAR72,
VAR122,
VAR131,
VAR28,
VAR98,
VAR71,
VAR80,
VAR146,
VAR118,
VAR90,
VAR48,
VAR128,
VAR42,
VAR31
);
parameter VAR100 = 64;
parameter VAR27 = 6;
parameter VAR108 = 64;
parameter VAR145 = 6;
parameter VAR142 = 64;
parameter VA... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/ip_top/mem_intfc.v | 31,700 | module MODULE1 #
(
parameter VAR25 = 100,
parameter VAR44 = 64,
parameter VAR38 = "1T",
parameter VAR2 = "0", parameter VAR35 = 3, parameter VAR43 = 2, parameter VAR234 = "8", parameter VAR243 = "VAR204", parameter VAR91 = 1, parameter VAR114 = 4'hc,
parameter VAR143 = 4'hf,
parameter VAR171 = 4'hf,
parameter VAR84 = 4... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.v | 2,272 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR8,
VAR5 ,
VAR3 ,
VAR4 ,
VAR7
);
output VAR1 ;
input VAR2 ;
input VAR8;
input VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR7 ;
VAR6 VAR9 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR1 ,
VAR2 ,
VAR8
);
output VA... | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/userio_osd.v | 18,275 | module MODULE1
(
input clk, input VAR99,
input VAR103,
input reset, input VAR3, input VAR91,
input VAR11, input VAR60, input VAR63,
input [7:0] VAR85, input VAR74, input VAR29, output VAR69, input VAR83, output VAR49, output VAR55, output reg VAR42 = 0, output reg VAR21 = 0, output reg [1:0] VAR70 = 0,
output reg [1:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3b/sky130_fd_sc_lp__nand3b.pp.blackbox.v | 1,320 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR5 ,
VAR7 ,
VAR4,
VAR8,
VAR6 ,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR5 ;
input VAR7 ;
input VAR4;
input VAR8;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/ip/hdl/verilog/image_filter_Block_Mat_exit1222_proc1.v | 14,243 | module MODULE1 (
VAR40,
VAR15,
VAR52,
VAR43,
VAR76,
VAR53,
VAR11,
VAR50,
VAR16,
VAR22,
VAR6,
VAR51,
VAR63,
VAR41,
VAR34,
VAR81,
VAR42,
VAR32,
VAR84,
VAR12,
VAR49,
VAR30,
VAR28,
VAR3,
VAR66
);
parameter VAR78 = 1'b1;
parameter VAR4 = 1'b0;
parameter VAR36 = 2'b1;
parameter VAR46 = 2'b10;
parameter VAR1 = 32'b00000000000... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_adc_channel.v | 14,005 | module MODULE1 (
VAR59,
VAR74,
VAR56,
VAR23,
VAR38,
VAR40,
VAR19,
VAR10,
VAR48,
VAR26,
VAR72,
VAR20,
VAR73,
VAR44,
VAR37,
VAR7,
VAR81,
VAR32,
VAR63,
VAR51,
VAR24,
VAR77,
VAR21,
VAR25,
VAR80,
VAR3,
VAR76,
VAR67,
VAR47,
VAR42,
VAR68,
VAR83,
VAR61,
VAR34,
VAR39,
VAR14,
VAR78,
VAR49,
VAR58,
VAR15,
VAR18,
VAR50,
VAR75,
VAR1... | gpl-3.0 |
ptracton/vscale_soc | rtl/wb_intercon-1.0/rtl/verilog/wb_data_resize.v | 1,733 | module MODULE1
input [VAR2-1:0] VAR10,
input [3:0] VAR24,
input VAR1,
input VAR11,
input VAR14,
input [2:0] VAR20,
input [1:0] VAR3,
output [VAR2-1:0] VAR23,
output VAR26,
output VAR4,
output VAR6,
output [VAR21-1:0] VAR9,
output [VAR18-1:0] VAR15,
output VAR17,
output VAR8,
output VAR22,
output [2:0] VAR5,
output [1:0... | mit |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/er1.v | 7,357 | module MODULE1 (input VAR9,
input VAR16,
output VAR14,
output reg VAR17,
input VAR22,
input VAR10,
input VAR24,
input VAR18,
input [14:0] VAR25,
output reg [14:0] VAR2,
input VAR15,
output VAR7,
output VAR31);
wire VAR20;
wire VAR19;
wire [3:0] VAR38;
wire [9:0] VAR27;
wire VAR23;
assign VAR14 = VAR27[0];
VAR8 VAR13 (.... | lgpl-3.0 |
mdsalman729/flexpret_project | fpga/atlys/4tf-16i-16d/ispm_bram.v | 1,071 | module MODULE1(input clk,
input [11:0] VAR13,
input VAR8,
output[31:0] VAR15,
input [11:0] VAR2,
input VAR10,
output[31:0] VAR3,
input VAR12,
input [31:0] VAR4,
input [11:0] VAR17,
input VAR11,
input [31:0] VAR5,
output VAR7
);
genvar VAR1;
generate
for(VAR1 = 0; VAR1 < 8; VAR1 = VAR1+1)
begin: VAR6
reg [3:0] VAR14 [40... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41o/sky130_fd_sc_hd__a41o.behavioral.v | 1,558 | module MODULE1 (
VAR4 ,
VAR12,
VAR2,
VAR8,
VAR3,
VAR6
);
output VAR4 ;
input VAR12;
input VAR2;
input VAR8;
input VAR3;
input VAR6;
supply1 VAR15;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR11 ;
wire VAR10 ;
wire VAR13;
and VAR14 (VAR10 , VAR12, VAR2, VAR8, VAR3 );
or VAR5 (VAR13, VAR10, VAR6 );
buf VAR7 (VAR4 , VAR13 );
... | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/bram_512x4M.v | 3,451 | module MODULE1 (
address,
VAR2,
VAR34,
clk,
VAR10,
reset,
write,
VAR12,
VAR21
)
;
parameter VAR6 = 4194304;
parameter VAR27 = 4194304;
parameter VAR23 = 22;
output [511: 0] VAR21;
input [ 21: 0] address;
input [ 63: 0] VAR2;
input VAR34;
input clk;
input VAR10;
input reset;
input write;
input [511: 0] VAR12;
reg [511: ... | mit |
velizarefremov/MIPS | Part 3/Verilog Code/Program Counter/pc_param_behav.v | 2,196 | module MODULE1
parameter VAR18 = 4,
parameter VAR12 = 8)
(
output [VAR29-1:0] VAR36,
input [VAR12-1:0] VAR22,
input [VAR18-1:0] VAR9,
input [VAR18-1:0] VAR8,
input VAR19,
input VAR3,
input VAR24,
input clk,
input rst,
input VAR20
);
wire [VAR29-1:0] sum;
wire [VAR29-1:0] VAR21;
wire [VAR29-1:0] VAR32;
wire [VAR29-1:0] ... | gpl-2.0 |
siamumar/TinyGarbled | circuit_synthesis/a23/a23_multiply.v | 6,896 | module MODULE1 (
input VAR3,
input VAR10,
input [31:0] VAR1, input [31:0] VAR8, input [1:0] VAR12,
input VAR11,
output [31:0] VAR4,
output [1:0] VAR7, output VAR6 );
wire enable;
wire VAR5;
reg [31:0] VAR9;
reg [3:0] VAR2;
assign enable = VAR12[0];
assign VAR5 = VAR12[1];
assign VAR4 = VAR9;
assign VAR7 = {VAR4[31], VA... | gpl-3.0 |
Jbag/edge_detect | version_1/edge_detect.v | 1,510 | module MODULE1(
input clk, input VAR5, input VAR6, output VAR7, output VAR1, output VAR2 );
reg VAR4,VAR3,VAR8; always @(posedge clk or negedge VAR5)
begin
if(!VAR5)
begin
VAR4 <= 1'b0;
VAR3 <= 1'b0;
VAR8 <= 1'b0;
end
else
begin
VAR4 <= VAR6; VAR3 <= VAR4; VAR8 <= VAR3; end
end
assign VAR7 = VAR3 & ~VAR8; assign VAR1 =... | gpl-3.0 |
anderson1008/NOCulator | hring/hw/buffered/src/c_credit_tracker.v | 4,767 | module MODULE1
(clk, reset, VAR10, VAR12, VAR16, VAR5);
parameter VAR2 = 8;
parameter VAR21 = VAR14;
localparam VAR13 = VAR27(VAR2);
localparam VAR9 = VAR27(VAR2+1);
input clk;
input reset;
input VAR10;
input VAR12;
output VAR16;
wire VAR16;
output [0:1] VAR5;
wire [0:1] VAR5;
wire VAR18, VAR15;
wire VAR8, VAR4;
assign... | mit |
mdsalman729/flexpret_project | fpga/atlys/core/ispm_bram.v | 1,172 | module MODULE1(input clk,
input [11:0] VAR13,
input VAR17,
output[31:0] VAR14,
input [11:0] VAR6,
input VAR15,
output[31:0] VAR7,
input VAR4,
input [31:0] VAR18,
input [11:0] VAR11,
input VAR3,
output [31:0] VAR16,
input VAR9,
input [31:0] VAR1,
output VAR10
);
genvar VAR8;
generate
for(VAR8 = 0; VAR8 < 8; VAR8 = VAR8+... | bsd-3-clause |
AmeerAbdelhadi/Switched-Multiported-RAM | lvt_bin.v | 8,780 | module MODULE1
localparam VAR23 = VAR25(VAR12); localparam VAR32 = VAR25(VAR13 );
wire [VAR32-1:0] VAR8 [VAR13-1:0];
genvar VAR21;
generate
for (VAR21=0;VAR21<VAR13;VAR21=VAR21+1) begin: VAR9
assign VAR8[VAR21]=VAR21;
end
endgenerate
reg [VAR23*VAR13-1:0] VAR10; reg [ VAR13-1:0] VAR6 ; always @(posedge clk) begin
VAR10... | bsd-3-clause |
bigeagle/riffa | fpga/riffa_hdl/scsdpram.v | 2,940 | module MODULE1
parameter VAR4 = 32,
parameter VAR6 = 1024
)
(
input VAR2,
input VAR10,
input [VAR11(VAR6)-1:0] VAR5,
output [VAR4-1:0] VAR12,
input VAR3,
input [VAR11(VAR6)-1:0] VAR9,
input [VAR4-1:0] VAR1
);
reg [VAR4-1:0] VAR7 [VAR6-1:0];
reg [VAR4-1:0] VAR8;
assign VAR12 = VAR8;
always @(posedge VAR2) begin
if (VAR3... | bsd-3-clause |
sehugg/8bitworkshop | presets/verilog/scoreboard.v | 2,204 | module MODULE1(reset, VAR7, VAR9, VAR8, VAR14, VAR17);
input reset;
output reg [3:0] VAR7;
output reg [3:0] VAR9;
input VAR14;
output reg [3:0] VAR8;
input VAR17;
always @(posedge VAR14 or posedge reset)
begin
if (reset) begin
VAR7 <= 0;
VAR9 <= 0;
end else if (VAR7 == 9) begin
VAR7 <= 0;
VAR9 <= VAR9 + 1;
end else beg... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32oi/sky130_fd_sc_lp__a32oi.pp.blackbox.v | 1,467 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR3 ,
VAR2 ,
VAR9 ,
VAR10 ,
VAR8,
VAR6,
VAR1 ,
VAR7
);
output VAR4 ;
input VAR5 ;
input VAR3 ;
input VAR2 ;
input VAR9 ;
input VAR10 ;
input VAR8;
input VAR6;
input VAR1 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s.pp.blackbox.v | 1,345 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR3,
VAR6,
VAR2 ,
VAR1
);
output VAR5 ;
input VAR4 ;
input VAR3;
input VAR6;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
jameshegarty/rigel | platform/axi/dramreader.v | 2,556 | module MODULE1(
input wire VAR24,
input wire VAR20,
output reg [31:0] VAR9,
input wire VAR14,
output wire VAR4,
input wire [63:0] VAR25,
output wire VAR8,
input wire [1:0] VAR12,
input wire VAR21,
input wire VAR19,
output wire [3:0] VAR11,
output wire [1:0] VAR5,
output wire [1:0] VAR16,
input wire VAR3,
output wire VA... | mit |
HighlandersFRC/fpga | led_string_no_gpio/led_string.srcs/sources_1/new/main.v | 1,358 | module MODULE1 (
input VAR14,
output reset,
output VAR12, output VAR11,
output VAR8,
output VAR9,
output VAR15,
output VAR13,
output VAR6,
output VAR4
);
VAR2 VAR10();
assign VAR15 = 0;
assign VAR9 = 0;
assign reset = 0;
assign VAR12 = 0;
assign VAR11 = 0;
assign VAR8 = 0;
assign VAR6 = 0;
assign VAR4 = 0;
assign VAR13... | mit |
Tao-J/nexys3MIPSSoC | Coprocessor.v | 1,542 | module MODULE1(
input clk,
input rst,
input [4:0] VAR5,
input [4:0] VAR8,
input [31:0] VAR7,
input [31:0] VAR4,
input VAR6,
input VAR2,
input VAR10,
input [1:0] VAR11,
output [31:0] VAR3,
output [31:0] VAR9
);
reg [31:0] register[12:14];
integer VAR1;
assign VAR3 = register[VAR5];
assign VAR9 = register[14];
always @(p... | gpl-3.0 |
omicronns/studies-sys-rek | de1-soc/Sdram_Control/command.v | 19,749 | module MODULE1(
VAR4,
VAR25,
VAR10,
VAR15,
VAR17,
VAR7,
VAR54,
VAR33,
VAR58,
VAR3,
VAR24,
VAR19,
VAR43,
VAR40,
VAR53,
VAR52,
VAR35,
VAR29,
VAR59,
VAR5,
VAR12,
VAR48,
VAR50
);
input VAR4; input VAR25; input [VAR49-1:0] VAR10; input VAR15; input VAR17; input VAR7; input VAR54; input VAR33; input VAR58; input VAR3; input ... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/ip_top/clk_ibuf.v | 4,263 | module MODULE1 #
(
parameter VAR1 = "VAR9" )
(
input VAR19, input VAR12,
input VAR10,
output VAR8
);
wire VAR16;
generate
if (VAR1 == "VAR9") begin: VAR15
VAR5 #
(
.VAR18 ("VAR2"),
.VAR11 ("VAR13")
)
VAR17
(
.VAR14 (VAR19),
.VAR6 (VAR12),
.VAR7 (VAR16)
);
end else if (VAR1 == "VAR4") begin: VAR3
VAR20 #
(
.VAR11 ("VAR1... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkbuf/sky130_fd_sc_ls__clkbuf_8.v | 2,034 | module MODULE2 (
VAR5 ,
VAR8 ,
VAR2,
VAR7,
VAR4 ,
VAR3
);
output VAR5 ;
input VAR8 ;
input VAR2;
input VAR7;
input VAR4 ;
input VAR3 ;
VAR1 VAR6 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR5,
VAR8
);
output VAR5;
input VAR8;
supply1 VAR2;
supply0 VAR7;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux4/sky130_fd_sc_hd__mux4.symbol.v | 1,368 | module MODULE1 (
input VAR2,
input VAR6,
input VAR9,
input VAR11,
output VAR7 ,
input VAR10,
input VAR3
);
supply1 VAR8;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_4.behavioral.v | 1,188 | module MODULE1( VAR3, VAR2, VAR5 );
input VAR5, VAR2;
output VAR3;
VAR6 VAR1(.VAR3(VAR3),.VAR2(VAR2),.VAR5(VAR5));
VAR6 VAR4(.VAR3(VAR3),.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/uart_decoder.v | 13,720 | module MODULE1(
input clk,
input rst,
input [7:0] VAR24,
input VAR13,
output reg VAR20 = 1'b0,
output reg [6:0] VAR6 = 7'd0,
output reg VAR23 = 1'b0,
output reg [6:0] VAR11 = 7'd0,
output reg [14:0] VAR3 = 15'd0,
output reg [6:0] VAR14 = 7'd0,
output reg VAR18 = 1'b0,
output reg [4:0] VAR2 = 5'd0,
output reg VAR19 = 1'... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_pwrgood_l_pp_pg_s/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg_s.symbol.v | 1,368 | module MODULE1 (
input VAR5 ,
output VAR3,
input VAR2 ,
input VAR1 ,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfstp/sky130_fd_sc_hvl__dfstp.functional.pp.v | 2,095 | module MODULE1 (
VAR8 ,
VAR13 ,
VAR10 ,
VAR15,
VAR3 ,
VAR16 ,
VAR1 ,
VAR5
);
output VAR8 ;
input VAR13 ;
input VAR10 ;
input VAR15;
input VAR3 ;
input VAR16 ;
input VAR1 ;
input VAR5 ;
wire VAR6 ;
wire VAR14 ;
wire VAR11;
not VAR2 (VAR14 , VAR15 );
VAR18 VAR17 VAR9 (VAR6 , VAR10, VAR13, VAR14, , VAR3, VAR16);
buf VAR12... | apache-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/unused_reg.v | 2,176 | module MODULE1
parameter VAR8 = 5
)
(
input VAR2,
output VAR10,
input VAR7,
input [VAR8 - 1:0] VAR9,
output [VAR1 - 1:0] VAR11,
input [VAR1 - 1:0] VAR5,
input clk,
input reset
);
reg VAR3;
assign VAR11 = 'VAR6 VAR4;
assign VAR10 = VAR2 && !VAR3;
always @(posedge clk)
begin
VAR3 <= VAR2;
end
endmodule | apache-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.