repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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|---|---|---|---|---|
manu3193/GatoTDD | Gato_FSM.v | 2,716 | module MODULE1(
clk,
reset,
state,
VAR12,
VAR14,
VAR22,
VAR19,
VAR9,
VAR7,
VAR3,
VAR1,
VAR2,
VAR24,
VAR23,
VAR13,
VAR4,
VAR18
);
input clk, reset;
input VAR12, VAR14;
input VAR22, VAR19, VAR9, VAR7, VAR3, VAR1;
output reg VAR24, VAR23;
output reg VAR2;
output reg VAR13, VAR4, VAR18;
output [3:0] state;
reg [3:0] state,... | mit |
lbl-cal/StanfordNoC | router/src/vcr_sw_alloc_sep_if.v | 19,144 | module MODULE1
(clk, reset, VAR56, VAR11, VAR40, VAR55,
VAR95, VAR53, VAR68, VAR18, VAR33, VAR24);
parameter VAR15 = 4;
parameter VAR81 = 5;
parameter VAR79 = VAR82;
parameter VAR64 = VAR92;
parameter VAR3 = VAR44;
input clk;
input reset;
input [0:VAR81-1] VAR56;
input [0:VAR81-1] VAR11;
input [0:VAR81*VAR15*VAR81-1] V... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/edfxbp/sky130_fd_sc_ls__edfxbp.behavioral.pp.v | 2,321 | module MODULE1 (
VAR5 ,
VAR15 ,
VAR19 ,
VAR10 ,
VAR9 ,
VAR12,
VAR14,
VAR11 ,
VAR1
);
output VAR5 ;
output VAR15 ;
input VAR19 ;
input VAR10 ;
input VAR9 ;
input VAR12;
input VAR14;
input VAR11 ;
input VAR1 ;
wire VAR3 ;
reg VAR20 ;
wire VAR18 ;
wire VAR4 ;
wire VAR8;
wire VAR13 ;
wire VAR2 ;
wire VAR16 ;
VAR22 VAR23 (V... | apache-2.0 |
AmeerAbdelhadi/Indirectly-Indexed-2D-Binary-Content-Addressable-Memory-BCAM | camctl.v | 6,025 | module MODULE1
( input clk , input rst , input VAR10 , input VAR15 , input VAR8, input VAR12, input VAR9,
output reg VAR4 , output reg VAR13 , output reg VAR14 , output reg VAR18 , output reg VAR7 , output reg VAR3 , output reg VAR2 , output reg VAR6 );
reg [1:0] VAR16, VAR11 ;
localparam VAR5 = 2'b00;
localparam VAR1 ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.v | 2,482 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR9,
VAR5 ,
VAR3 ,
VAR8 ,
VAR7 ,
VAR1 ,
VAR10
);
output VAR6 ;
output VAR4 ;
input VAR9;
input VAR5 ;
input VAR3 ;
input VAR8 ;
input VAR7 ;
input VAR1 ;
input VAR10 ;
VAR11 VAR2 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1),
.VA... | apache-2.0 |
karatekid/ultrasonic-fountain | hardware/src/avr_interface.v | 4,342 | module MODULE1 #(
parameter VAR62 = 50000000,
parameter VAR9 = 500000
)(
input clk,
input rst,
input VAR42,
output ready,
output VAR25,
input VAR19,
input VAR45,
input VAR10,
output VAR41,
input VAR48,
output [7:0] VAR60,
output VAR11,
input [7:0] VAR54,
input VAR20,
output VAR23,
input VAR57,
output [5:0] VAR44,
outpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221a/sky130_fd_sc_lp__o221a_2.v | 2,444 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR7 ,
VAR11 ,
VAR5 ,
VAR10 ,
VAR2,
VAR9,
VAR12 ,
VAR8
);
output VAR6 ;
input VAR4 ;
input VAR7 ;
input VAR11 ;
input VAR5 ;
input VAR10 ;
input VAR2;
input VAR9;
input VAR12 ;
input VAR8 ;
VAR1 VAR3 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR2... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/tlu/rtl/sparc_tlu_intctl.v | 20,831 | module MODULE1(
VAR87, VAR44, VAR48, VAR85, VAR26,
VAR63, VAR34, VAR65,
VAR57, VAR12, VAR50,
VAR74, VAR20, VAR70, VAR66,
VAR54, VAR18, VAR40,
VAR35, VAR46, VAR55, VAR21, VAR7, VAR5, VAR92, VAR3,
VAR62, VAR59, VAR24, VAR60,
VAR16, VAR75, VAR1, VAR39,
VAR82, VAR10, VAR4, VAR27,
VAR13, VAR43, VAR93, VAR86);
input VAR35, V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd/sky130_fd_sc_hdll__tapvgnd.pp.blackbox.v | 1,264 | module MODULE1 (
VAR2,
VAR3,
VAR1 ,
VAR4
);
input VAR2;
input VAR3;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
cpulabs/mist1032isa | src/dps/sci/dps_sci.v | 9,350 | module MODULE1(
input wire VAR45,
input wire VAR59,
input wire VAR21,
output wire VAR7,
output wire VAR1,
input wire VAR42,
output wire VAR60, input wire VAR28,
input wire [1:0] VAR31,
input wire [31:0] VAR10,
output wire VAR40,
output wire [31:0] VAR16,
output wire VAR8,
input wire VAR43,
output wire VAR44,
input wire... | bsd-2-clause |
FAST-Switch/fast | lib/hardware/pipeline/FIFO_OPENFLOW/ram_32_49.v | 9,581 | module MODULE1 (
VAR41,
VAR32,
VAR36,
VAR3,
VAR19,
VAR28,
VAR60,
VAR42);
input VAR41;
input VAR32;
input [48:0] VAR36;
input [4:0] VAR3;
input VAR19;
input [4:0] VAR28;
input VAR60;
output [48:0] VAR42;
tri0 VAR41;
tri1 VAR32;
tri1 VAR19;
tri0 VAR60;
wire [48:0] VAR56;
wire [48:0] VAR42 = VAR56[48:0];
VAR13 VAR52 (
.VA... | apache-2.0 |
d16-processor/d16 | verilog/src/control.v | 3,921 | module MODULE1(
input wire clk,
input wire en,
input wire rst,
input wire VAR6,
input wire VAR25,
input wire VAR16,
input wire VAR34,
output reg [VAR13:0] VAR14,
output reg [1:0] VAR5
);
localparam VAR3 = 0,
VAR19 = 4'h1,
VAR29 = 4'h2,
VAR28 = 4'h3,
VAR31 = 4'h4,
VAR27 = 4'h5,
VAR21 = 4'h6,
VAR4 = 4'h7,
VAR32 = 4'h8;
r... | mit |
binderclip/BCOpenMIPS | cpu-code/ex.v | 17,712 | module MODULE1 (
input wire rst,
input wire[VAR32] VAR77,
input wire[VAR43] VAR74,
input wire[VAR10] VAR65,
input wire[VAR10] VAR12,
input wire[VAR19] VAR56,
input wire VAR41,
input wire[VAR10] VAR16,
input wire VAR5,
input wire[VAR10] VAR55,
input wire[VAR10] VAR91,
input wire[VAR10] VAR23,
input wire VAR57,
input wir... | mit |
timtian090/Playground | UVM/UVMPlayground/Lab3/Lab3-Project/Switch_Debounce_Synchronizer.v | 2,490 | module MODULE1
parameter VAR6 = 50000000, parameter VAR3 = 10000, parameter VAR1 = 1'b0
)
(
input VAR5,
output reg VAR10,
input VAR8
);
localparam VAR13 = VAR3 / (1000000000.0 / VAR6);
localparam VAR2 = VAR7(VAR13);
localparam VAR14 = {1'b1, {(VAR2){1'b0}}} - VAR13;
reg [2:0] VAR12;
reg [VAR2:0] VAR4;
wire VAR9;
wire V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fa/sky130_fd_sc_ms__fa.functional.v | 1,881 | module MODULE1 (
VAR2,
VAR16 ,
VAR13 ,
VAR15 ,
VAR3
);
output VAR2;
output VAR16 ;
input VAR13 ;
input VAR15 ;
input VAR3 ;
wire VAR5 ;
wire VAR18 ;
wire VAR7 ;
wire VAR12 ;
wire VAR10 ;
wire VAR20 ;
wire VAR8;
wire VAR21 ;
or VAR22 (VAR5 , VAR3, VAR15 );
and VAR19 (VAR18 , VAR5, VAR13 );
and VAR4 (VAR7 , VAR15, VAR3 )... | apache-2.0 |
adbrant/zuma-fpga | verilog/platforms/xilinx/elut_xilinx.v | 4,035 | module MODULE1(
VAR1,
VAR29,
VAR45,
clk,
VAR43,
VAR19,
VAR33,
VAR32,
VAR61
);
input [5 : 0] VAR1;
input [0 : 0] VAR29;
input [5 : 0] VAR45;
input clk;
input VAR43;
input VAR19;
input VAR33;
output [0 : 0] VAR32;
output [0 : 0] VAR61;
VAR10 #(
.VAR62(6),
.VAR2("0"),
.VAR13(64),
.VAR22("VAR35"),
.VAR39(1),
.VAR26(1),
.VA... | bsd-2-clause |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/top/rdcost_decision.v | 24,387 | module MODULE1 (
clk ,
VAR132 ,
VAR13 ,
VAR261 ,
VAR34 ,
VAR121 ,
VAR156 ,
VAR232 ,
VAR265 ,
VAR262 ,
VAR251 ,
VAR45 ,
VAR61 ,
VAR28
);
input clk ;
input VAR132 ;
input VAR13 ;
input [5 : 0] VAR261 ;
input [1 : 0] VAR34 ;
input [1 : 0] VAR121 ;
input [7 : 0] VAR156 ;
input VAR232 ;
input [511 : 0] VAR265 ;
input VAR262... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4bb/sky130_fd_sc_hdll__or4bb.pp.blackbox.v | 1,353 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR1 ,
VAR9 ,
VAR3 ,
VAR4,
VAR6,
VAR2 ,
VAR7
);
output VAR8 ;
input VAR5 ;
input VAR1 ;
input VAR9 ;
input VAR3 ;
input VAR4;
input VAR6;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/ethmac/eth_wishbone.v | 78,506 | module MODULE1
(
VAR38, VAR206, VAR298,
VAR269, VAR45, VAR91,
VAR69,
VAR275,
VAR253, VAR67, VAR26,
VAR249, VAR183, VAR224,
VAR118, VAR137, VAR307,
VAR295, VAR139,
VAR228, VAR288, VAR74, VAR290, VAR63,
VAR205, VAR90, VAR271, VAR144, VAR46,
VAR209,
VAR177, VAR87, VAR25, VAR242, VAR119, VAR80,
VAR11,
VAR154, VAR313, VAR18... | mit |
tugrulyatagan/RISC-processor | xilinx_processor/pipeline_control_registers.v | 2,531 | module MODULE1(
input VAR17,
input VAR25,
input VAR11,
input [2:0] VAR27,
input VAR18,
input VAR9,
input [7:0] VAR4,
input VAR24,
input [15:0] VAR1,
input [2:0] VAR12,
input [2:0] VAR13,
output reg VAR7,
output reg [2:0] VAR16,
output reg VAR10,
output reg VAR8,
output reg [7:0] VAR5,
output reg VAR21,
output reg [15:0... | gpl-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ip/block_design_m01_regslice_0/synth/block_design_m01_regslice_0.v | 10,722 | module MODULE1 (
VAR57,
VAR24,
VAR93,
VAR35,
VAR58,
VAR3,
VAR40,
VAR67,
VAR52,
VAR1,
VAR60,
VAR42,
VAR22,
VAR30,
VAR49,
VAR92,
VAR65,
VAR86,
VAR21,
VAR25,
VAR99,
VAR23,
VAR16,
VAR77,
VAR55,
VAR9,
VAR89,
VAR5,
VAR76,
VAR91,
VAR106,
VAR50,
VAR75,
VAR54,
VAR107,
VAR19,
VAR17,
VAR20,
VAR82,
VAR51
);
input wire VAR57;
input... | gpl-3.0 |
CospanDesign/nysa-sdio-device | functions/nysa_host_interface/sdio_host_interface.v | 1,504 | module MODULE1 (
input clk,
input rst
);
localparam VAR1 = 32'h00000000;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdlclkp/sky130_fd_sc_hs__sdlclkp.pp.symbol.v | 1,299 | module MODULE1 (
input VAR1 ,
input VAR3 ,
input VAR6,
output VAR2,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v | 12,602 | module MODULE1 (
output wire [14:0] VAR21, output wire [2:0] VAR50, output wire VAR18, output wire VAR49, output wire VAR67, output wire VAR26, output wire VAR25, output wire VAR16, output wire VAR72, output wire VAR3, inout wire [31:0] VAR36, inout wire [3:0] VAR47, inout wire [3:0] VAR57, output wire VAR75, output wi... | mit |
Tommydag/CAN-Bus-Controller | Main.v | 1,258 | module MODULE1(
output VAR11,
input VAR16,
input VAR8,
input VAR4,
input VAR13,
input[7:0] VAR3
);
wire[63:0] VAR10;
wire VAR7;
assign VAR10 = {8{VAR3}};
parameter address = 11'h25, VAR12 = 1'b1;
VAR9 VAR5(VAR4,clk);
VAR6 VAR14(clk,VAR8,VAR15);
VAR1 VAR2(VAR11,VAR7,VAR16,VAR12,address,clk,VAR15,VAR8,VAR10,VAR13);
endmo... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufinv/sky130_fd_sc_hdll__bufinv.pp.symbol.v | 1,280 | module MODULE1 (
input VAR4 ,
output VAR5 ,
input VAR6 ,
input VAR2,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/vrt/vita_tx_chain.v | 7,370 | module MODULE1
parameter VAR103=10,
parameter VAR20=10,
parameter VAR25=0,
parameter VAR105=0,
parameter VAR3=0,
parameter VAR128=0,
parameter VAR41=0)
(input clk, input reset,
input VAR62, input [7:0] VAR2, input [31:0] VAR122,
input VAR54, input [7:0] VAR96, input [31:0] VAR31,
input [63:0] VAR121,
input [35:0] VAR19... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ha/sky130_fd_sc_ms__ha_2.v | 2,184 | module MODULE1 (
VAR9,
VAR1 ,
VAR7 ,
VAR8 ,
VAR10,
VAR2,
VAR6 ,
VAR3
);
output VAR9;
output VAR1 ;
input VAR7 ;
input VAR8 ;
input VAR10;
input VAR2;
input VAR6 ;
input VAR3 ;
VAR4 VAR5 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE1... | apache-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_frame_len.v | 3,499 | module MODULE1 #
(
parameter VAR13 = 64,
parameter VAR6 = (VAR13>8),
parameter VAR18 = (VAR13/8),
parameter VAR5 = 16
)
(
input wire clk,
input wire rst,
input wire [VAR18-1:0] VAR1,
input wire VAR7,
input wire VAR17,
input wire VAR10,
output wire [VAR5-1:0] VAR3,
output wire VAR15
);
reg [VAR5-1:0] VAR8 = 0, VAR14;
re... | mit |
SiLab-Bonn/basil | basil/firmware/modules/utils/clock_divider.v | 2,349 | module MODULE1 #(
parameter VAR7 = 40000000
) (
input wire VAR3,
input wire VAR5,
output reg VAR8, output reg VAR2 );
integer VAR6;
VAR1 VAR6 = 0;
integer VAR4;
VAR1 VAR4 = 0;
VAR1 VAR2 = 1'b0;
VAR1 VAR8 = 1'b0;
always @(posedge VAR3 or posedge VAR5)
begin
if (VAR5 == 1'b1)
begin
VAR8 <= 1'b0;
end
else
begin
if (VAR6 =... | bsd-3-clause |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_066.v | 1,564 | module MODULE1 (
VAR6,
VAR10
);
input [31:0] VAR6;
output [31:0]
VAR10;
wire [31:0]
VAR13,
VAR9,
VAR5,
VAR2,
VAR8,
VAR15,
VAR4,
VAR14,
VAR12,
VAR1;
assign VAR13 = VAR6;
assign VAR8 = VAR5 - VAR2;
assign VAR5 = VAR9 - VAR13;
assign VAR9 = VAR13 << 10;
assign VAR4 = VAR5 + VAR15;
assign VAR2 = VAR13 << 1;
assign VAR1 = V... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_pcie_pipe_misc.v | 8,089 | module MODULE1 #
(
parameter VAR16 = 0 )
(
input wire VAR25 , input wire VAR7 , input wire VAR15 , input wire VAR26 , input wire [2:0] VAR29 , input wire VAR1 ,
output wire VAR10 , output wire VAR9 , output wire VAR17 , output wire VAR27 , output wire [2:0] VAR14 , output wire VAR20 ,
input wire VAR2 , input wire VAR30... | lgpl-3.0 |
brysonli12/CS152A-Lab4-TicTacToe | AI/Lookup.v | 9,235 | module MODULE3 (
input [8:0] VAR5,
input [8:0] VAR18,
output wire [8:0] VAR3
);
wire [8:0] VAR7, VAR4, VAR17, VAR1, VAR12;
MODULE2 MODULE1 (VAR5, VAR18, VAR7);
MODULE2 MODULE5 ({VAR5[6], VAR5[3], VAR5[0], VAR5[7], VAR5[4], VAR5[1], VAR5[8], VAR5[5], VAR5[2]},
{VAR18[6], VAR18[3], VAR18[0], VAR18[7], VAR18[4], VAR18[1],... | mit |
migajv/mips_pipeline | verilog/im.v | 2,082 | module MODULE1(
input wire clk,
input wire rst,
input wire [31:0] addr,
input wire [31:0] VAR9,
input wire [31:0] VAR13,
input wire VAR12,
input wire VAR3,
input VAR1,
input VAR4,
output logic [31:0] VAR6,
output logic [31:0] VAR2,
output logic VAR10
);
parameter VAR5 = 128; parameter VAR14 = "VAR13.VAR7";
reg [31:0] V... | gpl-3.0 |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_VCU118/mkBoot_ROM.v | 54,584 | module MODULE1(VAR3,
VAR163,
VAR172,
VAR69,
VAR151,
VAR125,
VAR72,
VAR8,
VAR83,
VAR178,
VAR109,
VAR105,
VAR17,
VAR91,
VAR60,
VAR57,
VAR33,
VAR94,
VAR98,
VAR117,
VAR104,
VAR25,
VAR175,
VAR124,
VAR152,
VAR7,
VAR1,
VAR119,
VAR123,
VAR77,
VAR106,
VAR68,
VAR5,
VAR171,
VAR150,
VAR120,
VAR81,
VAR108,
VAR28,
VAR159,
VAR73,
VAR... | apache-2.0 |
cpulabs/mist1032isa | src/core/l1_data/l1_data_cache_64entry_4way_line64b_bus_8b_disable_cache.v | 1,736 | module MODULE1(
input wire VAR15,
input wire VAR22,
input wire VAR21,
input wire VAR1,
input wire VAR5,
output wire VAR24,
input wire [31:0] VAR4, output wire VAR18,
output wire VAR20,
input wire VAR14,
output wire [31:0] VAR17,
output wire [11:0] VAR10,
input wire VAR7,
output wire VAR3,
input wire [1:0] VAR16,
input ... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addh/gf180mcu_fd_sc_mcu9t5v0__addh_1.behavioral.pp.v | 1,568 | module MODULE1( VAR5, VAR6, VAR9, VAR8, VAR7, VAR1 );
input VAR6, VAR9;
inout VAR7, VAR1;
output VAR5, VAR8;
VAR2 VAR3(.VAR5(VAR5),.VAR6(VAR6),.VAR9(VAR9),.VAR8(VAR8),.VAR7(VAR7),.VAR1(VAR1));
VAR2 VAR4(.VAR5(VAR5),.VAR6(VAR6),.VAR9(VAR9),.VAR8(VAR8),.VAR7(VAR7),.VAR1(VAR1)); | apache-2.0 |
Pylonight/MIPS-CPU | cpu/Instruction_Memory.v | 4,965 | module MODULE1(
output [15 : 0] VAR1,
input [15 : 0] address
);
reg [15 : 0] memory [255 : 0];
begin | gpl-2.0 |
jotego/jt12 | hdl/jt12_eg_cnt.v | 1,322 | module MODULE1(
input rst,
input clk,
input VAR3 ,
input VAR4,
output reg [14:0] VAR1
);
reg [1:0] VAR5;
always @(posedge clk, posedge rst) begin : VAR2
if( rst ) begin
VAR5 <= 2'd0;
VAR1 <=15'd0;
end
else begin
if( VAR4 && VAR3 ) begin
if( VAR5 == 2'd2 ) begin
VAR1 <= VAR1 + 1'b1;
VAR5 <= 2'd0;
end
else VAR5 <= VAR5 +... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9122/axi_ad9122_core.v | 8,625 | module MODULE1 (
VAR72,
VAR40,
VAR85,
VAR28,
VAR1,
VAR5,
VAR73,
VAR66,
VAR21,
VAR83,
VAR89,
VAR44,
VAR43,
VAR36,
VAR49,
VAR32,
VAR17,
VAR14,
VAR57,
VAR67,
VAR33,
VAR65,
VAR7,
VAR64,
VAR25,
VAR86,
VAR53,
VAR87,
VAR79,
VAR59,
VAR2,
VAR18,
VAR78,
VAR63,
VAR42,
VAR82,
VAR46,
VAR30,
VAR16,
VAR38,
VAR50,
VAR61,
VAR11,
VAR15,... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | src/regfileww.v | 1,876 | module MODULE1(VAR6, VAR8, VAR4, VAR5, VAR10, VAR13,
VAR1, VAR9, VAR11, VAR3, clk);
output [0:127] VAR6, VAR8;
input [0:127] VAR4;
input clk;
input VAR11;
input VAR1, VAR9;
input [0:4] VAR13, VAR5, VAR10;
input [0:15] VAR3;
reg [0:127] VAR6, VAR8;
reg [0:127] VAR7 [0:31];
reg [0:127] VAR2, VAR12;
always @(posedge clk)
... | mit |
monotone-RK/FACE | MCSoC-15/4-way_2-parallel/src/vivado_ip_dram/phy/mig_7series_v2_3_ddr_phy_ocd_lim.v | 21,190 | module MODULE1 #
(parameter VAR5 = 7,
parameter VAR85 = 3,
parameter VAR23 = 9,
parameter VAR31 = 100,
parameter VAR13 = 56,
parameter VAR12 = 60,
parameter VAR88 = "VAR86")
(
VAR105, VAR44, VAR34, VAR17,
VAR108, VAR32, VAR100, VAR73, VAR56,
VAR29, VAR47, VAR15,
clk, rst, VAR84, VAR89, VAR10,
VAR1, VAR91,
VAR53, VAR94,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222o/sky130_fd_sc_hs__a222o_1.v | 2,402 | module MODULE2 (
VAR6 ,
VAR7 ,
VAR1 ,
VAR9 ,
VAR11 ,
VAR5 ,
VAR10 ,
VAR8,
VAR2
);
output VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR9 ;
input VAR11 ;
input VAR5 ;
input VAR10 ;
input VAR8;
input VAR2;
VAR4 VAR3 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR8(VAR8),
... | apache-2.0 |
peteasa/oh | src/common/hdl/oh_debouncer.v | 2,182 | module MODULE1 #( parameter VAR9 = 100, parameter VAR20 = 0.00001 )
(
input clk, input VAR6, input VAR1, output VAR3 );
parameter integer VAR14 = VAR18(VAR9/VAR20);
reg VAR10;
reg VAR3;
VAR21 VAR8 (.dout (VAR2),
.clk (clk),
.VAR6 (VAR6),
.din (VAR1));
VAR11 VAR17 (.VAR15 (VAR23),
.clk (clk),
.VAR7 (VAR6));
always @ (po... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o31ai/sky130_fd_sc_hdll__o31ai.pp.symbol.v | 1,367 | module MODULE1 (
input VAR8 ,
input VAR5 ,
input VAR4 ,
input VAR9 ,
output VAR1 ,
input VAR3 ,
input VAR7,
input VAR6,
input VAR2
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbus_common/rtl/bw_io_dtlhstl_rcv.v | 1,967 | module MODULE1 (
out, VAR8,
VAR13, ref, clk, VAR3, VAR12, VAR1, VAR9, VAR4
);
input VAR13;
input ref;
input clk;
input VAR3;
input VAR12;
input VAR1;
input VAR9;
input VAR4;
output out;
output VAR8;
assign VAR8 = out;
wire VAR10 = VAR9;
reg out;
always @(posedge clk) begin
casex ({ VAR3, VAR13, VAR12, VAR1 })
4'VAR2: o... | gpl-2.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_charReceived.v | 3,460 | module MODULE1 (
address,
VAR1,
clk,
VAR14,
VAR4,
VAR11,
VAR9,
irq,
VAR10
)
;
output irq;
output [ 31: 0] VAR10;
input [ 1: 0] address;
input VAR1;
input clk;
input VAR14;
input VAR4;
input VAR11;
input [ 31: 0] VAR9;
wire VAR15;
reg VAR12;
reg VAR3;
wire VAR6;
reg VAR7;
wire VAR5;
wire VAR13;
wire irq;
reg VAR8;
wire ... | gpl-3.0 |
MeshSr/onetswitch45 | ons45-app21-ref_switch/vivado/onets_7045_4x_ref_switch/ip/ref_switch_core/src/udp/udp_reg_master.v | 4,990 | module MODULE1
parameter VAR9 = 0,
parameter VAR27 = 127,
parameter VAR15 = 'VAR26 VAR8,
parameter VAR16 = 2
)
(
input VAR5,
output reg VAR19,
input VAR18,
input [VAR23 - 1:0] VAR11,
output reg [VAR10 - 1:0]VAR12,
input [VAR10 - 1:0] VAR3,
output reg VAR7,
output reg VAR4,
output reg VAR29,
output reg [VAR23 - 1:0] VAR... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/inv/sky130_fd_sc_hvl__inv.blackbox.v | 1,208 | module MODULE1 (
VAR5,
VAR6
);
output VAR5;
input VAR6;
supply1 VAR1;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufinv/sky130_fd_sc_hs__bufinv.behavioral.pp.v | 1,680 | module MODULE1 (
VAR3,
VAR1,
VAR5 ,
VAR4
);
input VAR3;
input VAR1;
output VAR5 ;
input VAR4 ;
wire VAR10 ;
wire VAR7;
not VAR9 (VAR10 , VAR4 );
VAR6 VAR2 (VAR7, VAR10, VAR3, VAR1);
buf VAR8 (VAR5 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2.pp.symbol.v | 1,357 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR4 ,
input VAR1,
input VAR6,
input VAR5
);
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/neek/bench/x28fxxxp30.v | 107,427 | module MODULE1(VAR27, VAR8, VAR31, VAR28, VAR14, VAR23, VAR3, VAR35, VAR29);
input [VAR2-1:0] VAR27; input [VAR10-1:0] VAR8;
input VAR31, VAR28, VAR14, VAR23, VAR3, VAR35;
input [VAR40] VAR29;
integer VAR4;
integer VAR39;
integer VAR15;
integer VAR25;
integer VAR37;
integer VAR21;
integer VAR11;
integer VAR17;
integer ... | gpl-2.0 |
alexforencich/verilog-ethernet | rtl/ptp_clock.v | 10,624 | module MODULE1 #
(
parameter VAR53 = 4,
parameter VAR54 = 4,
parameter VAR1 = 4,
parameter VAR51 = 16,
parameter VAR39 = 4'h6,
parameter VAR61 = 16'h6666,
parameter VAR32 = 1,
parameter VAR38 = 4'h0,
parameter VAR17 = 16'h0002,
parameter VAR65 = 16'h0005,
parameter VAR11 = 0
)
(
input wire clk,
input wire rst,
input wi... | mit |
bluespec/Flute | src_SSITH_P2/Verilog_RTL/mkAxiLowPower.v | 1,920 | module MODULE1(VAR10,
VAR6,
VAR12,
VAR8,
VAR7);
input VAR10;
input VAR6;
input VAR12;
output VAR8;
output VAR7;
wire VAR7, VAR8;
reg VAR4;
wire VAR1, VAR9;
wire VAR5, VAR11;
assign VAR5 = 1'd1 ;
assign VAR11 = 1'd1 ;
assign VAR8 = VAR4 ;
assign VAR7 = 1'd1 ;
assign VAR1 = VAR12 ;
assign VAR9 = 1'd1 ;
always@(posedge VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22oi/sky130_fd_sc_hs__a22oi.behavioral.v | 2,058 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR1 ,
VAR12 ,
VAR10 ,
VAR9,
VAR14
);
output VAR3 ;
input VAR5 ;
input VAR1 ;
input VAR12 ;
input VAR10 ;
input VAR9;
input VAR14;
wire VAR10 VAR4 ;
wire VAR10 VAR17 ;
wire VAR11 ;
wire VAR13;
nand VAR2 (VAR4 , VAR1, VAR5 );
nand VAR15 (VAR17 , VAR10, VAR12 );
and VAR8 (VAR11 , VAR4, VAR1... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcomms2/c5soc/system_top.v | 17,849 | module MODULE1 (
VAR254,
VAR249,
VAR155,
VAR232,
VAR18,
VAR187,
VAR301,
VAR220,
VAR34,
VAR127,
VAR104,
VAR26,
VAR138,
VAR4,
VAR146,
VAR2,
VAR309,
VAR263,
VAR323,
VAR123,
VAR36,
VAR213,
VAR170,
VAR184,
VAR224,
VAR27,
VAR117,
VAR324,
VAR96,
VAR142,
VAR141,
VAR109,
VAR42,
VAR145,
VAR212,
VAR121,
VAR251,
VAR79,
VAR143,
VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4/sky130_fd_sc_ms__or4.blackbox.v | 1,269 | module MODULE1 (
VAR8,
VAR2,
VAR5,
VAR6,
VAR9
);
output VAR8;
input VAR2;
input VAR5;
input VAR6;
input VAR9;
supply1 VAR4;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Control_DQ_Currents.v | 4,769 | module MODULE1
(
VAR15,
reset,
VAR8,
VAR19,
VAR7,
VAR28,
VAR24,
VAR14,
VAR23,
VAR6,
VAR21
);
input VAR15;
input reset;
input VAR8;
input VAR19;
input signed [17:0] VAR7; input signed [17:0] VAR28; input signed [17:0] VAR24; input signed [17:0] VAR14; input signed [17:0] VAR23; output signed [17:0] VAR6; output signed [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc.functional.pp.v | 2,064 | module MODULE1 (
VAR10 ,
VAR9,
VAR4 ,
VAR5 ,
VAR3 ,
VAR6 ,
VAR11
);
output VAR10 ;
input VAR9;
input VAR4 ;
input VAR5 ;
input VAR3 ;
input VAR6 ;
input VAR11 ;
wire VAR15 ;
wire VAR7 ;
wire VAR8;
not VAR12 (VAR15 , VAR9 );
and VAR14 (VAR7 , VAR15, VAR4 );
VAR13 VAR2 (VAR8, VAR7, VAR5, VAR3, VAR9);
buf VAR1 (VAR10 , VA... | apache-2.0 |
megari/sd2snes | verilog/sd2snes_gsu/gsu.v | 24,091 | module MODULE1(
input VAR74,
input [7:0] VAR131,
output [7:0] VAR102,
input [23:0] VAR35,
input VAR68,
input VAR28,
input [7:0] VAR82,
output [23:0] VAR123,
output VAR133,
input VAR96,
input [7:0] VAR113,
input [7:0] VAR117,
output [18:0] VAR134,
output VAR135,
output VAR78,
input VAR112,
output VAR56,
output VAR106,
o... | gpl-2.0 |
walkthetalk/fsref | ip/s2mm/src/include/FIFO2MM.v | 7,910 | module MODULE1 #
(
parameter integer VAR33 = 12,
parameter integer VAR28 = 16,
parameter integer VAR29 = 32,
parameter integer VAR10 = 32,
parameter integer VAR25 = 12,
parameter integer VAR56 = 12,
parameter integer VAR38 = 4
)
(
input wire VAR15,
output wire VAR43,
input wire [VAR25-1:0] VAR27,
input wire [VAR56-1:0]... | gpl-3.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/user_logic_if/user_logic_top.v | 6,248 | module MODULE1(
input VAR41, input VAR59, input VAR27,
input VAR43,
input [31:0] VAR39,
input [19:0] VAR20,
input VAR53,
output [31:0] VAR1,
output VAR54,
input VAR66,
output [255:0] VAR5,
output [31:0] VAR28,
output VAR33,
output [26:0] VAR47,
output VAR38,
input [255:0] VAR35,
input VAR23,
input VAR4,
input VAR46,
in... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi.symbol.v | 1,460 | module MODULE1 (
input VAR8,
input VAR5,
input VAR6 ,
input VAR3 ,
output VAR7
);
supply1 VAR9;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
Siliciumer/DOS-Mario-FPGA | DOS_Mario.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v | 7,150 | module MODULE1
( input VAR60,
output VAR37,
output VAR33,
input reset,
output VAR15
);
wire VAR89;
wire VAR26;
VAR81 VAR62
(.VAR22 (VAR89),
.VAR47 (VAR60));
wire VAR38;
wire VAR12;
wire VAR51;
wire VAR30;
wire VAR19;
wire VAR65;
wire VAR68;
wire [15:0] VAR25;
wire VAR41;
wire VAR92;
wire VAR66;
wire VAR73;
wire VAR29;
... | mit |
UA3MQJ/fpga-synth | modules/note_pitch2dds.v | 2,367 | module MODULE1(clk, VAR7, VAR10, VAR8, VAR15, VAR2, VAR20);
input wire clk;
input wire [6:0] VAR7;
input wire [13:0] VAR10;
input wire [7:0] VAR8;
input wire [6:0] VAR15;
input wire [6:0] VAR2;
output reg [31:0] VAR20;
wire signed [7:0] VAR12 = VAR7; wire signed [16:0] VAR13 = VAR12 <<< 8;
wire signed [14:0] VAR5 = VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31o/sky130_fd_sc_hdll__a31o.pp.symbol.v | 1,374 | module MODULE1 (
input VAR8 ,
input VAR3 ,
input VAR6 ,
input VAR5 ,
output VAR9 ,
input VAR1 ,
input VAR2,
input VAR4,
input VAR7
);
endmodule | apache-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_int_mult32u.v | 1,992 | module MODULE1 (
enable,
VAR4,
VAR10,
VAR12,
VAR14);
parameter VAR20 = 32;
parameter VAR7 = 32;
input enable;
input VAR4;
input [VAR20 - 1 : 0] VAR10;
input [VAR7 - 1 : 0] VAR12;
output reg[31:0] VAR14;
wire [VAR20 + VAR7 - 1 : 0] VAR9;
VAR11 VAR18 (
.VAR4 (VAR4),
.VAR12 (VAR12),
.VAR16 (enable),
.VAR10 (VAR10),
.VAR14... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_1.v | 2,615 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR1 ,
VAR6 ,
VAR12 ,
VAR7 ,
VAR13,
VAR11 ,
VAR3 ,
VAR5 ,
VAR10
);
output VAR8 ;
output VAR2 ;
input VAR1 ;
input VAR6 ;
input VAR12 ;
input VAR7 ;
input VAR13;
input VAR11 ;
input VAR3 ;
input VAR5 ;
input VAR10 ;
VAR4 VAR9 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR12(VAR... | apache-2.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_mid/bg_mid_stub.v | 1,264 | module MODULE1(VAR3, VAR4, VAR5, VAR1, VAR2)
;
input VAR3;
input [0:0]VAR4;
input [14:0]VAR5;
input [11:0]VAR1;
output [11:0]VAR2;
endmodule | gpl-3.0 |
bmartini/verilog-arbiter | src/example.v | 1,828 | module MODULE1
VAR3 = 3,
VAR1 = 10)
(input clk,
input rst,
input [VAR3-1:0] request,
output [VAR3-1:0] VAR2,
output VAR4
); | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hs__udp_dff_pr_pp_pg_n.symbol.v | 1,478 | module MODULE1 (
input VAR1 ,
output VAR5 ,
input VAR6 ,
input VAR2 ,
input VAR7,
input VAR4 ,
input VAR3
);
endmodule | apache-2.0 |
twlostow/dsi-shield | hdl/rtl/hpdmc/spartan6/hpdmc_iobuf32.v | 2,882 | module MODULE1(
input [31:0] VAR23,
input [31:0] VAR15,
output [31:0] VAR7,
inout [31:0] VAR27
);
VAR36 VAR2(
.VAR23(VAR23[0]),
.VAR15(VAR15[0]),
.VAR7(VAR7[0]),
.VAR27(VAR27[0])
);
VAR36 VAR9(
.VAR23(VAR23[1]),
.VAR15(VAR15[1]),
.VAR7(VAR7[1]),
.VAR27(VAR27[1])
);
VAR36 VAR20(
.VAR23(VAR23[2]),
.VAR15(VAR15[2]),
.VAR7... | lgpl-3.0 |
bit0fun/Fusion-Core | Fusion-Core-Base/decode_32.v | 10,160 | module MODULE1(
input[31:0] VAR55, input VAR52, input VAR44, input[31:0] VAR41, input VAR72,
output reg [4:0] VAR71, output reg [4:0] VAR43, output reg [4:0] VAR21, output reg [4:0] VAR49, output reg [20:0] VAR19,
output reg [3:0] VAR45,
output reg VAR18,
output reg VAR34,
output reg VAR6,
output reg VAR32,
output reg ... | gpl-3.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/nios_system_audio_0.v | 12,437 | module MODULE1 (
clk,
reset,
address,
VAR44,
read,
write,
VAR42,
VAR37,
VAR54,
VAR10,
VAR26,
irq,
VAR5,
VAR58
);
input clk;
input reset;
input [ 1: 0] address;
input VAR44;
input read;
input write;
input [31: 0] VAR42;
input VAR37;
input VAR10;
input VAR54;
input VAR26;
output reg irq;
output reg [31: 0] VAR5;
output V... | mit |
uwsampa/zynqWrapper | hardware/zynqWrapper.v | 12,913 | module MODULE1
(
VAR97,
VAR72,
VAR16,
VAR64,
VAR61,
VAR21,
VAR37,
VAR60,
VAR81,
VAR86,
VAR30,
VAR53,
VAR99,
VAR105,
VAR67,
VAR49,
VAR42,
VAR107,
VAR108,
VAR58
);
input VAR97;
input VAR72;
input VAR16;
input VAR64;
input VAR61;
input [VAR27-1:0] VAR21;
input VAR37;
input VAR60;
input VAR81;
output VAR86;
output VAR30;
o... | mit |
davidkoltak/tawas-core | ip/tawas/rtl/tawas_au.v | 7,582 | module MODULE1
(
input clk,
input rst,
input [31:0] VAR16,
input [31:0] VAR27,
input [31:0] VAR45,
input [31:0] VAR25,
input [31:0] VAR41,
input [31:0] VAR29,
input [31:0] VAR34,
input [31:0] VAR7,
input [4:0] VAR14,
output [31:0] VAR38,
input VAR17,
input [2:0] VAR10,
input [31:0] VAR42,
input VAR31,
input [14:0] VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2/sky130_fd_sc_lp__mux2_8.v | 2,187 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR3 ,
VAR2 ,
VAR10,
VAR1,
VAR9 ,
VAR5
);
output VAR4 ;
input VAR8 ;
input VAR3 ;
input VAR2 ;
input VAR10;
input VAR1;
input VAR9 ;
input VAR5 ;
VAR7 VAR6 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
SeanZarzycki/openSPARC-FPU | project/src/fpu_mul_exp_dp.v | 12,292 | module MODULE1 (
VAR52,
VAR56,
VAR29,
VAR86,
VAR61,
VAR41,
VAR46,
VAR32,
VAR14,
VAR71,
VAR85,
VAR50,
VAR30,
VAR53,
VAR73,
VAR16,
VAR40,
VAR15,
VAR12,
VAR4,
VAR79,
VAR75,
VAR62,
VAR77,
VAR84,
VAR45,
VAR20,
VAR44,
VAR72,
VAR6,
VAR18,
VAR67,
VAR24,
VAR21,
VAR23,
VAR51,
VAR11
);
input [62:52] VAR52; input [62:52] VAR56; in... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3/sky130_fd_sc_ms__and3_4.v | 2,164 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR8 ,
VAR10 ,
VAR1,
VAR3,
VAR7 ,
VAR9
);
output VAR5 ;
input VAR4 ;
input VAR8 ;
input VAR10 ;
input VAR1;
input VAR3;
input VAR7 ;
input VAR9 ;
VAR6 VAR2 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/proyecto-final/sounds_module.v | 1,533 | module MODULE1(input VAR1, input reset, input[2:0] VAR2,
output reg[15:0] VAR4, output reg[15:0] VAR6);
reg [2:0] VAR3;
parameter [15:0] VAR7 [2:0];
parameter [15:0] VAR5 [2:0];
begin
begin
begin
begin | mit |
tmolteno/TART | hardware/FPGA/ddrmem/iobs_control.v | 2,620 | module MODULE1 (
VAR2,
VAR4,
VAR3,
VAR10,
VAR7,
VAR9,
VAR1,
VAR6,
VAR8,
VAR5
);
input VAR2;
input VAR4;
input VAR3;
input VAR10;
input VAR7;
input VAR9;
output VAR1;
output VAR6;
output VAR8;
output VAR5;
reg VAR1 = 1;
reg VAR6 = 1;
reg VAR8 = 1;
reg VAR5 = 1;
always @(posedge VAR2)
begin
if (!VAR4)
begin
VAR1 <= 1;
VA... | lgpl-3.0 |
AngelTerrones/MUSB | Hardware/musb/musb_multiplier.v | 5,041 | module MODULE1(
input clk, input rst, input [31:0] VAR23, input [31:0] VAR13, input VAR4, input VAR9, input VAR24, input VAR25, output [63:0] VAR19, output VAR3, output ready );
reg [32:0] VAR14;
reg [32:0] VAR8;
reg [31:0] VAR27;
reg [31:0] VAR28;
reg [31:0] VAR16;
reg [31:0] VAR30; reg [31:0] VAR29;
reg [31:0] VAR1; ... | mit |
drichmond/riffa | fpga/xilinx/ac701/riffa_wrapper_ac701.v | 38,622 | module MODULE1
parameter VAR291 = 128,
parameter VAR309 = 256,
parameter VAR69 = 5,
parameter VAR162 = "VAR234")
( input [VAR291-1:0] VAR114,
input [(VAR291/8)-1:0] VAR315,
input VAR167,
input VAR79,
output VAR161,
input [VAR42-1:0] VAR258,
output VAR43,
output VAR299,
output [VAR291-1:0] VAR109,
output [(VAR291/8)-1:0... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21oi/sky130_fd_sc_hdll__a21oi.pp.blackbox.v | 1,367 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR6 ,
VAR8 ,
VAR1,
VAR3,
VAR4 ,
VAR5
);
output VAR2 ;
input VAR7 ;
input VAR6 ;
input VAR8 ;
input VAR1;
input VAR3;
input VAR4 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4bb/sky130_fd_sc_hdll__nand4bb.functional.v | 1,444 | module MODULE1 (
VAR2 ,
VAR10,
VAR3,
VAR6 ,
VAR5
);
output VAR2 ;
input VAR10;
input VAR3;
input VAR6 ;
input VAR5 ;
wire VAR7;
wire VAR4;
nand VAR8 (VAR7, VAR5, VAR6 );
or VAR9 (VAR4, VAR3, VAR10, VAR7);
buf VAR1 (VAR2 , VAR4 );
endmodule | apache-2.0 |
Marcoslz22/Tercer_Proyecto | Counter.v | 1,621 | module MODULE1(
VAR2, VAR6, VAR4, VAR7 );
parameter VAR1 = 799; parameter VAR5 = 10; parameter VAR3 = VAR1;
input VAR2; input VAR6; output reg VAR4; output reg [VAR5 - 1: 0] VAR7;
VAR8 begin VAR4 = 0;
VAR7 = VAR3;
end
always@(posedge VAR2) begin
if (VAR6) begin if (VAR7 == VAR1) VAR7 <= 0;
end
else
VAR7 <= VAR7 + 1; en... | mit |
jairov4/accel-oil | solution_spartan6/syn/verilog/nfa_accept_sample.v | 43,248 | module MODULE1 (
VAR29,
VAR99,
VAR73,
VAR247,
VAR11,
VAR208,
VAR209,
VAR106,
VAR240,
VAR164,
VAR122,
VAR125,
VAR2,
VAR51,
VAR268,
VAR239,
VAR219,
VAR55,
VAR89,
VAR207,
VAR194,
VAR189,
VAR15,
VAR254,
VAR230,
VAR273,
VAR38,
VAR174,
VAR217,
VAR185,
VAR220,
VAR50,
VAR78,
VAR210,
VAR158,
VAR203,
VAR171,
VAR281,
VAR119,
VAR2... | lgpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/011J1G2/hdl/uart/uart.v | 1,287 | module MODULE1(
VAR8, VAR10, VAR5, VAR9, VAR7, VAR13 );
input VAR5;
input [7:0] VAR9;
input VAR7;
input VAR13;
output VAR8;
output VAR10;
reg [3:0] VAR11;
reg [8:0] VAR1;
reg VAR10;
wire VAR8 = |VAR11[3:1];
wire VAR3 = |VAR11;
reg [28:0] VAR2;
wire [28:0] VAR12 = VAR2[28] ? (115200) : (115200 - 100000000);
wire [28:0] ... | gpl-3.0 |
fbelavenuto/msx1fpga | src/audio/jt51/jt51.v | 8,336 | module MODULE1(
input clk, input rst, input VAR100, input VAR50, input VAR25,
input [7:0] din, output [7:0] dout, output VAR2,
output VAR110,
output VAR7, output reg VAR11,
output VAR36, output signed [15:0] VAR69,
output signed [15:0] VAR35,
output signed [15:0] VAR104,
output signed [15:0] VAR71,
output [15:0] VAR68,... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_min/rtl/jbi_min_rq.v | 13,490 | module MODULE1(
VAR55, VAR22, VAR77, VAR61,
VAR10, VAR71, VAR7,
VAR63, VAR21, VAR64,
VAR26, VAR70, VAR74, VAR38,
VAR28, VAR54, VAR76, VAR46,
VAR65, VAR32, VAR84, VAR48,
VAR33, VAR13,
VAR52, VAR18,
VAR59, VAR23, VAR49, VAR57, VAR53, clk,
VAR34
);
input VAR34; input clk; input VAR53; input VAR57; input VAR49; input VAR23... | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nfc-substrate/tiger4_nfc_substrate-1.0.0/CompletionCommandChannel.v | 6,656 | module MODULE1
(
parameter VAR4 = 32 ,
parameter VAR31 = 32 ,
parameter VAR8 = 16 ,
parameter VAR15 = 1
)
(
VAR3 ,
VAR1 ,
VAR24 ,
VAR14 ,
VAR29 ,
VAR18 ,
VAR25 ,
VAR17 ,
VAR7 ,
VAR9 ,
VAR28 ,
VAR12 ,
VAR19 ,
VAR11 ,
VAR20 ,
VAR5 ,
VAR21
);
input VAR3 ;
input VAR1 ;
input [5:0] VAR24 ;
input [4:0] VAR14 ;
input [4:0] VA... | gpl-3.0 |
peteasa/oh | src/emesh/hdl/emesh2packet.v | 2,224 | module MODULE1 #(parameter VAR5 = 32, parameter VAR3 = 104) (
input VAR11,
input [1:0] VAR4,
input [4:0] VAR8,
input [VAR5-1:0] VAR9,
input [VAR5-1:0] VAR2,
input [VAR5-1:0] VAR6,
output [VAR3-1:0] VAR10
);
assign VAR10[0] = VAR11;
assign VAR10[2:1] = VAR4[1:0];
assign VAR10[7:3] = VAR8[4:0];
generate
if(VAR3==136)
beg... | mit |
iamllama/EE2020 | ee2020.srcs/sources_1/new/vga.v | 38,916 | module MODULE6(
input VAR40,
output reg VAR22,
output reg VAR26 = 0,
output reg VAR7 = 0,
output reg[10:0] hc = 0,
output reg[10:0] VAR51 = 0
);
parameter VAR50 = 800;
parameter VAR39 = 600;
parameter VAR14 = 56;
parameter VAR49 = 120;
parameter VAR20 = 1040;
parameter VAR33 = 37;
parameter VAR18 = 6;
parameter VAR56 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxtp/sky130_fd_sc_ls__sedfxtp.functional.v | 1,909 | module MODULE1 (
VAR13 ,
VAR14,
VAR9 ,
VAR5 ,
VAR7,
VAR4
);
output VAR13 ;
input VAR14;
input VAR9 ;
input VAR5 ;
input VAR7;
input VAR4;
wire VAR12 ;
wire VAR11;
wire VAR16 ;
VAR8 VAR15 (VAR11, VAR16, VAR7, VAR4 );
VAR8 VAR6 (VAR16 , VAR12, VAR9, VAR5 );
VAR1 VAR10 VAR3 (VAR12 , VAR11, VAR14 );
buf VAR2 (VAR13 , VAR12... | apache-2.0 |
wyvernSemi/lm32fpga | HDL/rtl/SEG7_LUT_4.v | 1,152 | module MODULE1 (VAR1, VAR7, VAR5, VAR8, VAR6);
input [31:0] VAR6;
output [6:0] VAR1, VAR7, VAR5, VAR8;
VAR2 VAR3 (VAR1, {VAR6[16], VAR6[3:0]} );
VAR2 VAR9 (VAR7, {VAR6[17], VAR6[7:4]} );
VAR2 VAR10 (VAR5, {VAR6[18], VAR6[11:8]} );
VAR2 VAR4 (VAR8, {VAR6[19], VAR6[15:12]});
endmodule | gpl-3.0 |
AE9RB/peaberry | peaberry.cydsn/FracN/FracN.v | 2,283 | module MODULE1 (
input clk
);
wire [7:0] VAR2;
wire [7:0] VAR9;
wire [13:0] VAR14 = {VAR2 [5:0], VAR9 [7:0]};
reg [13:0] VAR7;
reg [13:0] VAR1;
wire [14:0] VAR6 = VAR7 + VAR14;
wire [14:0] VAR17 = VAR1 + VAR7;
reg VAR5;
reg [6:0] VAR12;
VAR8 #(.VAR18 (8'h3D), .VAR10(VAR3))
VAR4 ( .VAR19(VAR2));
VAR8 #(.VAR18 (8'hF4), .... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22oi/sky130_fd_sc_hvl__a22oi.behavioral.pp.v | 2,175 | module MODULE1 (
VAR8 ,
VAR11 ,
VAR4 ,
VAR9 ,
VAR18 ,
VAR1,
VAR5,
VAR17 ,
VAR12
);
output VAR8 ;
input VAR11 ;
input VAR4 ;
input VAR9 ;
input VAR18 ;
input VAR1;
input VAR5;
input VAR17 ;
input VAR12 ;
wire VAR19 ;
wire VAR13 ;
wire VAR2 ;
wire VAR14;
nand VAR15 (VAR19 , VAR4, VAR11 );
nand VAR10 (VAR13 , VAR18, VAR9 ... | apache-2.0 |
twlostow/dsi-shield | hdl/rtl/hpdmc/hpdmc_ctlif.v | 3,326 | module MODULE1 #(
parameter VAR1 = 4'h0
) (
input VAR20,
input VAR19,
input [13:0] VAR5,
input VAR27,
input [31:0] VAR18,
output reg [31:0] VAR3,
output reg VAR6,
output reg VAR13,
output reg VAR2,
output reg VAR4,
output reg VAR9,
output reg VAR11,
output reg VAR23,
output reg [12:0] VAR21,
output reg [1:0] VAR17,
out... | lgpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/wb_conmax/wb_conmax_pri_enc.v | 7,395 | module MODULE1(
valid,
VAR17, VAR24, VAR8, VAR7,
VAR19, VAR14, VAR11, VAR16,
VAR9
);
parameter [1:0] VAR15 = 2'd0;
input [7:0] valid;
input [1:0] VAR17, VAR24, VAR8, VAR7;
input [1:0] VAR19, VAR14, VAR11, VAR16;
output [1:0] VAR9;
wire [3:0] VAR21, VAR30, VAR25, VAR12;
wire [3:0] VAR26, VAR22, VAR31, VAR1;
wire [3:0] V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311ai/sky130_fd_sc_lp__o311ai.behavioral.v | 1,577 | module MODULE1 (
VAR13 ,
VAR14,
VAR7,
VAR3,
VAR11,
VAR15
);
output VAR13 ;
input VAR14;
input VAR7;
input VAR3;
input VAR11;
input VAR15;
supply1 VAR12;
supply0 VAR10;
supply1 VAR8 ;
supply0 VAR4 ;
wire VAR6 ;
wire VAR2;
or VAR1 (VAR6 , VAR7, VAR14, VAR3 );
nand VAR5 (VAR2, VAR15, VAR6, VAR11);
buf VAR9 (VAR13 , VAR2 )... | apache-2.0 |
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