repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
olgirard/openmsp430 | fpga/altera_de0_nano_soc/bench/verilog/msp_debug.v | 14,939 | module MODULE1 (
VAR94, VAR115, VAR59, VAR69, VAR97, VAR19, VAR36 );
output [8*32-1:0] VAR94; output [8*32-1:0] VAR115; output [31:0] VAR59; output [8*32-1:0] VAR69; output [31:0] VAR97; output [15:0] VAR19; output [8*32-1:0] VAR36;
function [64*8-1:0] VAR37;
input [32*8-1:0] VAR112;
input [32*8-1:0] VAR83;
input [3:0]... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3b/sky130_fd_sc_lp__and3b.symbol.v | 1,307 | module MODULE1 (
input VAR1,
input VAR3 ,
input VAR7 ,
output VAR5
);
supply1 VAR4;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
MForever78/CPUFly | src/Keyboard_driver.v | 2,832 | module MODULE1(clk, reset, VAR7, VAR9, VAR8, VAR5, VAR2);
input clk;
input reset;
input VAR7;
input [7: 0] VAR9;
input VAR5;
output VAR8;
output [31: 0] VAR2;
reg [31: 0] VAR3 = 0;
reg [7: 0] VAR1;
reg [23: 0] VAR6 = 0;
reg VAR4 = 0;
assign VAR2 = {VAR1, VAR6};
assign VAR8 = VAR5;
always @(posedge VAR7) begin
if (VAR9 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp/sky130_fd_sc_lp__sdfrtp.pp.symbol.v | 1,517 | module MODULE1 (
input VAR2 ,
output VAR7 ,
input VAR4,
input VAR6 ,
input VAR5 ,
input VAR8 ,
input VAR9 ,
input VAR1 ,
input VAR3 ,
input VAR10
);
endmodule | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/altera_up_video_dma_control_slave.v | 6,238 | module MODULE1 (
clk,
reset,
address,
VAR4,
read,
write,
VAR11,
VAR9,
VAR3,
VAR1,
VAR14
);
parameter VAR5 = 32'h00000000;
parameter VAR7 = 32'h00000000;
parameter VAR16 = 640; parameter VAR17 = 480;
parameter VAR15 = 16'h0809;
parameter VAR8 = 4'h7; parameter VAR10 = 2'h2; parameter VAR12 = 1'b1;
parameter VAR2 = 1'b1;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_pwrgood_pp_p/sky130_fd_sc_hd__udp_pwrgood_pp_p.symbol.v | 1,285 | module MODULE1 (
input VAR1 ,
output VAR3,
input VAR2
);
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_stepper/rtl/stepper.v | 7,232 | module MODULE1 (
input clk,
input rst,
input VAR51,
input VAR48,
input VAR49,
input VAR15,
output VAR11,
output VAR43,
input VAR14,
input VAR57,
input VAR30,
input VAR21,
input VAR44,
input [31:0] VAR59,
output VAR35,
input [31:0] VAR24,
input [31:0] VAR19,
input [31:0] VAR47,
input [31:0] VAR2,
input [31:0] VAR29,
out... | mit |
r2t2sdr/r2t2 | fpga/modules/cores/axis_histogram_v1_0/src/axis_histogram.v | 2,807 | module MODULE1 #
(
parameter integer VAR2 = 16,
parameter integer VAR1 = 32,
parameter integer VAR22 = 14
)
(
input wire VAR9,
input wire VAR5,
output wire VAR17,
input wire [VAR2-1:0] VAR14,
input wire VAR12,
output wire VAR7,
output wire VAR6,
output wire [VAR22-1:0] VAR16,
output wire [VAR1-1:0] VAR15,
input wire [V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_4.behavioral.pp.v | 1,568 | module MODULE1( VAR1, VAR3, VAR6, VAR4, VAR8, VAR5 );
input VAR1, VAR3;
inout VAR8, VAR5;
output VAR6, VAR4;
VAR2 VAR7(.VAR1(VAR1),.VAR3(VAR3),.VAR6(VAR6),.VAR4(VAR4),.VAR8(VAR8),.VAR5(VAR5));
VAR2 VAR9(.VAR1(VAR1),.VAR3(VAR3),.VAR6(VAR6),.VAR4(VAR4),.VAR8(VAR8),.VAR5(VAR5)); | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_spram_32x24.v | 8,185 | module MODULE1(
VAR15, VAR25, VAR27,
clk, rst, VAR26, VAR7, VAR8, addr, VAR18, VAR21
);
parameter VAR13 = 5;
parameter VAR24 = 24;
input VAR15;
input [VAR9 - 1:0] VAR27;
output VAR25;
input clk; input rst; input VAR26; input VAR7; input VAR8; input [VAR13-1:0] addr; input [VAR24-1:0] VAR18; output [VAR24-1:0] VAR21;
wi... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnq/gf180mcu_fd_sc_mcu9t5v0__dffnq_1.behavioral.pp.v | 2,214 | module MODULE1( VAR2, VAR13, VAR4, VAR11, VAR12 );
input VAR2, VAR13;
inout VAR11, VAR12;
output VAR4;
reg VAR10;
VAR3 VAR1(.VAR2(VAR2),.VAR13(VAR13),.VAR4(VAR4),.VAR11(VAR11),.VAR12(VAR12),.VAR10(VAR10));
VAR3 VAR7(.VAR2(VAR2),.VAR13(VAR13),.VAR4(VAR4),.VAR11(VAR11),.VAR12(VAR12),.VAR10(VAR10));
not VAR8(VAR5,VAR13);
... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_p0_read_valid_selector.v | 2,321 | module MODULE1(
VAR13,
VAR17,
VAR23,
VAR8,
VAR2,
VAR6
);
parameter VAR14 = "";
localparam VAR15 = 2**VAR14;
input VAR13;
input VAR17;
input [VAR15-1:0] VAR23;
input [VAR14-1:0] VAR8;
output VAR2;
output VAR6;
wire [VAR15-1:0] VAR18;
reg [VAR15-1:0] VAR11;
reg VAR2;
reg VAR3;
reg VAR6;
wire [VAR15-1:0] VAR21;
VAR12 VAR2... | gpl-3.0 |
efabless/openlane | designs/s44/src/lut_s44.v | 1,243 | module MODULE1 #(
parameter VAR2=8
) (
input [6:0] addr,
output out,
input VAR3,
input VAR10,
input [VAR2-1:0] VAR5,
output [VAR2-1:0] VAR1
);
wire VAR8;
wire [VAR2-1:0] VAR4;
lut #(.VAR7(4)) VAR9 (
.addr(addr[6:3]),
.out(VAR8),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR1(VAR4)
);
lut #(.VAR7(4)) VAR6 (
.addr({VAR8,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31o/sky130_fd_sc_lp__a31o_m.v | 2,334 | module MODULE2 (
VAR2 ,
VAR7 ,
VAR1 ,
VAR4 ,
VAR11 ,
VAR5,
VAR9,
VAR3 ,
VAR10
);
output VAR2 ;
input VAR7 ;
input VAR1 ;
input VAR4 ;
input VAR11 ;
input VAR5;
input VAR9;
input VAR3 ;
input VAR10 ;
VAR8 VAR6 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR3(VAR3),
.VA... | apache-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v | 6,950 | module MODULE1 #(
parameter VAR12 = 16,
parameter [1:0] VAR55 = 0,
parameter [0:0] VAR6 = 0
) (
input wire VAR74,
input wire [13:0] VAR9,
input wire VAR64,
input wire VAR84,
input wire VAR85,
output wire VAR19,
output wire [31:0] VAR7,
input wire VAR83,
input wire [VAR12-1:0] VAR30,
input wire [7:0] VAR4,
output reg [7... | bsd-3-clause |
jotego/jt12 | hdl/jt12_eg_final.v | 1,641 | module MODULE1(
input [ 6:0] VAR11,
input VAR5,
input [ 1:0] VAR1,
input [ 6:0] VAR8,
input [ 9:0] VAR3,
input VAR6,
output reg [9:0] VAR10
);
reg [ 8:0] VAR7;
reg [11:0] VAR12;
reg [11:0] VAR4;
reg [ 5:0] VAR9;
reg [ 9:0] VAR2;
always @ begin
casez( {VAR5, VAR1 } )
default: VAR7 = 9'd0;
3'b101: VAR7 = { 5'd0, VAR9[5:2... | gpl-3.0 |
omicronns/studies-sys-rek | de1-soc-proc/src/proc/idecoder.v | 1,223 | module MODULE1(
input VAR4,
input [31:0] VAR11,
output VAR15,
output VAR5,
output VAR16,
output VAR6,
output [1:0] VAR13,
output [2:0] VAR9,
output VAR14,
output VAR3,
output VAR17,
output [3:0] VAR10,
output [3:0] VAR2,
output [3:0] VAR12,
output [7:0] VAR7
);
wire VAR1;
wire VAR8;
assign VAR1 = VAR11[27];
assign VAR8... | mit |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/eeprom_v1_07_a/hdl/verilog/clk_prescaler.v | 5,730 | module MODULE1(
VAR22, VAR1, VAR2, VAR12, VAR15, VAR7, VAR11, VAR16, VAR5);
input VAR22;
input VAR1; input VAR2; input VAR12; input VAR15; input VAR7;
input VAR11; input VAR16;
output VAR5;
wire VAR22;
wire VAR7;
wire VAR11;
wire VAR16;
wire VAR2;
wire VAR12;
wire VAR15;
wire VAR25; wire VAR5; reg VAR4; reg VAR10; reg ... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkinvkapwr/sky130_fd_sc_hd__lpflow_clkinvkapwr.symbol.v | 1,366 | module MODULE1 (
input VAR1,
output VAR4
);
supply1 VAR7;
supply1 VAR6 ;
supply0 VAR2 ;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
rbarzic/amba_components | ahb_to_ssram/rtl/verilog/ahb_to_ssram.v | 6,263 | module MODULE1 (
VAR28, VAR18, VAR36, VAR29, VAR33, VAR23,
VAR20, VAR34, VAR32,
VAR13, VAR11, VAR41, VAR8, VAR5, VAR40, VAR25, VAR1, VAR26,
VAR12
);
parameter VAR21 = 12;
localparam VAR24 = 1;
localparam VAR17 = 2;
localparam VAR38 = 0;
input wire VAR13; input wire VAR11; input wire VAR41; input wire [VAR21-1:0] VAR8; ... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/edk_bee3/pcores/aurora_201_pcore_v1_00_a/hdl/verilog/aurora_201_aurora_lane.v | 10,106 | module MODULE1
(
VAR17,
VAR64,
VAR9,
VAR47,
VAR49,
VAR37,
VAR10,
VAR30,
VAR20,
VAR45,
VAR46,
VAR19,
VAR54,
VAR50,
VAR53,
VAR28,
VAR65,
VAR61,
VAR48,
VAR18,
VAR44,
VAR60,
VAR59,
VAR2,
VAR36,
VAR62,
VAR43,
VAR15,
VAR8,
VAR34,
VAR63,
VAR6,
VAR35,
VAR5,
VAR29,
VAR4,
VAR31,
VAR32
);
input [15:0] VAR17; input [1:0] VAR64; in... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ifu/rtl/sparc_ifu_dcl.v | 27,916 | module MODULE1(
VAR151, VAR12, VAR99,
VAR6, VAR14, VAR155,
VAR160, VAR55, VAR94,
VAR135, VAR82,
VAR91, VAR158,
VAR68, VAR50,
VAR170, VAR156,
VAR159, VAR116, VAR75,
VAR112, VAR87, VAR177, VAR67, VAR3, VAR24,
VAR180, VAR85, VAR19,
VAR53, VAR169, VAR2,
VAR92, VAR7, VAR111, VAR49,
VAR171, VAR79, VAR37,
VAR150, VAR108, VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fahcin/sky130_fd_sc_lp__fahcin.behavioral.v | 1,848 | module MODULE1 (
VAR5,
VAR7 ,
VAR10 ,
VAR13 ,
VAR21
);
output VAR5;
output VAR7 ;
input VAR10 ;
input VAR13 ;
input VAR21 ;
supply1 VAR17;
supply0 VAR23;
supply1 VAR1 ;
supply0 VAR2 ;
wire VAR20 ;
wire VAR6;
wire VAR4 ;
wire VAR16 ;
wire VAR8 ;
wire VAR14;
not VAR18 (VAR20 , VAR21 );
xor VAR3 (VAR6, VAR10, VAR13, VAR20... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_51.v | 32,692 | module MODULE4 (
clk,
reset,
VAR163,
VAR94,
VAR85,
VAR138,
VAR203
);
parameter VAR245 = 18;
parameter VAR204 = 51;
parameter VAR213 = 26;
localparam VAR233 = 52;
input clk;
input reset;
input VAR163;
input VAR94;
input [VAR245-1:0] VAR85; output VAR138;
output [VAR245-1:0] VAR203;
localparam VAR216 = 18; localparam VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdlclkp/sky130_fd_sc_ms__sdlclkp.functional.v | 1,772 | module MODULE1 (
VAR12,
VAR8 ,
VAR5,
VAR11
);
output VAR12;
input VAR8 ;
input VAR5;
input VAR11 ;
wire VAR14 ;
wire VAR1 ;
wire VAR2 ;
wire VAR13;
not VAR7 (VAR1 , VAR14 );
not VAR4 (VAR2 , VAR11 );
nor VAR10 (VAR13, VAR5, VAR8 );
VAR6 VAR9 (VAR14 , VAR13, VAR2 );
and VAR3 (VAR12 , VAR1, VAR11 );
endmodule | apache-2.0 |
fbalakirev/red-pitaya-notes | projects/red_pitaya_0_92/red_pitaya_dfilt1.v | 4,043 | module MODULE1
(
input VAR21 , input VAR11 , input [ 14-1: 0] VAR25 , output [ 14-1: 0] VAR7 ,
input [ 18-1: 0] VAR29 , input [ 25-1: 0] VAR6 , input [ 25-1: 0] VAR26 , input [ 25-1: 0] VAR3 );
reg [ 18-1: 0] VAR19 ;
reg [ 25-1: 0] VAR16 ;
reg [ 25-1: 0] VAR1 ;
reg [ 25-1: 0] VAR17 ;
always @(posedge VAR21) begin
VAR19... | mit |
horia141/bachelor-thesis | prj/xtra/common/ClockManager/ClockManager.v | 1,457 | module MODULE1(VAR32,reset,VAR8,VAR14,VAR11,VAR15,VAR4,VAR6,VAR43,VAR34,VAR29);
parameter VAR18 = 0;
input wire VAR32;
input wire reset;
input wire VAR8;
output wire VAR14;
output wire VAR11;
output wire VAR15;
output wire VAR4;
output wire VAR6;
output wire VAR43;
output wire VAR34;
output wire VAR29;
wire VAR1;
wire ... | mit |
AmeerAbdelhadi/Dynamic-Frequency-Phase-Sweeping | phasemeter.v | 3,602 | module MODULE1
( input VAR12, input VAR8, input VAR1, output reg VAR3, output [11:0] VAR5);
wire VAR2 = VAR8 && ~VAR1;
localparam VAR7 = 8;
reg [VAR7-1:0] VAR6, VAR9,VAR6,VAR9;
always @(posedge VAR12)
if (!VAR2) VAR6 <= {VAR7{1'b0}};
else VAR6 <= VAR6+{VAR7{1'b1}};
always @(negedge VAR12)
if (!VAR2) VAR9 <= {VAR7{1'b0}... | bsd-3-clause |
mithro/HDMI2USB | hdl/edid/edidmaster.v | 6,271 | module MODULE1 (VAR26,clk,VAR21,VAR23,VAR15,VAR24,VAR6,VAR16,VAR7,VAR2,VAR3);
input clk;
input VAR15;
input VAR26;
output reg VAR23;
inout VAR21;
input VAR6;
input [7:0] VAR24;
input [7:0] VAR16;
input [7:0] VAR7;
output reg [7:0] VAR2;
output reg VAR3;
wire VAR19;
reg VAR12;
assign VAR21 = (VAR12 == 1'b0) ? 1'b0 : 1'V... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlclkp/sky130_fd_sc_hs__dlclkp.behavioral.v | 1,814 | module MODULE1 (
VAR13,
VAR6,
VAR8 ,
VAR10,
VAR5
);
output VAR13;
input VAR6;
input VAR8 ;
input VAR10;
input VAR5;
wire VAR4 ;
wire VAR15 ;
wire VAR11 ;
wire VAR2;
reg VAR7 ;
wire VAR14 ;
not VAR3 (VAR15 , VAR11 );
VAR1 VAR9 (VAR4 , VAR2, VAR15, VAR7, VAR10, VAR5);
and VAR12 (VAR13 , VAR4, VAR11 );
assign VAR14 = ( VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfbbp/sky130_fd_sc_ls__sdfbbp.pp.blackbox.v | 1,562 | module MODULE1 (
VAR12 ,
VAR8 ,
VAR2 ,
VAR5 ,
VAR4 ,
VAR3 ,
VAR7 ,
VAR11,
VAR6 ,
VAR10 ,
VAR1 ,
VAR9
);
output VAR12 ;
output VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR4 ;
input VAR3 ;
input VAR7 ;
input VAR11;
input VAR6 ;
input VAR10 ;
input VAR1 ;
input VAR9 ;
endmodule | apache-2.0 |
rkrajnc/minimig-de1 | lib/altera/lpm_mult.v | 5,579 | module MODULE1 (
VAR47, VAR12, sum, VAR8, VAR14, VAR26, VAR5 );
parameter VAR48 = "MODULE1";
parameter VAR37 = 1;
parameter VAR30 = 1;
parameter VAR10 = 1;
parameter VAR4 = 1;
parameter VAR43 = "VAR7";
parameter VAR15 = 0;
parameter VAR18 = "VAR34";
parameter VAR22 = "VAR34";
parameter VAR31 = ( VAR37 >= VAR30 ) ? VAR3... | gpl-3.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/clk_108MHz/clk_108MHz_stub.v | 1,171 | module MODULE1(VAR1, MODULE1, VAR2)
;
input VAR1;
output MODULE1;
output VAR2;
endmodule | gpl-2.0 |
charcole/NeoGeoHDMI | HDMIDirect.v | 29,232 | module MODULE1(
input VAR15,
input VAR24,
input VAR20,
input [16:0] VAR12,
input [4:0] VAR14, VAR27, VAR23,
input VAR18, VAR26,
input VAR19,
input sync,
input VAR1,
input VAR17,
input VAR25,
input VAR30,
input [7:0] VAR6,
output [2:0] VAR8, VAR16,
output VAR9, VAR4,
output [11:0] VAR13,
output VAR10,
output VAR3,
outpu... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_2.behavioral.v | 1,802 | module MODULE1( VAR1, VAR5, VAR3, VAR6, VAR8 );
input VAR3, VAR5, VAR6, VAR8;
output VAR1;
VAR2 VAR7(.VAR1(VAR1),.VAR5(VAR5),.VAR3(VAR3),.VAR6(VAR6),.VAR8(VAR8));
VAR2 VAR4(.VAR1(VAR1),.VAR5(VAR5),.VAR3(VAR3),.VAR6(VAR6),.VAR8(VAR8)); | apache-2.0 |
velizarefremov/MIPS | Part 3/Verilog Code/Post-Synthesis/barrel_shifter_synthesis.v | 27,171 | module MODULE1 (
VAR269, VAR258, VAR201, VAR143, VAR267
);
input VAR269;
input VAR258;
input [15 : 0] VAR201;
input [4 : 0] VAR143;
output [15 : 0] VAR267;
wire VAR71;
wire VAR181;
wire VAR190;
wire VAR166;
wire VAR142;
wire VAR107;
wire VAR94;
wire VAR266;
wire VAR38;
wire VAR268;
wire VAR116;
wire VAR211;
wire VAR106... | gpl-2.0 |
dvanmali/Superscalar_Pipeline_Processor | decode.v | 2,286 | module MODULE1(clk, VAR32,VAR42, VAR26,VAR30, VAR3,VAR15, VAR11,VAR40, VAR18,VAR22, VAR38, VAR16,VAR20, VAR5,VAR1,VAR10,
VAR17, VAR34,VAR8,VAR31, VAR12, VAR24,VAR39, VAR41,VAR2,VAR13, VAR19, VAR35,VAR29,VAR4, VAR9,VAR37,VAR7,VAR23);
input clk, VAR32,VAR42;
input [1:0] VAR26, VAR30,VAR3,VAR15;
input [31:0] VAR11,VAR40, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2/sky130_fd_sc_hs__nor2.behavioral.v | 1,675 | module MODULE1 (
VAR11 ,
VAR8 ,
VAR9 ,
VAR4,
VAR6
);
output VAR11 ;
input VAR8 ;
input VAR9 ;
input VAR4;
input VAR6;
wire VAR5 ;
wire VAR3;
nor VAR10 (VAR5 , VAR8, VAR9 );
VAR7 VAR1 (VAR3, VAR5, VAR4, VAR6);
buf VAR2 (VAR11 , VAR3 );
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/vga/grap_data_rd.v | 10,470 | module MODULE1
(
input VAR62,
input VAR21,
input VAR1,
input [3:0] VAR26,
input VAR43,
input VAR5,
input VAR56,
input VAR76,
input VAR72,
input VAR8,
input VAR75,
input VAR63,
input VAR41, input VAR39, input [1:0] VAR4,
input VAR10,
input VAR59,
input [3:0] VAR33,
input [3:0] VAR19,
input VAR60,
input VAR28,
input VAR3... | gpl-3.0 |
olajep/oh | src/elink/dv/dut_elink.v | 14,821 | module MODULE1(
VAR160, VAR73, VAR146, VAR120, VAR40,
VAR110, VAR2, VAR18, VAR75, VAR9, VAR81, VAR122, VAR31
);
parameter VAR112 = 32;
parameter VAR87 = 32;
parameter VAR58 = 2;
parameter VAR170 = 12;
parameter VAR55 = 6;
parameter VAR134 = 12;
parameter VAR144 = 104;
parameter VAR50 = 1;
input VAR110;
input VAR2;
outp... | mit |
ultraembedded/riscv | core/riscv/riscv_divider.v | 6,141 | module MODULE1
(
input VAR3
,input VAR4
,input VAR29
,input [ 31:0] VAR28
,input [ 31:0] VAR27
,input VAR26
,input [ 4:0] VAR30
,input [ 4:0] VAR21
,input [ 4:0] VAR8
,input [ 31:0] VAR14
,input [ 31:0] VAR15
,output VAR6
,output [ 31:0] VAR31
);
reg VAR25;
reg [31:0] VAR33;
wire VAR17 = (VAR28 & VAR35) == VAR32;
wire ... | bsd-3-clause |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/ram_harvard.v | 2,427 | module MODULE1
parameter VAR14=16384,
parameter VAR6=6,
parameter VAR7=6)
(input VAR28,
input VAR36,
input [VAR5-1:0] VAR10,
input [31:0] VAR33,
input [3:0] VAR9,
input VAR8,
input VAR29,
input VAR17,
input [VAR5-1:0] VAR24,
output [31:0] VAR11,
input [VAR5-1:0] VAR15,
input [31:0] VAR13,
output [31:0] VAR16,
input VAR... | gpl-2.0 |
rakeshkadamati/MIPS-32-Bit-Verilog | adder.v | 2,817 | module MODULE2(VAR73,VAR64,sum,VAR89,VAR41);
input VAR73,VAR64,VAR41;
output sum,VAR89;
xor VAR97(VAR111,VAR73,VAR64);
xor VAR51(sum,VAR111,VAR41);
and VAR52(VAR12,VAR111,VAR41);
and VAR79(VAR67,VAR73,VAR64);
or VAR8(VAR89,VAR12,VAR67);
endmodule
module MODULE1(VAR63,VAR5,VAR89,VAR90,VAR41);
input VAR41;
input [31:0] V... | mit |
vipinkmenon/scas | hw/fpga/source/user_logic_if/user_ddr_strm_arbitrator.v | 5,738 | module MODULE1 #(
parameter VAR35 = 'd4,
parameter VAR50 = 'd32,
parameter VAR8 = 'd256,
parameter VAR41 = 'd32
)
(
input VAR51,
input VAR42,
input [VAR35-1:0] VAR23,
output reg [VAR35-1:0] VAR21,
input [VAR50*VAR35-1 : 0] VAR10,
output reg [VAR8-1:0] VAR7,
output reg [VAR35-1:0] VAR3,
input [VAR35-1:0] VAR2,
output re... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlclkp/sky130_fd_sc_ms__dlclkp.blackbox.v | 1,259 | module MODULE1 (
VAR2,
VAR1,
VAR5
);
output VAR2;
input VAR1;
input VAR5 ;
supply1 VAR3;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck.v | 9,095 | module MODULE1 (
VAR31,
VAR12,
VAR35,
VAR2,
VAR37,
VAR8,
VAR20,
VAR18,
VAR28,
VAR1,
VAR13,
VAR27,
VAR6,
VAR24,
VAR25,
VAR34,
VAR32,
VAR33,
VAR4,
VAR22,
VAR9,
VAR11,
VAR30,
VAR16,
VAR15,
VAR39,
VAR29,
VAR23,
VAR10,
VAR17,
VAR3
)
;
output [ 1: 0] VAR29;
output VAR23;
output [ 37: 0] VAR10;
output VAR17;
output VAR3;
inpu... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp.blackbox.v | 1,301 | module MODULE1 (
VAR8,
VAR7 ,
VAR6,
VAR2
);
output VAR8;
input VAR7 ;
input VAR6;
input VAR2 ;
supply1 VAR1;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/common/rtl/cluster_header_ctu.v | 3,346 | module MODULE1 (
VAR24, VAR25, VAR13, VAR5,
VAR23, VAR12, VAR21, VAR14, VAR3, VAR7, VAR19,
VAR28
);
input VAR23;
input VAR12;
input VAR21;
input VAR14;
input VAR3;
input VAR7;
output VAR24;
output VAR25;
output VAR13;
input VAR19; input VAR28;
output VAR5;
wire VAR4;
wire VAR18;
wire VAR25;
wire VAR24;
wire VAR10;
VAR1... | gpl-2.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/syn/verilog/ANN_fcmp_32ns_32ns_1_1.v | 2,372 | module MODULE1
VAR1 = 6,
VAR23 = 1,
VAR26 = 32,
VAR31 = 32,
VAR7 = 1
)(
input wire [VAR26-1:0] VAR3,
input wire [VAR31-1:0] VAR24,
input wire [4:0] VAR12,
output wire [VAR7-1:0] dout
);
localparam [4:0]
VAR9 = 5'b00001,
VAR36 = 5'b00010,
VAR39 = 5'b00011,
VAR17 = 5'b00100,
VAR25 = 5'b00101,
VAR33 = 5'b00110,
VAR4 = 5'b... | gpl-3.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/FIFO_pixelq_op_img_cols_V_channel.v | 2,999 | module MODULE1 (
clk,
VAR17,
VAR20,
VAR4,
VAR22);
parameter VAR16 = 32'd12;
parameter VAR13 = 32'd2;
parameter VAR21 = 32'd3;
input clk;
input [VAR16-1:0] VAR17;
input VAR20;
input [VAR13-1:0] VAR4;
output [VAR16-1:0] VAR22;
reg[VAR16-1:0] VAR26 [0:VAR21-1];
integer VAR24;
always @ (posedge clk)
begin
if (VAR20)
begin
... | gpl-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/example_design/rtl/traffic_gen/mig_7series_v2_0_data_prbs_gen.v | 4,725 | module MODULE1 #
(
parameter VAR4 = 100,
parameter VAR6 = "VAR14",
parameter VAR9 = 32, parameter VAR5 = 32
)
(
input VAR12,
input VAR2,
input VAR13,
input VAR1, input [VAR9 - 1:0] VAR10,
output [VAR9 - 1:0] VAR11 );
reg [VAR9 - 1 :0] VAR7;
reg [VAR9 :1] VAR3;
integer VAR8;
always @ (posedge VAR12)
begin
if (VAR1 && VA... | bsd-2-clause |
davidkoltak/tawas-core | ip/rcn/rtl/rcn_slave.v | 1,337 | module MODULE1
(
input rst,
input clk,
input [68:0] VAR16,
output [68:0] VAR15,
output VAR5,
output wr,
output [3:0] VAR2,
output [23:0] addr,
output [31:0] VAR12,
input [31:0] VAR14
);
parameter VAR10 = 0;
parameter VAR13 = 1;
reg [68:0] VAR4;
reg [68:0] VAR6;
reg [68:0] VAR7;
assign VAR15 = VAR7;
wire [23:0] VAR11 = ... | mit |
Gum-Joe/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/pcie_dma_engine/internal_dma_ctrl.v | 7,494 | module MODULE1
(
input clk,
input rst,
input [31:0] VAR2,
input [6:0] VAR14,
input [6:0] VAR9,
input VAR10,
output reg [31:0] VAR1,
output [63:0] VAR7, output reg [31:0] VAR6, output reg [31:0] VAR11,
output VAR15, input VAR4,
input [31:0] VAR12,
input [31:0] VAR8
);
reg [31:0] VAR5, VAR13;
reg [31:0] VAR3;
assign VAR7... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/bufbuf/sky130_fd_sc_ls__bufbuf.blackbox.v | 1,224 | module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR2;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/xilinx_v6_pcie_wrapper.v | 15,249 | module MODULE1
(
VAR59, VAR100, VAR52, VAR55,
VAR1, VAR80, VAR68, VAR96,
VAR40, VAR95, VAR64, VAR74, VAR19,
VAR42, VAR48, VAR26, VAR11, VAR72,
VAR32, VAR22, VAR30, VAR45, VAR69,
VAR20, VAR33, VAR25,
VAR43, VAR58,
VAR31, VAR38,
VAR84, VAR15, VAR67,
VAR4, VAR92, VAR23, VAR71,
VAR90, VAR73, VAR50,
VAR46, VAR14, VAR3,
VAR9... | lgpl-3.0 |
alexforencich/verilog-mersenne | rtl/axis_mt19937_64.v | 7,901 | module MODULE1
(
input wire clk,
input wire rst,
output wire [63:0] VAR34,
output wire VAR26,
input wire VAR16,
output wire VAR10,
input wire [63:0] VAR11,
input wire VAR38
);
localparam [1:0]
VAR41 = 2'd0,
VAR2 = 2'd1;
reg [1:0] VAR3 = VAR41, VAR17;
reg [63:0] VAR4 [311:0];
reg [63:0] VAR9 = 0, VAR32;
reg [9:0] VAR30 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2/sky130_fd_sc_hdll__nor2.pp.blackbox.v | 1,268 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR3 ,
VAR7,
VAR2,
VAR5 ,
VAR1
);
output VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR7;
input VAR2;
input VAR5 ;
input VAR1 ;
endmodule | apache-2.0 |
aap/pdp6 | verilog/arbiter.v | 1,785 | module MODULE1(
input wire clk,
input wire reset,
input wire [17:0] VAR6,
input wire VAR4,
input wire VAR13,
input wire [35:0] VAR5,
output reg [35:0] VAR3,
output reg VAR11,
input wire [17:0] VAR21,
input wire VAR17,
input wire VAR23,
input wire [35:0] VAR10,
output reg [35:0] VAR19,
output reg VAR9,
output reg [17:0]... | mit |
GustavoOS/ARMAria | src/ALU.v | 5,603 | module MODULE1
parameter VAR4 = 32
)(
input [VAR4 - 1:0] VAR16, VAR1,
output reg [VAR4 - 1:0] VAR15,
input [3:0] VAR7,
input VAR5,
output reg VAR6, VAR13,
output reg VAR9, VAR2
);
wire [VAR4 - 1:0] VAR12;
wire VAR14, VAR3, VAR10, VAR11;
reg VAR8;
assign VAR14 = VAR15[VAR4 - 1];
assign VAR10 = VAR16[VAR4 -1];
assign VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22a/sky130_fd_sc_ls__o22a.symbol.v | 1,363 | module MODULE1 (
input VAR4,
input VAR3,
input VAR9,
input VAR8,
output VAR1
);
supply1 VAR5;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41a/sky130_fd_sc_lp__o41a.functional.v | 1,453 | module MODULE1 (
VAR5 ,
VAR10,
VAR3,
VAR7,
VAR9,
VAR6
);
output VAR5 ;
input VAR10;
input VAR3;
input VAR7;
input VAR9;
input VAR6;
wire VAR11 ;
wire VAR1;
or VAR8 (VAR11 , VAR9, VAR7, VAR3, VAR10 );
and VAR4 (VAR1, VAR11, VAR6 );
buf VAR2 (VAR5 , VAR1 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_hash_bank.v | 11,268 | module MODULE1 #(parameter VAR34(VAR31)
,parameter VAR34(VAR15),
VAR4=VAR19((2**VAR15+VAR31-1)/VAR31),
VAR11=VAR36(VAR31), VAR27=0)
(
input [VAR15-1:0] VAR7
,output [VAR11-1:0] VAR35
,output [VAR4-1:0] VAR10
);
genvar VAR3;
if (VAR31 == 1)
begin: VAR2
assign VAR10 = VAR7;
assign VAR35 = 1'b0;
end
else
if (VAR31 == 2)
b... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtp/sky130_fd_sc_lp__dlxtp.functional.v | 1,577 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR9
);
output VAR10 ;
input VAR6 ;
input VAR9;
wire VAR7 ;
wire VAR8;
wire VAR3 ;
VAR5 VAR1 VAR2 (VAR7 , VAR6, VAR9 );
buf VAR4 (VAR10 , VAR7 );
endmodule | apache-2.0 |
olgirard/openmsp430 | core/synthesis/altera/src/megawizard/cyclone2_dmem.v | 7,460 | module MODULE1 (
address,
VAR31,
VAR53,
VAR23,
VAR45,
VAR25,
VAR22);
input [9:0] address;
input [1:0] VAR31;
input VAR53;
input VAR23;
input [15:0] VAR45;
input VAR25;
output [15:0] VAR22;
tri1 [1:0] VAR31;
tri1 VAR53;
tri1 VAR23;
wire [15:0] VAR37;
wire [15:0] VAR22 = VAR37[15:0];
VAR46 VAR42 (
.VAR38 (VAR53),
.VAR17 ... | bsd-3-clause |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_dc_fsm.v | 13,664 | module MODULE1(
clk, rst,
VAR3, VAR12, VAR15, VAR14, VAR13,
VAR23, VAR20, VAR5, VAR6, VAR24,
VAR4, VAR17, VAR21, VAR7, VAR30, VAR1,
VAR25, VAR22, VAR27
);
input clk;
input rst;
input VAR3;
input VAR12;
input VAR15;
input VAR14;
input [3:0] VAR13;
input VAR23;
input VAR20;
input VAR5;
input [31:0] VAR6;
output [31:0] VA... | gpl-2.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Proyectos Funcionales Francis Jeffrey/CORDICO/CORDICO.srcs/sources_1/imports/Floating-Point-Unit-master/FPU_Add_subt_Mult/project_1/project_1.srcs/sources_1/imports/Proyecto_De_Graduacion/FPU_FLM/RTL/Add-Subt/LZD.v | 1,306 | module MODULE1#(parameter VAR3=26, parameter VAR1=5)(
input wire clk,
input wire rst,
input wire VAR4,
input wire [VAR3-1:0] VAR14,
output wire [VAR1-1:0] VAR11
);
wire [VAR1-1:0] VAR13;
generate
case (VAR3)
26:begin
VAR9 VAR7(
.VAR18(VAR14),
.VAR5(VAR13)
);
end
55:begin
VAR2 VAR15(
.VAR18(VAR14),
.VAR5(VAR13)
);
end
e... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/sync_fifo.v | 5,636 | module MODULE1 #(
parameter VAR16 = 32, parameter VAR2 = 1024, parameter VAR34 = 0, parameter VAR14 = 2**VAR25(VAR2),
parameter VAR17 = VAR10(VAR14),
parameter VAR4 = VAR10(VAR14+1)
)
(
input VAR29, input VAR24, input [VAR16-1:0] VAR7, input VAR9, output [VAR16-1:0] VAR35, input VAR19, output VAR20, output VAR31, outpu... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/cores/axi_bram_reader_v1_0/src/axi_bram_reader.v | 2,392 | module MODULE1 #
(
parameter integer VAR13 = 32,
parameter integer VAR11 = 32,
parameter integer VAR12 = 32,
parameter integer VAR16 = 10
)
(
input wire VAR4,
input wire VAR7,
input wire [VAR11-1:0] VAR6, input wire VAR17, output wire VAR2, output wire [VAR13-1:0] VAR15, output wire [1:0] VAR22, output wire VAR9, input... | gpl-3.0 |
borti4938/sd2snes | verilog/sd2snes_cx4/snescmd_buf.v | 10,645 | module MODULE1 (
VAR34,
VAR12,
VAR54,
VAR58,
VAR27,
VAR26,
VAR21,
VAR53,
VAR55);
input [8:0] VAR34;
input [8:0] VAR12;
input VAR54;
input [7:0] VAR58;
input [7:0] VAR27;
input VAR26;
input VAR21;
output [7:0] VAR53;
output [7:0] VAR55;
tri1 VAR54;
tri0 VAR26;
tri0 VAR21;
wire [7:0] VAR31;
wire [7:0] VAR50;
wire [7:0] V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgnd/sky130_fd_sc_ls__tapvgnd.pp.blackbox.v | 1,256 | module MODULE1 (
VAR3,
VAR2,
VAR4 ,
VAR1
);
input VAR3;
input VAR2;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
aquaxis/FPGAMAG18 | fmrv32im-artya7.nonos/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ip/fmrv32im_artya7_fmrv32im_0/synth/fmrv32im_artya7_fmrv32im_0.v | 4,816 | module MODULE1 (
VAR2,
VAR12,
VAR11,
VAR10,
VAR14,
VAR4,
VAR13,
VAR5,
VAR19,
VAR18,
VAR6,
VAR15,
VAR16,
VAR3,
VAR1,
VAR7
);
input wire VAR2;
input wire VAR12;
input wire VAR11;
output wire VAR10;
output wire [31 : 0] VAR14;
input wire [31 : 0] VAR4;
input wire VAR13;
input wire VAR5;
output wire VAR19;
output wire [3 :... | mit |
UA3MQJ/fpga-synth | modules/note_pitch2dds_3st_gen.v | 2,559 | module MODULE1(clk, VAR3, VAR5, VAR2);
input wire clk;
input wire [6:0] VAR3;
input wire [13:0] VAR5;
output reg [31:0] VAR2;
reg [32:0] VAR6;
reg [7:0] VAR4;
reg [3:0] state;
reg [6:0] VAR1;
reg [13:0] VAR7; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrbp/sky130_fd_sc_ls__dlrbp.pp.blackbox.v | 1,440 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR5,
VAR9 ,
VAR3 ,
VAR2 ,
VAR6 ,
VAR1 ,
VAR8
);
output VAR4 ;
output VAR7 ;
input VAR5;
input VAR9 ;
input VAR3 ;
input VAR2 ;
input VAR6 ;
input VAR1 ;
input VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32o/sky130_fd_sc_hdll__a32o.blackbox.v | 1,433 | module MODULE1 (
VAR1 ,
VAR7,
VAR5,
VAR4,
VAR3,
VAR9
);
output VAR1 ;
input VAR7;
input VAR5;
input VAR4;
input VAR3;
input VAR9;
supply1 VAR2;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfstp/sky130_fd_sc_hd__dfstp.behavioral.v | 2,130 | module MODULE1 (
VAR4 ,
VAR13 ,
VAR14 ,
VAR8
);
output VAR4 ;
input VAR13 ;
input VAR14 ;
input VAR8;
supply1 VAR21;
supply0 VAR11;
supply1 VAR3 ;
supply0 VAR15 ;
wire VAR16 ;
wire VAR1 ;
reg VAR6 ;
wire VAR5 ;
wire VAR18;
wire VAR9 ;
wire VAR12 ;
wire VAR19 ;
wire VAR20 ;
not VAR17 (VAR1 , VAR18 );
VAR2 VAR10 (VAR16 ,... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/mor1kx-generic/rtl/verilog/orpsoc_top.v | 7,676 | module MODULE1 #(
parameter VAR210 = 0
)(
input VAR70,
input VAR72,
output VAR150,
input VAR94,
input VAR178,
input VAR152
);
localparam VAR126 = 32;
localparam VAR16 = 32;
localparam VAR20 = 23;
wire VAR49 = VAR70;
wire VAR229 = VAR72;
wire VAR22;
wire VAR11;
wire VAR65;
wire VAR176;
wire VAR142;
wire VAR145;
wire VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfstp/sky130_fd_sc_ls__dfstp.functional.pp.v | 1,825 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR10 ,
VAR3,
VAR12 ,
VAR4 ,
VAR8 ,
VAR15
);
output VAR7 ;
input VAR6 ;
input VAR10 ;
input VAR3;
input VAR12 ;
input VAR4 ;
input VAR8 ;
input VAR15 ;
wire VAR14;
wire VAR11 ;
not VAR5 (VAR11 , VAR3 );
VAR2 VAR13 VAR1 (VAR14 , VAR10, VAR6, VAR11, , VAR12, VAR4);
buf VAR9 (VAR7 , VAR14 );... | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_data_in.v | 1,884 | module MODULE1 (
address,
clk,
VAR2,
VAR5,
VAR4
)
;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input clk;
input [ 7: 0] VAR2;
input VAR5;
wire VAR3;
wire [ 7: 0] VAR6;
wire [ 7: 0] VAR1;
reg [ 31: 0] VAR4;
assign VAR3 = 1;
assign VAR1 = {8 {(address == 0)}} & VAR6;
always @(posedge clk or negedge VAR5)
begin
if (VAR5... | gpl-3.0 |
rkrajnc/minimig-de1 | rtl/or1200/or1200_top_wrapper.v | 3,466 | module MODULE1 #(
parameter VAR55 = 24
)(
input wire clk,
input wire rst,
output wire VAR70,
output wire VAR44,
output wire [ 4-1:0] VAR7,
output wire [ VAR55-1:0] VAR1,
output wire [ 32-1:0] VAR5,
input wire [ 32-1:0] VAR33,
input wire VAR60,
output wire VAR79,
output wire VAR49,
output wire [ 4-1:0] VAR26,
output wir... | gpl-3.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_07_a/hdl/verilog/user_logic.v | 34,277 | /* VAR157 VAR204:
module MODULE1
(
VAR179,
VAR57,
VAR226,
VAR219,
VAR110,
VAR124,
VAR227,
VAR212,
VAR13,
VAR73,
VAR35,
VAR116,
VAR65,
VAR83,
VAR127,
VAR198,
VAR224,
VAR58,
VAR169,
VAR192,
VAR121,
VAR84,
VAR7,
VAR151,
VAR138,
VAR80,
VAR51,
VAR105,
VAR97,
VAR66,
VAR155,
VAR202,
VAR50,
VAR63,
VAR38,
VAR146,
VAR196,
VAR16,... | bsd-2-clause |
asicguy/gplgpu | hdl/mc_cache/mc_cache.v | 13,629 | module MODULE1
(
input VAR56,
input VAR88,
input [3:0] VAR15,
input VAR108,
input VAR123,
input VAR26,
input [23:0] VAR105,
input [127:0] VAR33,
input [15:0] VAR97,
input [5:0] VAR71,
output VAR113,
output reg [127:0] VAR43,
output reg VAR83,
input VAR102,
input VAR106,
input [255:0] VAR74,
output reg VAR52,
output reg... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25_1.v | 2,163 | module MODULE2 (
VAR5 ,
VAR3 ,
VAR2,
VAR1,
VAR6 ,
VAR7
);
output VAR5 ;
input VAR3 ;
input VAR2;
input VAR1;
input VAR6 ;
input VAR7 ;
VAR8 VAR4 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR5,
VAR3
);
output VAR5;
input VAR3;
supply1 VAR2;
supply0 VAR1;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o32ai/sky130_fd_sc_hdll__o32ai.symbol.v | 1,399 | module MODULE1 (
input VAR9,
input VAR3,
input VAR8,
input VAR6,
input VAR7,
output VAR10
);
supply1 VAR4;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111ai/sky130_fd_sc_ms__o2111ai_4.v | 2,461 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR12 ,
VAR5 ,
VAR7 ,
VAR11 ,
VAR4,
VAR2,
VAR10 ,
VAR1
);
output VAR6 ;
input VAR9 ;
input VAR12 ;
input VAR5 ;
input VAR7 ;
input VAR11 ;
input VAR4;
input VAR2;
input VAR10 ;
input VAR1 ;
VAR3 VAR8 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR4... | apache-2.0 |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/alt_vipitc131_common_sync_generation.v | 4,063 | module MODULE1(
input wire rst,
input wire clk,
input wire VAR45,
input wire VAR12,
input wire VAR30,
input wire VAR22,
input wire VAR35,
input wire VAR31,
input wire [13:0] VAR36,
input wire VAR44,
input wire [12:0] VAR4,
input wire VAR15,
input wire VAR25,
input wire [13:0] VAR9,
input wire [13:0] VAR29,
input wire [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_lp__udp_dff_nsr_pp_pg_n.symbol.v | 1,655 | module MODULE1 (
input VAR7 ,
output VAR3 ,
input VAR6 ,
input VAR5 ,
input VAR2 ,
input VAR4,
input VAR1 ,
input VAR8
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd/sky130_fd_sc_hdll__tapvgnd_1.v | 1,954 | module MODULE2 (
VAR2,
VAR6,
VAR5 ,
VAR3
);
input VAR2;
input VAR6;
input VAR5 ;
input VAR3 ;
VAR4 VAR1 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE2 ();
supply1 VAR2;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR3 ;
VAR4 VAR1 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111a/sky130_fd_sc_ls__o2111a_4.v | 2,448 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR3 ,
VAR11 ,
VAR12 ,
VAR8 ,
VAR4,
VAR7,
VAR9 ,
VAR6
);
output VAR1 ;
input VAR2 ;
input VAR3 ;
input VAR11 ;
input VAR12 ;
input VAR8 ;
input VAR4;
input VAR7;
input VAR9 ;
input VAR6 ;
VAR5 VAR10 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR4(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111oi/sky130_fd_sc_ms__a2111oi.behavioral.pp.v | 2,082 | module MODULE1 (
VAR6 ,
VAR17 ,
VAR13 ,
VAR3 ,
VAR5 ,
VAR9 ,
VAR7,
VAR11,
VAR12 ,
VAR15
);
output VAR6 ;
input VAR17 ;
input VAR13 ;
input VAR3 ;
input VAR5 ;
input VAR9 ;
input VAR7;
input VAR11;
input VAR12 ;
input VAR15 ;
wire VAR2 ;
wire VAR8 ;
wire VAR18;
and VAR14 (VAR2 , VAR17, VAR13 );
nor VAR10 (VAR8 , VAR3, V... | apache-2.0 |
UviDTE-UviSpace/UviSpace | DE1-SoC/FPGA_Design/ip/sdram_control/control_interface.v | 5,614 | module MODULE1(
VAR21,
VAR7,
VAR16,
VAR8,
VAR12,
VAR10,
VAR6,
VAR3,
VAR20,
VAR4,
VAR11,
VAR5,
VAR17,
VAR2,
VAR18,
VAR14,
VAR19
);
input VAR21; input VAR7; input [2:0] VAR16; input [VAR22-1:0] VAR8; input VAR12; input VAR10; input VAR6; output VAR3; output VAR20; output VAR4; output VAR11; output VAR5; output VAR17; out... | gpl-3.0 |
rkrajnc/minimig-de1 | rtl/or1200/or1200_dc_fsm.v | 9,687 | module MODULE1(
clk, rst,
VAR12, VAR31, VAR7, VAR25, VAR14,
VAR32, VAR2, VAR27, VAR16, VAR18,
VAR8, VAR6, VAR20, VAR4, VAR23, VAR15,
VAR3, VAR19, VAR5
);
input clk;
input rst;
input VAR12;
input VAR31;
input VAR7;
input VAR25;
input [3:0] VAR14;
input VAR32;
input VAR2;
input VAR27;
input [31:0] VAR16;
output [31:0] VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4b/sky130_fd_sc_hd__and4b_4.v | 2,300 | module MODULE2 (
VAR11 ,
VAR8 ,
VAR10 ,
VAR4 ,
VAR7 ,
VAR6,
VAR5,
VAR3 ,
VAR1
);
output VAR11 ;
input VAR8 ;
input VAR10 ;
input VAR4 ;
input VAR7 ;
input VAR6;
input VAR5;
input VAR3 ;
input VAR1 ;
VAR2 VAR9 (
.VAR11(VAR11),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_1.behavioral.v | 1,101 | module MODULE1( VAR2, VAR5 );
input VAR2;
output VAR5;
VAR4 VAR1(.VAR2(VAR2),.VAR5(VAR5));
VAR4 VAR3(.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_1.behavioral.pp.v | 1,407 | module MODULE1( VAR1, VAR4, VAR5, VAR8, VAR7, VAR2, VAR3 );
input VAR7, VAR8, VAR5, VAR1;
inout VAR2, VAR3;
output VAR4;
VAR6 VAR9(.VAR1(VAR1),.VAR4(VAR4),.VAR5(VAR5),.VAR8(VAR8),.VAR7(VAR7),.VAR2(VAR2),.VAR3(VAR3));
VAR6 VAR10(.VAR1(VAR1),.VAR4(VAR4),.VAR5(VAR5),.VAR8(VAR8),.VAR7(VAR7),.VAR2(VAR2),.VAR3(VAR3)); | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/SyncHandshake.v | 4,042 | module MODULE1(
VAR2,
VAR15,
VAR5,
VAR7,
VAR3,
VAR16
);
parameter VAR13 = 1'b0;
input VAR2 ;
input VAR15 ;
input VAR7 ;
output VAR3 ;
input VAR5 ;
output VAR16 ;
reg VAR1, VAR8 ;
reg VAR12 ;
reg VAR17 ;
reg VAR6, VAR4 ;
assign VAR16 = VAR8 != VAR12 ;
assign VAR3 = VAR4 == VAR17;
always @(posedge VAR2 or VAR9 VAR15)
beg... | lgpl-3.0 |
borti4938/sd2snes | verilog/sd2snes_obc1/main.v | 21,897 | module MODULE1(
output [22:0] VAR160,
output VAR161,
input VAR241,
output VAR331,
input VAR175,
output [21:0] VAR160,
output VAR156,
output VAR220,
output VAR131,
output VAR217,
output VAR91,
input VAR77,
input VAR60,
input [23:0] VAR252,
input VAR308,
input VAR259,
input VAR270,
inout [7:0] VAR257,
input VAR144,
input... | gpl-2.0 |
tugrulyatagan/RISC-processor | xilinx_processor/glbl.v | 1,345 | module MODULE1 ();
parameter VAR18 = 100000;
parameter VAR10 = 0;
wire VAR21;
wire VAR25;
wire VAR9;
wire VAR5;
tri1 VAR7;
tri (weak1, strong0) VAR1 = VAR7;
wire VAR27;
reg VAR20;
reg VAR22;
reg VAR28;
wire VAR23;
wire VAR6;
wire VAR26;
wire VAR4;
wire VAR13;
reg VAR24;
reg VAR30;
reg VAR2;
reg VAR14;
reg VAR12;
reg VA... | gpl-2.0 |
horia141/bachelor-thesis | prj/components/RegBank/RegBankS8.v | 11,895 | module MODULE1(VAR20,reset,VAR5,VAR31,out);
input wire VAR20;
input wire reset;
input wire [11:0] VAR5;
input wire VAR31;
output wire [7:0] out;
reg [1:0] VAR8;
reg [2:0] VAR36;
reg [7:0] VAR33;
reg [7:0] VAR1;
reg [7:0] VAR16;
reg [7:0] VAR17;
reg [7:0] VAR24;
reg [7:0] VAR39;
reg [7:0] VAR14;
reg [7:0] VAR4;
wire [7:... | mit |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/rtr_channel_input.v | 13,525 | module MODULE1
(clk, reset, VAR16, VAR41, VAR42, VAR54,
VAR46, VAR38, VAR5, VAR26,
VAR27);
parameter VAR56 = 4;
parameter VAR20 = VAR30;
parameter VAR40 = 4;
parameter VAR50 = 1;
parameter VAR49 = 14;
parameter VAR6 = 1;
parameter VAR47 = 64;
parameter VAR18 = VAR57;
localparam VAR34 = VAR3(VAR56);
localparam VAR28
= V... | gpl-2.0 |
piotr-wiszowaty/atari_xlxe_sd_cartridge | cpld/main.v | 5,357 | module MODULE1(
input VAR4,
output VAR26,
input VAR50,
input VAR10,
input VAR21,
input VAR2,
input VAR7,
output reg VAR22 = 1,
output reg VAR20 = 1,
input [12:0] VAR35,
inout [7:0] VAR40,
output VAR34,
output VAR19,
output [14:0] VAR16,
inout [7:0] VAR17,
input clk,
inout [7:0] VAR39,
output reg VAR33 = 0,
input VAR37,... | gpl-3.0 |
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