repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/Kintex7_160T_experimental/uart_transmitter.v | 1,700 | module MODULE1 # (
parameter VAR7 = 100000000,
parameter VAR2 = 115200
) (
input clk,
output VAR1,
input VAR6,
input [7:0] VAR5,
output VAR3
);
localparam [15:0] VAR4 = (VAR7 / VAR2) - 1;
reg [15:0] VAR9 = 16'd0;
reg [9:0] state = 10'd1023, VAR8 = 10'd1023;
assign VAR1 = VAR8[0];
assign VAR3 = state[0] & ~VAR6;
always ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvgnd/sky130_fd_sc_lp__tapvgnd.pp.symbol.v | 1,258 | module MODULE1 (
input VAR2 ,
input VAR3,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
versaloon/vsf | vsf/old/example/vsfusbh/proj/Keil_v5_CMEM7/fpga/src/pll_v1.v | 3,995 | module MODULE1(
VAR25,
VAR44,
VAR23,
VAR30
);
input VAR25;
output VAR44;
output VAR23;
output VAR30;
VAR20 #(
.VAR56 (1'b0),
.VAR49 (4'b0000),
.VAR32 ("VAR41"),
.VAR31 (2'b01),
.VAR7 (2'b00),
.VAR45 (8'b00111011),
.VAR5 (8'b00000000),
.VAR6 (8'b00000101),
.VAR16 (8'b01100011),
.VAR47 (8'b00000111),
.VAR62 (8'b00000010)... | gpl-3.0 |
LSaldyt/qnp | output/vs/var21_multi.v | 1,618 | module MODULE1 (VAR5, VAR9, VAR21, VAR1, VAR20, VAR11, VAR25, VAR27, VAR13, VAR17, VAR8, VAR12, VAR23, VAR14, VAR26, VAR24, VAR3, VAR6, VAR4, VAR15, VAR22, valid);
input VAR5, VAR9, VAR21, VAR1, VAR20, VAR11, VAR25, VAR27, VAR13, VAR17, VAR8, VAR12, VAR23, VAR14, VAR26, VAR24, VAR3, VAR6, VAR4, VAR15, VAR22;
output val... | mit |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/hb/mac.v | 2,497 | module MODULE1 (input VAR7, input reset, input enable, input VAR4,
input signed [15:0] VAR1, input signed [15:0] VAR2,
input [7:0] VAR8, output [15:0] VAR5 );
reg signed [30:0] VAR9;
reg signed [39:0] VAR10;
reg signed [15:0] VAR3;
reg VAR6;
always @(posedge VAR7)
VAR6 <= enable;
always @(posedge VAR7)
if(reset | VAR4)... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtn/sky130_fd_sc_ls__dlrtn.symbol.v | 1,416 | module MODULE1 (
input VAR1 ,
output VAR4 ,
input VAR8,
input VAR3
);
supply1 VAR7;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_compressor_block.v | 4,769 | module MODULE1
parameter VAR7 = 4, parameter VAR14 = 14, parameter VAR4 = 10 )
(
input VAR16,
input VAR25 ,
input [VAR7:0] VAR27,
input VAR5,
input VAR17,
input signed [VAR14-1:0] VAR19,
input signed [VAR14-1:0] VAR6,
output signed [VAR14-1:0] VAR15
);
reg signed [VAR14+VAR18-1:0] VAR26;
reg signed [VAR14+VAR18-1:0] VA... | mit |
jotego/jt12 | hdl/jt12_eg_comb.v | 4,080 | module MODULE1(
input VAR10,
input VAR17,
input [2:0] VAR57,
input [9:0] VAR12,
input [4:0] VAR18, input [4:0] VAR37, input [4:0] VAR47, input [3:0] VAR36,
input [3:0] VAR43, input VAR39,
input [2:0] VAR20,
input VAR25,
output VAR19,
output [4:0] VAR23,
output [2:0] VAR35,
output VAR34,
input VAR50,
input [ 4:0] VAR7,
... | gpl-3.0 |
hhuang25/uwaterloo_ece224 | Lab1/pio_period.v | 2,084 | module MODULE1 (
address,
VAR1,
clk,
VAR6,
VAR5,
VAR3,
VAR4,
VAR8
)
;
output [ 3: 0] VAR4;
output [ 3: 0] VAR8;
input [ 1: 0] address;
input VAR1;
input clk;
input VAR6;
input VAR5;
input [ 3: 0] VAR3;
wire VAR9;
reg [ 3: 0] VAR2;
wire [ 3: 0] VAR4;
wire [ 3: 0] VAR7;
wire [ 3: 0] VAR8;
assign VAR9 = 1;
assign VAR7 = {... | mit |
ECE492-Team5/Platform | soc-platform-quartusii/hps_fpga_system.v | 14,278 | module MODULE1(
output VAR154,
output VAR132,
output VAR51,
input VAR66,
inout [15:0] VAR120,
inout VAR80,
input VAR96,
input VAR32,
input VAR29,
inout [35:0] VAR61,
inout [35:0] VAR67,
inout VAR135,
output [14:0] VAR139,
output [2:0] VAR116,
output VAR75,
output VAR99,
output VAR3,
output VAR30,
output VAR118,
output ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s.symbol.v | 1,358 | module MODULE1 (
input VAR4,
output VAR3
);
supply1 VAR6;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
Raamakrishnan/MyProc | MyProc2/ID.v | 2,386 | module MODULE1 (
input wire clk, input wire VAR12,
input wire [VAR16 - 1:0] VAR14,
input wire [VAR16 - 3:0] VAR30,
output wire [VAR16 - 1:0] VAR11,
output wire [VAR16 - 3:0] VAR21,
output wire [VAR16 - 1:0] VAR13,
output wire [VAR16 - 1:0] VAR29,
output reg [VAR15 - 1:0] VAR6,
input wire [VAR16 - 1:0] VAR8,
output reg ... | mit |
KorotkiyEugene/LAG_sv_syn_quartus | LAG_fifo.v | 7,711 | typedef struct packed
{
logic VAR17, VAR16, VAR31, VAR7;
} VAR30;
module MODULE2 (VAR6, VAR34, VAR13, VAR28, VAR5, clk, VAR33);
parameter VAR8 = 8;
input VAR6, VAR34;
output VAR30 VAR5;
input VAR14 VAR13;
output VAR14 VAR28;
input clk, VAR33;
logic VAR11, VAR4;
VAR14 VAR23, VAR15;
MODULE1 #(.VAR8(VAR8))
VAR27 (VAR6, VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fa/sky130_fd_sc_hs__fa_4.v | 2,151 | module MODULE2 (
VAR8,
VAR4 ,
VAR2 ,
VAR7 ,
VAR3 ,
VAR6,
VAR9
);
output VAR8;
output VAR4 ;
input VAR2 ;
input VAR7 ;
input VAR3 ;
input VAR6;
input VAR9;
VAR1 VAR5 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR8,
VAR4 ,
VAR2 ,
VAR7 ,
VAR3
)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22ai/sky130_fd_sc_ls__o22ai.behavioral.v | 1,615 | module MODULE1 (
VAR10 ,
VAR3,
VAR6,
VAR5,
VAR2
);
output VAR10 ;
input VAR3;
input VAR6;
input VAR5;
input VAR2;
supply1 VAR8;
supply0 VAR16;
supply1 VAR9 ;
supply0 VAR1 ;
wire VAR14 ;
wire VAR11 ;
wire VAR4;
nor VAR13 (VAR14 , VAR5, VAR2 );
nor VAR7 (VAR11 , VAR3, VAR6 );
or VAR12 (VAR4, VAR11, VAR14);
buf VAR15 (VAR... | apache-2.0 |
hakehuang/pycpld | ips/ip/uart8bit/data_deal.v | 1,672 | module MODULE1(
clk,
VAR3,
VAR5,
VAR1,
VAR2,
VAR8,
VAR7,
VAR9
);
input clk;
input VAR3;
input [7:0] VAR5;
input VAR1;
output [7:0] VAR2;
output VAR8;
input VAR7;
output VAR9;
reg [7:0] VAR4;
reg [3:0] VAR6;
reg VAR9;
reg [7:0] VAR2;
reg VAR8;
always @(posedge clk or negedge VAR3)begin
if(!VAR3)begin
VAR4 <= 8'h0;
VAR6 ... | mit |
Obijuan/open-fpga-verilog-tutorial | tutorial/ICESTICK/T15-divisor/divM.v | 1,281 | module MODULE1(input wire VAR4, output wire VAR3);
parameter VAR2 = 12000000;
localparam VAR1 = VAR6(VAR2);
reg [VAR1-1:0] VAR5 = 0;
always @(posedge VAR4)
if (VAR5 == VAR2 - 1)
VAR5 <= 0;
else
VAR5 <= VAR5 + 1;
assign VAR3 = VAR5[VAR1-1];
endmodule | gpl-2.0 |
lokisz/openzcore | pippo-0.9/rtl/verilog/pippo_if.v | 12,305 | module MODULE1(
clk, rst,
VAR14, VAR25, VAR3,
VAR15, VAR28, VAR20, VAR18,
VAR10, VAR13, VAR16, VAR12,
VAR33, VAR8, VAR31, VAR35, VAR21,
VAR5, VAR24, VAR27, VAR19,
VAR34
);
input clk;
input rst;
input [31:0] VAR20;
input VAR15;
input VAR28;
input [31:0] VAR18;
input VAR3;
output [31:0] VAR14;
output VAR25;
input [29:0] ... | gpl-2.0 |
toyoshim/mc6502 | rtl/MC6502ExecutionController.v | 11,992 | module MODULE1(
clk,
VAR124,
VAR56,
VAR123,
VAR138,
VAR135,
VAR28,
VAR6,
VAR17,
VAR36,
VAR103,
VAR9,
VAR76,
VAR82,
VAR85,
VAR22,
VAR43,
VAR46,
VAR113,
VAR70,
VAR35,
VAR75,
VAR105,
VAR5,
VAR32,
VAR121,
VAR125,
VAR119,
VAR118,
VAR31,
VAR107,
VAR1,
VAR106,
VAR4,
VAR134,
VAR115,
VAR139,
VAR2,
VAR89,
VAR88,
VAR104,
VAR128,
... | bsd-3-clause |
cr88192/bgbtech_bjx1core | bjx1c32b1/DecOp4.v | 43,554 | module MODULE1(
clk,
VAR136,
VAR81,
VAR121,
VAR8,
VAR344,
VAR328,
VAR107,
VAR197,
VAR51
);
parameter VAR282 = 0; parameter VAR53 = 0; parameter VAR220 = 1;
input clk; input[47:0] VAR136; input[15:0] VAR81;
output[6:0] VAR121;
output[6:0] VAR8;
output[6:0] VAR344;
output[31:0] VAR328;
output[3:0] VAR107;
output[3:0] VAR... | mit |
sabertazimi/hust-lab | verilog/labs/lab2/src/decoder_74138_dataflow.v | 1,077 | module MODULE1(
input [0:2] VAR3,
input VAR1,
input VAR4,
input VAR5,
output [7:0] VAR2
);
assign VAR2[0] = VAR4|VAR5|(~VAR1)|VAR3[0]|VAR3[1]|VAR3[2];
assign VAR2[1] = VAR4|VAR5|(~VAR1)|VAR3[0]|VAR3[1]|(~VAR3[2]);
assign VAR2[2] = VAR4|VAR5|(~VAR1)|VAR3[0]|(~VAR3[1])|VAR3[2];
assign VAR2[3] = VAR4|VAR5|(~VAR1)|VAR3[0]|... | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4SharedKES_v1_0_1/c727b95e/src/d_KES_CS_buffer.v | 14,090 | module MODULE1
parameter VAR4 = 2,
parameter VAR26 = 12,
parameter VAR22 = 9,
parameter VAR46 = 15
)
(
VAR3 ,
VAR42 ,
VAR9 ,
VAR29 ,
VAR1 ,
VAR18 ,
VAR24 ,
VAR16 ,
VAR48 ,
VAR7 ,
VAR13 ,
VAR36 ,
VAR45 ,
VAR47 ,
VAR40 ,
VAR17 ,
VAR25 ,
VAR19 ,
VAR2 ,
VAR60 ,
VAR20 ,
VAR30 ,
VAR52 ,
VAR11 ,
VAR5 ,
VAR44 ,
VAR33 ,
VAR31 ,... | gpl-3.0 |
ncos/Xilinx-Verilog | GYRACC/src/GYRO/spi_interface.v | 5,167 | module MODULE1(
VAR7,
VAR19,
VAR18,
VAR21,
clk,
rst,
VAR2,
VAR3,
VAR5,
VAR15
);
input [7:0] VAR7;
input VAR19;
input VAR18;
input VAR21;
input clk;
input rst;
output [7:0] VAR2;
output VAR3;
output VAR5;
output VAR15;
reg [7:0] VAR2;
reg VAR3;
reg VAR5;
parameter [11:0] VAR20 = 12'hFFF;
reg [11:0] VAR14;
reg VAR4;
reg ... | mit |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/HCORDIC_Pipeline.v | 3,318 | module MODULE1(
input [15:0] VAR55,
input VAR7,
output [31:0] VAR79,
output [31:0] VAR66,
output [31:0] VAR9,
output VAR47
);
wire VAR72,VAR70,VAR18,VAR15;
wire VAR8,VAR41,VAR51,VAR24;
wire [1:0] VAR1,VAR28,VAR37,VAR69;
wire [31:0] VAR40, VAR60, VAR62, VAR53, VAR78;
wire [31:0] VAR64, VAR36, VAR13, VAR23, VAR11;
wire [... | apache-2.0 |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/altera_avalon_st_bytes_to_packets.v | 8,093 | module MODULE1
parameter VAR3 = 0 )
(
input clk,
input VAR10,
input VAR6,
output reg VAR20,
output reg [7: 0] VAR17,
output reg [VAR8-1: 0] VAR21,
output reg VAR5,
output reg VAR12,
output reg VAR16,
input VAR9,
input [7: 0] VAR11
);
reg VAR19, VAR4, VAR2;
wire VAR18, VAR13, VAR15, VAR14, VAR7;
wire [7:0] VAR1;
assign ... | epl-1.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_pipe_eq.v | 35,634 | module MODULE1 #
(
parameter VAR83 = "VAR34",
parameter VAR42 = "VAR29",
parameter VAR50 = 1
)
(
input VAR108,
input VAR91,
input VAR125,
input [ 1:0] VAR86,
input [ 3:0] VAR71,
input [ 3:0] VAR23,
input [ 5:0] VAR117,
input [ 1:0] VAR98,
input [ 2:0] VAR54,
input [ 5:0] VAR32,
input [ 3:0] VAR123,
input VAR69,
input [... | gpl-3.0 |
impedimentToProgress/ProbableCause | ddr2/cores/ram_wb/ram_wb_b3.v | 7,673 | module MODULE1(
VAR22, VAR31, VAR33, VAR3, VAR29, VAR26,
VAR7, VAR27,
VAR28, VAR37, VAR9, VAR30,
VAR2, VAR8);
parameter VAR16 = 32;
parameter VAR14 = 32;
input [VAR14-1:0] VAR22;
input [1:0] VAR31;
input [2:0] VAR33;
input VAR3;
input [VAR16-1:0] VAR29;
input [3:0] VAR26;
input VAR7;
input VAR27;
output VAR28;
output V... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_reset_controller_171/synth/altera_reset_controller.v | 12,012 | module MODULE1
parameter VAR42 = 6,
parameter VAR34 = 0,
parameter VAR45 = 0,
parameter VAR76 = 0,
parameter VAR68 = 0,
parameter VAR21 = 0,
parameter VAR70 = 0,
parameter VAR46 = 0,
parameter VAR77 = 0,
parameter VAR64 = 0,
parameter VAR44 = 0,
parameter VAR40 = 0,
parameter VAR20 = 0,
parameter VAR31 = 0,
parameter V... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_cmos2_term_up.v | 1,120 | module MODULE1 (
VAR1, out
);
inout out;
input VAR1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xnor2/sky130_fd_sc_hvl__xnor2.symbol.v | 1,305 | module MODULE1 (
input VAR7,
input VAR6,
output VAR3
);
supply1 VAR5;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2.blackbox.v | 1,323 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR1;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtx_x8_125/source/pcie_blk_ll_credit.v | 36,978 | module MODULE1
parameter VAR109 = 0,
parameter VAR37 = 4,
parameter VAR201 = 9,
parameter VAR89 = 12,
parameter VAR148 = 72'h6808682C6808680CFF, parameter VAR179 = 96'h406044644C6C2024282C3034,
parameter VAR144 = 3'b101,
parameter VAR122 = 0,
parameter VAR13 = 0,
parameter VAR90 = 0,
parameter VAR196 = 0,
parameter VAR... | lgpl-3.0 |
osrf/wandrr | firmware/motor_controller/fpga/foc_consts_32x32.v | 1,433 | module MODULE1
(input VAR1,
input [ 4:0] addr,
output reg [31:0] VAR2);
VAR3 VAR2 = 32'h0;
always @(posedge VAR1) begin
case (addr)
5'h00: VAR2 = 32'hc6800000; 5'h01: VAR2 = 32'h3bd55555; 5'h02: VAR2 = 32'h3f2aaaab; 5'h03: VAR2 = 32'hbeaaaaab; 5'h04: VAR2 = 32'h3f13cd36; 5'h05: VAR2 = 32'hbf13cd36; 5'h06: VAR2 = 32'hbf... | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/bus/bus.v | 13,926 | module MODULE1(
input wire clk , input wire reset , input wire VAR41 , output wire VAR29 , input wire [VAR6] VAR2 , input wire VAR14 , input wire VAR50 , input wire [VAR25] VAR59 , input wire VAR10 , output wire VAR9 , input wire [VAR6] VAR43 , input wire VAR19 , input wire VAR46 , input wire [VAR25] VAR28 , input wire... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxtp/sky130_fd_sc_hs__edfxtp.functional.v | 1,632 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR5 ,
VAR4 ,
VAR2,
VAR9
);
output VAR11 ;
input VAR3 ;
input VAR5 ;
input VAR4 ;
input VAR2;
input VAR9;
wire VAR6;
VAR7 VAR10 VAR1 (VAR6 , VAR5, VAR3, VAR4, VAR2, VAR9);
buf VAR8 (VAR11 , VAR6 );
endmodule | apache-2.0 |
thucoldwind/ucore_mips | CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/pc.v | 1,025 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR11,
input wire[31:0] VAR5,
input wire VAR8,
input wire VAR9,
input wire VAR6,
input wire[31:0] VAR4,
output reg[31:0] VAR2
);
wire[31:0] VAR10 = VAR2 + 32'h4;
wire[31:0] VAR3 = VAR2;
always @(posedge clk) begin
if (rst == VAR7) begin
VAR2 <= 32'h80000000 - 4... | unlicense |
SiLab-Bonn/basil | basil/firmware/modules/bram_fifo/bram_fifo.v | 2,876 | module MODULE1 #(
parameter VAR24 = 32'h0000,
parameter VAR2 = 32'h0000,
parameter VAR23 = 32,
parameter VAR38 = 32'h0000,
parameter VAR32 = 32'h0000,
parameter VAR31 = 32'h8000*8,
parameter VAR18 = 95, parameter VAR15 = 5 ) (
input wire VAR16,
input wire VAR14,
input wire [VAR23-1:0] VAR42,
inout wire [31:0] VAR37,
in... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32oi/sky130_fd_sc_ms__a32oi_2.v | 2,483 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR7 ,
VAR5 ,
VAR6 ,
VAR11 ,
VAR3,
VAR4,
VAR10 ,
VAR1
);
output VAR8 ;
input VAR2 ;
input VAR7 ;
input VAR5 ;
input VAR6 ;
input VAR11 ;
input VAR3;
input VAR4;
input VAR10 ;
input VAR1 ;
VAR9 VAR12 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR3(VA... | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/fpu/hardlogic/syn2.v | 2,483 | module MODULE1(VAR26,
reset,
VAR38,
VAR5,
VAR36,
VAR19,
VAR45,
VAR24,
VAR10,
VAR25,
VAR12
);
input VAR26;
input reset;
input [VAR9-1:0] VAR38;
input [VAR9-1:0] VAR5;
input [VAR9-1:0] VAR36;
input [VAR9-1:0] VAR19;
input [VAR9-1:0] VAR45;
output [VAR9-1:0] VAR24;
output [VAR9-1:0] VAR10;
output [VAR9-1:0] VAR25;
output ... | mit |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/alu.v | 2,590 | module MODULE1 (
input wire [VAR5] VAR2, input wire [VAR5] VAR7, input wire [VAR1] VAR8, output reg [VAR5] out, output reg VAR11 );
wire signed [VAR5] VAR9 = (VAR2); wire signed [VAR5] VAR4 = (VAR7); wire signed [VAR5] VAR10 = (out);
always @ begin
case (VAR8)
((VAR9 < 0) && (VAR4 < 0) && (VAR10 > 0))) begin
VAR11 = VA... | apache-2.0 |
htuNCSU/MmcCommunicationVerilog | MAX10_SLAVE/phyIniCommand0.v | 1,139 | module MODULE1
(
input [(VAR1-1):0] VAR2,
input [(VAR5-1):0] addr,
input VAR7, clk,
output [(VAR1-1):0] VAR4
);
reg [VAR1-1:0] VAR3[2**VAR5-1:0];
reg [VAR5-1:0] VAR6;
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4bb/sky130_fd_sc_ms__nor4bb_4.v | 2,325 | module MODULE2 (
VAR9 ,
VAR6 ,
VAR8 ,
VAR5 ,
VAR4 ,
VAR7,
VAR2,
VAR1 ,
VAR10
);
output VAR9 ;
input VAR6 ;
input VAR8 ;
input VAR5 ;
input VAR4 ;
input VAR7;
input VAR2;
input VAR1 ;
input VAR10 ;
VAR11 VAR3 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR10... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/one_hot_mux.v | 4,781 | module MODULE1
parameter VAR3 = 2,
parameter VAR4 = VAR3*VAR5
)
(
input [VAR3-1:0] VAR8,
input [VAR4-1:0] VAR2,
output [VAR5-1:0] VAR9);
genvar VAR6;
wire [VAR5-1:0] VAR10[(1<<VAR3):1];
reg [VAR5-1:0] VAR7;
assign VAR9 = VAR7;
generate
for( VAR6 = 0 ; VAR6 < VAR3; VAR6 = VAR6 + 1 ) begin : VAR1
assign VAR10[(1<<VAR6)] ... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_004.v | 1,561 | module MODULE1 (
VAR15,
VAR6
);
input [31:0] VAR15;
output [31:0]
VAR6;
wire [31:0]
VAR12,
VAR9,
VAR2,
VAR1,
VAR10,
VAR8,
VAR13,
VAR4,
VAR5,
VAR11;
assign VAR12 = VAR15;
assign VAR9 = VAR12 << 7;
assign VAR2 = VAR12 + VAR9;
assign VAR1 = VAR2 << 4;
assign VAR11 = VAR5 << 3;
assign VAR10 = VAR2 + VAR1;
assign VAR5 = VAR... | mit |
ludisu13/Estructuras2 | Tarea_final_Decodificador/decodificador.v | 6,239 | module MODULE1(
input wire VAR14,
input wire[15:0] VAR1,
input wire VAR2, VAR7, VAR5, VAR12, VAR8, VAR9,
output reg VAR6,
output reg VAR11;
output reg[9:0] VAR4,
output reg[7:0] VAR3,
output reg VAR13,
output reg VAR10
);
always @(posedge VAR14)
begin
case(VAR1[15:0])
begin
VAR11<=0;
VAR13<=0;
VAR10<=0;
VAR6<=0;
VAR4<=... | gpl-3.0 |
zhangly/azpr_cpu | rtl/top/lib/altera_dpram_bb.v | 8,727 | module MODULE1 (
VAR4,
VAR8,
VAR5,
VAR10,
VAR7,
VAR2,
VAR6,
VAR1,
VAR3,
VAR9);
input [11:0] VAR4;
input [11:0] VAR8;
input VAR5;
input VAR10;
input [31:0] VAR7;
input [31:0] VAR2;
input VAR6;
input VAR1;
output [31:0] VAR3;
output [31:0] VAR9;
tri1 VAR5;
tri0 VAR6;
tri0 VAR1;
endmodule | mit |
asicguy/gplgpu | hdl/altera_ddr3/alt_ddrx_bank_tracking.v | 52,084 | module MODULE1 #
( parameter
VAR38 = 2,
VAR106 = 2,
VAR124 = 16, VAR18 = 3,
VAR33 = 6, VAR85 = 8
)
(
VAR6,
VAR77,
VAR73,
VAR8,
VAR70,
VAR36,
VAR92,
VAR148,
VAR58,
VAR39,
VAR108,
VAR164,
VAR67,
VAR40,
VAR127,
VAR176,
VAR49,
VAR21,
VAR42,
VAR41,
VAR20,
VAR154,
VAR134,
VAR24,
VAR177,
VAR7,
VAR153,
VAR53,
VAR1,
VAR75,
VAR2... | gpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_sa1/sa1_iram.v | 10,701 | module MODULE1 (
VAR18,
VAR17,
VAR23,
VAR47,
VAR27,
VAR2,
VAR33,
VAR13,
VAR34);
input [10:0] VAR18;
input [10:0] VAR17;
input VAR23;
input [7:0] VAR47;
input [7:0] VAR27;
input VAR2;
input VAR33;
output [7:0] VAR13;
output [7:0] VAR34;
tri1 VAR23;
tri0 VAR2;
tri0 VAR33;
wire [7:0] VAR35;
wire [7:0] VAR19;
wire [7:0] VA... | gpl-2.0 |
kyzhai/NUNY | src/hardware/letterf.v | 6,374 | module MODULE1 (
address,
VAR5,
VAR22);
input [11:0] address;
input VAR5;
output [11:0] VAR22;
tri1 VAR5;
wire [11:0] VAR11;
wire [11:0] VAR22 = VAR11[11:0];
VAR52 VAR38 (
.VAR17 (address),
.VAR3 (VAR5),
.VAR23 (VAR11),
.VAR46 (1'b0),
.VAR12 (1'b0),
.VAR31 (1'b1),
.VAR39 (1'b0),
.VAR33 (1'b0),
.VAR28 (1'b1),
.VAR43 (1'... | gpl-2.0 |
rohit91/HDMI2USB | hdl/UART/TX_module.v | 4,287 | module MODULE1
parameter VAR15 = 8, VAR6 = 16 )
(
input wire clk, reset,
input wire VAR7, VAR2,
input wire [7:0] din,
output reg VAR4,
output wire VAR12
);
localparam [1:0]VAR17 = 2'b00,VAR14 = 2'b01,VAR13 = 2'b10,VAR16 = 2'b11;
reg [1:0] state, VAR11;
reg [3:0] VAR19, VAR9;
reg [2:0] VAR18, VAR5;
reg [7:0] VAR10, VAR1... | bsd-2-clause |
sabertazimi/hust-lab | digitalLogic/design/clock_design/src/timing_clock.v | 3,862 | module MODULE1
(
input VAR10,
input [(VAR16-1):0] VAR19,
input VAR2,
input VAR3,
input VAR5,
input enable,
input reset,
input [2:0] VAR1,
input [2:0] VAR20,
input [(VAR16-1):0] VAR23,
input [(VAR16-1):0] VAR12,
input [(VAR16-1):0] VAR17,
output [7:0] VAR15,
output [7:0] VAR14,
output [(VAR4-1):0] VAR18
);
wire [(VAR16-... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211a/sky130_fd_sc_hs__o211a.pp.blackbox.v | 1,336 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR3 ,
VAR6 ,
VAR7 ,
VAR5,
VAR4
);
output VAR2 ;
input VAR1 ;
input VAR3 ;
input VAR6 ;
input VAR7 ;
input VAR5;
input VAR4;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_adc_pack/util_adc_pack.v | 17,218 | module MODULE1 (
clk,
VAR46,
VAR26,
VAR44,
VAR38,
VAR2,
VAR30,
VAR50,
VAR37,
VAR15,
VAR6,
VAR21,
VAR32,
VAR13,
VAR19,
VAR3,
VAR52,
VAR20,
VAR34,
VAR23,
VAR39,
VAR56,
VAR17,
VAR40,
VAR22,
VAR11,
VAR57,
VAR48
);
parameter VAR42 = 8 ; parameter VAR41 = 16;
input clk;
input VAR46;
input VAR26;
input [(VAR41-1):0] VAR44;
in... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_axi_basic_tx_pipeline.v | 22,439 | module MODULE1 #(
parameter VAR49 = 128, parameter VAR50 = "VAR26", parameter VAR40 = 1,
parameter VAR38 = (VAR49 == 128) ? 2 : 1, parameter VAR39 = VAR49 / 8 ) (
input [VAR49-1:0] VAR62, input VAR31, output VAR44, input [VAR39-1:0] VAR19, input VAR12, input [3:0] VAR6,
output [VAR49-1:0] VAR33, output VAR13, output VA... | gpl-3.0 |
ptracton/pmodacl2 | soc/tasks/uart_tasks.v | 2,827 | module MODULE1;
task VAR3;
begin
@(posedge VAR5);
@(posedge VAR5);
@(posedge VAR5);
@(posedge VAR5);
@(posedge VAR5);
@(posedge VAR5);
end
endtask
task VAR1;
input [7:0] VAR2;
begin
@(posedge VAR5);
end
endtask
task VAR4;
input [7:0] VAR6;
begin
begin
end
end
endtask
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fa/sky130_fd_sc_lp__fa_2.v | 2,278 | module MODULE2 (
VAR8,
VAR2 ,
VAR1 ,
VAR11 ,
VAR4 ,
VAR5,
VAR9,
VAR3 ,
VAR10
);
output VAR8;
output VAR2 ;
input VAR1 ;
input VAR11 ;
input VAR4 ;
input VAR5;
input VAR9;
input VAR3 ;
input VAR10 ;
VAR6 VAR7 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR... | apache-2.0 |
DeanoC/ice40k-zpu | zpu_rom.v | 1,076 | module MODULE1(
input clk,
input [VAR7-1:0] addr,
output [7:0] dout);
parameter VAR7 = 8;
reg [7:0] dout;
reg [7:0] VAR11;
VAR19 #(
.VAR6(256'h80DA0B80C0A8808C0C0B0B0B0BA00881),
.VAR24(256'h050B0B0B0BA00C0B0B0B0B8004000000),
.VAR5(256'h00000001000000000000000000000000),
.VAR13(256'h00000000000000900000000000000090),
.V... | mit |
glennchid/font5-firmware | src/verilog/synthesis/MuxModule_old (1).v | 2,022 | module MODULE1(
input VAR10,
input [1:0] sel,
input signed[12:0] VAR17,
input signed [12:0] VAR20,
input signed [12:0] VAR16,
input signed [12:0] VAR9,
input signed [12:0] VAR8,
input signed [12:0] VAR15,
output reg signed [14:0] VAR6,
output reg signed [14:0] VAR14,
output reg signed [14:0] VAR18,
output reg signed [1... | gpl-3.0 |
freecores/orsoc_graphics_accelerator | bench/verilog/gfx/interp_bench.v | 3,012 | module MODULE1();
parameter VAR15 = 16;
parameter VAR4 = 5;
parameter VAR2 = 3;
reg VAR6; reg VAR13; reg VAR17;
wire VAR11;
reg VAR14;
reg [2*VAR15 -1:0] VAR3; reg [2*VAR15 -1:0] VAR10; reg [2*VAR15 -1:0] VAR8;
reg [VAR15 -1:0] VAR16;
reg [VAR15 -1:0] VAR1;
wire [VAR15 -1:0] VAR12;
wire [VAR15 -1:0] VAR5;
wire [VAR15 -... | gpl-3.0 |
Canaan-Creative/MM | verilog/superkdf9/components/spi/wb_spi.v | 24,050 | module MODULE1 #(
parameter VAR45 = 0,
parameter VAR47 = 0,
parameter VAR23 = 0,
parameter VAR32 = 7,
parameter VAR7 = 1,
parameter VAR6 = 1,
parameter VAR69 = 32,
parameter VAR11 = 2,
parameter VAR13 = 5,
parameter VAR64 = 2)
(
VAR74, VAR61, VAR31,
VAR44,
VAR4,
VAR8,
VAR1,
VAR60,
VAR58,
VAR71, VAR26,
VAR35,
VAR62,
VAR... | unlicense |
ludisu13/Estructuras2 | Tarea_final_Memoria/generator.v | 1,703 | module MODULE2(clk, VAR4, VAR3, VAR1, VAR6, VAR7, VAR2);
output clk, VAR3, VAR1, VAR6;
output [7:0] VAR4;
output [9:0] VAR7;
output [9:0] VAR2;
MODULE1 MODULE1(clk);
VAR8 VAR5(VAR4, VAR3, VAR1, VAR6, VAR7, VAR2);
endmodule
module MODULE1(clk);
output reg clk;
begin
begin
begin | gpl-3.0 |
sabertazimi/hust-lab | verilog/labs/lab5/src/_4bit_binary_multiplier.v | 2,997 | module MODULE1(
module 4bitbinarymultiplier
(
input VAR20,
input clk,
input [VAR6:0] VAR16,
input [VAR6:0] VAR22,
output [((VAR6*2)-1):0] VAR2,
output VAR3
);
reg [(VAR6-1):0] VAR9 [0: (2*(2**VAR6)-1)];
wire VAR5, VAR14, VAR19, VAR23, VAR15;
wire VAR18;
wire [(VAR6-1):0] VAR4, VAR10;
wire VAR7;
wire VAR8, VAR12, VAR1;
... | mit |
TalentlessAlpaca/Automated_Vacuum_Cleaner | Ultrasonico/ultrasonic_ctrl.v | 1,914 | module MODULE1 (
input clk ,
input enable ,
input VAR5 ,
output [15:0] VAR2 ,
output reg VAR11
) ;
reg [2:0] state ;
reg VAR6 ;
reg VAR18 ;
reg VAR7 ;
reg VAR13 ;
wire [31:0] VAR19 ;
wire VAR14 ;
wire VAR12 ;
localparam VAR4 = 3'b000 ; localparam VAR8 = 3'b001 ; localparam VAR16 = 3'b010 ;
always @ ( negedge clk )
if (... | mit |
CospanDesign/nysa-verilog | verilog/generic/uart_controller.v | 6,880 | module MODULE1 #(
parameter VAR59 = 115200
)(
input clk,
input rst,
input VAR40,
output VAR35,
output reg VAR58,
input VAR53,
input VAR57,
input VAR12,
output [31:0] VAR3,
input VAR28,
input [31:0] VAR8,
output [31:0] VAR5,
input VAR16,
input [7:0] VAR38,
output VAR27,
output [31:0] VAR32,
output [31:0] VAR52,
output V... | mit |
SymbiFlow/yosys | techlibs/xilinx/lut_map.v | 3,501 | module MODULE1 (VAR2, VAR19);
parameter VAR35 = 0;
parameter VAR21 = 0;
input [VAR35-1:0] VAR2;
output VAR19;
generate
if (VAR35 == 1) begin
if (VAR21 == 2'b01) begin
VAR20 VAR15 (.VAR36(VAR19), .VAR5(VAR2[0]));
end else begin
VAR30 #(.VAR38(VAR21)) VAR15 (.VAR36(VAR19),
.VAR17(VAR2[0]));
end
end else
if (VAR35 == 2) b... | isc |
olajep/oh | src/emesh/hdl/packet2emesh.v | 2,814 | module MODULE1 #(parameter VAR4 = 32, parameter VAR2 = 104) (
input [VAR2-1:0] VAR1,
output VAR13, output [1:0] VAR8, output [4:0] VAR5, output [VAR4-1:0] VAR9, output [VAR4-1:0] VAR12, output [VAR4-1:0] VAR11 );
generate
if(VAR2==104)
begin : VAR7
assign VAR13 = VAR1[0];
assign VAR8[1:0] = VAR1[2:1];
assign VAR5[4:0] ... | mit |
alexforencich/verilog-lfsr | rtl/lfsr.v | 15,991 | module MODULE1 #
(
parameter VAR2 = 31,
parameter VAR20 = 31'h10000001,
parameter VAR16 = "VAR19",
parameter VAR17 = 0,
parameter VAR9 = 0,
parameter VAR18 = 8,
parameter VAR12 = "VAR13"
)
(
input wire [VAR18-1:0] VAR8,
input wire [VAR2-1:0] VAR3,
output wire [VAR18-1:0] VAR6,
output wire [VAR2-1:0] VAR15
);
reg [VAR2-... | mit |
sstallion/apple-mini | cpld/cpld.v | 2,276 | module MODULE1(input reset,
input VAR3,
input [3:0] addr,
output VAR13, VAR28, VAR17, VAR20, VAR23, VAR2,
input VAR25,
output VAR24,
input VAR18,
output VAR11, VAR6,
input VAR12, VAR8,
output [6:0] VAR27,
input [6:0] VAR7,
output VAR21,
input VAR26, VAR14,
output VAR22, VAR5,
inout [7:0] VAR9);
VAR15 VAR10(
.addr(addr)... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21o/sky130_fd_sc_hdll__a21o.blackbox.v | 1,334 | module MODULE1 (
VAR7 ,
VAR3,
VAR6,
VAR1
);
output VAR7 ;
input VAR3;
input VAR6;
input VAR1;
supply1 VAR5;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
kDaniu/miaow | src/verilog/rtl/dispatcher/global_resource_table.v | 26,303 | module MODULE1
(
VAR15, VAR100, VAR142,
VAR93, VAR46, VAR110,
VAR64, VAR163, VAR33,
VAR169, VAR160, VAR149,
VAR129, VAR32, VAR67,
VAR189, VAR6,
clk, rst, VAR139, VAR61,
VAR102, VAR114,
VAR130, VAR97, VAR190,
VAR26, VAR98,
VAR49, VAR44,
VAR19, VAR181,
VAR18, VAR85
);
parameter VAR121 = 64;
parameter VAR79 = 6;
parameter... | bsd-3-clause |
alexforencich/xfcp | lib/eth/rtl/rgmii_phy_if.v | 7,377 | module MODULE1 #
(
parameter VAR52 = "VAR54",
parameter VAR13 = "VAR32",
parameter VAR3 = "VAR25",
parameter VAR36 = "VAR15"
)
(
input wire clk,
input wire VAR59,
input wire rst,
output wire VAR58,
output wire VAR37,
output wire [7:0] VAR57,
output wire VAR46,
output wire VAR10,
output wire VAR26,
output wire VAR56,
ou... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21oi/sky130_fd_sc_ls__a21oi_1.v | 2,261 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR6 ,
VAR3 ,
VAR8,
VAR5,
VAR4 ,
VAR7
);
output VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR3 ;
input VAR8;
input VAR5;
input VAR4 ;
input VAR7 ;
VAR2 VAR10 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE1 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3/sky130_fd_sc_hdll__nor3.functional.pp.v | 1,862 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR11 ,
VAR12 ,
VAR4,
VAR14,
VAR9 ,
VAR5
);
output VAR7 ;
input VAR10 ;
input VAR11 ;
input VAR12 ;
input VAR4;
input VAR14;
input VAR9 ;
input VAR5 ;
wire VAR3 ;
wire VAR2;
nor VAR13 (VAR3 , VAR12, VAR10, VAR11 );
VAR8 VAR6 (VAR2, VAR3, VAR4, VAR14);
buf VAR1 (VAR7 , VAR2 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor4/gf180mcu_fd_sc_mcu9t5v0__nor4_2.behavioral.v | 1,336 | module MODULE1( VAR6, VAR4, VAR5, VAR1, VAR7 );
input VAR7, VAR1, VAR6, VAR5;
output VAR4;
VAR3 VAR2(.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5),.VAR1(VAR1),.VAR7(VAR7));
VAR3 VAR8(.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5),.VAR1(VAR1),.VAR7(VAR7)); | apache-2.0 |
YoelRP/PROYECTO | bin/enpoint/CRC5_D5.v | 1,421 | module MODULE1(
VAR3,
VAR6,
VAR4
);
output [4:0] VAR3;
input [4:0] VAR6;
input [4:0] VAR4;
reg [4:0] VAR5;
reg [4:0] VAR2;
reg [4:0] VAR1;
begin
VAR5 = VAR6;
VAR2 = VAR4;
VAR1[0] = VAR5[3] ^ VAR5[0] ^ VAR2[0] ^ VAR2[3];
VAR1[1] = VAR5[4] ^ VAR5[1] ^ VAR2[1] ^ VAR2[4];
VAR1[2] = VAR5[3] ^ VAR5[2] ^ VAR5[0] ^ VAR2[0] ^ V... | gpl-3.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | decodificador_cs_registros.v | 1,962 | module MODULE1(
input [1:0]VAR10,
output reg VAR4,
output reg VAR3,
output reg VAR1,
output reg VAR6,
output reg VAR9,
output reg VAR2,
output reg VAR5,
output reg VAR7,
output reg VAR8
);
always@*
begin
case(VAR10)
2'b00: begin
VAR4 = 1'b0;
VAR3= 1'b0;
VAR1= 1'b0;
VAR6= 1'b0;
VAR9= 1'b0;
VAR2= 1'b0;
VAR5= 1'b0;
VAR7= ... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/io_cpx_reqdata_ff.v | 2,469 | module MODULE1(
VAR12, VAR10, VAR1,
VAR9, VAR8, VAR11, VAR2, VAR13
);
output [VAR3-1:0] VAR12;
output [7:0] VAR10;
output VAR1;
input [VAR3-1:0] VAR9;
input [7:0] VAR8;
input VAR11;
input VAR2;
input VAR13;
VAR4 #(VAR3) VAR14(
.din (VAR9[VAR3-1:0]),
.VAR6 (VAR12[VAR3-1:0]),
.clk (VAR11),
.VAR13 (VAR13),
.VAR7 (VAR3'd0)... | gpl-2.0 |
bettse/proxmark3 | fpga/lo_read.v | 2,881 | module MODULE1(
input VAR17, input [7:0] VAR7, input VAR10,
output VAR5, output VAR3,
output VAR9, output VAR8, output VAR16, output VAR11,
input [7:0] VAR2, output VAR1,
output VAR15, output VAR13, output VAR6,
output VAR4,
input VAR14
);
reg [7:0] VAR12;
always @(posedge VAR17)
begin
if((VAR7 == 8'd7) && !VAR10)
VAR1... | gpl-2.0 |
aap/pdp6 | verilog/core256k_x.v | 10,213 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR155,
input wire VAR56,
input wire VAR97,
input wire VAR82,
input wire VAR45,
input wire VAR1,
input wire VAR96,
input wire [21:35] VAR62,
input wire [18:21] VAR125,
input wire VAR123,
input wire [0:35] VAR4,
output wire VAR54,
output wire VAR12,
output wir... | mit |
asicguy/gplgpu | hdl/math/real_log2_table.v | 18,767 | module MODULE1
(
input clk,
input VAR3,
input [8:0] VAR1,
output reg [8:0] VAR2
);
always @(posedge clk, negedge VAR3) begin
if(!VAR3) VAR2 <= 9'h0;
end
else begin
case(VAR1)
0: VAR2 <= 9'd0; 1: VAR2 <= 9'd0; 2: VAR2 <= 9'd32; 3: VAR2 <= 9'd50; 4: VAR2 <= 9'd64; 5: VAR2 <= 9'd74; 6: VAR2 <= 9'd82; 7: VAR2 <= 9'd89; 8: ... | gpl-3.0 |
timtian090/Playground | UVM/UVMPlayground/Lab3/Lab3-Project/CLS_PWM_Interval_Timer.v | 1,849 | module MODULE1
parameter VAR2 = 50000000, parameter VAR4 = 1000 )
(
output reg VAR1,
input VAR3
);
begin
begin
begin
end
begin | mit |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2/alt_ddrx_encoder.v | 2,057 | module MODULE1 #
( parameter
VAR1 = 64,
VAR11 = 72
)
(
VAR12,
VAR6,
VAR9
);
input VAR12;
input [VAR1 - 1 : 0] VAR6;
output [VAR11 - 1 : 0] VAR9;
wire [VAR11 - 1 : 0] VAR9;
generate
if (VAR11 == 40)
begin
VAR8 VAR4
(
.VAR2 (VAR12),
.VAR7 (VAR6),
.VAR10 (VAR9 [VAR11 - 2 : 0])
);
assign VAR9 [VAR11 - 1] = 1'b0;
end
else i... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41ai/sky130_fd_sc_ms__o41ai_2.v | 2,424 | module MODULE2 (
VAR7 ,
VAR3 ,
VAR12 ,
VAR5 ,
VAR2 ,
VAR8 ,
VAR6,
VAR4,
VAR11 ,
VAR10
);
output VAR7 ;
input VAR3 ;
input VAR12 ;
input VAR5 ;
input VAR2 ;
input VAR8 ;
input VAR6;
input VAR4;
input VAR11 ;
input VAR10 ;
VAR1 VAR9 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR6(V... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_2.behavioral.pp.v | 1,164 | module MODULE1( VAR5, VAR6, VAR2, VAR1 );
input VAR5;
inout VAR2, VAR1;
output VAR6;
VAR4 VAR3(.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR1(VAR1));
VAR4 VAR7(.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR1(VAR1)); | apache-2.0 |
efabless/openlane | designs/151/src/riscv_arbiter.v | 1,414 | module MODULE1
(
input clk,
input reset,
input VAR8,
output VAR3,
input [VAR5-1:0] VAR10,
output VAR2,
input VAR16,
output VAR18,
input VAR9,
input [VAR5-1:0] VAR4,
output VAR1,
output VAR17,
input VAR14,
output VAR7,
output [VAR5-1:0] VAR13,
output [VAR6-1:0] VAR11,
input VAR15,
input [VAR6-1:0] VAR12
);
assign VAR3 =... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/sqr.v | 6,875 | module MODULE1(VAR1, VAR2);
input wire [232:0] VAR1;
output wire [232:0] VAR2;
assign VAR2[0] = VAR1[0] ^ VAR1[196];
assign VAR2[1] = VAR1[117];
assign VAR2[2] = VAR1[1] ^ VAR1[197];
assign VAR2[3] = VAR1[118];
assign VAR2[4] = VAR1[2] ^ VAR1[198];
assign VAR2[5] = VAR1[119];
assign VAR2[6] = VAR1[3] ^ VAR1[199];
assig... | gpl-3.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/pixelq_op_OUTPUT_STREAM_if.v | 11,190 | module MODULE2 (
input wire VAR11,
input wire VAR38,
output wire VAR31,
input wire VAR57,
output wire [23:0] VAR65,
output wire [2:0] VAR28,
output wire [2:0] VAR15,
output wire [0:0] VAR29,
output wire [0:0] VAR82,
output wire [0:0] VAR18,
output wire [0:0] VAR49,
input wire [23:0] VAR7,
output wire VAR23,
input wire ... | gpl-2.0 |
Jbag/frequency_divider | design/frequency_divider.v | 1,324 | module MODULE1(
input clk,
input VAR2,
output VAR1
);
parameter VAR7= 6;
reg VAR3;
reg [9:0] VAR4;
always @(posedge clk or negedge VAR2)
begin
if(!VAR2)
begin
VAR4 <= 10'd0;
VAR3 <= 1'd0;
end
else
begin
if(VAR7==2)
VAR3 <= ~VAR3;
end
else
if(VAR4 <= ((VAR7-1'd1)/2)- 1'd1)
begin
VAR4 <= VAR4 +1'd1;
VAR3 <= 1'd1;
end
els... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvgnd2/sky130_fd_sc_ms__tapvgnd2.behavioral.pp.v | 1,237 | module MODULE1 (
VAR3,
VAR2,
VAR1 ,
VAR4
);
input VAR3;
input VAR2;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
luebbers/reconos | support/refdesigns/10.1/xup/eth_tft_cf/pcores/plb_tft_cntlr_ref_v1_00_c/hdl/verilog/rgb_bram.v | 8,797 | module MODULE1(
VAR28, VAR58, VAR33,
VAR31, VAR35,
VAR49, VAR23,
VAR51, VAR6, VAR34, VAR10,
VAR16,VAR46,VAR2,VAR45,VAR26,VAR11, VAR55,VAR24,VAR43,VAR15,VAR39,VAR14, VAR53,VAR44,VAR1,VAR12,VAR8,VAR56 );
input VAR28;
input VAR58;
input VAR33;
input VAR31;
input VAR35;
input VAR49;
input VAR23;
input [0:63] VAR51;
input [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuf/sky130_fd_sc_lp__clkbuf.pp.blackbox.v | 1,249 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR5,
VAR2,
VAR6 ,
VAR1
);
output VAR4 ;
input VAR3 ;
input VAR5;
input VAR2;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
cpulabs/mist1032isa | src/memory_pipe_arbiter.v | 7,771 | module MODULE1(
input wire VAR27,
input wire VAR65,
input wire VAR54,
output wire VAR11,
input wire [1:0] VAR46,
input wire [3:0] VAR66,
input wire VAR49,
input wire [13:0] VAR6,
input wire [1:0] VAR63,
input wire [2:0] VAR81,
input wire [31:0] VAR75,
input wire [31:0] VAR64,
input wire [31:0] VAR20,
output wire VAR31,... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbn/sky130_fd_sc_hs__dlxbn_2.v | 2,177 | module MODULE2 (
VAR7 ,
VAR4 ,
VAR6 ,
VAR3,
VAR1 ,
VAR5
);
output VAR7 ;
output VAR4 ;
input VAR6 ;
input VAR3;
input VAR1 ;
input VAR5 ;
VAR8 VAR2 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR7 ,
VAR4 ,
VAR6 ,
VAR3
);
output VAR7 ;
output VAR4 ;
input ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_4.behavioral.v | 1,116 | module MODULE1( VAR5, VAR1 );
input VAR5;
output VAR1;
VAR4 VAR3(.VAR5(VAR5),.VAR1(VAR1));
VAR4 VAR2(.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor2/sky130_fd_sc_hvl__nor2.behavioral.pp.v | 1,792 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR11 ,
VAR7,
VAR10,
VAR8 ,
VAR6
);
output VAR3 ;
input VAR5 ;
input VAR11 ;
input VAR7;
input VAR10;
input VAR8 ;
input VAR6 ;
wire VAR1 ;
wire VAR9;
nor VAR4 (VAR1 , VAR5, VAR11 );
VAR12 VAR2 (VAR9, VAR1, VAR7, VAR10);
buf VAR13 (VAR3 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxbp/sky130_fd_sc_ls__dlxbp_1.v | 2,262 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR10 ,
VAR8,
VAR6,
VAR9,
VAR5 ,
VAR3
);
output VAR2 ;
output VAR4 ;
input VAR10 ;
input VAR8;
input VAR6;
input VAR9;
input VAR5 ;
input VAR3 ;
VAR1 VAR7 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311oi/sky130_fd_sc_hd__a311oi.symbol.v | 1,395 | module MODULE1 (
input VAR10,
input VAR8,
input VAR5,
input VAR6,
input VAR4,
output VAR1
);
supply1 VAR3;
supply0 VAR2;
supply1 VAR7 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
Miltonhill/WaterbearCPU | waterbear.v | 6,728 | module MODULE1(
input clk,
input rst,
output[7:0] VAR5);
parameter VAR26=2'b00;
parameter VAR25=2'b01;
parameter VAR22=2'b10;
parameter VAR1=2'b11;
integer VAR6;
reg[1:0] VAR14;
reg[1:0] VAR15;
parameter VAR21 = 4'b001; parameter VAR24 = 4'b010; parameter VAR16 = 4'b011; parameter VAR19 = 4'b100; parameter VAR2 = 4'b10... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9649_v1_00_a/hdl/verilog/cf_adc_wr.v | 5,202 | module MODULE1 (
VAR12,
VAR8,
VAR3,
VAR24,
VAR14,
VAR16,
VAR13,
VAR18,
VAR2,
VAR7,
VAR15,
VAR17,
VAR26,
VAR10,
VAR5,
VAR27,
VAR19,
VAR25,
VAR21,
VAR6);
parameter VAR23 = 0;
input VAR12;
input [13:0] VAR8;
input VAR3;
output VAR24;
output VAR14;
output [63:0] VAR16;
output VAR13;
output VAR18;
output VAR2;
input VAR7;
i... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32o/sky130_fd_sc_ls__a32o.functional.v | 1,580 | module MODULE1 (
VAR8 ,
VAR7,
VAR2,
VAR13,
VAR11,
VAR3
);
output VAR8 ;
input VAR7;
input VAR2;
input VAR13;
input VAR11;
input VAR3;
wire VAR10 ;
wire VAR5 ;
wire VAR4;
and VAR9 (VAR10 , VAR13, VAR7, VAR2 );
and VAR1 (VAR5 , VAR11, VAR3 );
or VAR6 (VAR4, VAR5, VAR10);
buf VAR12 (VAR8 , VAR4 );
endmodule | apache-2.0 |
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