repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/prcfg/qpsk/Raised_Cosine_Receive_Filter.v | 1,850 | module MODULE1
(
clk,
reset,
VAR12,
VAR11,
VAR5,
VAR7,
VAR8
);
input clk;
input reset;
input VAR12;
input signed [15:0] VAR11; input signed [15:0] VAR5; output signed [15:0] VAR7; output signed [15:0] VAR8;
wire signed [15:0] VAR3; wire signed [15:0] VAR1;
VAR10 VAR9 (.clk(clk),
.VAR12(VAR12),
.reset(reset),
.VAR4(VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s.blackbox.v | 1,324 | module MODULE1 (
VAR5,
VAR3
);
output VAR5;
input VAR3;
supply1 VAR6;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
mamijaz/RISC-V | src/riscv_instruction_cache/VICTIM_CACHE.v | 7,723 | module MODULE1 #(
parameter VAR15 = 512 ,
parameter VAR9 = 26 ,
parameter VAR22 = "VAR8" ,
localparam VAR14 = 4 ,
localparam VAR5 = VAR19(VAR14-1)
) (
input VAR6 ,
input [VAR9 - 1 : 0] VAR12 ,
input [VAR15 - 1 : 0] VAR4 ,
input VAR13 ,
input [VAR9 - 1 : 0] VAR21 ,
input VAR20 ,
output VAR16 ,
output [VAR15 - 1 : 0] VAR... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkinv/sky130_fd_sc_hd__clkinv_16.v | 2,042 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR1,
VAR3,
VAR7 ,
VAR6
);
output VAR4 ;
input VAR8 ;
input VAR1;
input VAR3;
input VAR7 ;
input VAR6 ;
VAR2 VAR5 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR4,
VAR8
);
output VAR4;
input VAR8;
supply1 VAR1;
supply0 VAR3;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxbp/sky130_fd_sc_lp__dfxbp.pp.blackbox.v | 1,314 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR3 ,
VAR5 ,
VAR4,
VAR1,
VAR2 ,
VAR8
);
output VAR6 ;
output VAR7 ;
input VAR3 ;
input VAR5 ;
input VAR4;
input VAR1;
input VAR2 ;
input VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4bb/sky130_fd_sc_hdll__nand4bb.symbol.v | 1,347 | module MODULE1 (
input VAR7,
input VAR2,
input VAR1 ,
input VAR6 ,
output VAR5
);
supply1 VAR9;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxtp/sky130_fd_sc_ms__sdfxtp_2.v | 2,345 | module MODULE2 (
VAR7 ,
VAR9 ,
VAR8 ,
VAR3 ,
VAR4 ,
VAR1,
VAR10,
VAR6 ,
VAR5
);
output VAR7 ;
input VAR9 ;
input VAR8 ;
input VAR3 ;
input VAR4 ;
input VAR1;
input VAR10;
input VAR6 ;
input VAR5 ;
VAR2 VAR11 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor2/sky130_fd_sc_hvl__nor2.functional.v | 1,258 | module MODULE1 (
VAR5,
VAR4,
VAR6
);
output VAR5;
input VAR4;
input VAR6;
wire VAR2;
nor VAR1 (VAR2, VAR4, VAR6 );
buf VAR3 (VAR5 , VAR2 );
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pcie_pipe_misc.v | 10,197 | module MODULE1 #
(
parameter VAR18 = 100,
parameter VAR39 = 0 ) (
input wire VAR37 , input wire VAR27 , input wire [1:0] VAR15 , input wire VAR22 , input wire [2:0] VAR35 , input wire VAR26 , input wire [5:0] VAR11 , input wire [5:0] VAR17 , output wire VAR38 , output wire VAR36 , output wire [1:0] VAR33 , output wire ... | gpl-3.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/userlogic/mapreducer/user_logic.v | 5,779 | module MODULE1(
input VAR7, input VAR27, input VAR42, input VAR83,
input [31:0] VAR70,
input [19:0] VAR11,
input VAR49,
output [31:0] VAR53,
output reg VAR66,
input VAR5,
output [255:0] VAR16,
output [31:0] VAR15,
output VAR67,
output [26:0] VAR1,
output VAR30,
input [255:0] VAR8,
input VAR23,
input VAR4,
input VAR14,
... | mit |
olofk/wb_streamer | rtl/verilog/wb_stream_reader_cfg.v | 2,056 | module MODULE1
parameter VAR10 = 32)
(
input VAR21,
input VAR2,
input [4:0] VAR3,
input [VAR10-1:0] VAR16,
input [VAR10/8-1:0] VAR12,
input VAR15 ,
input VAR17,
input VAR20,
input [2:0] VAR5,
input [1:0] VAR6,
output [VAR10-1:0] VAR1,
output reg VAR19,
output VAR14,
output reg irq,
input VAR8,
output reg enable,
input ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22a/sky130_fd_sc_lp__o22a_4.v | 2,339 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR10 ,
VAR9 ,
VAR7 ,
VAR4,
VAR11,
VAR6 ,
VAR5
);
output VAR8 ;
input VAR3 ;
input VAR10 ;
input VAR9 ;
input VAR7 ;
input VAR4;
input VAR11;
input VAR6 ;
input VAR5 ;
VAR2 VAR1 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR6(VAR6),
.... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/4-way_2-tree/src/riffa/rx_engine_ultrascale.v | 10,579 | module MODULE1
( input VAR42,
input VAR10, input VAR62, output VAR46,
output VAR19,
input VAR66,
input VAR73,
input [VAR22-1:0] VAR48,
input [(VAR22/32)-1:0] VAR13,
input [VAR59-1:0] VAR25,
output VAR29,
input VAR61,
input VAR37,
input [VAR22-1:0] VAR27,
input [(VAR22/32)-1:0] VAR30,
input [VAR31-1:0] VAR50,
output VAR... | mit |
chriz2600/DreamcastHDMI | Core/source/ram/text_ram.v | 9,504 | module MODULE1 (
VAR7,
VAR44,
VAR25,
VAR13,
VAR59,
VAR60,
VAR21);
input [7:0] VAR7;
input [9:0] VAR44;
input VAR25;
input [9:0] VAR13;
input VAR59;
input VAR60;
output [7:0] VAR21;
tri1 VAR59;
tri0 VAR60;
wire [7:0] VAR30;
wire [7:0] VAR21 = VAR30[7:0];
VAR54 VAR23 (
.VAR2 (VAR13),
.VAR15 (VAR44),
.VAR52 (VAR59),
.VAR1... | mit |
hoglet67/CoPro6502 | src/Tube/ph_fifo_core_spartan3.v | 13,728 | module MODULE1(
rst,
VAR308,
VAR267,
din,
VAR43,
VAR128,
dout,
VAR393,
VAR99
);
input rst;
input VAR308;
input VAR267;
input [7 : 0] din;
input VAR43;
input VAR128;
output [7 : 0] dout;
output VAR393;
output VAR99;
VAR242 #(
.VAR154(0),
.VAR323(0),
.VAR342(0),
.VAR56(0),
.VAR149(0),
.VAR137(0),
.VAR277(0),
.VAR273(32),... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4b/sky130_fd_sc_ms__or4b.pp.blackbox.v | 1,335 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR9 ,
VAR8 ,
VAR5 ,
VAR3,
VAR2,
VAR1 ,
VAR6
);
output VAR7 ;
input VAR4 ;
input VAR9 ;
input VAR8 ;
input VAR5 ;
input VAR3;
input VAR2;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ip/dma_loopback_xlconcat_0_0/synth/dma_loopback_xlconcat_0_0.v | 4,515 | module MODULE1 (
VAR15,
VAR39,
dout
);
input wire [0 : 0] VAR15;
input wire [0 : 0] VAR39;
output wire [1 : 0] dout;
VAR6 #(
.VAR13(1),
.VAR69(1),
.VAR54(1),
.VAR32(1),
.VAR44(1),
.VAR10(1),
.VAR59(1),
.VAR27(1),
.VAR36(1),
.VAR20(1),
.VAR19(1),
.VAR49(1),
.VAR28(1),
.VAR38(1),
.VAR62(1),
.VAR35(1),
.VAR24(1),
.VAR34(1... | mit |
bunnie/novena-gpbb-fpga | novena-gpbb.srcs/sources_1/ip/bclk_dll/bclk_dll.v | 5,699 | module MODULE1
( input VAR44,
output VAR37,
input VAR15,
output VAR17
);
assign VAR40 = VAR44;
wire VAR39;
wire VAR41;
wire [7:0] VAR30;
wire VAR11;
wire VAR5;
VAR20
.VAR22 (1),
.VAR27 (4),
.VAR46 ("VAR42"),
.VAR10 (7.518),
.VAR14 ("VAR31"),
.VAR29 ("1X"),
.VAR21 ("VAR26"),
.VAR2 (0),
.VAR36 ("VAR42"))
VAR43
(.VAR16 (V... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab1/adders_prj/solution1/syn/verilog/adders.v | 1,943 | module MODULE1 (
VAR4,
VAR12,
VAR8,
VAR10,
VAR5,
VAR14
);
parameter VAR13 = 2'd1;
parameter VAR11 = 2'd2;
input VAR4;
input VAR12;
input [31:0] VAR8;
input [31:0] VAR10;
input [31:0] VAR5;
output [31:0] VAR14;
wire [31:0] VAR3;
reg [31:0] VAR7;
reg [1:0] VAR6;
wire VAR2;
wire VAR1;
reg [1:0] VAR9; | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapmet1/sky130_fd_sc_ls__tapmet1.pp.symbol.v | 1,232 | module MODULE1 (
input VAR1 ,
input VAR3,
input VAR2,
input VAR4
);
endmodule | apache-2.0 |
fpgaminer/fpgaminer-vanitygen | cores/sha256/sha-256-functions.v | 1,640 | module MODULE1 (VAR1, VAR3);
input [31:0] VAR1;
output [31:0] VAR3;
assign VAR3 = {VAR1[1:0],VAR1[31:2]} ^ {VAR1[12:0],VAR1[31:13]} ^ {VAR1[21:0],VAR1[31:22]};
endmodule
module MODULE4 (VAR1, VAR3);
input [31:0] VAR1;
output [31:0] VAR3;
assign VAR3 = {VAR1[5:0],VAR1[31:6]} ^ {VAR1[10:0],VAR1[31:11]} ^ {VAR1[24:0],VAR1... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/generic/dpb.v | 1,560 | module MODULE1 #(
parameter VAR13 = 32,
parameter VAR8 = 10,
parameter VAR3 = "VAR14",
parameter VAR5 = 0,
parameter VAR4 = 0
) (
input VAR12,
input VAR17,
input wire [VAR8 - 1: 0] VAR11,
input wire [VAR13 - 1: 0] VAR7,
output reg [VAR13 - 1: 0] VAR18 = 0,
input VAR6,
input VAR1,
input wire [VAR8 - 1: 0] VAR10,
input w... | mit |
takeshineshiro/fpga_linear_128 | DynamicDelay_Start_bb.v | 5,195 | module MODULE1 (
address,
VAR2,
VAR1);
input [0:0] address;
input VAR2;
output [127:0] VAR1;
endmodule | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/h265core.v | 26,234 | module MODULE1(
clk ,
VAR42 ,
VAR95 ,
VAR87 ,
VAR176 ,
VAR128 ,
VAR29 ,
VAR161 ,
VAR100 ,
VAR94 ,
VAR135 ,
VAR120 ,
VAR168 ,
VAR130 ,
VAR64 ,
VAR10 ,
VAR127 ,
VAR164 ,
VAR20 ,
VAR147 ,
VAR92 ,
VAR50 ,
VAR167 ,
VAR66
);
parameter VAR115 = 0 ,
VAR61 = 1 ;
parameter VAR49 = 0 ,
VAR65 = 1 , VAR16 = 2 , VAR144 = 3 , VAR83 =... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/soc/minimig_avnet_top.v | 18,905 | module MODULE1 (
input wire VAR285, input wire VAR240, input wire [ 2-1:0] VAR44, input wire [ 4-1:0] VAR278, output wire [ 8-1:0] VAR158, output wire [ 8-1:0] VAR155, output wire [ 8-1:0] VAR91, output wire VAR215, input wire VAR5, inout wire VAR286, output wire VAR101, inout wire VAR287, inout wire VAR95, inout wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22ai/sky130_fd_sc_lp__o22ai.symbol.v | 1,371 | module MODULE1 (
input VAR6,
input VAR3,
input VAR8,
input VAR1,
output VAR4
);
supply1 VAR2;
supply0 VAR5;
supply1 VAR9 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
bluespec/Flute | builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkNear_Mem_IO_AXI4.v | 97,895 | module MODULE1(VAR108,
VAR125,
VAR264,
VAR314,
VAR105,
VAR308,
VAR19,
VAR172,
VAR35,
VAR336,
VAR103,
VAR162,
VAR122,
VAR262,
VAR263,
VAR341,
VAR293,
VAR261,
VAR46,
VAR27,
VAR72,
VAR309,
VAR284,
VAR113,
VAR33,
VAR167,
VAR18,
VAR64,
VAR332,
VAR185,
VAR333,
VAR62,
VAR21,
VAR49,
VAR320,
VAR151,
VAR74,
VAR120,
VAR70,
VAR56,... | apache-2.0 |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mult_17x16/mult_17x16_stub.v | 1,266 | module MODULE1(VAR3, VAR4, VAR1, VAR2)
;
input VAR3;
input [16:0]VAR4;
input [15:0]VAR1;
output [24:0]VAR2;
endmodule | bsd-3-clause |
alexforencich/verilog-axis | rtl/axis_srl_register.v | 5,085 | module MODULE1 #
(
parameter VAR23 = 8,
parameter VAR24 = (VAR23>8),
parameter VAR16 = ((VAR23+7)/8),
parameter VAR5 = 1,
parameter VAR36 = 0,
parameter VAR1 = 8,
parameter VAR28 = 0,
parameter VAR22 = 8,
parameter VAR35 = 1,
parameter VAR32 = 1
)
(
input wire clk,
input wire rst,
input wire [VAR23-1:0] VAR18,
input wi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32a/sky130_fd_sc_ms__o32a.pp.blackbox.v | 1,417 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR6 ,
VAR5 ,
VAR10 ,
VAR1 ,
VAR8,
VAR7,
VAR9 ,
VAR3
);
output VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR5 ;
input VAR10 ;
input VAR1 ;
input VAR8;
input VAR7;
input VAR9 ;
input VAR3 ;
endmodule | apache-2.0 |
olgirard/openmsp430 | core/synthesis/altera/src/megawizard/cyclone3_pmem.v | 7,637 | module MODULE1 (
address,
VAR23,
VAR24,
VAR19,
VAR1,
VAR55,
VAR38);
input [11:0] address;
input [1:0] VAR23;
input VAR24;
input VAR19;
input [15:0] VAR1;
input VAR55;
output [15:0] VAR38;
tri1 [1:0] VAR23;
tri1 VAR24;
tri1 VAR19;
wire [15:0] VAR35;
wire [15:0] VAR38 = VAR35[15:0];
VAR4 VAR25 (
.VAR13 (VAR24),
.VAR42 (V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxbp/sky130_fd_sc_hs__sedfxbp.pp.blackbox.v | 1,402 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR5 ,
VAR1 ,
VAR3 ,
VAR2 ,
VAR7 ,
VAR6,
VAR4
);
output VAR8 ;
output VAR9 ;
input VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR2 ;
input VAR7 ;
input VAR6;
input VAR4;
endmodule | apache-2.0 |
kernelpanics/Grad | CORDIC-Natural-Logarithm/Verilog/UART/Mux_8x1.v | 1,226 | module MODULE1(
input wire [2:0] select,
input wire [7:0] VAR9,
input wire [7:0] VAR8,
input wire [7:0] VAR3,
input wire [7:0] VAR4,
input wire [7:0] VAR6,
input wire [7:0] VAR1,
input wire [7:0] VAR7,
input wire [7:0] VAR2,
output reg [7:0] VAR5
);
always @*
begin
case(select)
3'b111: VAR5 = VAR9;
3'b110: VAR5 = VAR8;... | gpl-3.0 |
rkrajnc/minimig-de1 | rtl/or1200/or1200_spram_64x22.v | 8,917 | module MODULE1(
VAR4, VAR2, VAR24,
clk, rst, VAR34, VAR7, VAR43, addr, VAR21, VAR9
);
parameter VAR36 = 6;
parameter VAR48 = 22;
input VAR4;
input [VAR35 - 1:0] VAR24;
output VAR2;
input clk; input rst; input VAR34; input VAR7; input VAR43; input [VAR36-1:0] addr; input [VAR48-1:0] VAR21; output [VAR48-1:0] VAR9;
wire ... | gpl-3.0 |
ChrisPVille/RL02 | FPGA/top_sch.v | 8,762 | module MODULE1(VAR66,
VAR12,
VAR29,
VAR128,
VAR135,
VAR75,
VAR51,
VAR17,
VAR42,
VAR101,
VAR27,
VAR77,
VAR111,
VAR107,
VAR134,
VAR65,
VAR62,
VAR33,
VAR124,
VAR103,
VAR126,
VAR10,
VAR97,
VAR40,
VAR52,
VAR73);
input VAR66;
input VAR12;
input VAR29;
input VAR128;
input VAR135;
input VAR75;
input VAR51;
input VAR126;
output... | gpl-3.0 |
google/myelin-acorn-electron-hardware | master_updateable_megarom/cpld/master_updateable_megarom.v | 6,316 | module MODULE1(
inout wire [7:0] VAR13,
input wire [16:0] VAR6,
output wire [18:0] VAR17,
output wire VAR21,
output wire VAR5,
input wire VAR10,
input wire VAR24,
input wire VAR11,
output reg VAR19,
input wire [1:0] VAR8
);
assign VAR1 = VAR10;
reg VAR2 = 1'b0;
reg [1:0] VAR23 = 2'b0;
wire VAR16;
wire VAR22;
reg [18:0]... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s18/sky130_fd_sc_hd__clkdlybuf4s18.pp.blackbox.v | 1,343 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR5,
VAR4,
VAR6 ,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR5;
input VAR4;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
lvd2/ngs | fpga/obsolete/fpgaF_dma2/dma/dma_sequencer2.v | 6,367 | module MODULE1(
input wire clk,
input wire VAR21,
input wire VAR24,
input wire VAR18,
input wire VAR14,
input wire VAR53,
input wire [20:0] VAR61,
input wire [20:0] VAR29,
input wire [20:0] VAR50,
input wire [20:0] VAR31,
input wire VAR6,
input wire VAR11,
input wire VAR1,
input wire VAR49,
input wire [7:0] VAR4,
input... | gpl-3.0 |
alexforencich/verilog-ethernet | rtl/eth_mac_mii.v | 4,683 | module MODULE1 #
(
parameter VAR58 = "VAR54",
parameter VAR28 = "VAR6",
parameter VAR38 = 1,
parameter VAR49 = 64
)
(
input wire rst,
output wire VAR42,
output wire VAR32,
output wire VAR35,
output wire VAR21,
input wire [7:0] VAR36,
input wire VAR48,
output wire VAR23,
input wire VAR10,
input wire VAR62,
output wire [... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_adcfifo/util_adcfifo.v | 8,219 | module MODULE1 (
VAR23,
VAR21,
VAR32,
VAR35,
VAR4,
VAR26,
VAR52,
VAR49,
VAR22,
VAR60,
VAR55);
parameter VAR58 = 256;
parameter VAR59 = 64;
parameter VAR14 = 1;
parameter VAR31 = 10;
localparam VAR51 = VAR58/VAR59;
localparam VAR39 = (VAR51 == 2) ? (VAR31 - 1) :
((VAR51 == 4) ? (VAR31 - 2) : (VAR31 - 3));
localparam VAR... | gpl-3.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_spram_256x21.v | 11,081 | module MODULE1(
VAR48, VAR18, VAR27,
clk, rst, VAR43, VAR53, VAR51, addr, VAR11, VAR19
);
parameter VAR12 = 8;
parameter VAR15 = 21;
input VAR48;
input [VAR33 - 1:0] VAR27;
output VAR18;
input clk; input rst; input VAR43; input VAR53; input VAR51; input [VAR12-1:0] addr; input [VAR15-1:0] VAR11; output [VAR15-1:0] VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxbp/sky130_fd_sc_ms__sedfxbp.behavioral.v | 2,734 | module MODULE1 (
VAR11 ,
VAR27,
VAR8,
VAR31 ,
VAR12 ,
VAR22,
VAR23
);
output VAR11 ;
output VAR27;
input VAR8;
input VAR31 ;
input VAR12 ;
input VAR22;
input VAR23;
supply1 VAR1;
supply0 VAR16;
supply1 VAR4 ;
supply0 VAR20 ;
wire VAR13 ;
reg VAR14 ;
wire VAR21 ;
wire VAR29 ;
wire VAR19;
wire VAR5;
wire VAR30;
wire VAR2... | apache-2.0 |
tdene/synth_opt_adders | src/pptrees/mappings/sky130_fd_sc_ls_map.v | 4,263 | module MODULE1
(
VAR35, VAR43
);
output VAR35;
input VAR43;
VAR23 MODULE1(.VAR35(VAR35), .VAR43(VAR43));
endmodule
module MODULE25
(
VAR35, VAR43
);
output VAR35;
input VAR43;
VAR31 MODULE25(.VAR26(VAR35), .VAR43(VAR43));
endmodule
module MODULE15
(
VAR35, VAR43, VAR8
);
output VAR35;
input VAR43, VAR8;
VAR32 MODULE15(... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_dipsw_pio/synth/ghrd_10as066n2_dipsw_pio.v | 1,517 | module MODULE1 (
input wire clk, input wire [3:0] VAR1, output wire irq, input wire VAR8, input wire [1:0] address, input wire VAR2, input wire [31:0] VAR6, input wire VAR7, output wire [31:0] VAR4 );
VAR3 VAR5 (
.clk (clk), .VAR8 (VAR8), .address (address), .VAR2 (VAR2), .VAR6 (VAR6), .VAR7 (VAR7), .VAR4 (VAR4), .VAR1... | mit |
sam-falvo/kestrel | cores/KCP53K/bottleneck/rtl/verilog/BottleneckSequencer.v | 4,528 | module MODULE1(
input VAR10,
input VAR28,
input VAR16,
input VAR19,
input VAR9,
input VAR23,
input VAR20,
input VAR30,
input VAR7,
input VAR8,
input VAR13,
input VAR14,
output VAR3,
output VAR4,
output VAR36,
output VAR25,
output VAR29,
output VAR2,
output VAR21,
output VAR31,
output VAR34,
output VAR17,
output VAR35,
... | mpl-2.0 |
tmeissner/cryptocores | cbcdes/rtl/verilog/cbcdes.v | 3,714 | module MODULE1
(
input VAR16, input VAR25, input VAR1, input VAR19, input [0:63] VAR5, input [0:63] VAR24, input [0:63] VAR8, input VAR2, output reg VAR21, output reg [0:63] VAR14, output VAR13 );
reg VAR18;
wire VAR22;
reg VAR10;
reg [0:63] VAR23;
wire [0:63] VAR6;
reg [0:63] VAR3;
reg [0:63] VAR12;
reg [0:63] VAR20;
... | gpl-2.0 |
marmolejo/zet | cores/flash/bootrom.v | 1,593 | module MODULE1 (
input clk,
input rst,
input [15:0] VAR1,
output [15:0] VAR3,
input [19:1] VAR9,
input VAR11,
input VAR10,
input VAR8,
input VAR4,
input [ 1:0] VAR5,
output VAR7
);
reg [15:0] VAR12[0:127];
wire [ 6:0] VAR6;
wire VAR2;
assign VAR6 = VAR9[7:1];
assign VAR2 = VAR8 & VAR4;
assign VAR7 = VAR2;
assign VAR3 =... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_4.behavioral.pp.v | 1,182 | module MODULE1( VAR4, VAR6, VAR2, VAR5 );
input VAR4;
inout VAR2, VAR5;
output VAR6;
VAR7 VAR3(.VAR4(VAR4),.VAR6(VAR6),.VAR2(VAR2),.VAR5(VAR5));
VAR7 VAR1(.VAR4(VAR4),.VAR6(VAR6),.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
efabless/openlane | designs/usb_cdc_core/src/usbf_crc16.v | 3,731 | module MODULE1
(
input [ 15:0] VAR3
,input [ 7:0] VAR2
,output [ 15:0] VAR1
);
assign VAR1[15] = VAR2[0] ^ VAR2[1] ^ VAR2[2] ^ VAR2[3] ^ VAR2[4] ^ VAR2[5] ^ VAR2[6] ^ VAR2[7] ^
VAR3[7] ^ VAR3[6] ^ VAR3[5] ^ VAR3[4] ^ VAR3[3] ^ VAR3[2] ^ VAR3[1] ^ VAR3[0];
assign VAR1[14] = VAR2[0] ^ VAR2[1] ^ VAR2[2] ^ VAR2[3] ^ VAR2[4... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211a/sky130_fd_sc_hs__o211a_2.v | 2,221 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR3 ,
VAR9 ,
VAR7 ,
VAR2,
VAR8
);
output VAR6 ;
input VAR5 ;
input VAR3 ;
input VAR9 ;
input VAR7 ;
input VAR2;
input VAR8;
VAR1 VAR4 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR6 ,
VAR5,
VAR3,
VAR9,
VAR7
);... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/triple_speed_ethernet-library/altera_tse_pma_lvds_rx.v | 12,598 | module MODULE1 (
VAR42,
VAR7,
VAR66,
VAR58,
VAR89,
VAR75,
VAR52,
VAR62,
VAR61,
VAR25);
input VAR42;
input [0:0] VAR7;
input [0:0] VAR66;
input [0:0] VAR58;
input VAR89;
input [0:0] VAR75;
output [0:0] VAR52;
output VAR62;
output [9:0] VAR61;
output VAR25;
wire [0:0] VAR23;
wire VAR92;
wire [9:0] VAR91;
wire VAR16;
wire... | mit |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/Direccion/peripheral_direccion.v | 1,453 | module MODULE1 (
input clk,
input rst,
input [15:0] din, input VAR8, input [3:0] addr, input rd, input wr,
output reg [15:0] dout,
output [1:0] VAR7 ,
output [1:0] VAR4
);
reg [1:0] VAR6; reg [1:0] VAR3;
always @(*) begin case(addr)
4'h0: VAR6 = (VAR8 && wr) ? 2'b01 : 2'b00 ; 4'h2: VAR6 = (VAR8 && wr) ? 2'b10 : 2'b00 ;... | mit |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/submodules/wasca_altpll_1.v | 10,656 | module MODULE1
(
VAR9,
VAR8,
VAR3,
VAR5) ;
input VAR9;
input VAR8;
input [0:0] VAR3;
output [0:0] VAR5;
tri0 VAR9;
tri1 VAR8;
reg [0:0] VAR10;
reg [0:0] VAR2;
reg [0:0] VAR7;
wire VAR4;
wire VAR6;
wire VAR1; | gpl-2.0 |
Jafet95/I-Proyecto-Laboratorio-de-Dise-o-Sistemas-Digitales | Modificacion_Ciclo_Trabajo.v | 1,674 | module MODULE1(
input wire VAR8,
input wire VAR18,
input wire rst,
input wire VAR5,
input wire VAR9,
input wire VAR4, output wire VAR13,
output wire [3:0]VAR6
);
wire [3:0] ref; wire VAR11,VAR17;
wire [3:0]VAR12;
VAR1 VAR19 (
.in(VAR12),
.out(VAR13),
.rst(rst),
.ref(ref),
.clk(VAR18)
);
VAR21 VAR23
(
.VAR7(VAR5),
.VAR1... | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_02/02 verilog/ProyectoDigital1/Microfono/Microfono.v | 1,514 | module MODULE1(clk, reset, VAR2, VAR28, VAR6, VAR3, VAR23, VAR22, VAR10, rd, wr, VAR8, VAR18);
input wire clk;
input wire reset;
input wire VAR2;
input wire VAR28;
output wire VAR6;
output wire VAR3;
input wire VAR23;
output wire VAR22;
output wire VAR10;
output wire rd;
output wire wr;
output wire VAR8;
output wire VA... | gpl-3.0 |
secworks/sha3 | src/rtl/sha3.v | 9,192 | module MODULE1(
input wire clk,
input wire VAR44,
input wire VAR10,
input wire VAR34,
input wire [7 : 0] address,
input wire [31 : 0] VAR6,
output wire [31 : 0] VAR30
);
localparam VAR49 = 8'h00;
localparam VAR58 = 8'h01;
localparam VAR59 = 8'h02;
localparam VAR1 = 8'h08;
localparam VAR17 = 0;
localparam VAR36 = 1;
loc... | bsd-2-clause |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/NVMeHostController4L/src/pcie_rx_dma.v | 6,096 | module MODULE1 # (
parameter VAR17 = 128,
parameter VAR49 = 36,
parameter VAR16 = 64
)
(
input VAR55,
input VAR2,
input [2:0] VAR23,
input VAR66,
input [33:0] VAR60,
output VAR61,
output VAR5,
output [7:0] VAR46,
output [11:2] VAR27,
output [VAR49-1:2] VAR64,
input VAR24,
input [7:0] VAR68,
input [VAR17-1:0] VAR22,
inp... | gpl-3.0 |
dries007/Basys3 | FPGA-Z/FPGA-Z.ip_user_files/ip/FrameBuffer/FrameBuffer_stub.v | 1,488 | module MODULE1(VAR10, VAR1, VAR3, VAR4, VAR9, VAR2, VAR11, VAR6, VAR8, VAR7, VAR5)
;
input VAR10;
input VAR1;
input [0:0]VAR3;
input [13:0]VAR4;
input [7:0]VAR9;
output [7:0]VAR2;
input VAR11;
input [0:0]VAR6;
input [13:0]VAR8;
input [7:0]VAR7;
output [7:0]VAR5;
endmodule | mit |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/Karat_ASIC_Synp/integracion_fisica/front_end/source/FPU_Multiplication_Function_v2.v | 8,385 | module MODULE1
wire VAR80; wire VAR50; wire VAR64;
wire VAR126;
wire VAR40;
wire VAR107;
wire [VAR78-1:0] VAR93;
wire [VAR78-1:0] VAR88;
wire VAR119;
wire [VAR83:0] VAR100;
wire [1:0] VAR104;
wire [VAR83-1:0] VAR69;
wire VAR53;
wire [VAR83:0] VAR131;
wire [2*VAR120+1:0] VAR38;
wire[VAR120:0] VAR25;
wire[VAR120:0] VAR97... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_sao_compare_cost.v | 4,481 | module MODULE1(
VAR18 ,
VAR15 ,
VAR11 ,
VAR8 ,
VAR16 ,
VAR13 ,
VAR12
);
parameter VAR19 = 25 ;
input signed [VAR19+2:0 ] VAR18 ;
input signed [VAR19+2:0 ] VAR15 ;
input signed [VAR19+2:0 ] VAR11 ;
input signed [VAR19+2:0 ] VAR8 ;
input signed [VAR19+2:0 ] VAR16 ;
output signed [VAR19+2:0 ] VAR13 ;
output [ 2:0 ] VAR12 ... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9122_v6_00_a/hdl/verilog/axi_ad9122_core.v | 10,446 | module MODULE1 (
VAR85,
VAR25,
VAR54,
VAR7,
VAR86,
VAR60,
VAR4,
VAR55,
VAR46,
VAR77,
VAR1,
VAR36,
VAR51,
VAR72,
VAR78,
VAR16,
VAR33,
VAR93,
VAR29,
VAR18,
VAR42,
VAR13,
VAR83,
VAR14,
VAR34,
VAR48,
VAR91,
VAR89,
VAR9,
VAR63,
VAR17,
VAR30,
VAR45,
VAR3,
VAR35,
VAR21,
VAR62,
VAR87,
VAR73,
VAR41,
VAR66);
parameter VAR71 = 0;... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/daq2/a10gx/system_top.v | 8,784 | module MODULE1 (
VAR46,
VAR40,
VAR15,
VAR121,
VAR27,
VAR60,
VAR32,
VAR34,
VAR77,
VAR29,
VAR57,
VAR18,
VAR83,
VAR106,
VAR98,
VAR16,
VAR64,
VAR20,
VAR52,
VAR74,
VAR88,
VAR61,
VAR1,
VAR6,
VAR107,
VAR80,
VAR111,
VAR37,
VAR24,
VAR113,
VAR65,
VAR31,
VAR50,
VAR25,
VAR63,
VAR104,
VAR102,
VAR14,
VAR17,
VAR3,
VAR19,
VAR100,
VAR1... | gpl-3.0 |
PerezFederico/UART_Arquitectura | Interface.v | 5,854 | module MODULE1
parameter VAR39 = 'b000000000010,
parameter VAR45 = 'b000000000100,
parameter VAR11 = 'b000000001000,
parameter VAR25 = 'b000000010000,
parameter VAR27 = 'b000000100000,
parameter VAR23 = 'b000001000000,
parameter VAR30 = 'b000010000000,
parameter VAR14 = 'b000100000000,
parameter VAR40 = 'b001000000000,... | gpl-3.0 |
secworks/ChaCha20-Poly1305 | src/rtl/chacha20_poly1305.v | 9,979 | module MODULE1(
input wire clk,
input wire VAR60,
input wire VAR66,
input wire VAR54,
input wire [7 : 0] address,
input wire [31 : 0] VAR27,
output wire [31 : 0] VAR36
);
localparam VAR61 = 8'h00;
localparam VAR58 = 8'h01;
localparam VAR46 = 8'h02;
localparam VAR16 = 8'h08;
localparam VAR55 = 0;
localparam VAR51 = 1;
l... | bsd-2-clause |
impedimentToProgress/ProbableCause | ddr2/cores/bench/cy7c1354.v | 11,073 | module MODULE1 ( VAR1, clk, VAR28, VAR30, VAR11, VAR12, VAR10, VAR48, VAR44, VAR41, VAR21, VAR6);
inout [VAR55:0] VAR1;
input clk, VAR11, VAR12, VAR10, VAR48, VAR44, VAR41, VAR21, VAR6; input [3:0] VAR30; input [18:0] VAR28;
reg VAR23; reg VAR25;
reg VAR15;
reg VAR26;
reg VAR5;
reg VAR37;
reg VAR20;
reg VAR7;
reg VAR40... | mit |
glennchid/font5-firmware | src/verilog/synthesis/reset_ctrl.v | 2,359 | module MODULE1(
input VAR3,
input VAR6,
input VAR1,
output reg VAR2 = 1'b0,
output reg VAR7 = 1'b0
);
reg VAR5 = 1'b0;
reg [23:0] VAR4 = 24'd0;
always @(posedge VAR3) begin
if (VAR5) begin
VAR4 <= VAR4 + 1'd1;
case (VAR4)
24'd0: begin
VAR2 <= 1'b1;
VAR7 <= VAR7;
VAR5 <= VAR5;
end
24'd8500000: begin
VAR2 <= 1'b0;
VAR7 <... | gpl-3.0 |
rkrajnc/minimig-de1 | rtl/or1200/or1200_dpram_32x32.v | 11,370 | module MODULE1(
VAR137, VAR159, VAR80, VAR53, VAR37, VAR160,
VAR5, VAR39, VAR13, VAR68, VAR11, VAR55
);
parameter VAR45 = 5;
parameter VAR124 = 32;
input VAR137; input VAR159; input VAR80; input VAR53; input [VAR45-1:0] VAR37; output [VAR124-1:0] VAR160; input VAR5; input VAR39; input VAR13; input VAR68; input [VAR45-1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkbuf/sky130_fd_sc_hdll__clkbuf.functional.pp.v | 1,790 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR5,
VAR2,
VAR7 ,
VAR11
);
output VAR4 ;
input VAR8 ;
input VAR5;
input VAR2;
input VAR7 ;
input VAR11 ;
wire VAR9 ;
wire VAR1;
buf VAR6 (VAR9 , VAR8 );
VAR10 VAR3 (VAR1, VAR9, VAR5, VAR2);
buf VAR12 (VAR4 , VAR1 );
endmodule | apache-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/vfabric_lsu_pipelined.v | 6,341 | module MODULE1(VAR24, VAR47,
VAR7, VAR41, VAR17,
VAR60, VAR44, VAR27,
VAR48, VAR9, VAR13, VAR8,
VAR14, VAR12, VAR1,
VAR50, VAR54, VAR59);
parameter VAR2 = 32;
parameter VAR40 = 4;
parameter VAR34 = 32;
parameter VAR31 = 64;
input VAR24, VAR47;
input [VAR2-1:0] VAR7;
input VAR60;
input VAR41, VAR44;
output VAR17, VAR27;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111oi/sky130_fd_sc_hd__a2111oi.behavioral.pp.v | 2,082 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR6 ,
VAR11 ,
VAR18 ,
VAR5 ,
VAR17,
VAR10,
VAR3 ,
VAR15
);
output VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR11 ;
input VAR18 ;
input VAR5 ;
input VAR17;
input VAR10;
input VAR3 ;
input VAR15 ;
wire VAR2 ;
wire VAR9 ;
wire VAR7;
and VAR14 (VAR2 , VAR8, VAR6 );
nor VAR4 (VAR9 , VAR11, VAR1... | apache-2.0 |
mballance/oc_wb_ip | rtl/wb_uart/uart_top.v | 13,066 | module MODULE1 #(
parameter reg VAR39=1,
parameter reg VAR33=0,
parameter reg VAR5=1
) (
VAR52, VAR45,
VAR37, VAR35, VAR43, VAR16, VAR13, VAR51, VAR9, VAR28,
VAR12,
VAR32, VAR21,
VAR17, VAR4, VAR26, VAR50, VAR1, VAR46,
VAR18, VAR8
);
parameter VAR6 = (VAR33==1)?8:32;
parameter VAR29 = (VAR33==1)?3:5;
input VAR52;
input... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/cordic_Arch3/Mux_3x1_b_v2.v | 1,035 | module MODULE1 #(parameter VAR1=32)
(
input wire [1:0] select,
input wire [VAR1-1:0] VAR5,
input wire [VAR1-1:0] VAR2,
input wire [VAR1-1:0] VAR3,
output reg [VAR1-1:0] VAR4
);
always @*
begin
case(select)
2'b00: VAR4 <= {VAR1{1'b0}};
2'b01: VAR4 <= VAR5;
2'b10: VAR4 <= VAR2;
2'b11: VAR4 <= VAR3;
endcase
end
endmodule | gpl-3.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/memory/memory.v | 2,085 | module MODULE1(
VAR2,
VAR12,
VAR14,
VAR4,
VAR7,
VAR11,
VAR6,
VAR13,
ack,
clk,
rst
);
input clk;
input rst;
input VAR2;
input VAR12, VAR14;
input [31:0] VAR4;
input [31:0] VAR7;
input [6:0] VAR11;
output [6:0] VAR13;
output ack;
output [31:0] VAR6;
reg[7:0] VAR15[50000:0];
reg[7:0] VAR10[65535:0];
reg VAR9;
reg [6:0] VA... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/ddr3_s4_uniphy_example_if0_p0_flop_mem.v | 2,654 | module MODULE1(
VAR17,
VAR5,
VAR13,
VAR24,
VAR7,
VAR29,
VAR23,
VAR14,
VAR19
);
parameter VAR31 = "";
parameter VAR6 = "";
parameter VAR25 = "";
parameter VAR12 = "";
parameter VAR26 = "";
parameter VAR1 = "";
input VAR17;
input VAR5;
input [VAR6-1:0] VAR13;
input [VAR25-1:0] VAR24;
input VAR7;
input VAR29;
input VAR23;... | lgpl-3.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/button_pio.v | 4,321 | module MODULE1 (
address,
VAR7,
clk,
VAR2,
VAR14,
VAR12,
VAR8,
irq,
VAR13
)
;
output irq;
output [ 31: 0] VAR13;
input [ 1: 0] address;
input VAR7;
input clk;
input [ 3: 0] VAR2;
input VAR14;
input VAR12;
input [ 31: 0] VAR8;
wire VAR4;
reg [ 3: 0] VAR6;
reg [ 3: 0] VAR1;
wire [ 3: 0] VAR11;
reg [ 3: 0] VAR15;
wire VAR... | gpl-3.0 |
alexforencich/verilog-ethernet | lib/axis/rtl/arbiter.v | 4,993 | module MODULE1 #
(
parameter VAR14 = 4,
parameter VAR13 = 0,
parameter VAR21 = 0,
parameter VAR20 = 1,
parameter VAR15 = 0
)
(
input wire clk,
input wire rst,
input wire [VAR14-1:0] request,
input wire [VAR14-1:0] acknowledge,
output wire [VAR14-1:0] VAR24,
output wire VAR11,
output wire [VAR12(VAR14)-1:0] VAR17
);
reg... | mit |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ip/dma_loopback_xbar_1/synth/dma_loopback_xbar_1.v | 19,730 | module MODULE1 (
VAR100,
VAR30,
VAR84,
VAR114,
VAR110,
VAR108,
VAR49,
VAR79,
VAR16,
VAR85,
VAR101,
VAR51,
VAR61,
VAR82,
VAR77,
VAR32,
VAR36,
VAR130,
VAR9,
VAR99,
VAR5,
VAR74,
VAR125,
VAR42,
VAR72,
VAR3,
VAR116,
VAR81,
VAR117,
VAR47,
VAR25,
VAR62,
VAR39,
VAR29,
VAR120,
VAR1,
VAR95,
VAR50,
VAR127,
VAR57,
VAR27,
VAR106,
V... | mit |
HarmonInstruments/verilog | sincos/cosrom_RAMB36E1.v | 12,632 | module MODULE1 (
input VAR149, input [9:0] VAR160, VAR2, output [34:0] d0, VAR85);
wire [35:0] o0, o1;
assign d0 = o0[34:0];
assign VAR85 = o1[34:0];
VAR176 #(
.VAR67(1),.VAR76(1),
.VAR62(36'h000000000), .VAR34(36'h000000000),
.VAR121("VAR21"),
.VAR40(36), .VAR30(36),
.VAR100(36), .VAR144(36),
.VAR61(256'hFFE1A04AFFE9A... | gpl-3.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/CS_bak/synthesis/submodules/altera_up_avalon_video_dma_ctrl_addr_trans.v | 8,010 | module MODULE1 (
clk,
reset,
VAR11,
VAR3,
VAR1,
VAR13,
VAR6,
VAR2,
VAR15,
VAR8,
VAR7,
VAR14,
VAR5,
VAR9,
VAR4,
VAR10
);
parameter VAR12 = 32'hC0000000;
input clk;
input reset;
input [ 1: 0] VAR11;
input [ 3: 0] VAR3;
input VAR1;
input VAR13;
input [31: 0] VAR6;
input [31: 0] VAR2;
input VAR15;
output [31: 0] VAR8;
outp... | mit |
cr88192/bgbtech_bjx1core | srvcore/DecOp_0.v | 2,041 | module MODULE1(
clk,
VAR6,
VAR1,
VAR7,
VAR10,
VAR11,
VAR8,
VAR12,
VAR9,
VAR2
);
input clk; input[31:0] VAR6; input[31:0] VAR1;
output[6:0] VAR7;
output[6:0] VAR10;
output[6:0] VAR11;
output[31:0] VAR8;
output[1:0] VAR12;
output[11:0] VAR9;
output[31:0] VAR2;
reg[11:0] VAR3[256];
reg[31:0] VAR4[4096];
reg[7:0] VAR5;
beg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s.blackbox.v | 1,324 | module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR3;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4/sky130_fd_sc_lp__and4.pp.symbol.v | 1,297 | module MODULE1 (
input VAR8 ,
input VAR6 ,
input VAR3 ,
input VAR4 ,
output VAR5 ,
input VAR2 ,
input VAR7,
input VAR1,
input VAR9
);
endmodule | apache-2.0 |
andykarpov/radio-86rk-wxeda | src/video/hvsync_generator.v | 1,932 | module MODULE1(clk, VAR2, VAR12, VAR7, VAR8, VAR1);
input clk;
output VAR2, VAR12;
output VAR7;
output [10:0] VAR8;
output [10:0] VAR1;
integer VAR18 = 11'd800; integer VAR6 = 11'd600; integer VAR19 = 11'd1056; integer VAR13 = 11'd625;
integer VAR14 = 11'd16; integer VAR3 = 11'd80; integer VAR17 = 11'd160;
integer VAR1... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ai/sky130_fd_sc_lp__o21ai.pp.symbol.v | 1,352 | module MODULE1 (
input VAR5 ,
input VAR3 ,
input VAR6 ,
output VAR1 ,
input VAR4 ,
input VAR8,
input VAR7,
input VAR2
);
endmodule | apache-2.0 |
twlostow/dsi-shield | hdl/rtl/dsi_core/dsi_packet_assembler.v | 7,089 | module MODULE1
(
VAR39,
VAR49,
VAR52,
VAR10,
VAR38,
VAR28,
VAR13,
VAR43,
VAR34,
VAR5,
VAR63,
VAR26,
VAR16,
VAR11,
VAR37,
VAR35
);
parameter VAR8 = 1;
parameter VAR55 = 3;
input VAR39;
input VAR49;
input VAR52;
input VAR10;
input [5:0] VAR38;
input [15:0] VAR28;
input [15:0] VAR13;
input [VAR8 * 24-1:0] VAR43;
input VAR... | lgpl-3.0 |
freecores/verilog_fixed_point_math_library | qmult.v | 2,457 | module MODULE1 #(
parameter VAR7 = 15,
parameter VAR3 = 32
)
(
input [VAR3-1:0] VAR6,
input [VAR3-1:0] VAR4,
output [VAR3-1:0] VAR1,
output reg VAR2
);
reg [2*VAR3-1:0] VAR8; reg [VAR3-1:0] VAR5;
assign VAR1 = VAR5;
always @(VAR6, VAR4) begin VAR8 <= VAR6[VAR3-2:0] * VAR4[VAR3-2:0]; VAR2 <= 1'b0; end
always @(VAR8) beg... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv.pp.blackbox.v | 1,409 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR7 ,
VAR6 ,
VAR5,
VAR2 ,
VAR4
);
output VAR1 ;
input VAR3 ;
input VAR7 ;
input VAR6 ;
input VAR5;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/txr_engine_ultrascale.v | 24,004 | module MODULE3
parameter VAR41 = 128,
parameter VAR3 = 1,
parameter VAR115 = 1,
parameter VAR156 = 10,
parameter VAR90 = 256
)
(
input VAR139,
input VAR78,
input [VAR168-1:0] VAR167,
input VAR6,
output VAR13,
output VAR145,
output [VAR41-1:0] VAR26,
output [(VAR41/32)-1:0] VAR53,
output [VAR92-1:0] VAR83,
input VAR157,... | gpl-3.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_pipe_rate.v | 46,234 | module MODULE1 #
(
parameter VAR101 = "VAR20", parameter VAR14 = "VAR135", parameter VAR41 = "3.0", parameter VAR115 = "VAR10", parameter VAR130 = "VAR53", parameter VAR81 = "VAR20", parameter VAR9 = "VAR20", parameter VAR3 = "VAR53", parameter VAR6 = 4'd15
)
(
input VAR64,
input VAR23,
input VAR75,
input VAR31,
input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41ai/sky130_fd_sc_lp__o41ai.blackbox.v | 1,375 | module MODULE1 (
VAR3 ,
VAR5,
VAR1,
VAR4,
VAR6,
VAR2
);
output VAR3 ;
input VAR5;
input VAR1;
input VAR4;
input VAR6;
input VAR2;
supply1 VAR8;
supply0 VAR10;
supply1 VAR9 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_jsp_biu.v | 17,178 | module MODULE1
(
VAR87,
VAR28,
VAR13,
VAR98,
VAR60,
VAR71,
VAR89,
VAR12,
VAR34,
VAR39,
VAR24,
VAR23,
VAR18,
VAR92,
VAR19,
VAR57,
VAR2,
VAR100,
VAR97,
VAR36,
VAR40,
VAR8,
VAR107
);
input VAR87;
input VAR28;
input [7:0] VAR13; output [7:0] VAR98;
output [3:0] VAR71;
output [3:0] VAR60;
input VAR89;
input VAR12;
input VAR... | gpl-2.0 |
h-j-13/MyNote | Programming language/Verilog/sync_FIFO/Source_Code/FIFO_2.v | 2,203 | module MODULE1(clk,VAR1,din,VAR2,VAR9,dout,VAR4,VAR7);
input clk; input VAR1; input[15:0]din; input VAR2; input VAR9;
output[15:0]dout; output VAR4; output VAR7;
parameter VAR3=2, VAR10=2'b11;
reg[15:0]dout;
reg VAR4;
reg VAR7;
reg[(VAR3-1):0] VAR5; reg[(VAR3-1):0] head; reg[(VAR3-1):0] VAR6; reg[15:0]VAR8[0:VAR10];
al... | gpl-3.0 |
P3Stor/P3Stor | pcie/IP core/ssd_command_fifo.v | 13,435 | module MODULE1(
clk,
rst,
din,
VAR35,
VAR89,
dout,
VAR412,
VAR24,
VAR410
);
input clk;
input rst;
input [127 : 0] din;
input VAR35;
input VAR89;
output [127 : 0] dout;
output VAR412;
output VAR24;
output [6 : 0] VAR410;
VAR297 #(
.VAR246(0),
.VAR405(0),
.VAR154(0),
.VAR302(0),
.VAR144(0),
.VAR94(0),
.VAR397(0),
.VAR21(... | gpl-2.0 |
m-labs/milkymist | cores/ac97/rtl/ac97_dma.v | 3,750 | module MODULE1(
input VAR27,
input VAR9,
output reg [31:0] VAR3,
output [2:0] VAR31,
output reg VAR32,
output VAR22,
output VAR26,
input VAR12,
input [31:0] VAR21,
output [31:0] VAR37,
output reg VAR30,
input VAR1,
output reg VAR23,
output reg [19:0] VAR39,
output reg VAR11,
output reg [19:0] VAR42,
output reg VAR13,
i... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp.pp.blackbox.v | 1,402 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR4 ,
VAR7 ,
VAR1 ,
VAR3 ,
VAR10,
VAR8,
VAR9 ,
VAR5
);
output VAR6 ;
output VAR2 ;
input VAR4 ;
input VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR10;
input VAR8;
input VAR9 ;
input VAR5 ;
endmodule | apache-2.0 |
HSID/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_count_to_16x.v | 2,085 | module MODULE1(clk, rst, VAR1, VAR2);
input clk, rst, VAR1;
output [3:0] VAR2;
reg [3:0] VAR3;
assign VAR2 = VAR3;
always@(posedge clk or posedge rst) begin
if(rst == 1'b1) begin
VAR3 = 4'h0;
end
else if ( VAR1 == 1'b1 ) begin
VAR3 = VAR3 + 1;
end
else begin
VAR3 = VAR2;
end
end
endmodule | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxtp/sky130_fd_sc_ms__sdfxtp.pp.blackbox.v | 1,363 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR4 ,
VAR5 ,
VAR2 ,
VAR7,
VAR1,
VAR8 ,
VAR9
);
output VAR3 ;
input VAR6 ;
input VAR4 ;
input VAR5 ;
input VAR2 ;
input VAR7;
input VAR1;
input VAR8 ;
input VAR9 ;
endmodule | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_PPS_OPENFLOW/IPE_PPS.v | 4,390 | module MODULE1(
input clk,
input reset,
input [5:0] VAR24,
input VAR2,input [31:0] VAR44,input VAR62,
input [133:0] VAR41,
input VAR6,
input VAR4,
output VAR47,
output VAR53,
output [133:0] VAR60,
output VAR18,
output VAR14,
input VAR42,
input VAR35,
input [133:0] VAR5,
input VAR12,
input VAR15,
output VAR57,
output VA... | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_022.v | 1,522 | module MODULE1 (
VAR7,
VAR3
);
input [31:0] VAR7;
output [31:0]
VAR3;
wire [31:0]
VAR12,
VAR1,
VAR13,
VAR6,
VAR8,
VAR14,
VAR9,
VAR11,
VAR10;
assign VAR12 = VAR7;
assign VAR11 = VAR12 << 10;
assign VAR10 = VAR9 - VAR11;
assign VAR9 = VAR8 - VAR14;
assign VAR8 = VAR6 - VAR12;
assign VAR6 = VAR13 << 12;
assign VAR14 = VAR... | mit |
mamijaz/RISC-V | src/riscv_pipeline/hazard_control_unit/HAZARD_CONTROL_UNIT.v | 6,688 | module MODULE1 #(
parameter VAR21 = 5 ,
parameter VAR20 = 3 ,
parameter VAR9 = 3'b000 ,
parameter VAR14 = 1'b1 ,
parameter VAR8 = 1'b0
) (
input VAR17 ,
input VAR7 ,
input VAR34 ,
input [VAR21 -1 : 0] VAR33 ,
input [VAR21 -1 : 0] VAR5 ,
input [VAR20 - 1 : 0] VAR16 ,
input [VAR21 -1 : 0] VAR31 ,
input [VAR20 - 1 : 0] VA... | bsd-2-clause |
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