repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrbp/sky130_fd_sc_lp__dfrbp.behavioral.pp.v | 2,354 | module MODULE1 (
VAR16 ,
VAR13 ,
VAR14 ,
VAR17 ,
VAR6,
VAR22 ,
VAR3 ,
VAR21 ,
VAR5
);
output VAR16 ;
output VAR13 ;
input VAR14 ;
input VAR17 ;
input VAR6;
input VAR22 ;
input VAR3 ;
input VAR21 ;
input VAR5 ;
wire VAR23 ;
wire VAR18 ;
reg VAR15 ;
wire VAR4 ;
wire VAR12;
wire VAR1 ;
wire VAR11 ;
wire VAR8 ;
wire VAR9 ;... | apache-2.0 |
unsignedzero/verilogLabs | labs/lab11/sram/sram_fifo.v | 2,497 | module MODULE1(
VAR12, VAR13, VAR4, VAR2, clk, rst );
parameter VAR14 = 8;
parameter VAR3 = 3;
parameter VAR10 = 1<<VAR3;
input VAR12, VAR13, clk, rst;
reg VAR8, VAR18;
input [VAR14-1:0] VAR4;
wire [VAR14-1:0] VAR4;
reg [VAR14-1:0] VAR7;
output [VAR14-1:0] VAR2;
wire [VAR14-1:0] VAR2;
reg [2:0] VAR15; reg [2:0] VAR11; ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dff_pr/sky130_fd_sc_hd__udp_dff_pr.blackbox.v | 1,249 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR1 ,
VAR2
);
output VAR3 ;
input VAR4 ;
input VAR1 ;
input VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2b/sky130_fd_sc_ls__nor2b_1.v | 2,173 | module MODULE2 (
VAR7 ,
VAR6 ,
VAR5 ,
VAR9,
VAR4,
VAR1 ,
VAR3
);
output VAR7 ;
input VAR6 ;
input VAR5 ;
input VAR9;
input VAR4;
input VAR1 ;
input VAR3 ;
VAR2 VAR8 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR7 ,
VAR6 ,
VAR5
);
output VAR7... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4bb/sky130_fd_sc_ls__or4bb_4.v | 2,314 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR1 ,
VAR8 ,
VAR11 ,
VAR10,
VAR5,
VAR7 ,
VAR6
);
output VAR3 ;
input VAR2 ;
input VAR1 ;
input VAR8 ;
input VAR11 ;
input VAR10;
input VAR5;
input VAR7 ;
input VAR6 ;
VAR9 VAR4 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7),
.... | apache-2.0 |
alexforencich/verilog-ethernet | example/VCU108/fpga_10g/rtl/fpga.v | 19,231 | module MODULE1 (
input wire VAR197,
input wire VAR173,
input wire reset,
input wire VAR10,
input wire VAR208,
input wire VAR108,
input wire VAR34,
input wire VAR68,
input wire [3:0] VAR192,
output wire [7:0] VAR216,
inout wire VAR279,
inout wire VAR160,
input wire VAR152,
input wire VAR97,
input wire VAR136,
input wire... | mit |
AmeerAbdelhadi/2D-Binary-Content-Addressable-Memory-BCAM | spram.v | 3,813 | module MODULE1
integer VAR3;
reg [VAR7-1:0] VAR2 [0:VAR9-1]; VAR4
if (VAR1)
for (VAR3=0; VAR3<VAR9; VAR3=VAR3+1) VAR2[VAR3] = {VAR7{1'b0}};
else
if (VAR5 != "")
always @(posedge clk) begin
if (VAR6) begin
VAR2[addr] <= VAR10; VAR8 <= VAR10; end else
VAR8 <= VAR2[addr]; end
endmodule | bsd-3-clause |
asicguy/gplgpu | hdl/altera_project/fifo_181x128a/fifo_181x128a_bb.v | 6,082 | module MODULE1 (
VAR7,
VAR6,
VAR2,
VAR1,
VAR3,
VAR10,
VAR5,
VAR4,
VAR8,
VAR9);
input VAR7;
input [180:0] VAR6;
input VAR2;
input VAR1;
input VAR3;
input VAR10;
output [180:0] VAR5;
output VAR4;
output VAR8;
output [6:0] VAR9;
tri0 VAR7;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32ai/sky130_fd_sc_ls__o32ai.symbol.v | 1,391 | module MODULE1 (
input VAR2,
input VAR1,
input VAR6,
input VAR3,
input VAR5,
output VAR10
);
supply1 VAR7;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
INTI-CMNB/Lattuino_IP_Core | FPGA/lattuino_stick_v_icestorm/lattuino_stick.v | 5,499 | module MODULE1
(
input VAR40, input VAR2, output VAR72,
output VAR114,
output VAR91,
output VAR37,
output VAR13,
output VAR17, input VAR60, input VAR80);
localparam integer VAR93=VAR34/VAR11/4.0+0.5;
localparam integer VAR65=VAR34/1e6; localparam VAR54=1; localparam VAR102=0;
wire [15:0] VAR23; wire [VAR108-1:0] VAR6; ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/decap/sky130_fd_sc_hvl__decap.symbol.v | 1,215 | module MODULE1 ();
supply1 VAR3;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
mosukiton/mipsprocessor | Mips_single_cycle.srcs/sources_1/new/instructiondecode.v | 2,409 | module MODULE1(
output [31:0] VAR35, VAR9, VAR11, VAR27,
output [27:0] VAR31,
output [4:0] VAR33, rd,
output [2:0] VAR22,
output VAR43, VAR38, VAR36, VAR44, VAR41, VAR23, VAR13,
input [31:0] VAR2, VAR16, VAR8,
input [4:0] VAR32,
input VAR42, clk
);
wire [25:0] VAR14;
wire [15:0] VAR18;
wire [5:0] VAR15, VAR28;
wire [4:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtn/sky130_fd_sc_lp__dlrtn.pp.blackbox.v | 1,385 | module MODULE1 (
VAR5 ,
VAR1,
VAR2 ,
VAR8 ,
VAR7 ,
VAR4 ,
VAR3 ,
VAR6
);
output VAR5 ;
input VAR1;
input VAR2 ;
input VAR8 ;
input VAR7 ;
input VAR4 ;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/priority_encoder.v | 3,210 | module MODULE1 #
(
parameter VAR4 = 4,
parameter VAR9 = 0
)
(
input wire [VAR4-1:0] VAR11,
output wire VAR14,
output wire [VAR3(VAR4)-1:0] VAR5,
output wire [VAR4-1:0] VAR16
);
parameter VAR15 = VAR4 > 2 ? VAR3(VAR4) : 1;
parameter VAR12 = 2**VAR15;
wire [VAR12-1:0] VAR17 = {{VAR12-VAR4{1'b0}}, VAR11};
wire [VAR12/2-1:... | mit |
rkrajnc/minimig-mist | rtl/minimig/userio_ps2mouse.v | 7,711 | module MODULE1
(
input clk, input VAR10,
input reset, inout VAR4, inout VAR2, input [5:0] VAR34,
input VAR19,
output reg [7:0]VAR37, output reg [7:0]VAR1, output reg [7:0]VAR13, output reg VAR39, output reg VAR30, output reg VAR3, input VAR9, input [15:0] VAR35 );
reg VAR15;
wire VAR29;
reg [ 2-1:0] VAR36;
reg [ 3-1:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4/sky130_fd_sc_hdll__and4.behavioral.v | 1,400 | module MODULE1 (
VAR3,
VAR8,
VAR5,
VAR2,
VAR1
);
output VAR3;
input VAR8;
input VAR5;
input VAR2;
input VAR1;
supply1 VAR12;
supply0 VAR11;
supply1 VAR4 ;
supply0 VAR6 ;
wire VAR9;
and VAR10 (VAR9, VAR8, VAR5, VAR2, VAR1 );
buf VAR7 (VAR3 , VAR9 );
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/extramfifo/ext_fifo.v | 6,388 | module MODULE1
(
input VAR47,
input VAR15,
input rst,
input [VAR39-1:0] VAR48,
output [VAR39-1:0] VAR6,
output VAR58,
output [VAR24-1:0] VAR29,
output VAR59,
output VAR26,
output VAR43,
output VAR50,
output VAR16,
input [VAR36-1:0] VAR28,
input VAR34, output VAR49, output [VAR36-1:0] VAR46,
output VAR62, input VAR4, ou... | gpl-2.0 |
itpcc/FPGA-IA-Journy-game | verilog/pink_beam-v2-30x30.v | 27,997 | module MODULE1(
input clk,
input wire [9:0] VAR1,
input wire [8:0] VAR3,
input wire [9:0] VAR2,
input wire [8:0] VAR7,
output reg [2:0] VAR4
);
reg [9:0] VAR6;
reg [9:0] VAR5; | mit |
Vadman97/ImageAES | des/DES/decrypt_dumb.v | 1,995 | module MODULE1(
input [63:0] VAR3,
input [63:0] VAR4,
output reg [63:0] VAR2,
output VAR1,
input clk,
input reset,
input enable,
input ack
);
reg [63:0] rand;
begin
begin
end
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21bai/sky130_fd_sc_lp__o21bai_m.v | 2,326 | module MODULE2 (
VAR5 ,
VAR8 ,
VAR4 ,
VAR1,
VAR9,
VAR6,
VAR7 ,
VAR10
);
output VAR5 ;
input VAR8 ;
input VAR4 ;
input VAR1;
input VAR9;
input VAR6;
input VAR7 ;
input VAR10 ;
VAR2 VAR3 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR10(VAR10)
);
endmodule
module MODULE2 ... | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/vfabric_trunc.v | 1,470 | module MODULE1(VAR2, VAR3,
VAR5, VAR7, VAR10,
VAR1, VAR8, VAR6);
parameter VAR9 = 64;
parameter VAR4 = 32;
input VAR2, VAR3;
input [VAR9-1:0] VAR5;
input VAR7;
output VAR10;
output [VAR4-1:0] VAR1;
input VAR8;
output VAR6;
assign VAR1 = VAR5[VAR4-1:0];
assign VAR10 = VAR8;
assign VAR6 = VAR7;
endmodule | mit |
tmolteno/TART | hardware/FPGA/ddrmem/controller.v | 15,572 | module MODULE1 (
VAR73, VAR44,
VAR49,
VAR14,
VAR15,
VAR40,
VAR62,
VAR30,
VAR41,
VAR21,
VAR51, VAR6,
VAR4,
VAR35, VAR57, VAR13,
VAR42,
VAR55,
VAR61,
VAR25,
VAR2,
VAR46,
VAR37
);
parameter VAR59 = 1040;
input VAR73; input VAR44;
output VAR49;
output VAR14;
output VAR15;
output VAR40;
output VAR62;
output [1:0] VAR30; out... | lgpl-3.0 |
KorotkiyEugene/Netmaker_vc_router_syn_quartus | NW_vc_unrestricted_allocator.v | 8,037 | function automatic logic[15:0] VAR8 (input VAR2 VAR3);
begin
case (VAR3.VAR7.VAR40)
begin
VAR8='1;
end
begin
if (VAR3.VAR7.VAR33+1<0) begin
VAR8=4'b0011;
end else begin
VAR8=4'b1100;
end
end
begin
if (VAR3.VAR7.VAR5-1>0) begin
VAR8=4'b0011;
end else begin
VAR8=4'b1100;
end
end
begin
if (VAR3.VAR7.VAR33-1>0) begin
VAR8=... | gpl-2.0 |
huhydro/chriskyElbertV2FPGA | ElbertV2_FPGA_Board.v | 4,750 | module MODULE1(
input[5:0] VAR29,
input clk,
output[7:0] VAR2,
output [7:0] VAR55,
output [2:0] VAR41,
output VAR35,
output VAR15,
inout VAR4
);
wire VAR49;
wire VAR60;
wire VAR6;
wire VAR44;
reg [1:0] VAR14;
wire VAR23;
wire VAR46;
wire VAR43;
wire VAR58;
wire VAR38;
wire VAR27;
wire VAR36;
wire VAR54;
wire [9:0] VAR6... | gpl-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/HDLNeuralNetwork/FSMNeuronalNetwork.v | 20,678 | module MODULE1(VAR42, reset,VAR6,VAR51,VAR5,VAR2,VAR45,VAR21,
VAR37,VAR25,VAR14,VAR29,VAR49,VAR43,VAR38,
VAR50,VAR32,VAR20);
input VAR42;
input reset;
input VAR6;
input VAR51;
input [8:0] VAR5;
output reg VAR2 =0;
output reg VAR45=0;
output reg VAR21=0;
output reg VAR37=0;
output reg [4:0] VAR25=0;
output reg VAR14=0;
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0n/sky130_fd_sc_lp__inputiso0n.functional.v | 1,285 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR4
);
output VAR1 ;
input VAR3 ;
input VAR4;
and VAR2 (VAR1 , VAR3, VAR4 );
endmodule | apache-2.0 |
tdaede/daala_zynq | daala_idct4_mmap_1.0/hdl/daala_idct4_mmap_v1_0_S00_AXI.v | 14,603 | module MODULE1 #
(
parameter integer VAR38 = 32,
parameter integer VAR21 = 4
)
(
input wire VAR49,
input wire VAR60,
input wire [VAR21-1 : 0] VAR39,
input wire [2 : 0] VAR59,
input wire VAR56,
output wire VAR18,
input wire [VAR38-1 : 0] VAR7,
input wire [(VAR38/8)-1 : 0] VAR34,
input wire VAR57,
output wire VAR4,
outpu... | bsd-2-clause |
MegaShow/college-programming | Homework/Computer Organization and Interfacing/Single Cycle CPU/Single Cycle CPU.srcs/sources_1/new/Basys3.v | 1,696 | module MODULE1(
input [1:0] VAR13,
input VAR9,
input VAR10,
input reset,
output wire [7:0] VAR36,
output wire [3:0] VAR17
);
reg [15:0] VAR4[0:3];
reg [15:0] VAR29;
wire clk;
wire [31:0] VAR11, VAR16;
wire [31:0] VAR6;
wire [31:26] VAR8;
wire [25:21] VAR2;
wire [20:16] VAR12;
wire [15:11] rd;
wire [10:6] VAR37;
wire [1... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_12.v | 10,601 | module MODULE4 (
clk,
reset,
VAR36,
VAR58,
VAR4,
VAR42,
VAR17
);
parameter VAR23 = 18;
parameter VAR1 = 12;
parameter VAR24 = 6;
localparam VAR3 = 13;
input clk;
input reset;
input VAR36;
input VAR58;
input [VAR23-1:0] VAR4; output VAR42;
output [VAR23-1:0] VAR17;
localparam VAR82 = 18; localparam VAR79 = 36; localpara... | mit |
aquaxis/FPGAMAG18 | fmrv32im-artya7.nonos/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/5d65/src/fmrv32im_reg.v | 5,439 | module MODULE1
(
input VAR1,
input VAR40,
input [4:0] VAR12,
input VAR41,
input [31:0] VAR47,
input [4:0] VAR45,
output reg [31:0] VAR21,
input [4:0] VAR48,
output reg [31:0] VAR28,
output [31:0] VAR26,
output [31:0] VAR30,
output [31:0] VAR17,
output [31:0] VAR42,
output [31:0] VAR5,
output [31:0] VAR32,
input VAR24,
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor3/sky130_fd_sc_hdll__xnor3.functional.pp.v | 1,846 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR7 ,
VAR1 ,
VAR2,
VAR6,
VAR14 ,
VAR12
);
output VAR5 ;
input VAR8 ;
input VAR7 ;
input VAR1 ;
input VAR2;
input VAR6;
input VAR14 ;
input VAR12 ;
wire VAR10 ;
wire VAR4;
xnor VAR11 (VAR10 , VAR8, VAR7, VAR1 );
VAR9 VAR13 (VAR4, VAR10, VAR2, VAR6);
buf VAR3 (VAR5 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211ai/sky130_fd_sc_lp__o211ai_m.v | 2,358 | module MODULE2 (
VAR5 ,
VAR4 ,
VAR1 ,
VAR11 ,
VAR2 ,
VAR3,
VAR7,
VAR10 ,
VAR6
);
output VAR5 ;
input VAR4 ;
input VAR1 ;
input VAR11 ;
input VAR2 ;
input VAR3;
input VAR7;
input VAR10 ;
input VAR6 ;
VAR8 VAR9 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR10(VAR10),
.... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/slaveController/slaveGetpacket.v | 12,476 | module MODULE1 (VAR19, VAR36, VAR4, VAR38, VAR41, VAR31, VAR18, VAR60, VAR24, VAR3, VAR68, VAR70, VAR32, VAR43, VAR37, clk, VAR14, VAR5, VAR45, rst);
input [7:0] VAR4;
input VAR38;
input VAR31;
input [7:0] VAR3;
input VAR32; input clk;
input VAR5;
input VAR45;
input rst;
output VAR19;
output VAR36;
output [7:0] VAR41;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/conb/sky130_fd_sc_ms__conb.pp.blackbox.v | 1,255 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR6,
VAR5,
VAR1 ,
VAR2
);
output VAR4 ;
output VAR3 ;
input VAR6;
input VAR5;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
mwswartwout/EECS318 | hw2/problem1/arithmetic.v | 1,374 | module MODULE1(VAR6, VAR8, VAR9, VAR2, VAR3, enable);
output reg [15:0] VAR6;
output reg VAR8;
input [15:0] VAR9,VAR2;
input [4:0] VAR3;
input enable;
reg signed [16:0] VAR7;
reg unsigned [16:0] VAR1;
wire signed [15:0] VAR4, VAR5;
assign VAR4 = VAR9;
assign VAR5 = VAR2;
begin
begin
begin
begin
begin
begin | mit |
YosysHQ/yosys | techlibs/xilinx/brams_xcv_map.v | 5,210 | module MODULE1 (...);
parameter VAR42 = 0;
parameter VAR78 = 1;
parameter VAR8 = 1;
parameter VAR15 = 1;
parameter VAR35 = 0;
input VAR61;
input VAR56;
input [11:0] VAR75;
input [VAR78-1:0] VAR24;
input VAR1;
output [VAR78-1:0] VAR64;
input VAR14;
input VAR29;
input VAR46;
input [11:0] VAR48;
input [VAR8-1:0] VAR70;
in... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and3/sky130_fd_sc_hs__and3_1.v | 2,037 | module MODULE2 (
VAR4 ,
VAR8 ,
VAR3 ,
VAR6 ,
VAR1,
VAR2
);
output VAR4 ;
input VAR8 ;
input VAR3 ;
input VAR6 ;
input VAR1;
input VAR2;
VAR5 VAR7 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR4,
VAR8,
VAR3,
VAR6
);
output VAR4;
input VAR8;
input VAR3;
in... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/e47788bd6dc9e881/zqynq_lab_1_design_auto_pc_4_stub.v | 4,584 | module MODULE1(VAR57, VAR16, VAR52, VAR42,
VAR7, VAR50, VAR28, VAR46, VAR3, VAR5,
VAR25, VAR44, VAR43, VAR21, VAR29, VAR1, VAR41,
VAR51, VAR30, VAR2, VAR55, VAR38, VAR15, VAR35,
VAR53, VAR58, VAR56, VAR54, VAR19, VAR32,
VAR48, VAR33, VAR45, VAR23, VAR9, VAR6, VAR26,
VAR49, VAR12, VAR13, VAR18, VAR10, VAR59,
VAR36, VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221oi/sky130_fd_sc_lp__a221oi.pp.symbol.v | 1,409 | module MODULE1 (
input VAR7 ,
input VAR6 ,
input VAR9 ,
input VAR2 ,
input VAR3 ,
output VAR10 ,
input VAR8 ,
input VAR5,
input VAR4,
input VAR1
);
endmodule | apache-2.0 |
wendlers/lattice-logic-sniffer | logic/lib/ram.v | 102,109 | module MODULE1 (VAR182, VAR39, VAR165, VAR147, VAR129, VAR69, VAR124,
VAR139, VAR30, VAR45);
input wire [13:0] VAR182;
input wire [13:0] VAR39;
input wire [7:0] VAR165;
input wire VAR147;
input wire VAR129;
input wire VAR69;
input wire VAR124;
input wire VAR139;
input wire VAR30;
output wire [7:0] VAR45;
wire VAR20;
wi... | mit |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_1_stub.v | 1,424 | module MODULE1(VAR4, VAR3, VAR2, VAR7, VAR8, VAR1, VAR5, VAR6)
;
input VAR4;
input [0:0]VAR3;
input [11:0]VAR2;
input [7:0]VAR7;
input VAR8;
input VAR1;
input [9:0]VAR5;
output [31:0]VAR6;
endmodule | mit |
HarmonInstruments/verilog | fir/halfband_decim/halfband_decim.v | 5,396 | module MODULE1
(
input VAR65,
input [17:0] VAR26,
input [VAR68-1:0] VAR7,
input [23:0] VAR16, input [23:0] VAR20, output [23:0] VAR10
);
parameter integer VAR23 = 4; parameter integer VAR68 = 3;
wire signed [47:0] VAR25 [0:VAR68-1];
wire signed [47:0] VAR73 [0:VAR68-1];
wire signed [23:0] VAR63 [0:VAR68-1];
wire signed... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_ncio/rtl/jbi_ncio_prtq_buf.v | 4,475 | module MODULE1(
VAR29,
clk, VAR24, VAR19, VAR20, VAR7,
VAR21, VAR11, VAR26, VAR3,
VAR27, VAR2
);
input clk;
input VAR24;
input VAR19;
input VAR20;
input [4:0] VAR7;
input [4:0] VAR21;
input VAR11;
input VAR26;
input [VAR13-1:0] VAR3;
input [VAR13-1:0] VAR27;
input [VAR10-1:0] VAR2;
output [VAR10-1:0] VAR29;
wire [VAR10... | gpl-2.0 |
hrshishym/DriveTFT18 | DriveTFT18.srcs/sources_1/timer_wait.v | 1,030 | module MODULE1(
input wire clk,
input wire VAR5,
input wire VAR4,
input wire req,
input wire [7:0] VAR8,
output wire ack
);
wire VAR6; reg [15:0] VAR2; reg [7:0] VAR3;
reg VAR1;
wire VAR7;
always @(posedge clk) begin
if(VAR5) VAR1 <= 0;
end
else VAR1 <= req;
end
assign VAR7 = (VAR4) & (req & ~VAR1);
always @(posedge cl... | mit |
peladex/RHD2132_FPGA | src/spi_wb/spi_top.v | 12,506 | module MODULE1
(
VAR67, VAR65, VAR37, VAR8, VAR59, VAR62,
VAR42, VAR48, VAR19, VAR1, VAR50, VAR7,
VAR58, VAR11, VAR41, VAR33
);
parameter VAR45 = 1;
input VAR67; input VAR65; input [4:0] VAR37; input [32-1:0] VAR8; output [32-1:0] VAR59; input [3:0] VAR62; input VAR42; input VAR48; input VAR19; output VAR1; output VAR5... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/tlu/rtl/tlu_misctl.v | 19,836 | module MODULE1 (
VAR68, VAR73, VAR107, VAR85,
VAR25, VAR63, VAR64,
VAR106, VAR88, VAR89,
VAR132, VAR69,
VAR100, VAR124, VAR24, VAR94, VAR70,
VAR127, VAR84, VAR115, VAR34,
VAR101, VAR80, VAR59, VAR60, VAR20,
VAR49, VAR5, VAR36, VAR130, VAR40,
VAR50, VAR133, VAR46, VAR140,
VAR6, VAR83, VAR113,
VAR72, VAR43, VAR26, VAR135... | gpl-2.0 |
loonquawl/fermiac | bus/bus.v | 11,158 | module MODULE5
parameter VAR49=32,
parameter VAR27=16 )
(
input clk,
inout [VAR49-1:0] VAR8,
inout [VAR27-1:0] VAR36, inout [VAR27-1:0] VAR16, input [VAR27-1:0] VAR54, output reg [VAR27-1:0] VAR23 );
reg [VAR27-1:0] VAR72=0;
generate
genvar VAR83;
for (VAR83=1; VAR83<VAR27; VAR83=VAR83+1) begin: VAR73
always @(negedge ... | mit |
olajep/oh | src/adi/hdl/library/common/ad_datafmt.v | 3,541 | module MODULE1 #(
parameter VAR3 = 16,
parameter VAR8 = 0) (
input clk,
input valid,
input [(VAR3-1):0] VAR2,
output VAR7,
output [15:0] VAR12,
input VAR5,
input VAR1,
input VAR10);
reg VAR13 = 'd0;
reg [15:0] VAR4 = 'd0;
wire VAR14;
wire [15:0] VAR11;
generate
if (VAR8 == 1) begin
assign VAR7 = valid;
assign VAR12 = V... | mit |
SI-RISCV/e200_opensource | rtl/e203/core/e203_exu_alu_bjp.v | 4,970 | module MODULE1(
input VAR52, output VAR11,
input [VAR49-1:0] VAR20,
input [VAR49-1:0] VAR26,
input [VAR49-1:0] VAR44,
input [VAR1-1:0] VAR5,
input [VAR19-1:0] VAR41,
output VAR27, input VAR10, output [VAR49-1:0] VAR24,
output VAR33,
output VAR53,
output VAR22,
output VAR31,
output VAR12,
output VAR29, output VAR35,
out... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu7t5v0__aoi222_1.functional.v | 3,002 | module MODULE1( VAR16, VAR26, VAR3, VAR25, VAR24, VAR11, VAR33 );
input VAR33, VAR11, VAR3, VAR24, VAR26, VAR16;
output VAR25;
wire VAR15;
not VAR23( VAR15, VAR33 );
wire VAR4;
not VAR35( VAR4, VAR3 );
wire VAR5;
not VAR12( VAR5, VAR26 );
wire VAR7;
and VAR22( VAR7, VAR15, VAR4, VAR5 );
wire VAR29;
not VAR19( VAR29, VA... | apache-2.0 |
Digilent/vivado-library | ip/MotorFeedback_1.0/hdl/MotorFeedback_v1_0.v | 2,592 | module MODULE1 #
(
parameter integer VAR6 = 32,
parameter integer VAR11 = 5
)
(
input wire VAR42,
input wire VAR32,
input wire VAR13,
input wire VAR15,
input wire [VAR11-1 : 0] VAR41,
input wire [2 : 0] VAR7,
input wire VAR36,
output wire VAR37,
input wire [VAR6-1 : 0] VAR8,
input wire [(VAR6/8)-1 : 0] VAR44,
input wir... | mit |
DigitalLogicSummerTerm2015/mips-cpu-alu | src/alu.v | 1,101 | module MODULE1(
output reg [31:0] VAR5,
input [31:0] VAR6,
input [31:0] VAR3,
input [5:0] VAR17,
input VAR16
);
wire VAR7, VAR10, VAR4;
wire [31:0] VAR22, VAR11, VAR12, VAR23;
VAR8 VAR9(.VAR5 (VAR7),
.VAR21 (VAR10),
.VAR19 (VAR4),
.dout(VAR22),
.VAR6 (VAR6),
.VAR3 (VAR3),
.VAR1(VAR17[0]),
.VAR16(VAR16));
VAR13 VAR14(.d... | mit |
nlsynth/nli | lib/fp/fp16raddsub.v | 6,498 | module MODULE2(
input clk,
input rst,
input [15:0] VAR59,
input [15:0] VAR12,
input VAR17,
output [15:0] VAR14,
output [15:0] VAR20,
output VAR16,
output VAR15);
wire [15:0] VAR61;
wire [15:0] VAR1;
wire VAR26;
wire VAR48;
wire VAR27;
wire [15:0] VAR66;
wire VAR53;
wire [4:0] VAR62;
wire [4:0] VAR51;
wire VAR3;
wire VA... | gpl-3.0 |
aj-michael/Digital-Systems | Lab2-Part2-Controller7SegmentDisplayKeypadScanner/KeyEncoderAJM.v | 2,169 | module MODULE1(VAR13, VAR12, VAR22, VAR6, VAR23, VAR17, VAR20);
input [3:0] VAR13;
input [3:0] VAR12;
input VAR22, VAR6;
output reg [3:0] VAR23;
output reg [3:0] VAR17;
output reg VAR20;
parameter VAR8 = 9'd0;
parameter VAR10 = 9'b100000001;
parameter VAR3 = 9'b100000010;
parameter VAR15 = 9'b100000011;
parameter VAR4 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p.functional.pp.v | 2,304 | module MODULE1 (
VAR13 ,
VAR4 ,
VAR6 ,
VAR18,
VAR16 ,
VAR7 ,
VAR3,
VAR14 ,
VAR8
);
output VAR13 ;
input VAR4 ;
input VAR6 ;
input VAR18;
input VAR16 ;
input VAR7 ;
input VAR3;
input VAR14 ;
input VAR8 ;
wire VAR17 ;
wire VAR19 ;
wire VAR10;
wire VAR12 ;
not VAR11 (VAR17 , VAR4 );
VAR2 VAR15 (VAR19 , VAR6, VAR16, VAR7 )... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1n/sky130_fd_sc_lp__iso1n.pp.symbol.v | 1,279 | module MODULE1 (
input VAR6 ,
output VAR7 ,
input VAR1,
input VAR3 ,
input VAR2 ,
input VAR4 ,
input VAR5
);
endmodule | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/edc/edc_corrector.v | 6,165 | module MODULE1 (
input [31:0] VAR3,
input [7:0] VAR2,
output [31:0] VAR5,
output VAR6,
output VAR1
);
wire [7:0] VAR8[0:39];
wire [39:0] VAR4;
generate
assign VAR8[39] = 8'b10101000;
assign VAR8[38] = 8'b01101000;
assign VAR8[37] = 8'b10100100;
assign VAR8[36] = 8'b01100100;
assign VAR8[35] = 8'b10100010;
assign VAR8[3... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxbp/sky130_fd_sc_ls__dlxbp.behavioral.v | 1,963 | module MODULE1 (
VAR3 ,
VAR9 ,
VAR15 ,
VAR6
);
output VAR3 ;
output VAR9 ;
input VAR15 ;
input VAR6;
supply1 VAR14;
supply0 VAR12;
supply1 VAR13 ;
supply0 VAR11 ;
wire VAR7 ;
wire VAR10;
wire VAR16 ;
reg VAR1 ;
wire VAR17 ;
VAR8 VAR4 (VAR7 , VAR16, VAR10, VAR1, VAR14, VAR12);
buf VAR5 (VAR3 , VAR7 );
not VAR2 (VAR9 , V... | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/rtl/cache_4word.v | 19,554 | module MODULE1(clk,
rst,
VAR11,
VAR34,
VAR32,
VAR23,
VAR55,
VAR53,
VAR10,
VAR19,
VAR36,
VAR6,
VAR45,
VAR61,
VAR17,
VAR30,
VAR37,
VAR52,
VAR56,
VAR35,
VAR12,
VAR28,
VAR58,
VAR41);
parameter VAR48 = 14;
input wire clk, rst;
input wire [24:0] VAR11;
input wire [3:0] VAR34;
input wire [31:0] VAR32;
input wire VAR23, VAR55;... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fa/sky130_fd_sc_ms__fa.functional.pp.v | 3,007 | module MODULE1 (
VAR28,
VAR8 ,
VAR12 ,
VAR13 ,
VAR29 ,
VAR31,
VAR15,
VAR18 ,
VAR25
);
output VAR28;
output VAR8 ;
input VAR12 ;
input VAR13 ;
input VAR29 ;
input VAR31;
input VAR15;
input VAR18 ;
input VAR25 ;
wire VAR16 ;
wire VAR4 ;
wire VAR20 ;
wire VAR19 ;
wire VAR14 ;
wire VAR24 ;
wire VAR7 ;
wire VAR23;
wire VAR1... | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | communication_assist/commu_assist.v | 32,660 | module MODULE1( clk,
rst,
VAR241, VAR25, VAR194, VAR98,
VAR189,
VAR69,
VAR166, VAR129,
VAR231, VAR186, VAR72, VAR225, VAR224, VAR101, VAR18,
VAR154,
VAR112, VAR233, VAR252, VAR97, VAR29, VAR255,
VAR258, VAR16, VAR191,
VAR249, VAR51, VAR197, VAR223,
VAR77, VAR122, VAR35, VAR17,
VAR4, VAR218, VAR26, VAR163, VAR145, VAR40... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22ai/sky130_fd_sc_hd__o22ai.behavioral.v | 1,615 | module MODULE1 (
VAR10 ,
VAR4,
VAR7,
VAR13,
VAR2
);
output VAR10 ;
input VAR4;
input VAR7;
input VAR13;
input VAR2;
supply1 VAR9;
supply0 VAR14;
supply1 VAR5 ;
supply0 VAR15 ;
wire VAR12 ;
wire VAR6 ;
wire VAR16;
nor VAR8 (VAR12 , VAR13, VAR2 );
nor VAR1 (VAR6 , VAR4, VAR7 );
or VAR11 (VAR16, VAR6, VAR12);
buf VAR3 (VA... | apache-2.0 |
alexforencich/verilog-ethernet | example/S10DX_DK/fpga_10g/rtl/fpga.v | 20,414 | module MODULE1 (
input wire VAR311,
input wire VAR140,
input wire VAR274,
output wire [3:0] VAR51,
output wire [3:0] VAR2,
output wire [3:0] VAR224,
input wire [3:0] VAR101,
input wire [3:0] VAR267,
output wire [3:0] VAR131,
output wire [3:0] VAR180,
input wire [3:0] VAR46,
input wire [3:0] VAR13,
input wire VAR87
);
w... | mit |
huhydro/chriskyElbertV2FPGA | mySevenSegment.v | 1,628 | module MODULE1(
input clk,
input VAR5,
input [3:0] VAR2,
input [3:0] VAR4,
input [3:0] VAR6,
output [6:0] VAR8,
output reg [2:0] VAR7
);
reg [6:0] out;
integer VAR1;
reg[3:0] VAR3;
integer counter;
assign VAR8 = ~out;
always @(posedge clk or negedge VAR5)
begin
if (~VAR5)
begin
out <= 7'b0;
VAR7<=3'b110;
counter<=0;
en... | gpl-2.0 |
Nrpickle/ECE272 | Lab5_TekBotSM/Lab4_SmartTekbotRemote/Section5_Top_prim.v | 13,233 | module MODULE3 (VAR27, VAR126, VAR78, VAR136) ; input VAR27; input VAR126; input VAR78; output [3:0]VAR136;
wire VAR22; wire VAR73; wire VAR4; wire VAR9; wire [3:0]VAR29; wire clk; wire VAR26;
wire VAR102;
VAR45 VAR31 (.VAR132(VAR102));
VAR43 VAR42 (.VAR18(VAR22), .VAR125(clk)) ;
MODULE2 MODULE1 (.VAR26(VAR26), .clk(c... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4b/sky130_fd_sc_lp__nand4b.functional.v | 1,432 | module MODULE1 (
VAR2 ,
VAR8,
VAR5 ,
VAR4 ,
VAR1
);
output VAR2 ;
input VAR8;
input VAR5 ;
input VAR4 ;
input VAR1 ;
wire VAR3 ;
wire VAR9;
not VAR10 (VAR3 , VAR8 );
nand VAR6 (VAR9, VAR1, VAR4, VAR5, VAR3);
buf VAR7 (VAR2 , VAR9 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/reset_sync.v | 1,927 | module MODULE1(
VAR2,
clk,
VAR6
);
parameter VAR7 = 4;
parameter VAR3 = 1;
input VAR2;
input clk;
output [VAR3-1:0] VAR6;
reg [VAR7+VAR3-2:0] VAR4 ;
generate
genvar VAR1;
for (VAR1=0; VAR1<VAR7+VAR3-1; VAR1=VAR1+1)
begin: VAR5
always @(posedge clk or negedge VAR2)
begin
if (~VAR2)
VAR4[VAR1] <= 1'b0;
end
else
begin
if ... | lgpl-3.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/pcie_7x_v1_8_pcie_brams_7x.v | 9,066 | module MODULE1
parameter [3:0] VAR7 = 4'h1, parameter [5:0] VAR25 = 6'h08, parameter VAR15 = "VAR13",
parameter VAR2 = 0,
parameter VAR14 = 1,
parameter VAR22 = 1,
parameter VAR21 = 1
)
(
input VAR24,
input VAR12,
input VAR11,
input [12:0] VAR10,
input [71:0] VAR9,
input VAR23,
input VAR1,
input [12:0] VAR8,
output [71... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/inv/sky130_fd_sc_hd__inv.pp.symbol.v | 1,238 | module MODULE1 (
input VAR5 ,
output VAR3 ,
input VAR2 ,
input VAR4,
input VAR1,
input VAR6
);
endmodule | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | Timer_Counter/Periph_gen_clk_tst.v | 2,639 | module MODULE1;
reg clk;
reg rst;
reg VAR10;
reg [15:0] din;
reg VAR6;
reg [3:0] addr;
reg rd;
reg wr;
wire [15:0] dout;
VAR9 VAR1 (
.clk(clk),
.rst(rst),
.din(din),
.VAR6(VAR6),
.addr(addr),
.rd(rd),
.wr(wr),
.dout(dout)
);
parameter VAR3 = 20;
parameter real VAR7 = 0.5;
parameter VAR5 = 0;
reg [20:0] VAR2;
VAR8 VAR4;... | mit |
gtaylormb/opl3_fpga | fpga/bd/opl3_cpu/ip/opl3_cpu_auto_pc_0/axi_protocol_converter_v2_1_8/hdl/verilog/axi_protocol_converter_v2_1_b2s_ar_channel.v | 3,933 | module MODULE1 #
(
parameter integer VAR18 = 4,
parameter integer VAR2 = 32
)
(
input wire clk ,
input wire reset ,
input wire [VAR18-1:0] VAR15 ,
input wire [VAR2-1:0] VAR21 ,
input wire [7:0] VAR24 ,
input wire [2:0] VAR19 ,
input wire [1:0] VAR17 ,
input wire VAR1 ,
output wire VAR7 ,
output wire VAR29 ,
output wire... | lgpl-3.0 |
P3Stor/P3Stor | DDR3/ip_top/memc_ui_top.v | 33,271 | module MODULE1 #
(
parameter VAR144 = 200,
parameter VAR161 = "VAR154",
parameter VAR7 = "VAR213",
parameter VAR204 = 2,
parameter VAR10 = "VAR22",
parameter VAR36 = 1,
parameter VAR219 = 6,
parameter VAR35 = 3,
parameter VAR6 = 1,
parameter VAR225 = 3,
parameter VAR55 = 2,
parameter VAR43 = 2,
parameter VAR71 = 10,
pa... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufbuf/sky130_fd_sc_ms__bufbuf_8.v | 2,030 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR7,
VAR6,
VAR5 ,
VAR4
);
output VAR8 ;
input VAR3 ;
input VAR7;
input VAR6;
input VAR5 ;
input VAR4 ;
VAR1 VAR2 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR8,
VAR3
);
output VAR8;
input VAR3;
supply1 VAR7;
supply0 VAR6;... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_KOA/integracion_fisica/front_end/source/RecursiveKOA.v | 5,733 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR15,
input wire [VAR35-1:0] VAR18,
input wire [VAR35-1:0] VAR27,
output reg [2*VAR35-1:0] VAR30
);
wire [1:0] VAR8;
wire [3:0] VAR19;
assign VAR8 = 2'b00;
assign VAR19 = 4'b0000;
wire [VAR35/2-1:0] VAR26;
wire [VAR35/2:0] VAR23;
wire [VAR35/2-3:0] VAR36;
wir... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.v | 2,168 | module MODULE2 (
VAR3,
VAR7 ,
VAR1 ,
VAR5 ,
VAR4
);
output VAR3;
input VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR4 ;
VAR2 VAR6 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR3,
VAR7
);
output VAR3;
input VAR7 ;
supply1 VAR1;
supply1 VAR5 ;
supply0 VAR4 ;
VAR2 VAR6 (
.... | apache-2.0 |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodACL_v1_0/src/PmodACL.v | 13,868 | module MODULE1
(VAR154,
VAR145,
VAR208,
VAR142,
VAR88,
VAR116,
VAR85,
VAR27,
VAR183,
VAR26,
VAR46,
VAR9,
VAR203,
VAR56,
VAR196,
VAR76,
VAR112,
VAR158,
VAR162,
VAR6,
VAR153,
VAR156,
VAR100,
VAR2,
VAR108,
VAR161,
VAR101,
VAR172,
VAR177,
VAR212,
VAR129,
VAR64,
VAR211,
VAR111,
VAR176,
VAR34,
VAR96,
VAR126,
VAR110,
VAR188,
... | bsd-3-clause |
esonghori/TinyGarbled | circuit_synthesis/knns/first_nns_comb.v | 1,465 | module MODULE1
(
parameter VAR9 = 15,
parameter VAR20 = 32
)
(
VAR1,
VAR26,
VAR6
);
function integer VAR2;
input [31:0] VAR22;
reg [31:0] VAR4;
begin
VAR4 = VAR22;
for (VAR2=0; VAR4>0; VAR2=VAR2+1)
VAR4 = VAR4>>1;
end
endfunction
localparam VAR25 = VAR2(VAR9);
input [VAR9-1:0] VAR1;
input [VAR9*VAR20-1:0] VAR26;
output... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd_1.v | 1,803 | module MODULE1 (
VAR2,
VAR3
);
input VAR2;
input VAR3;
VAR4 VAR1 (
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE1 ();
supply1 VAR2;
supply0 VAR3;
VAR4 VAR1 ();
endmodule | apache-2.0 |
orbancedric/DeepGate | src/interface/custom/spi_slave.v | 1,101 | module MODULE1 #(
parameter VAR13 = 8
)(
input clk,
input VAR3,
input VAR11,
input VAR5,
output reg VAR1 = 0,
input [VAR13 - 1:0] VAR16,
input VAR10,
output reg [VAR13 - 1:0] VAR6 = 0,
output reg VAR2 = 0,
output wire VAR9
);
reg VAR4 = 0;
reg VAR12 = 1;
reg [1:0] VAR14 = 2'b11;
reg [1:0] VAR15 = 0;
reg [VAR13 - 1:0] V... | gpl-3.0 |
Separius/Custom-Single-Cycle-MIPS | ALU.v | 3,401 | module MODULE1(input clk,rst,input[4:0] VAR5,input signed[7:0] VAR4,VAR10,output reg signed[7:0] VAR9,output VAR1,VAR6);
reg VAR2,VAR11,VAR7;
reg VAR8,VAR3;
assign VAR1 = VAR8;
assign VAR6 = VAR3;
always@(posedge clk,posedge rst)
if(rst)
begin
VAR2=1'b0;
VAR11=1'b0;
end
else
begin
VAR8 = VAR2;
VAR3 = VAR11;
end
always@... | gpl-3.0 |
monotone-RK/FACE | MCSoC-15/16-way_4-parallel/ise/ipcore_dir/dram/user_design/rtl/phy/mig_7series_v1_9_ddr_of_pre_fifo.v | 8,144 | module MODULE1 #
(
parameter VAR2 = 100, parameter VAR11 = 4, parameter VAR1 = 32 )
(
input clk, input rst, input VAR23, input VAR14, input [VAR1-1:0] din, output VAR8, output [VAR1-1:0] dout, output VAR12 );
localparam VAR13
= (VAR11 == 2) ? 1 :
((VAR11 == 3) || (VAR11 == 4)) ? 2 :
(((VAR11 == 5) || (VAR11 == 6) ||
(V... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_mux_one_hot.v | 1,304 | if (VAR5 && VAR11 == VAR3 && VAR15 == VAR12) \
begin: VAR13 \
VAR1 VAR14 \
(.* \
); \
end
module MODULE1 #(parameter VAR10(VAR15)
, VAR11=1
, VAR5=1
)
(
input [VAR11-1:0][VAR15-1:0] VAR18
,input [VAR11-1:0] VAR17
,output [VAR15-1:0] VAR6
);
wire [VAR11-1:0][VAR15-1:0] VAR16;
genvar VAR8,VAR4;
else
else
begin : VAR2
for... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2/sky130_fd_sc_hdll__or2_8.v | 2,091 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR5 ,
VAR2,
VAR7,
VAR3 ,
VAR4
);
output VAR6 ;
input VAR8 ;
input VAR5 ;
input VAR2;
input VAR7;
input VAR3 ;
input VAR4 ;
VAR9 VAR1 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR6,
VAR8,
VAR5
);
output VAR6;
... | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_extract_exp.v | 2,495 | module MODULE1( VAR10, VAR15, enable, VAR1, VAR7, VAR4, VAR5, VAR14, VAR13);
parameter VAR2 = 32;
parameter VAR6 = 1;
input VAR10, VAR15;
input enable, VAR1, VAR4;
output VAR7, VAR5;
input [VAR2-1:0] VAR14;
output [31:0] VAR13;
reg VAR12;
wire VAR8;
wire VAR3 = (VAR6 == 1) ? (~VAR12 | ~VAR8) : enable;
assign VAR5 = VAR... | mit |
VerticalResearchGroup/miaow | src/verilog/rtl/common/encoder.v | 1,210 | module MODULE1(in,out);
input [39:0] in;
output [5:0] out;
assign out = (in[0]==1'b1)?6'd0:
(in[1]==1'b1)?6'd1:
(in[2]==1'b1)?6'd2:
(in[3]==1'b1)?6'd3:
(in[4]==1'b1)?6'd4:
(in[5]==1'b1)?6'd5:
(in[6]==1'b1)?6'd6:
(in[7]==1'b1)?6'd7:
(in[8]==1'b1)?6'd8:
(in[9]==1'b1)?6'd9:
(in[10]==1'b1)?6'd10:
(in[11]==1'b1)?6'd11:
(in[... | bsd-3-clause |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/acl_fp_convert_with_rounding_8.v | 10,010 | module MODULE1(VAR25, VAR22, VAR36, VAR28, VAR13, VAR38, VAR10, VAR39, enable);
parameter VAR19 = 1;
parameter VAR35 = 0;
parameter VAR32 = 1;
input VAR25;
input enable, VAR22;
input [31:0] VAR36;
output [7:0] VAR28;
input VAR13, VAR10;
output VAR39, VAR38;
wire VAR14;
wire [7:0] VAR8;
wire [22:0] VAR9;
wire [23:0] VAR... | mit |
plindstroem/oh | elink/dv/dv_elink_system.v | 29,657 | module MODULE1(
VAR28, VAR69, VAR70, VAR112, VAR36,
VAR161, VAR299, VAR271, VAR327, VAR262,
VAR294,
clk, reset, VAR187, VAR304, VAR84, VAR292,
VAR98, VAR139, VAR278, VAR56, VAR116
);
parameter VAR7=32;
parameter VAR314=32;
parameter VAR66=2; parameter VAR40=12;
input [VAR66-1:0] clk; input reset; output VAR28; output V... | gpl-3.0 |
MarcoVogt/basil | firmware/modules/i2c/i2c_core.v | 8,745 | module MODULE1 #(
parameter VAR22 = 16,
parameter VAR39 = 1
)(
input wire VAR9,
input wire VAR50,
input wire [VAR22-1:0] VAR33,
input wire [7:0] VAR24,
input wire VAR67,
input wire VAR1,
output reg [7:0] VAR52,
input wire VAR63,
inout wire VAR51,
inout wire VAR35
);
localparam VAR38 = 1;
reg [7:0] VAR58 [7:0];
wire VAR... | bsd-3-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_link/bsg_link_sdr_downstream.v | 3,591 | module MODULE1
,parameter VAR19 = 3
,parameter VAR1 = 0
,parameter VAR14 = 0
)
( input VAR2
,input VAR9
,output VAR10
,output [VAR29-1:0] VAR11
,input VAR17
,input VAR18
,input VAR33
,input VAR6
,input [VAR29-1:0] VAR13
,output VAR27
);
logic VAR31, VAR4;
logic [VAR29-1:0] VAR26;
VAR24
) VAR32
(.VAR28 (VAR33)
,.VAR15 (... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbn/sky130_fd_sc_hs__dlrbn.functional.pp.v | 2,067 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR3 ,
VAR8 ,
VAR6,
VAR16 ,
VAR13
);
input VAR5 ;
input VAR4 ;
output VAR3 ;
output VAR8 ;
input VAR6;
input VAR16 ;
input VAR13 ;
wire VAR11 ;
wire VAR7;
wire VAR2 ;
not VAR14 (VAR11 , VAR6 );
not VAR17 (VAR7, VAR13 );
VAR9 VAR15 VAR10 (VAR2 , VAR16, VAR7, VAR11, VAR5, VAR4);
buf VAR12 (... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v | 18,618 | module MODULE1
VAR28 = 2,
VAR9 = 1,
VAR13 = 4,
VAR45 = 4
)
(
VAR38,
VAR14,
VAR17,
VAR53,
VAR25,
VAR31,
VAR2,
VAR44,
VAR16,
VAR40,
VAR27,
VAR24
);
localparam integer VAR39 = 2**VAR13;
localparam integer VAR32 = 6; localparam integer VAR15 = 4; localparam integer VAR52 = VAR28 / 2;
input VAR38;
input VAR14;
input [VAR13-... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_4.behavioral.pp.v | 3,497 | module MODULE1( VAR3, VAR11, VAR5, VAR6, VAR2, VAR8, VAR9, VAR4 );
input VAR5, VAR3, VAR11, VAR8, VAR2;
inout VAR9, VAR4;
output VAR6;
VAR1 VAR10(.VAR3(VAR3),.VAR11(VAR11),.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR8(VAR8),.VAR9(VAR9),.VAR4(VAR4));
VAR1 VAR7(.VAR3(VAR3),.VAR11(VAR11),.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbn/sky130_fd_sc_lp__dlxbn.behavioral.v | 2,022 | module MODULE1 (
VAR12 ,
VAR10 ,
VAR2 ,
VAR3
);
output VAR12 ;
output VAR10 ;
input VAR2 ;
input VAR3;
supply1 VAR4;
supply0 VAR16;
supply1 VAR13 ;
supply0 VAR15 ;
wire VAR5 ;
wire VAR18 ;
wire VAR11;
wire VAR7 ;
reg VAR8 ;
VAR9 VAR1 (VAR18 , VAR7, VAR5, VAR8, VAR4, VAR16);
not VAR17 (VAR5 , VAR11 );
buf VAR6 (VAR12 , ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221ai/sky130_fd_sc_hs__o221ai.behavioral.v | 2,106 | module MODULE1 (
VAR10 ,
VAR16 ,
VAR3 ,
VAR11 ,
VAR17 ,
VAR7 ,
VAR13,
VAR6
);
output VAR10 ;
input VAR16 ;
input VAR3 ;
input VAR11 ;
input VAR17 ;
input VAR7 ;
input VAR13;
input VAR6;
wire VAR17 VAR4 ;
wire VAR17 VAR15 ;
wire VAR14 ;
wire VAR2;
or VAR12 (VAR4 , VAR17, VAR11 );
or VAR8 (VAR15 , VAR3, VAR16 );
nand VAR... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/4-way_2-tree/src/riffa/tx_port_64.v | 7,852 | module MODULE1 #(
parameter VAR78 = 9'd64,
parameter VAR20 = 512,
parameter VAR49 = VAR39((2**VAR39(VAR20))+1)
)
(
input VAR69,
input VAR6,
input [2:0] VAR19,
output VAR59, input VAR79, output [31:0] VAR67, output [31:0] VAR35, output [31:0] VAR63, output VAR74, input VAR21,
input [VAR78-1:0] VAR11, input VAR23, output... | mit |
natsutan/NPU | fpga_implement/npu8/src/npu8_top.v | 4,289 | module MODULE1
(
input VAR41,
input VAR69,
input [7:0] VAR61,
input VAR29,
input VAR2,
output [31:0] VAR1,
input [31:0] VAR70,
output VAR67
);
wire VAR26;
wire VAR25;
wire VAR22;
wire [1:0] VAR51; wire [1:0] VAR36;
wire [1:0] VAR50;
wire [1:0] VAR30;
wire VAR19;
wire VAR58;
wire [31:0] VAR15;
wire [9:0] VAR14;
wire [9:... | bsd-3-clause |
olajep/oh | src/adi/hdl/library/xilinx/common/ad_data_clk.v | 2,731 | module MODULE1 #(
parameter VAR14 = 0,
parameter VAR13 = 0) (
input rst,
output VAR17,
input VAR16,
input VAR5,
output clk);
localparam VAR12 = 0;
localparam VAR9 = 2;
localparam VAR3 = 3;
wire VAR6;
assign VAR17 = 1'b1;
generate
if (VAR14 == 1) begin
VAR7 VAR10 (
.VAR11 (VAR16),
.VAR4 (VAR6));
end else begin
VAR2 VAR1... | mit |
jayrandez/Processor | core.v | 2,385 | module MODULE1(
input wire VAR18,
input wire VAR21,
output wire[15:0] VAR23,
output wire[31:0] VAR8,
output wire[31:0] VAR19,
input wire[31:0] VAR43,
output wire VAR5,
output wire VAR14,
output reg[11:0] VAR16,
output reg[7:0] VAR3,
output reg VAR20 = 0
);
parameter VAR39 = 2'b00;
parameter VAR27 = 2'b01;
parameter VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fah/sky130_fd_sc_ls__fah.behavioral.v | 1,744 | module MODULE1 (
VAR16,
VAR1 ,
VAR14 ,
VAR10 ,
VAR19
);
output VAR16;
output VAR1 ;
input VAR14 ;
input VAR10 ;
input VAR19 ;
supply1 VAR11;
supply0 VAR8;
supply1 VAR12 ;
supply0 VAR9 ;
wire VAR7;
wire VAR15 ;
wire VAR3 ;
wire VAR2 ;
wire VAR5;
xor VAR18 (VAR7, VAR14, VAR10, VAR19 );
buf VAR17 (VAR1 , VAR7 );
and VAR20... | apache-2.0 |
nickdesaulniers/Omicron | alu.v | 2,847 | module MODULE1(
input wire [15:0] VAR13, input wire [15:0] VAR19, input wire [10:0] VAR20, input wire VAR12, input wire VAR11, output reg [15:0] out, output wire VAR9 );
parameter VAR16 = 11'b00000000001;
parameter VAR5 = 11'b00000000010;
parameter VAR10 = 11'b00000000100;
parameter VAR7 = 11'b00000001000;
parameter VA... | gpl-3.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.